nrfx_uarte.c 24 KB

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  1. /**
  2. * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
  3. *
  4. * All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without modification,
  7. * are permitted provided that the following conditions are met:
  8. *
  9. * 1. Redistributions of source code must retain the above copyright notice, this
  10. * list of conditions and the following disclaimer.
  11. *
  12. * 2. Redistributions in binary form, except as embedded into a Nordic
  13. * Semiconductor ASA integrated circuit in a product or a software update for
  14. * such product, must reproduce the above copyright notice, this list of
  15. * conditions and the following disclaimer in the documentation and/or other
  16. * materials provided with the distribution.
  17. *
  18. * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
  19. * contributors may be used to endorse or promote products derived from this
  20. * software without specific prior written permission.
  21. *
  22. * 4. This software, with or without modification, must only be used with a
  23. * Nordic Semiconductor ASA integrated circuit.
  24. *
  25. * 5. Any software provided in binary form under this license must not be reverse
  26. * engineered, decompiled, modified and/or disassembled.
  27. *
  28. * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
  29. * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  30. * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
  31. * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
  32. * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  33. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  34. * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  37. * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38. *
  39. */
  40. #include <nrfx.h>
  41. #if NRFX_CHECK(NRFX_UARTE_ENABLED)
  42. #if !(NRFX_CHECK(NRFX_UARTE0_ENABLED) || \
  43. NRFX_CHECK(NRFX_UARTE1_ENABLED) || \
  44. NRFX_CHECK(NRFX_UARTE2_ENABLED) || \
  45. NRFX_CHECK(NRFX_UARTE3_ENABLED))
  46. #error "No enabled UARTE instances. Check <nrfx_config.h>."
  47. #endif
  48. #include <nrfx_uarte.h>
  49. #include "prs/nrfx_prs.h"
  50. #include <hal/nrf_gpio.h>
  51. #define NRFX_LOG_MODULE UARTE
  52. #include <nrfx_log.h>
  53. #define EVT_TO_STR(event) \
  54. (event == NRF_UARTE_EVENT_ERROR ? "NRF_UARTE_EVENT_ERROR" : \
  55. "UNKNOWN EVENT")
  56. #define UARTEX_LENGTH_VALIDATE(peripheral, drv_inst_idx, len1, len2) \
  57. (((drv_inst_idx) == NRFX_CONCAT_3(NRFX_, peripheral, _INST_IDX)) && \
  58. NRFX_EASYDMA_LENGTH_VALIDATE(peripheral, len1, len2))
  59. #if NRFX_CHECK(NRFX_UARTE0_ENABLED)
  60. #define UARTE0_LENGTH_VALIDATE(...) UARTEX_LENGTH_VALIDATE(UARTE0, __VA_ARGS__)
  61. #else
  62. #define UARTE0_LENGTH_VALIDATE(...) 0
  63. #endif
  64. #if NRFX_CHECK(NRFX_UARTE1_ENABLED)
  65. #define UARTE1_LENGTH_VALIDATE(...) UARTEX_LENGTH_VALIDATE(UARTE1, __VA_ARGS__)
  66. #else
  67. #define UARTE1_LENGTH_VALIDATE(...) 0
  68. #endif
  69. #if NRFX_CHECK(NRFX_UARTE2_ENABLED)
  70. #define UARTE2_LENGTH_VALIDATE(...) UARTEX_LENGTH_VALIDATE(UARTE2, __VA_ARGS__)
  71. #else
  72. #define UARTE2_LENGTH_VALIDATE(...) 0
  73. #endif
  74. #if NRFX_CHECK(NRFX_UARTE3_ENABLED)
  75. #define UARTE3_LENGTH_VALIDATE(...) UARTEX_LENGTH_VALIDATE(UARTE3, __VA_ARGS__)
  76. #else
  77. #define UARTE3_LENGTH_VALIDATE(...) 0
  78. #endif
  79. #define UARTE_LENGTH_VALIDATE(drv_inst_idx, length) \
  80. (UARTE0_LENGTH_VALIDATE(drv_inst_idx, length, 0) || \
  81. UARTE1_LENGTH_VALIDATE(drv_inst_idx, length, 0) || \
  82. UARTE2_LENGTH_VALIDATE(drv_inst_idx, length, 0) || \
  83. UARTE3_LENGTH_VALIDATE(drv_inst_idx, length, 0))
  84. typedef struct
  85. {
  86. void * p_context;
  87. nrfx_uarte_event_handler_t handler;
  88. uint8_t const * p_tx_buffer;
  89. uint8_t * p_rx_buffer;
  90. uint8_t * p_rx_secondary_buffer;
  91. volatile size_t tx_buffer_length;
  92. size_t rx_buffer_length;
  93. size_t rx_secondary_buffer_length;
  94. nrfx_drv_state_t state;
  95. } uarte_control_block_t;
  96. static uarte_control_block_t m_cb[NRFX_UARTE_ENABLED_COUNT];
  97. static void apply_config(nrfx_uarte_t const * p_instance,
  98. nrfx_uarte_config_t const * p_config)
  99. {
  100. if (p_config->pseltxd != NRF_UARTE_PSEL_DISCONNECTED)
  101. {
  102. nrf_gpio_pin_set(p_config->pseltxd);
  103. nrf_gpio_cfg_output(p_config->pseltxd);
  104. }
  105. if (p_config->pselrxd != NRF_UARTE_PSEL_DISCONNECTED)
  106. {
  107. nrf_gpio_cfg_input(p_config->pselrxd, NRF_GPIO_PIN_NOPULL);
  108. }
  109. nrf_uarte_baudrate_set(p_instance->p_reg, p_config->baudrate);
  110. nrf_uarte_configure(p_instance->p_reg, p_config->parity, p_config->hwfc);
  111. nrf_uarte_txrx_pins_set(p_instance->p_reg, p_config->pseltxd, p_config->pselrxd);
  112. if (p_config->hwfc == NRF_UARTE_HWFC_ENABLED)
  113. {
  114. if (p_config->pselcts != NRF_UARTE_PSEL_DISCONNECTED)
  115. {
  116. nrf_gpio_cfg_input(p_config->pselcts, NRF_GPIO_PIN_NOPULL);
  117. }
  118. if (p_config->pselrts != NRF_UARTE_PSEL_DISCONNECTED)
  119. {
  120. nrf_gpio_pin_set(p_config->pselrts);
  121. nrf_gpio_cfg_output(p_config->pselrts);
  122. }
  123. nrf_uarte_hwfc_pins_set(p_instance->p_reg, p_config->pselrts, p_config->pselcts);
  124. }
  125. }
  126. static void interrupts_enable(nrfx_uarte_t const * p_instance,
  127. uint8_t interrupt_priority)
  128. {
  129. nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ENDRX);
  130. nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ENDTX);
  131. nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ERROR);
  132. nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_RXTO);
  133. nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED);
  134. nrf_uarte_int_enable(p_instance->p_reg, NRF_UARTE_INT_ENDRX_MASK |
  135. NRF_UARTE_INT_ENDTX_MASK |
  136. NRF_UARTE_INT_ERROR_MASK |
  137. NRF_UARTE_INT_RXTO_MASK |
  138. NRF_UARTE_INT_TXSTOPPED_MASK);
  139. NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number((void *)p_instance->p_reg),
  140. interrupt_priority);
  141. NRFX_IRQ_ENABLE(nrfx_get_irq_number((void *)p_instance->p_reg));
  142. }
  143. static void interrupts_disable(nrfx_uarte_t const * p_instance)
  144. {
  145. nrf_uarte_int_disable(p_instance->p_reg, NRF_UARTE_INT_ENDRX_MASK |
  146. NRF_UARTE_INT_ENDTX_MASK |
  147. NRF_UARTE_INT_ERROR_MASK |
  148. NRF_UARTE_INT_RXTO_MASK |
  149. NRF_UARTE_INT_TXSTOPPED_MASK);
  150. NRFX_IRQ_DISABLE(nrfx_get_irq_number((void *)p_instance->p_reg));
  151. }
  152. static void pins_to_default(nrfx_uarte_t const * p_instance)
  153. {
  154. /* Reset pins to default states */
  155. uint32_t txd;
  156. uint32_t rxd;
  157. uint32_t rts;
  158. uint32_t cts;
  159. txd = nrf_uarte_tx_pin_get(p_instance->p_reg);
  160. rxd = nrf_uarte_rx_pin_get(p_instance->p_reg);
  161. rts = nrf_uarte_rts_pin_get(p_instance->p_reg);
  162. cts = nrf_uarte_cts_pin_get(p_instance->p_reg);
  163. nrf_uarte_txrx_pins_disconnect(p_instance->p_reg);
  164. nrf_uarte_hwfc_pins_disconnect(p_instance->p_reg);
  165. if (txd != NRF_UARTE_PSEL_DISCONNECTED)
  166. {
  167. nrf_gpio_cfg_default(txd);
  168. }
  169. if (rxd != NRF_UARTE_PSEL_DISCONNECTED)
  170. {
  171. nrf_gpio_cfg_default(rxd);
  172. }
  173. if (cts != NRF_UARTE_PSEL_DISCONNECTED)
  174. {
  175. nrf_gpio_cfg_default(cts);
  176. }
  177. if (rts != NRF_UARTE_PSEL_DISCONNECTED)
  178. {
  179. nrf_gpio_cfg_default(rts);
  180. }
  181. }
  182. nrfx_err_t nrfx_uarte_init(nrfx_uarte_t const * p_instance,
  183. nrfx_uarte_config_t const * p_config,
  184. nrfx_uarte_event_handler_t event_handler)
  185. {
  186. NRFX_ASSERT(p_config);
  187. uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
  188. nrfx_err_t err_code = NRFX_SUCCESS;
  189. if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
  190. {
  191. err_code = NRFX_ERROR_INVALID_STATE;
  192. NRFX_LOG_WARNING("Function: %s, error code: %s.",
  193. __func__,
  194. NRFX_LOG_ERROR_STRING_GET(err_code));
  195. return err_code;
  196. }
  197. #if NRFX_CHECK(NRFX_PRS_ENABLED)
  198. static nrfx_irq_handler_t const irq_handlers[NRFX_UARTE_ENABLED_COUNT] = {
  199. #if NRFX_CHECK(NRFX_UARTE0_ENABLED)
  200. nrfx_uarte_0_irq_handler,
  201. #endif
  202. #if NRFX_CHECK(NRFX_UARTE1_ENABLED)
  203. nrfx_uarte_1_irq_handler,
  204. #endif
  205. #if NRFX_CHECK(NRFX_UARTE2_ENABLED)
  206. nrfx_uarte_2_irq_handler,
  207. #endif
  208. #if NRFX_CHECK(NRFX_UARTE3_ENABLED)
  209. nrfx_uarte_3_irq_handler,
  210. #endif
  211. };
  212. if (nrfx_prs_acquire(p_instance->p_reg,
  213. irq_handlers[p_instance->drv_inst_idx]) != NRFX_SUCCESS)
  214. {
  215. err_code = NRFX_ERROR_BUSY;
  216. NRFX_LOG_WARNING("Function: %s, error code: %s.",
  217. __func__,
  218. NRFX_LOG_ERROR_STRING_GET(err_code));
  219. return err_code;
  220. }
  221. #endif // NRFX_CHECK(NRFX_PRS_ENABLED)
  222. apply_config(p_instance, p_config);
  223. #if defined(NRF5340_XXAA_APPLICATION) || defined(NRF5340_XXAA_NETWORK) || defined(NRF9160_XXAA)
  224. // Apply workaround for anomalies:
  225. // - nRF9160 - anomaly 23
  226. // - nRF5340 - anomaly 44
  227. volatile uint32_t const * rxenable_reg =
  228. (volatile uint32_t *)(((uint32_t)p_instance->p_reg) + 0x564);
  229. volatile uint32_t const * txenable_reg =
  230. (volatile uint32_t *)(((uint32_t)p_instance->p_reg) + 0x568);
  231. if (*txenable_reg == 1)
  232. {
  233. nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STOPTX);
  234. }
  235. if (*rxenable_reg == 1)
  236. {
  237. nrf_uarte_enable(p_instance->p_reg);
  238. nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STOPRX);
  239. while (*rxenable_reg)
  240. {}
  241. (void)nrf_uarte_errorsrc_get_and_clear(p_instance->p_reg);
  242. nrf_uarte_disable(p_instance->p_reg);
  243. }
  244. #endif // defined(NRF5340_XXAA_APPLICATION) || defined(NRF5340_XXAA_NETWORK) || defined(NRF9160_XXAA)
  245. p_cb->handler = event_handler;
  246. p_cb->p_context = p_config->p_context;
  247. if (p_cb->handler)
  248. {
  249. interrupts_enable(p_instance, p_config->interrupt_priority);
  250. }
  251. nrf_uarte_enable(p_instance->p_reg);
  252. p_cb->rx_buffer_length = 0;
  253. p_cb->rx_secondary_buffer_length = 0;
  254. p_cb->tx_buffer_length = 0;
  255. p_cb->state = NRFX_DRV_STATE_INITIALIZED;
  256. NRFX_LOG_WARNING("Function: %s, error code: %s.",
  257. __func__,
  258. NRFX_LOG_ERROR_STRING_GET(err_code));
  259. return err_code;
  260. }
  261. void nrfx_uarte_uninit(nrfx_uarte_t const * p_instance)
  262. {
  263. uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
  264. NRF_UARTE_Type * p_reg = p_instance->p_reg;
  265. if (p_cb->handler)
  266. {
  267. interrupts_disable(p_instance);
  268. }
  269. // Make sure all transfers are finished before UARTE is disabled
  270. // to achieve the lowest power consumption.
  271. nrf_uarte_shorts_disable(p_reg, NRF_UARTE_SHORT_ENDRX_STARTRX);
  272. // Check if there is any ongoing reception.
  273. if (p_cb->rx_buffer_length)
  274. {
  275. nrf_uarte_event_clear(p_reg, NRF_UARTE_EVENT_RXTO);
  276. nrf_uarte_task_trigger(p_reg, NRF_UARTE_TASK_STOPRX);
  277. }
  278. nrf_uarte_event_clear(p_reg, NRF_UARTE_EVENT_TXSTOPPED);
  279. nrf_uarte_task_trigger(p_reg, NRF_UARTE_TASK_STOPTX);
  280. // Wait for TXSTOPPED event and for RXTO event, provided that there was ongoing reception.
  281. while (!nrf_uarte_event_check(p_reg, NRF_UARTE_EVENT_TXSTOPPED) ||
  282. (p_cb->rx_buffer_length && !nrf_uarte_event_check(p_reg, NRF_UARTE_EVENT_RXTO)))
  283. {}
  284. nrf_uarte_disable(p_reg);
  285. pins_to_default(p_instance);
  286. #if NRFX_CHECK(NRFX_PRS_ENABLED)
  287. nrfx_prs_release(p_reg);
  288. #endif
  289. p_cb->state = NRFX_DRV_STATE_UNINITIALIZED;
  290. p_cb->handler = NULL;
  291. NRFX_LOG_INFO("Instance uninitialized: %d.", p_instance->drv_inst_idx);
  292. }
  293. nrfx_err_t nrfx_uarte_tx(nrfx_uarte_t const * p_instance,
  294. uint8_t const * p_data,
  295. size_t length)
  296. {
  297. uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
  298. NRFX_ASSERT(p_cb->state == NRFX_DRV_STATE_INITIALIZED);
  299. NRFX_ASSERT(p_data);
  300. NRFX_ASSERT(length > 0);
  301. NRFX_ASSERT(UARTE_LENGTH_VALIDATE(p_instance->drv_inst_idx, length));
  302. nrfx_err_t err_code;
  303. // EasyDMA requires that transfer buffers are placed in DataRAM,
  304. // signal error if the are not.
  305. if (!nrfx_is_in_ram(p_data))
  306. {
  307. err_code = NRFX_ERROR_INVALID_ADDR;
  308. NRFX_LOG_WARNING("Function: %s, error code: %s.",
  309. __func__,
  310. NRFX_LOG_ERROR_STRING_GET(err_code));
  311. return err_code;
  312. }
  313. if (nrfx_uarte_tx_in_progress(p_instance))
  314. {
  315. err_code = NRFX_ERROR_BUSY;
  316. NRFX_LOG_WARNING("Function: %s, error code: %s.",
  317. __func__,
  318. NRFX_LOG_ERROR_STRING_GET(err_code));
  319. return err_code;
  320. }
  321. p_cb->tx_buffer_length = length;
  322. p_cb->p_tx_buffer = p_data;
  323. NRFX_LOG_INFO("Transfer tx_len: %d.", p_cb->tx_buffer_length);
  324. NRFX_LOG_DEBUG("Tx data:");
  325. NRFX_LOG_HEXDUMP_DEBUG(p_cb->p_tx_buffer,
  326. p_cb->tx_buffer_length * sizeof(p_cb->p_tx_buffer[0]));
  327. err_code = NRFX_SUCCESS;
  328. nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ENDTX);
  329. nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED);
  330. nrf_uarte_tx_buffer_set(p_instance->p_reg, p_cb->p_tx_buffer, p_cb->tx_buffer_length);
  331. nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STARTTX);
  332. if (p_cb->handler == NULL)
  333. {
  334. bool endtx;
  335. bool txstopped;
  336. do
  337. {
  338. endtx = nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_ENDTX);
  339. txstopped = nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED);
  340. }
  341. while ((!endtx) && (!txstopped));
  342. if (txstopped)
  343. {
  344. err_code = NRFX_ERROR_FORBIDDEN;
  345. }
  346. else
  347. {
  348. // Transmitter has to be stopped by triggering the STOPTX task to achieve
  349. // the lowest possible level of the UARTE power consumption.
  350. nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STOPTX);
  351. while (!nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED))
  352. {}
  353. }
  354. p_cb->tx_buffer_length = 0;
  355. }
  356. NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
  357. return err_code;
  358. }
  359. bool nrfx_uarte_tx_in_progress(nrfx_uarte_t const * p_instance)
  360. {
  361. return (m_cb[p_instance->drv_inst_idx].tx_buffer_length != 0);
  362. }
  363. nrfx_err_t nrfx_uarte_rx(nrfx_uarte_t const * p_instance,
  364. uint8_t * p_data,
  365. size_t length)
  366. {
  367. uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
  368. NRFX_ASSERT(m_cb[p_instance->drv_inst_idx].state == NRFX_DRV_STATE_INITIALIZED);
  369. NRFX_ASSERT(p_data);
  370. NRFX_ASSERT(length > 0);
  371. NRFX_ASSERT(UARTE_LENGTH_VALIDATE(p_instance->drv_inst_idx, length));
  372. nrfx_err_t err_code;
  373. // EasyDMA requires that transfer buffers are placed in DataRAM,
  374. // signal error if the are not.
  375. if (!nrfx_is_in_ram(p_data))
  376. {
  377. err_code = NRFX_ERROR_INVALID_ADDR;
  378. NRFX_LOG_WARNING("Function: %s, error code: %s.",
  379. __func__,
  380. NRFX_LOG_ERROR_STRING_GET(err_code));
  381. return err_code;
  382. }
  383. bool second_buffer = false;
  384. if (p_cb->handler)
  385. {
  386. nrf_uarte_int_disable(p_instance->p_reg, NRF_UARTE_INT_ERROR_MASK |
  387. NRF_UARTE_INT_ENDRX_MASK);
  388. }
  389. if (p_cb->rx_buffer_length != 0)
  390. {
  391. if (p_cb->rx_secondary_buffer_length != 0)
  392. {
  393. if (p_cb->handler)
  394. {
  395. nrf_uarte_int_enable(p_instance->p_reg, NRF_UARTE_INT_ERROR_MASK |
  396. NRF_UARTE_INT_ENDRX_MASK);
  397. }
  398. err_code = NRFX_ERROR_BUSY;
  399. NRFX_LOG_WARNING("Function: %s, error code: %s.",
  400. __func__,
  401. NRFX_LOG_ERROR_STRING_GET(err_code));
  402. return err_code;
  403. }
  404. second_buffer = true;
  405. }
  406. if (!second_buffer)
  407. {
  408. p_cb->rx_buffer_length = length;
  409. p_cb->p_rx_buffer = p_data;
  410. p_cb->rx_secondary_buffer_length = 0;
  411. }
  412. else
  413. {
  414. p_cb->p_rx_secondary_buffer = p_data;
  415. p_cb->rx_secondary_buffer_length = length;
  416. }
  417. NRFX_LOG_INFO("Transfer rx_len: %d.", length);
  418. err_code = NRFX_SUCCESS;
  419. nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ENDRX);
  420. nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_RXTO);
  421. nrf_uarte_rx_buffer_set(p_instance->p_reg, p_data, length);
  422. if (!second_buffer)
  423. {
  424. nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STARTRX);
  425. }
  426. else
  427. {
  428. nrf_uarte_shorts_enable(p_instance->p_reg, NRF_UARTE_SHORT_ENDRX_STARTRX);
  429. }
  430. if (m_cb[p_instance->drv_inst_idx].handler == NULL)
  431. {
  432. bool endrx;
  433. bool rxto;
  434. bool error;
  435. do {
  436. endrx = nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_ENDRX);
  437. rxto = nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_RXTO);
  438. error = nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_ERROR);
  439. } while ((!endrx) && (!rxto) && (!error));
  440. m_cb[p_instance->drv_inst_idx].rx_buffer_length = 0;
  441. if (error)
  442. {
  443. err_code = NRFX_ERROR_INTERNAL;
  444. }
  445. if (rxto)
  446. {
  447. err_code = NRFX_ERROR_FORBIDDEN;
  448. }
  449. }
  450. else
  451. {
  452. nrf_uarte_int_enable(p_instance->p_reg, NRF_UARTE_INT_ERROR_MASK |
  453. NRF_UARTE_INT_ENDRX_MASK);
  454. }
  455. NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
  456. return err_code;
  457. }
  458. bool nrfx_uarte_rx_ready(nrfx_uarte_t const * p_instance)
  459. {
  460. return nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_ENDRX);
  461. }
  462. uint32_t nrfx_uarte_errorsrc_get(nrfx_uarte_t const * p_instance)
  463. {
  464. nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ERROR);
  465. return nrf_uarte_errorsrc_get_and_clear(p_instance->p_reg);
  466. }
  467. static void rx_done_event(uarte_control_block_t * p_cb,
  468. size_t bytes,
  469. uint8_t * p_data)
  470. {
  471. nrfx_uarte_event_t event;
  472. event.type = NRFX_UARTE_EVT_RX_DONE;
  473. event.data.rxtx.bytes = bytes;
  474. event.data.rxtx.p_data = p_data;
  475. p_cb->handler(&event, p_cb->p_context);
  476. }
  477. static void tx_done_event(uarte_control_block_t * p_cb,
  478. size_t bytes)
  479. {
  480. nrfx_uarte_event_t event;
  481. event.type = NRFX_UARTE_EVT_TX_DONE;
  482. event.data.rxtx.bytes = bytes;
  483. event.data.rxtx.p_data = (uint8_t *)p_cb->p_tx_buffer;
  484. p_cb->tx_buffer_length = 0;
  485. p_cb->handler(&event, p_cb->p_context);
  486. }
  487. void nrfx_uarte_tx_abort(nrfx_uarte_t const * p_instance)
  488. {
  489. uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
  490. nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED);
  491. nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STOPTX);
  492. if (p_cb->handler == NULL)
  493. {
  494. while (!nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED))
  495. {}
  496. }
  497. NRFX_LOG_INFO("TX transaction aborted.");
  498. }
  499. void nrfx_uarte_rx_abort(nrfx_uarte_t const * p_instance)
  500. {
  501. uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
  502. // Short between ENDRX event and STARTRX task must be disabled before
  503. // aborting transmission.
  504. if (p_cb->rx_secondary_buffer_length != 0)
  505. {
  506. nrf_uarte_shorts_disable(p_instance->p_reg, NRF_UARTE_SHORT_ENDRX_STARTRX);
  507. }
  508. nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STOPRX);
  509. NRFX_LOG_INFO("RX transaction aborted.");
  510. }
  511. static void uarte_irq_handler(NRF_UARTE_Type * p_uarte,
  512. uarte_control_block_t * p_cb)
  513. {
  514. if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_ERROR))
  515. {
  516. nrfx_uarte_event_t event;
  517. nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_ERROR);
  518. event.type = NRFX_UARTE_EVT_ERROR;
  519. event.data.error.error_mask = nrf_uarte_errorsrc_get_and_clear(p_uarte);
  520. event.data.error.rxtx.bytes = nrf_uarte_rx_amount_get(p_uarte);
  521. event.data.error.rxtx.p_data = p_cb->p_rx_buffer;
  522. // Abort transfer.
  523. p_cb->rx_buffer_length = 0;
  524. p_cb->rx_secondary_buffer_length = 0;
  525. p_cb->handler(&event, p_cb->p_context);
  526. }
  527. else if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_ENDRX))
  528. {
  529. nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_ENDRX);
  530. size_t amount = nrf_uarte_rx_amount_get(p_uarte);
  531. // If the transfer was stopped before completion, amount of transfered bytes
  532. // will not be equal to the buffer length. Interrupted transfer is ignored.
  533. if (amount == p_cb->rx_buffer_length)
  534. {
  535. if (p_cb->rx_secondary_buffer_length != 0)
  536. {
  537. uint8_t * p_data = p_cb->p_rx_buffer;
  538. nrf_uarte_shorts_disable(p_uarte, NRF_UARTE_SHORT_ENDRX_STARTRX);
  539. p_cb->rx_buffer_length = p_cb->rx_secondary_buffer_length;
  540. p_cb->p_rx_buffer = p_cb->p_rx_secondary_buffer;
  541. p_cb->rx_secondary_buffer_length = 0;
  542. rx_done_event(p_cb, amount, p_data);
  543. }
  544. else
  545. {
  546. p_cb->rx_buffer_length = 0;
  547. rx_done_event(p_cb, amount, p_cb->p_rx_buffer);
  548. }
  549. }
  550. }
  551. if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_RXTO))
  552. {
  553. nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_RXTO);
  554. if (p_cb->rx_buffer_length != 0)
  555. {
  556. p_cb->rx_buffer_length = 0;
  557. // In case of using double-buffered reception both variables storing buffer length
  558. // have to be cleared to prevent incorrect behaviour of the driver.
  559. p_cb->rx_secondary_buffer_length = 0;
  560. rx_done_event(p_cb, nrf_uarte_rx_amount_get(p_uarte), p_cb->p_rx_buffer);
  561. }
  562. }
  563. if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_ENDTX))
  564. {
  565. nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_ENDTX);
  566. // Transmitter has to be stopped by triggering STOPTX task to achieve
  567. // the lowest possible level of the UARTE power consumption.
  568. nrf_uarte_task_trigger(p_uarte, NRF_UARTE_TASK_STOPTX);
  569. if (p_cb->tx_buffer_length != 0)
  570. {
  571. tx_done_event(p_cb, nrf_uarte_tx_amount_get(p_uarte));
  572. }
  573. }
  574. if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_TXSTOPPED))
  575. {
  576. nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_TXSTOPPED);
  577. if (p_cb->tx_buffer_length != 0)
  578. {
  579. tx_done_event(p_cb, nrf_uarte_tx_amount_get(p_uarte));
  580. }
  581. }
  582. }
  583. #if NRFX_CHECK(NRFX_UARTE0_ENABLED)
  584. void nrfx_uarte_0_irq_handler(void)
  585. {
  586. uarte_irq_handler(NRF_UARTE0, &m_cb[NRFX_UARTE0_INST_IDX]);
  587. }
  588. #endif
  589. #if NRFX_CHECK(NRFX_UARTE1_ENABLED)
  590. void nrfx_uarte_1_irq_handler(void)
  591. {
  592. uarte_irq_handler(NRF_UARTE1, &m_cb[NRFX_UARTE1_INST_IDX]);
  593. }
  594. #endif
  595. #if NRFX_CHECK(NRFX_UARTE2_ENABLED)
  596. void nrfx_uarte_2_irq_handler(void)
  597. {
  598. uarte_irq_handler(NRF_UARTE2, &m_cb[NRFX_UARTE2_INST_IDX]);
  599. }
  600. #endif
  601. #if NRFX_CHECK(NRFX_UARTE3_ENABLED)
  602. void nrfx_uarte_3_irq_handler(void)
  603. {
  604. uarte_irq_handler(NRF_UARTE3, &m_cb[NRFX_UARTE3_INST_IDX]);
  605. }
  606. #endif
  607. #endif // NRFX_CHECK(NRFX_UARTE_ENABLED)