nrf_block_dev_ram.c 8.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244
  1. /**
  2. * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA
  3. *
  4. * All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without modification,
  7. * are permitted provided that the following conditions are met:
  8. *
  9. * 1. Redistributions of source code must retain the above copyright notice, this
  10. * list of conditions and the following disclaimer.
  11. *
  12. * 2. Redistributions in binary form, except as embedded into a Nordic
  13. * Semiconductor ASA integrated circuit in a product or a software update for
  14. * such product, must reproduce the above copyright notice, this list of
  15. * conditions and the following disclaimer in the documentation and/or other
  16. * materials provided with the distribution.
  17. *
  18. * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
  19. * contributors may be used to endorse or promote products derived from this
  20. * software without specific prior written permission.
  21. *
  22. * 4. This software, with or without modification, must only be used with a
  23. * Nordic Semiconductor ASA integrated circuit.
  24. *
  25. * 5. Any software provided in binary form under this license must not be reverse
  26. * engineered, decompiled, modified and/or disassembled.
  27. *
  28. * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
  29. * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  30. * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
  31. * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
  32. * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  33. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  34. * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  37. * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38. *
  39. */
  40. #include "sdk_common.h"
  41. #if NRF_MODULE_ENABLED(NRF_BLOCK_DEV_RAM)
  42. #include "nrf_block_dev_ram.h"
  43. #include <inttypes.h>
  44. /**@file
  45. *
  46. * @ingroup nrf_block_dev
  47. * @{
  48. *
  49. * @brief This module implements block device API. It should be used as a reference block device.
  50. */
  51. #if NRF_BLOCK_DEV_RAM_CONFIG_LOG_ENABLED
  52. #define NRF_LOG_LEVEL NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL
  53. #define NRF_LOG_INFO_COLOR NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR
  54. #define NRF_LOG_INST_DEBUG_COLOR NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR
  55. #else
  56. #define NRF_LOG_LEVEL 0
  57. #endif
  58. #include "nrf_log.h"
  59. static ret_code_t block_dev_ram_init(nrf_block_dev_t const * p_blk_dev,
  60. nrf_block_dev_ev_handler ev_handler,
  61. void const * p_context)
  62. {
  63. ASSERT(p_blk_dev);
  64. nrf_block_dev_ram_t const * p_ram_dev = CONTAINER_OF(p_blk_dev, nrf_block_dev_ram_t, block_dev);
  65. nrf_block_dev_ram_work_t * p_work = p_ram_dev->p_work;
  66. NRF_LOG_INST_DEBUG(p_ram_dev->p_log, "Init");
  67. /* Calculate block device geometry.... */
  68. p_work->geometry.blk_size = p_ram_dev->ram_config.block_size;
  69. p_work->geometry.blk_count = p_ram_dev->ram_config.size /
  70. p_ram_dev->ram_config.block_size;
  71. p_work->p_context = p_context;
  72. p_work->ev_handler = ev_handler;
  73. if (p_work->ev_handler)
  74. {
  75. /*Asynchronous operation (simulation)*/
  76. const nrf_block_dev_event_t ev = {
  77. NRF_BLOCK_DEV_EVT_INIT,
  78. NRF_BLOCK_DEV_RESULT_SUCCESS,
  79. NULL,
  80. p_work->p_context
  81. };
  82. p_work->ev_handler(p_blk_dev, &ev);
  83. }
  84. return NRF_SUCCESS;
  85. }
  86. static ret_code_t block_dev_ram_uninit(nrf_block_dev_t const * p_blk_dev)
  87. {
  88. ASSERT(p_blk_dev);
  89. nrf_block_dev_ram_t const * p_ram_dev = CONTAINER_OF(p_blk_dev, nrf_block_dev_ram_t, block_dev);
  90. nrf_block_dev_ram_work_t * p_work = p_ram_dev->p_work;
  91. NRF_LOG_INST_DEBUG(p_ram_dev->p_log, "Uninit");
  92. if (p_work->ev_handler)
  93. {
  94. /*Asynchronous operation (simulation)*/
  95. const nrf_block_dev_event_t ev = {
  96. NRF_BLOCK_DEV_EVT_UNINIT,
  97. NRF_BLOCK_DEV_RESULT_SUCCESS,
  98. NULL,
  99. p_work->p_context
  100. };
  101. p_work->ev_handler(p_blk_dev, &ev);
  102. }
  103. memset(p_work, 0, sizeof(nrf_block_dev_ram_work_t));
  104. return NRF_SUCCESS;
  105. }
  106. static ret_code_t block_dev_ram_req(nrf_block_dev_t const * p_blk_dev,
  107. nrf_block_req_t const * p_blk,
  108. nrf_block_dev_event_type_t event)
  109. {
  110. ASSERT(p_blk_dev);
  111. ASSERT(p_blk);
  112. nrf_block_dev_ram_t const * p_ram_dev = CONTAINER_OF(p_blk_dev, nrf_block_dev_ram_t, block_dev);
  113. nrf_block_dev_ram_config_t const * p_ram_config = &p_ram_dev->ram_config;
  114. nrf_block_dev_ram_work_t const * p_work = p_ram_dev->p_work;
  115. NRF_LOG_INST_DEBUG(p_ram_dev->p_log,
  116. ((event == NRF_BLOCK_DEV_EVT_BLK_READ_DONE) ?
  117. "Read req from block %"PRIu32" size %"PRIu32"(x%"PRIu32") to %"PRIXPTR
  118. :
  119. "Write req to block %"PRIu32" size %"PRIu32"(x%"PRIu32") from %"PRIXPTR),
  120. p_blk->blk_id,
  121. p_blk->blk_count,
  122. p_blk_dev->p_ops->geometry(p_blk_dev)->blk_size,
  123. p_blk->p_buff);
  124. if ((p_blk->blk_id + p_blk->blk_count) > p_work->geometry.blk_count)
  125. {
  126. NRF_LOG_INST_ERROR(p_ram_dev->p_log,
  127. ((event == NRF_BLOCK_DEV_EVT_BLK_READ_DONE) ?
  128. "Out of range read req block %"PRIu32" count %"PRIu32" while max is %"PRIu32
  129. :
  130. "Out of range write req block %"PRIu32" count %"PRIu32", while max is %"PRIu32),
  131. p_blk->blk_id,
  132. p_blk->blk_count,
  133. p_blk_dev->p_ops->geometry(p_blk_dev)->blk_count);
  134. return NRF_ERROR_INVALID_ADDR;
  135. }
  136. /*Synchronous operation*/
  137. uint8_t * p_buff = p_ram_config->p_work_buffer;
  138. p_buff += p_blk->blk_id * p_work->geometry.blk_size;
  139. const void * p_src = (event == NRF_BLOCK_DEV_EVT_BLK_READ_DONE) ? p_buff : p_blk->p_buff;
  140. void * p_dst = (event == NRF_BLOCK_DEV_EVT_BLK_READ_DONE) ? p_blk->p_buff : p_buff;
  141. memcpy(p_dst, p_src, p_work->geometry.blk_size * p_blk->blk_count);
  142. if (p_work->ev_handler)
  143. {
  144. /*Asynchronous operation (simulation)*/
  145. const nrf_block_dev_event_t ev = {
  146. event,
  147. NRF_BLOCK_DEV_RESULT_SUCCESS,
  148. p_blk,
  149. p_work->p_context
  150. };
  151. p_work->ev_handler(p_blk_dev, &ev);
  152. }
  153. return NRF_SUCCESS;
  154. }
  155. static ret_code_t block_dev_ram_read_req(nrf_block_dev_t const * p_blk_dev,
  156. nrf_block_req_t const * p_blk)
  157. {
  158. return block_dev_ram_req(p_blk_dev, p_blk, NRF_BLOCK_DEV_EVT_BLK_READ_DONE);
  159. }
  160. static ret_code_t block_dev_ram_write_req(nrf_block_dev_t const * p_blk_dev,
  161. nrf_block_req_t const * p_blk)
  162. {
  163. return block_dev_ram_req(p_blk_dev, p_blk, NRF_BLOCK_DEV_EVT_BLK_WRITE_DONE);
  164. }
  165. static ret_code_t block_dev_ram_ioctl(nrf_block_dev_t const * p_blk_dev,
  166. nrf_block_dev_ioctl_req_t req,
  167. void * p_data)
  168. {
  169. nrf_block_dev_ram_t const * p_ram_dev = CONTAINER_OF(p_blk_dev, nrf_block_dev_ram_t, block_dev);
  170. switch (req)
  171. {
  172. case NRF_BLOCK_DEV_IOCTL_REQ_CACHE_FLUSH:
  173. {
  174. bool * p_flushing = p_data;
  175. NRF_LOG_INST_DEBUG(p_ram_dev->p_log, "IOCtl: Cache flush");
  176. if (p_flushing)
  177. {
  178. *p_flushing = false;
  179. }
  180. return NRF_SUCCESS;
  181. }
  182. case NRF_BLOCK_DEV_IOCTL_REQ_INFO_STRINGS:
  183. {
  184. if (p_data == NULL)
  185. {
  186. return NRF_ERROR_INVALID_PARAM;
  187. }
  188. nrf_block_dev_info_strings_t const * * pp_strings = p_data;
  189. *pp_strings = &p_ram_dev->info_strings;
  190. return NRF_SUCCESS;
  191. }
  192. default:
  193. break;
  194. }
  195. return NRF_ERROR_NOT_SUPPORTED;
  196. }
  197. static nrf_block_dev_geometry_t const * block_dev_ram_geometry(nrf_block_dev_t const * p_blk_dev)
  198. {
  199. ASSERT(p_blk_dev);
  200. nrf_block_dev_ram_t const * p_ram_dev = CONTAINER_OF(p_blk_dev, nrf_block_dev_ram_t, block_dev);
  201. nrf_block_dev_ram_work_t const * p_work = p_ram_dev->p_work;
  202. return &p_work->geometry;
  203. }
  204. const nrf_block_dev_ops_t nrf_block_device_ram_ops = {
  205. .init = block_dev_ram_init,
  206. .uninit = block_dev_ram_uninit,
  207. .read_req = block_dev_ram_read_req,
  208. .write_req = block_dev_ram_write_req,
  209. .ioctl = block_dev_ram_ioctl,
  210. .geometry = block_dev_ram_geometry,
  211. };
  212. /** @} */
  213. #endif // NRF_MODULE_ENABLED(NRF_BLOCK_DEV_RAM)