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- #ifndef NRFX_CONFIG_H__
- #define NRFX_CONFIG_H__
- #define NRF_CLOCK NRF_CLOCK_S
- #define NRF_DPPIC NRF_DPPIC_S
- #define NRF_EGU0 NRF_EGU0_S
- #define NRF_EGU1 NRF_EGU1_S
- #define NRF_EGU2 NRF_EGU2_S
- #define NRF_EGU3 NRF_EGU3_S
- #define NRF_EGU4 NRF_EGU4_S
- #define NRF_EGU5 NRF_EGU5_S
- #define NRF_FPU NRF_FPU_S
- #define NRF_P0 NRF_P0_S
- #define NRF_I2S NRF_I2S_S
- #define NRF_KMU NRF_KMU_S
- #define NRF_NVMC NRF_NVMC_S
- #define NRF_PDM NRF_PDM_S
- #define NRF_POWER NRF_POWER_S
- #define NRF_PWM0 NRF_PWM0_S
- #define NRF_PWM1 NRF_PWM1_S
- #define NRF_PWM2 NRF_PWM2_S
- #define NRF_PWM3 NRF_PWM3_S
- #define NRF_REGULATORS NRF_REGULATORS_S
- #define NRF_RTC0 NRF_RTC0_S
- #define NRF_RTC1 NRF_RTC1_S
- #define NRF_SAADC NRF_SAADC_S
- #define NRF_SPIM0 NRF_SPIM0_S
- #define NRF_SPIM1 NRF_SPIM1_S
- #define NRF_SPIM2 NRF_SPIM2_S
- #define NRF_SPIM3 NRF_SPIM3_S
- #define NRF_SPIS0 NRF_SPIS0_S
- #define NRF_SPIS1 NRF_SPIS1_S
- #define NRF_SPIS2 NRF_SPIS2_S
- #define NRF_SPIS3 NRF_SPIS3_S
- #define NRF_TIMER0 NRF_TIMER0_S
- #define NRF_TIMER1 NRF_TIMER1_S
- #define NRF_TIMER2 NRF_TIMER2_S
- #define NRF_TWIM0 NRF_TWIM0_S
- #define NRF_TWIM1 NRF_TWIM1_S
- #define NRF_TWIM2 NRF_TWIM2_S
- #define NRF_TWIM3 NRF_TWIM3_S
- #define NRF_TWIS0 NRF_TWIS0_S
- #define NRF_TWIS1 NRF_TWIS1_S
- #define NRF_TWIS2 NRF_TWIS2_S
- #define NRF_TWIS3 NRF_TWIS3_S
- #define NRF_UARTE0 NRF_UARTE0_S
- #define NRF_UARTE1 NRF_UARTE1_S
- #define NRF_UARTE2 NRF_UARTE2_S
- #define NRF_UARTE3 NRF_UARTE3_S
- #define NRF_VMC NRF_VMC_S
- #define NRF_WDT NRF_WDT_S
- #define NRF_CRYPTOCELL NRF_CRYPTOCELL_S
- #define NRF_FICR NRF_FICR_S
- #define NRF_GPIOTE0 NRF_GPIOTE0_S
- #define NRF_GPIOTE1 NRF_GPIOTE1_NS
- #define NRF_SPU NRF_SPU_S
- #define NRF_UICR NRF_UICR_S
- #define NRF_GPIOTE NRF_GPIOTE0_S
- #define GPIOTE_IRQHandler GPIOTE0_IRQHandler
- #ifndef NRFX_CLOCK_ENABLED
- #define NRFX_CLOCK_ENABLED 1
- #endif
- #ifndef NRFX_CLOCK_CONFIG_LF_SRC
- #define NRFX_CLOCK_CONFIG_LF_SRC 2
- #endif
- #ifndef NRFX_CLOCK_CONFIG_IRQ_PRIORITY
- #define NRFX_CLOCK_CONFIG_IRQ_PRIORITY 7
- #endif
- #ifndef NRFX_CLOCK_CONFIG_LOG_ENABLED
- #define NRFX_CLOCK_CONFIG_LOG_ENABLED 0
- #endif
- #ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL
- #define NRFX_CLOCK_CONFIG_LOG_LEVEL 3
- #endif
- #ifndef NRFX_CLOCK_CONFIG_INFO_COLOR
- #define NRFX_CLOCK_CONFIG_INFO_COLOR 0
- #endif
- #ifndef NRFX_CLOCK_CONFIG_DEBUG_COLOR
- #define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0
- #endif
- #ifndef NRFX_DPPI_ENABLED
- #define NRFX_DPPI_ENABLED 1
- #endif
- #ifndef NRFX_DPPI_CONFIG_LOG_ENABLED
- #define NRFX_DPPI_CONFIG_LOG_ENABLED 0
- #endif
- #ifndef NRFX_DPPI_CONFIG_LOG_LEVEL
- #define NRFX_DPPI_CONFIG_LOG_LEVEL 3
- #endif
- #ifndef NRFX_DPPI_CONFIG_INFO_COLOR
- #define NRFX_DPPI_CONFIG_INFO_COLOR 0
- #endif
- #ifndef NRFX_DPPI_CONFIG_DEBUG_COLOR
- #define NRFX_DPPI_CONFIG_DEBUG_COLOR 0
- #endif
- #ifndef NRFX_GPIOTE_ENABLED
- #define NRFX_GPIOTE_ENABLED 1
- #endif
- #ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS
- #define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
- #endif
- #ifndef NRFX_GPIOTE_CONFIG_IRQ_PRIORITY
- #define NRFX_GPIOTE_CONFIG_IRQ_PRIORITY 7
- #endif
- #ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED
- #define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0
- #endif
- #ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL
- #define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3
- #endif
- #ifndef NRFX_GPIOTE_CONFIG_INFO_COLOR
- #define NRFX_GPIOTE_CONFIG_INFO_COLOR 0
- #endif
- #ifndef NRFX_GPIOTE_CONFIG_DEBUG_COLOR
- #define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0
- #endif
- #ifndef NRFX_I2S_ENABLED
- #define NRFX_I2S_ENABLED 1
- #endif
- #ifndef NRFX_I2S_CONFIG_SCK_PIN
- #define NRFX_I2S_CONFIG_SCK_PIN 31
- #endif
- #ifndef NRFX_I2S_CONFIG_LRCK_PIN
- #define NRFX_I2S_CONFIG_LRCK_PIN 30
- #endif
- #ifndef NRFX_I2S_CONFIG_MCK_PIN
- #define NRFX_I2S_CONFIG_MCK_PIN 255
- #endif
- #ifndef NRFX_I2S_CONFIG_SDOUT_PIN
- #define NRFX_I2S_CONFIG_SDOUT_PIN 29
- #endif
- #ifndef NRFX_I2S_CONFIG_SDIN_PIN
- #define NRFX_I2S_CONFIG_SDIN_PIN 28
- #endif
- #ifndef NRFX_I2S_CONFIG_MASTER
- #define NRFX_I2S_CONFIG_MASTER 0
- #endif
- #ifndef NRFX_I2S_CONFIG_FORMAT
- #define NRFX_I2S_CONFIG_FORMAT 0
- #endif
- #ifndef NRFX_I2S_CONFIG_ALIGN
- #define NRFX_I2S_CONFIG_ALIGN 0
- #endif
- #ifndef NRFX_I2S_CONFIG_SWIDTH
- #define NRFX_I2S_CONFIG_SWIDTH 1
- #endif
- #ifndef NRFX_I2S_CONFIG_CHANNELS
- #define NRFX_I2S_CONFIG_CHANNELS 1
- #endif
- #ifndef NRFX_I2S_CONFIG_MCK_SETUP
- #define NRFX_I2S_CONFIG_MCK_SETUP 536870912
- #endif
- #ifndef NRFX_I2S_CONFIG_RATIO
- #define NRFX_I2S_CONFIG_RATIO 5
- #endif
- #ifndef NRFX_I2S_CONFIG_IRQ_PRIORITY
- #define NRFX_I2S_CONFIG_IRQ_PRIORITY 7
- #endif
- #ifndef NRFX_I2S_CONFIG_LOG_ENABLED
- #define NRFX_I2S_CONFIG_LOG_ENABLED 0
- #endif
- #ifndef NRFX_I2S_CONFIG_LOG_LEVEL
- #define NRFX_I2S_CONFIG_LOG_LEVEL 3
- #endif
- #ifndef NRFX_I2S_CONFIG_INFO_COLOR
- #define NRFX_I2S_CONFIG_INFO_COLOR 0
- #endif
- #ifndef NRFX_I2S_CONFIG_DEBUG_COLOR
- #define NRFX_I2S_CONFIG_DEBUG_COLOR 0
- #endif
- #ifndef NRFX_NVMC_ENABLED
- #define NRFX_NVMC_ENABLED 1
- #endif
- #ifndef NRFX_PDM_ENABLED
- #define NRFX_PDM_ENABLED 1
- #endif
- #ifndef NRFX_PDM_CONFIG_MODE
- #define NRFX_PDM_CONFIG_MODE 1
- #endif
- #ifndef NRFX_PDM_CONFIG_EDGE
- #define NRFX_PDM_CONFIG_EDGE 0
- #endif
- #ifndef NRFX_PDM_CONFIG_CLOCK_FREQ
- #define NRFX_PDM_CONFIG_CLOCK_FREQ 138412032
- #endif
- #ifndef NRFX_PDM_CONFIG_IRQ_PRIORITY
- #define NRFX_PDM_CONFIG_IRQ_PRIORITY 7
- #endif
- #ifndef NRFX_PDM_CONFIG_LOG_ENABLED
- #define NRFX_PDM_CONFIG_LOG_ENABLED 0
- #endif
- #ifndef NRFX_PDM_CONFIG_LOG_LEVEL
- #define NRFX_PDM_CONFIG_LOG_LEVEL 3
- #endif
- #ifndef NRFX_PDM_CONFIG_INFO_COLOR
- #define NRFX_PDM_CONFIG_INFO_COLOR 0
- #endif
- #ifndef NRFX_PDM_CONFIG_DEBUG_COLOR
- #define NRFX_PDM_CONFIG_DEBUG_COLOR 0
- #endif
- #ifndef NRFX_POWER_ENABLED
- #define NRFX_POWER_ENABLED 1
- #endif
- #ifndef NRFX_POWER_CONFIG_IRQ_PRIORITY
- #define NRFX_POWER_CONFIG_IRQ_PRIORITY 7
- #endif
- #ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCEN
- #define NRFX_POWER_CONFIG_DEFAULT_DCDCEN 0
- #endif
- #ifndef NRFX_PRS_ENABLED
- #define NRFX_PRS_ENABLED 1
- #endif
- #ifndef NRFX_PRS_BOX_0_ENABLED
- #define NRFX_PRS_BOX_0_ENABLED 1
- #endif
- #ifndef NRFX_PRS_BOX_1_ENABLED
- #define NRFX_PRS_BOX_1_ENABLED 1
- #endif
- #ifndef NRFX_PRS_BOX_2_ENABLED
- #define NRFX_PRS_BOX_2_ENABLED 1
- #endif
- #ifndef NRFX_PRS_BOX_3_ENABLED
- #define NRFX_PRS_BOX_3_ENABLED 1
- #endif
- #ifndef NRFX_PRS_CONFIG_LOG_ENABLED
- #define NRFX_PRS_CONFIG_LOG_ENABLED 0
- #endif
- #ifndef NRFX_PRS_CONFIG_LOG_LEVEL
- #define NRFX_PRS_CONFIG_LOG_LEVEL 3
- #endif
- #ifndef NRFX_PRS_CONFIG_INFO_COLOR
- #define NRFX_PRS_CONFIG_INFO_COLOR 0
- #endif
- #ifndef NRFX_PRS_CONFIG_DEBUG_COLOR
- #define NRFX_PRS_CONFIG_DEBUG_COLOR 0
- #endif
- #ifndef NRFX_PWM_ENABLED
- #define NRFX_PWM_ENABLED 1
- #endif
- #ifndef NRFX_PWM0_ENABLED
- #define NRFX_PWM0_ENABLED 1
- #endif
- #ifndef NRFX_PWM1_ENABLED
- #define NRFX_PWM1_ENABLED 1
- #endif
- #ifndef NRFX_PWM2_ENABLED
- #define NRFX_PWM2_ENABLED 1
- #endif
- #ifndef NRFX_PWM3_ENABLED
- #define NRFX_PWM3_ENABLED 1
- #endif
- #ifndef NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN
- #define NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN 31
- #endif
- #ifndef NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN
- #define NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN 31
- #endif
- #ifndef NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN
- #define NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN 31
- #endif
- #ifndef NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN
- #define NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN 31
- #endif
- #ifndef NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK
- #define NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK 4
- #endif
- #ifndef NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE
- #define NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE 0
- #endif
- #ifndef NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE
- #define NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE 1000
- #endif
- #ifndef NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE
- #define NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE 0
- #endif
- #ifndef NRFX_PWM_DEFAULT_CONFIG_STEP_MODE
- #define NRFX_PWM_DEFAULT_CONFIG_STEP_MODE 0
- #endif
- #ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
- #define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 7
- #endif
- #ifndef NRFX_PWM_CONFIG_LOG_ENABLED
- #define NRFX_PWM_CONFIG_LOG_ENABLED 0
- #endif
- #ifndef NRFX_PWM_CONFIG_LOG_LEVEL
- #define NRFX_PWM_CONFIG_LOG_LEVEL 3
- #endif
- #ifndef NRFX_PWM_CONFIG_INFO_COLOR
- #define NRFX_PWM_CONFIG_INFO_COLOR 0
- #endif
- #ifndef NRFX_PWM_CONFIG_DEBUG_COLOR
- #define NRFX_PWM_CONFIG_DEBUG_COLOR 0
- #endif
- #ifndef NRFX_RTC_ENABLED
- #define NRFX_RTC_ENABLED 1
- #endif
- #ifndef NRFX_RTC0_ENABLED
- #define NRFX_RTC0_ENABLED 1
- #endif
- #ifndef NRFX_RTC1_ENABLED
- #define NRFX_RTC1_ENABLED 1
- #endif
- #ifndef NRFX_RTC_MAXIMUM_LATENCY_US
- #define NRFX_RTC_MAXIMUM_LATENCY_US 2000
- #endif
- #ifndef NRFX_RTC_DEFAULT_CONFIG_FREQUENCY
- #define NRFX_RTC_DEFAULT_CONFIG_FREQUENCY 32768
- #endif
- #ifndef NRFX_RTC_DEFAULT_CONFIG_RELIABLE
- #define NRFX_RTC_DEFAULT_CONFIG_RELIABLE 0
- #endif
- #ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
- #define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 7
- #endif
- #ifndef NRFX_RTC_CONFIG_LOG_ENABLED
- #define NRFX_RTC_CONFIG_LOG_ENABLED 0
- #endif
- #ifndef NRFX_RTC_CONFIG_LOG_LEVEL
- #define NRFX_RTC_CONFIG_LOG_LEVEL 3
- #endif
- #ifndef NRFX_RTC_CONFIG_INFO_COLOR
- #define NRFX_RTC_CONFIG_INFO_COLOR 0
- #endif
- #ifndef NRFX_RTC_CONFIG_DEBUG_COLOR
- #define NRFX_RTC_CONFIG_DEBUG_COLOR 0
- #endif
- #ifndef NRFX_SAADC_ENABLED
- #define NRFX_SAADC_ENABLED 1
- #endif
- #ifndef NRFX_SAADC_CONFIG_RESOLUTION
- #define NRFX_SAADC_CONFIG_RESOLUTION 1
- #endif
- #ifndef NRFX_SAADC_CONFIG_OVERSAMPLE
- #define NRFX_SAADC_CONFIG_OVERSAMPLE 0
- #endif
- #ifndef NRFX_SAADC_CONFIG_LP_MODE
- #define NRFX_SAADC_CONFIG_LP_MODE 0
- #endif
- #ifndef NRFX_SAADC_CONFIG_IRQ_PRIORITY
- #define NRFX_SAADC_CONFIG_IRQ_PRIORITY 7
- #endif
- #ifndef NRFX_SAADC_CONFIG_LOG_ENABLED
- #define NRFX_SAADC_CONFIG_LOG_ENABLED 0
- #endif
- #ifndef NRFX_SAADC_CONFIG_LOG_LEVEL
- #define NRFX_SAADC_CONFIG_LOG_LEVEL 3
- #endif
- #ifndef NRFX_SAADC_CONFIG_INFO_COLOR
- #define NRFX_SAADC_CONFIG_INFO_COLOR 0
- #endif
- #ifndef NRFX_SAADC_CONFIG_DEBUG_COLOR
- #define NRFX_SAADC_CONFIG_DEBUG_COLOR 0
- #endif
- #ifndef NRFX_SPIM_ENABLED
- #define NRFX_SPIM_ENABLED 1
- #endif
- #ifndef NRFX_SPIM0_ENABLED
- #define NRFX_SPIM0_ENABLED 1
- #endif
- #ifndef NRFX_SPIM1_ENABLED
- #define NRFX_SPIM1_ENABLED 1
- #endif
- #ifndef NRFX_SPIM2_ENABLED
- #define NRFX_SPIM2_ENABLED 1
- #endif
- #ifndef NRFX_SPIM3_ENABLED
- #define NRFX_SPIM3_ENABLED 1
- #endif
- #ifndef NRFX_SPIM_MISO_PULL_CFG
- #define NRFX_SPIM_MISO_PULL_CFG 1
- #endif
- #ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
- #define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 7
- #endif
- #ifndef NRFX_SPIM_CONFIG_LOG_ENABLED
- #define NRFX_SPIM_CONFIG_LOG_ENABLED 0
- #endif
- #ifndef NRFX_SPIM_CONFIG_LOG_LEVEL
- #define NRFX_SPIM_CONFIG_LOG_LEVEL 3
- #endif
- #ifndef NRFX_SPIM_CONFIG_INFO_COLOR
- #define NRFX_SPIM_CONFIG_INFO_COLOR 0
- #endif
- #ifndef NRFX_SPIM_CONFIG_DEBUG_COLOR
- #define NRFX_SPIM_CONFIG_DEBUG_COLOR 0
- #endif
- #ifndef NRFX_SPIS_ENABLED
- #define NRFX_SPIS_ENABLED 1
- #endif
- #ifndef NRFX_SPIS0_ENABLED
- #define NRFX_SPIS0_ENABLED 1
- #endif
- #ifndef NRFX_SPIS1_ENABLED
- #define NRFX_SPIS1_ENABLED 1
- #endif
- #ifndef NRFX_SPIS2_ENABLED
- #define NRFX_SPIS2_ENABLED 1
- #endif
- #ifndef NRFX_SPIS3_ENABLED
- #define NRFX_SPIS3_ENABLED 1
- #endif
- #ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
- #define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 7
- #endif
- #ifndef NRFX_SPIS_DEFAULT_DEF
- #define NRFX_SPIS_DEFAULT_DEF 255
- #endif
- #ifndef NRFX_SPIS_DEFAULT_ORC
- #define NRFX_SPIS_DEFAULT_ORC 255
- #endif
- #ifndef NRFX_SPIS_CONFIG_LOG_ENABLED
- #define NRFX_SPIS_CONFIG_LOG_ENABLED 0
- #endif
- #ifndef NRFX_SPIS_CONFIG_LOG_LEVEL
- #define NRFX_SPIS_CONFIG_LOG_LEVEL 3
- #endif
- #ifndef NRFX_SPIS_CONFIG_INFO_COLOR
- #define NRFX_SPIS_CONFIG_INFO_COLOR 0
- #endif
- #ifndef NRFX_SPIS_CONFIG_DEBUG_COLOR
- #define NRFX_SPIS_CONFIG_DEBUG_COLOR 0
- #endif
- #ifndef NRFX_SWI_ENABLED
- #define NRFX_SWI_ENABLED 1
- #endif
- #ifndef NRFX_EGU_ENABLED
- #define NRFX_EGU_ENABLED 1
- #endif
- #ifndef NRFX_SWI0_DISABLED
- #define NRFX_SWI0_DISABLED 0
- #endif
- #ifndef NRFX_SWI1_DISABLED
- #define NRFX_SWI1_DISABLED 0
- #endif
- #ifndef NRFX_SWI2_DISABLED
- #define NRFX_SWI2_DISABLED 0
- #endif
- #ifndef NRFX_SWI3_DISABLED
- #define NRFX_SWI3_DISABLED 0
- #endif
- #ifndef NRFX_SWI4_DISABLED
- #define NRFX_SWI4_DISABLED 0
- #endif
- #ifndef NRFX_SWI5_DISABLED
- #define NRFX_SWI5_DISABLED 0
- #endif
- #ifndef NRFX_SWI_CONFIG_LOG_ENABLED
- #define NRFX_SWI_CONFIG_LOG_ENABLED 0
- #endif
- #ifndef NRFX_SWI_CONFIG_LOG_LEVEL
- #define NRFX_SWI_CONFIG_LOG_LEVEL 3
- #endif
- #ifndef NRFX_SWI_CONFIG_INFO_COLOR
- #define NRFX_SWI_CONFIG_INFO_COLOR 0
- #endif
- #ifndef NRFX_SWI_CONFIG_DEBUG_COLOR
- #define NRFX_SWI_CONFIG_DEBUG_COLOR 0
- #endif
- #ifndef NRFX_SYSTICK_ENABLED
- #define NRFX_SYSTICK_ENABLED 1
- #endif
- #ifndef NRFX_TIMER_ENABLED
- #define NRFX_TIMER_ENABLED 1
- #endif
- #ifndef NRFX_TIMER0_ENABLED
- #define NRFX_TIMER0_ENABLED 1
- #endif
- #ifndef NRFX_TIMER1_ENABLED
- #define NRFX_TIMER1_ENABLED 1
- #endif
- #ifndef NRFX_TIMER2_ENABLED
- #define NRFX_TIMER2_ENABLED 1
- #endif
- #ifndef NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY
- #define NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY 0
- #endif
- #ifndef NRFX_TIMER_DEFAULT_CONFIG_MODE
- #define NRFX_TIMER_DEFAULT_CONFIG_MODE 0
- #endif
- #ifndef NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH
- #define NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH 0
- #endif
- #ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
- #define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 7
- #endif
- #ifndef NRFX_TIMER_CONFIG_LOG_ENABLED
- #define NRFX_TIMER_CONFIG_LOG_ENABLED 0
- #endif
- #ifndef NRFX_TIMER_CONFIG_LOG_LEVEL
- #define NRFX_TIMER_CONFIG_LOG_LEVEL 3
- #endif
- #ifndef NRFX_TIMER_CONFIG_INFO_COLOR
- #define NRFX_TIMER_CONFIG_INFO_COLOR 0
- #endif
- #ifndef NRFX_TIMER_CONFIG_DEBUG_COLOR
- #define NRFX_TIMER_CONFIG_DEBUG_COLOR 0
- #endif
- #ifndef NRFX_TWIM_ENABLED
- #define NRFX_TWIM_ENABLED 1
- #endif
- #ifndef NRFX_TWIM0_ENABLED
- #define NRFX_TWIM0_ENABLED 1
- #endif
- #ifndef NRFX_TWIM1_ENABLED
- #define NRFX_TWIM1_ENABLED 1
- #endif
- #ifndef NRFX_TWIM2_ENABLED
- #define NRFX_TWIM2_ENABLED 1
- #endif
- #ifndef NRFX_TWIM3_ENABLED
- #define NRFX_TWIM3_ENABLED 1
- #endif
- #ifndef NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY
- #define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY 26738688
- #endif
- #ifndef NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT
- #define NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
- #endif
- #ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
- #define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 7
- #endif
- #ifndef NRFX_TWIM_CONFIG_LOG_ENABLED
- #define NRFX_TWIM_CONFIG_LOG_ENABLED 0
- #endif
- #ifndef NRFX_TWIM_CONFIG_LOG_LEVEL
- #define NRFX_TWIM_CONFIG_LOG_LEVEL 3
- #endif
- #ifndef NRFX_TWIM_CONFIG_INFO_COLOR
- #define NRFX_TWIM_CONFIG_INFO_COLOR 0
- #endif
- #ifndef NRFX_TWIM_CONFIG_DEBUG_COLOR
- #define NRFX_TWIM_CONFIG_DEBUG_COLOR 0
- #endif
- #ifndef NRFX_TWIS_ENABLED
- #define NRFX_TWIS_ENABLED 1
- #endif
- #ifndef NRFX_TWIS0_ENABLED
- #define NRFX_TWIS0_ENABLED 1
- #endif
- #ifndef NRFX_TWIS1_ENABLED
- #define NRFX_TWIS1_ENABLED 1
- #endif
- #ifndef NRFX_TWIS2_ENABLED
- #define NRFX_TWIS2_ENABLED 1
- #endif
- #ifndef NRFX_TWIS3_ENABLED
- #define NRFX_TWIS3_ENABLED 1
- #endif
- #ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY
- #define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
- #endif
- #ifndef NRFX_TWIS_NO_SYNC_MODE
- #define NRFX_TWIS_NO_SYNC_MODE 0
- #endif
- #ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR0
- #define NRFX_TWIS_DEFAULT_CONFIG_ADDR0 0
- #endif
- #ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR1
- #define NRFX_TWIS_DEFAULT_CONFIG_ADDR1 0
- #endif
- #ifndef NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL
- #define NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL 0
- #endif
- #ifndef NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL
- #define NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL 0
- #endif
- #ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
- #define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 7
- #endif
- #ifndef NRFX_TWIS_CONFIG_LOG_ENABLED
- #define NRFX_TWIS_CONFIG_LOG_ENABLED 0
- #endif
- #ifndef NRFX_TWIS_CONFIG_LOG_LEVEL
- #define NRFX_TWIS_CONFIG_LOG_LEVEL 3
- #endif
- #ifndef NRFX_TWIS_CONFIG_INFO_COLOR
- #define NRFX_TWIS_CONFIG_INFO_COLOR 0
- #endif
- #ifndef NRFX_TWIS_CONFIG_DEBUG_COLOR
- #define NRFX_TWIS_CONFIG_DEBUG_COLOR 0
- #endif
- #ifndef NRFX_UARTE_ENABLED
- #define NRFX_UARTE_ENABLED 1
- #endif
- #ifndef NRFX_UARTE0_ENABLED
- #define NRFX_UARTE0_ENABLED 1
- #endif
- #ifndef NRFX_UARTE1_ENABLED
- #define NRFX_UARTE1_ENABLED 1
- #endif
- #ifndef NRFX_UARTE2_ENABLED
- #define NRFX_UARTE2_ENABLED 1
- #endif
- #ifndef NRFX_UARTE3_ENABLED
- #define NRFX_UARTE3_ENABLED 1
- #endif
- #ifndef NRFX_UARTE_DEFAULT_CONFIG_HWFC
- #define NRFX_UARTE_DEFAULT_CONFIG_HWFC 0
- #endif
- #ifndef NRFX_UARTE_DEFAULT_CONFIG_PARITY
- #define NRFX_UARTE_DEFAULT_CONFIG_PARITY 0
- #endif
- #ifndef NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE
- #define NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE 30801920
- #endif
- #ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
- #define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 7
- #endif
- #ifndef NRFX_UARTE_CONFIG_LOG_ENABLED
- #define NRFX_UARTE_CONFIG_LOG_ENABLED 0
- #endif
- #ifndef NRFX_UARTE_CONFIG_LOG_LEVEL
- #define NRFX_UARTE_CONFIG_LOG_LEVEL 3
- #endif
- #ifndef NRFX_UARTE_CONFIG_INFO_COLOR
- #define NRFX_UARTE_CONFIG_INFO_COLOR 0
- #endif
- #ifndef NRFX_UARTE_CONFIG_DEBUG_COLOR
- #define NRFX_UARTE_CONFIG_DEBUG_COLOR 0
- #endif
- #ifndef NRFX_WDT_ENABLED
- #define NRFX_WDT_ENABLED 1
- #endif
- #ifndef NRFX_WDT_CONFIG_BEHAVIOUR
- #define NRFX_WDT_CONFIG_BEHAVIOUR 1
- #endif
- #ifndef NRFX_WDT_CONFIG_RELOAD_VALUE
- #define NRFX_WDT_CONFIG_RELOAD_VALUE 2000
- #endif
- #ifndef NRFX_WDT_CONFIG_NO_IRQ
- #define NRFX_WDT_CONFIG_NO_IRQ 0
- #endif
- #ifndef NRFX_WDT_CONFIG_IRQ_PRIORITY
- #define NRFX_WDT_CONFIG_IRQ_PRIORITY 7
- #endif
- #ifndef NRFX_WDT_CONFIG_LOG_ENABLED
- #define NRFX_WDT_CONFIG_LOG_ENABLED 0
- #endif
- #ifndef NRFX_WDT_CONFIG_LOG_LEVEL
- #define NRFX_WDT_CONFIG_LOG_LEVEL 3
- #endif
- #ifndef NRFX_WDT_CONFIG_INFO_COLOR
- #define NRFX_WDT_CONFIG_INFO_COLOR 0
- #endif
- #ifndef NRFX_WDT_CONFIG_DEBUG_COLOR
- #define NRFX_WDT_CONFIG_DEBUG_COLOR 0
- #endif
- #endif
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