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- #ifndef NRF_SPU_H__
- #define NRF_SPU_H__
- #include <nrfx.h>
- #ifdef __cplusplus
- extern "C" {
- #endif
- typedef enum
- {
- NRF_SPU_EVENT_RAMACCERR = offsetof(NRF_SPU_Type, EVENTS_RAMACCERR),
- NRF_SPU_EVENT_FLASHACCERR = offsetof(NRF_SPU_Type, EVENTS_FLASHACCERR),
- NRF_SPU_EVENT_PERIPHACCERR = offsetof(NRF_SPU_Type, EVENTS_PERIPHACCERR)
- } nrf_spu_event_t;
- typedef enum
- {
- NRF_SPU_INT_RAMACCERR_MASK = SPU_INTENSET_RAMACCERR_Msk,
- NRF_SPU_INT_FLASHACCERR_MASK = SPU_INTENSET_FLASHACCERR_Msk,
- NRF_SPU_INT_PERIPHACCERR_MASK = SPU_INTENSET_PERIPHACCERR_Msk
- } nrf_spu_int_mask_t;
- typedef enum
- {
- NRF_SPU_NSC_SIZE_DISABLED = 0,
- NRF_SPU_NSC_SIZE_32B = 1,
- NRF_SPU_NSC_SIZE_64B = 2,
- NRF_SPU_NSC_SIZE_128B = 3,
- NRF_SPU_NSC_SIZE_256B = 4,
- NRF_SPU_NSC_SIZE_512B = 5,
- NRF_SPU_NSC_SIZE_1024B = 6,
- NRF_SPU_NSC_SIZE_2048B = 7,
- NRF_SPU_NSC_SIZE_4096B = 8
- } nrf_spu_nsc_size_t;
- typedef enum
- {
- NRF_SPU_MEM_PERM_EXECUTE = SPU_FLASHREGION_PERM_EXECUTE_Msk,
- NRF_SPU_MEM_PERM_WRITE = SPU_FLASHREGION_PERM_WRITE_Msk,
- NRF_SPU_MEM_PERM_READ = SPU_FLASHREGION_PERM_READ_Msk
- } nrf_spu_mem_perm_t;
- __STATIC_INLINE void nrf_spu_event_clear(NRF_SPU_Type * p_reg,
- nrf_spu_event_t event);
- __STATIC_INLINE bool nrf_spu_event_check(NRF_SPU_Type const * p_reg,
- nrf_spu_event_t event);
- __STATIC_INLINE void nrf_spu_int_enable(NRF_SPU_Type * p_reg,
- uint32_t mask);
- __STATIC_INLINE void nrf_spu_int_disable(NRF_SPU_Type * p_reg,
- uint32_t mask);
- __STATIC_INLINE bool nrf_spu_int_enable_check(NRF_SPU_Type const * p_reg,
- uint32_t spu_int);
- __STATIC_INLINE void nrf_spu_publish_set(NRF_SPU_Type * p_reg,
- nrf_spu_event_t event,
- uint32_t channel);
- __STATIC_INLINE void nrf_spu_publish_clear(NRF_SPU_Type * p_reg,
- nrf_spu_event_t event);
- __STATIC_INLINE bool nrf_spu_tz_is_available(NRF_SPU_Type const * p_reg);
- __STATIC_INLINE void nrf_spu_dppi_config_set(NRF_SPU_Type * p_reg,
- uint8_t dppi_id,
- uint32_t channels_mask,
- bool lock_conf);
- __STATIC_INLINE void nrf_spu_gpio_config_set(NRF_SPU_Type * p_reg,
- uint8_t gpio_port,
- uint32_t gpio_mask,
- bool lock_conf);
- __STATIC_INLINE void nrf_spu_flashnsc_set(NRF_SPU_Type * p_reg,
- uint8_t flash_nsc_id,
- nrf_spu_nsc_size_t flash_nsc_size,
- uint8_t region_number,
- bool lock_conf);
- __STATIC_INLINE void nrf_spu_ramnsc_set(NRF_SPU_Type * p_reg,
- uint8_t ram_nsc_id,
- nrf_spu_nsc_size_t ram_nsc_size,
- uint8_t region_number,
- bool lock_conf);
- __STATIC_INLINE void nrf_spu_flashregion_set(NRF_SPU_Type * p_reg,
- uint8_t region_id,
- bool secure_attr,
- uint32_t permissions,
- bool lock_conf);
- __STATIC_INLINE void nrf_spu_ramregion_set(NRF_SPU_Type * p_reg,
- uint8_t region_id,
- bool secure_attr,
- uint32_t permissions,
- bool lock_conf);
- __STATIC_INLINE void nrf_spu_peripheral_set(NRF_SPU_Type * p_reg,
- uint32_t peripheral_id,
- bool secure_attr,
- bool secure_dma,
- bool lock_conf);
- #ifndef SUPPRESS_INLINE_IMPLEMENTATION
- __STATIC_INLINE void nrf_spu_event_clear(NRF_SPU_Type * p_reg,
- nrf_spu_event_t event)
- {
- *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
- }
- __STATIC_INLINE bool nrf_spu_event_check(NRF_SPU_Type const * p_reg,
- nrf_spu_event_t event)
- {
- return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
- }
- __STATIC_INLINE void nrf_spu_int_enable(NRF_SPU_Type * p_reg,
- uint32_t mask)
- {
- p_reg->INTENSET = mask;
- }
- __STATIC_INLINE void nrf_spu_int_disable(NRF_SPU_Type * p_reg,
- uint32_t mask)
- {
- p_reg->INTENCLR = mask;
- }
- __STATIC_INLINE bool nrf_spu_int_enable_check(NRF_SPU_Type const * p_reg,
- uint32_t spu_int)
- {
- return (bool)(p_reg->INTENSET & spu_int);
- }
- __STATIC_INLINE void nrf_spu_publish_set(NRF_SPU_Type * p_reg,
- nrf_spu_event_t event,
- uint32_t channel)
- {
- *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
- (channel | (SPU_PUBLISH_RAMACCERR_EN_Msk));
- }
- __STATIC_INLINE void nrf_spu_publish_clear(NRF_SPU_Type * p_reg,
- nrf_spu_event_t event)
- {
- *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
- }
- __STATIC_INLINE bool nrf_spu_tz_is_available(NRF_SPU_Type const * p_reg)
- {
- return (p_reg->CAP & SPU_CAP_TZM_Msk ? true : false);
- }
- __STATIC_INLINE void nrf_spu_dppi_config_set(NRF_SPU_Type * p_reg,
- uint8_t dppi_id,
- uint32_t channels_mask,
- bool lock_conf)
- {
- NRFX_ASSERT(!(p_reg->DPPI[dppi_id].LOCK & SPU_DPPI_LOCK_LOCK_Msk));
- p_reg->DPPI[dppi_id].PERM = channels_mask;
- if (lock_conf)
- {
- p_reg->DPPI[dppi_id].LOCK = (SPU_DPPI_LOCK_LOCK_Msk);
- }
- }
- __STATIC_INLINE void nrf_spu_gpio_config_set(NRF_SPU_Type * p_reg,
- uint8_t gpio_port,
- uint32_t gpio_mask,
- bool lock_conf)
- {
- NRFX_ASSERT(!(p_reg->GPIOPORT[gpio_port].LOCK & SPU_GPIOPORT_LOCK_LOCK_Msk));
- p_reg->GPIOPORT[gpio_port].PERM = gpio_mask;
- if (lock_conf)
- {
- p_reg->GPIOPORT[gpio_port].LOCK = (SPU_GPIOPORT_LOCK_LOCK_Msk);
- }
- }
- __STATIC_INLINE void nrf_spu_flashnsc_set(NRF_SPU_Type * p_reg,
- uint8_t flash_nsc_id,
- nrf_spu_nsc_size_t flash_nsc_size,
- uint8_t region_number,
- bool lock_conf)
- {
- NRFX_ASSERT(!(p_reg->FLASHNSC[flash_nsc_id].REGION & SPU_FLASHNSC_REGION_LOCK_Msk));
- NRFX_ASSERT(!(p_reg->FLASHNSC[flash_nsc_id].SIZE & SPU_FLASHNSC_SIZE_LOCK_Msk));
- p_reg->FLASHNSC[flash_nsc_id].REGION = (uint32_t)region_number |
- (lock_conf ? SPU_FLASHNSC_REGION_LOCK_Msk : 0);
- p_reg->FLASHNSC[flash_nsc_id].SIZE = (uint32_t)flash_nsc_size |
- (lock_conf ? SPU_FLASHNSC_SIZE_LOCK_Msk : 0);
- }
- __STATIC_INLINE void nrf_spu_ramnsc_set(NRF_SPU_Type * p_reg,
- uint8_t ram_nsc_id,
- nrf_spu_nsc_size_t ram_nsc_size,
- uint8_t region_number,
- bool lock_conf)
- {
- NRFX_ASSERT(!(p_reg->RAMNSC[ram_nsc_id].REGION & SPU_RAMNSC_REGION_LOCK_Msk));
- NRFX_ASSERT(!(p_reg->RAMNSC[ram_nsc_id].SIZE & SPU_RAMNSC_SIZE_LOCK_Msk));
- p_reg->RAMNSC[ram_nsc_id].REGION = (uint32_t)region_number |
- (lock_conf ? SPU_RAMNSC_REGION_LOCK_Msk : 0);
- p_reg->RAMNSC[ram_nsc_id].SIZE = (uint32_t)ram_nsc_size |
- (lock_conf ? SPU_RAMNSC_SIZE_LOCK_Msk : 0);
- }
- __STATIC_INLINE void nrf_spu_flashregion_set(NRF_SPU_Type * p_reg,
- uint8_t region_id,
- bool secure_attr,
- uint32_t permissions,
- bool lock_conf)
- {
- NRFX_ASSERT(!(p_reg->FLASHREGION[region_id].PERM & SPU_FLASHREGION_PERM_LOCK_Msk));
- p_reg->FLASHREGION[region_id].PERM = permissions |
- (secure_attr ? SPU_FLASHREGION_PERM_SECATTR_Msk : 0) |
- (lock_conf ? SPU_FLASHREGION_PERM_LOCK_Msk : 0);
- }
- __STATIC_INLINE void nrf_spu_ramregion_set(NRF_SPU_Type * p_reg,
- uint8_t region_id,
- bool secure_attr,
- uint32_t permissions,
- bool lock_conf)
- {
- NRFX_ASSERT(!(p_reg->RAMREGION[region_id].PERM & SPU_RAMREGION_PERM_LOCK_Msk));
- p_reg->RAMREGION[region_id].PERM = permissions |
- (secure_attr ? SPU_RAMREGION_PERM_SECATTR_Msk : 0) |
- (lock_conf ? SPU_RAMREGION_PERM_LOCK_Msk : 0);
- }
- __STATIC_INLINE void nrf_spu_peripheral_set(NRF_SPU_Type * p_reg,
- uint32_t peripheral_id,
- bool secure_attr,
- bool secure_dma,
- bool lock_conf)
- {
- NRFX_ASSERT(p_reg->PERIPHID[peripheral_id].PERM & SPU_PERIPHID_PERM_PRESENT_Msk);
- NRFX_ASSERT(!(p_reg->PERIPHID[peripheral_id].PERM & SPU_PERIPHID_PERM_LOCK_Msk));
- p_reg->PERIPHID[peripheral_id].PERM =
- (secure_attr ? SPU_PERIPHID_PERM_SECATTR_Msk : 0) |
- (secure_dma ? SPU_PERIPHID_PERM_DMASEC_Msk : 0) |
- (lock_conf ? SPU_PERIPHID_PERM_LOCK_Msk : 0);
- }
- #endif
- #ifdef __cplusplus
- }
- #endif
- #endif
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