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- #ifndef NRF_PWM_H__
- #define NRF_PWM_H__
- #include <nrfx.h>
- #ifdef __cplusplus
- extern "C" {
- #endif
- #define NRF_PWM_PIN_NOT_CONNECTED 0xFFFFFFFF
- #define NRF_PWM_CHANNEL_COUNT 4
- #define NRF_PWM_VALUES_LENGTH(array) (sizeof(array) / sizeof(uint16_t))
- typedef enum
- {
- NRF_PWM_TASK_STOP = offsetof(NRF_PWM_Type, TASKS_STOP),
- NRF_PWM_TASK_SEQSTART0 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[0]),
- NRF_PWM_TASK_SEQSTART1 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[1]),
- NRF_PWM_TASK_NEXTSTEP = offsetof(NRF_PWM_Type, TASKS_NEXTSTEP)
- } nrf_pwm_task_t;
- typedef enum
- {
- NRF_PWM_EVENT_STOPPED = offsetof(NRF_PWM_Type, EVENTS_STOPPED),
- NRF_PWM_EVENT_SEQSTARTED0 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[0]),
- NRF_PWM_EVENT_SEQSTARTED1 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[1]),
- NRF_PWM_EVENT_SEQEND0 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[0]),
- NRF_PWM_EVENT_SEQEND1 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[1]),
- NRF_PWM_EVENT_PWMPERIODEND = offsetof(NRF_PWM_Type, EVENTS_PWMPERIODEND),
- NRF_PWM_EVENT_LOOPSDONE = offsetof(NRF_PWM_Type, EVENTS_LOOPSDONE)
- } nrf_pwm_event_t;
- typedef enum
- {
- NRF_PWM_INT_STOPPED_MASK = PWM_INTENSET_STOPPED_Msk,
- NRF_PWM_INT_SEQSTARTED0_MASK = PWM_INTENSET_SEQSTARTED0_Msk,
- NRF_PWM_INT_SEQSTARTED1_MASK = PWM_INTENSET_SEQSTARTED1_Msk,
- NRF_PWM_INT_SEQEND0_MASK = PWM_INTENSET_SEQEND0_Msk,
- NRF_PWM_INT_SEQEND1_MASK = PWM_INTENSET_SEQEND1_Msk,
- NRF_PWM_INT_PWMPERIODEND_MASK = PWM_INTENSET_PWMPERIODEND_Msk,
- NRF_PWM_INT_LOOPSDONE_MASK = PWM_INTENSET_LOOPSDONE_Msk
- } nrf_pwm_int_mask_t;
- typedef enum
- {
- NRF_PWM_SHORT_SEQEND0_STOP_MASK = PWM_SHORTS_SEQEND0_STOP_Msk,
- NRF_PWM_SHORT_SEQEND1_STOP_MASK = PWM_SHORTS_SEQEND1_STOP_Msk,
- NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk,
- NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk,
- NRF_PWM_SHORT_LOOPSDONE_STOP_MASK = PWM_SHORTS_LOOPSDONE_STOP_Msk
- } nrf_pwm_short_mask_t;
- typedef enum
- {
- NRF_PWM_MODE_UP = PWM_MODE_UPDOWN_Up,
- NRF_PWM_MODE_UP_AND_DOWN = PWM_MODE_UPDOWN_UpAndDown,
- } nrf_pwm_mode_t;
- typedef enum
- {
- NRF_PWM_CLK_16MHz = PWM_PRESCALER_PRESCALER_DIV_1,
- NRF_PWM_CLK_8MHz = PWM_PRESCALER_PRESCALER_DIV_2,
- NRF_PWM_CLK_4MHz = PWM_PRESCALER_PRESCALER_DIV_4,
- NRF_PWM_CLK_2MHz = PWM_PRESCALER_PRESCALER_DIV_8,
- NRF_PWM_CLK_1MHz = PWM_PRESCALER_PRESCALER_DIV_16,
- NRF_PWM_CLK_500kHz = PWM_PRESCALER_PRESCALER_DIV_32,
- NRF_PWM_CLK_250kHz = PWM_PRESCALER_PRESCALER_DIV_64,
- NRF_PWM_CLK_125kHz = PWM_PRESCALER_PRESCALER_DIV_128
- } nrf_pwm_clk_t;
- typedef enum
- {
- NRF_PWM_LOAD_COMMON = PWM_DECODER_LOAD_Common,
- NRF_PWM_LOAD_GROUPED = PWM_DECODER_LOAD_Grouped,
- NRF_PWM_LOAD_INDIVIDUAL = PWM_DECODER_LOAD_Individual,
- NRF_PWM_LOAD_WAVE_FORM = PWM_DECODER_LOAD_WaveForm
- } nrf_pwm_dec_load_t;
- typedef enum
- {
- NRF_PWM_STEP_AUTO = PWM_DECODER_MODE_RefreshCount,
- NRF_PWM_STEP_TRIGGERED = PWM_DECODER_MODE_NextStep
- } nrf_pwm_dec_step_t;
- typedef uint16_t nrf_pwm_values_common_t;
- typedef struct {
- uint16_t group_0;
- uint16_t group_1;
- } nrf_pwm_values_grouped_t;
- typedef struct
- {
- uint16_t channel_0;
- uint16_t channel_1;
- uint16_t channel_2;
- uint16_t channel_3;
- } nrf_pwm_values_individual_t;
- typedef struct {
- uint16_t channel_0;
- uint16_t channel_1;
- uint16_t channel_2;
- uint16_t counter_top;
- } nrf_pwm_values_wave_form_t;
- typedef union {
- nrf_pwm_values_common_t const * p_common;
- nrf_pwm_values_grouped_t const * p_grouped;
- nrf_pwm_values_individual_t const * p_individual;
- nrf_pwm_values_wave_form_t const * p_wave_form;
- uint16_t const * p_raw;
- } nrf_pwm_values_t;
- typedef struct
- {
- nrf_pwm_values_t values;
-
- uint16_t length;
- uint32_t repeats;
- uint32_t end_delay;
- } nrf_pwm_sequence_t;
- __STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,
- nrf_pwm_task_t task);
- __STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,
- nrf_pwm_task_t task);
- __STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg,
- nrf_pwm_event_t event);
- __STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg,
- nrf_pwm_event_t event);
- __STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,
- nrf_pwm_event_t event);
- __STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,
- uint32_t mask);
- __STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,
- uint32_t mask);
- __STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,
- uint32_t mask);
- __STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg,
- uint32_t mask);
- __STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg,
- uint32_t mask);
- __STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg,
- uint32_t mask);
- __STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg,
- nrf_pwm_int_mask_t pwm_int);
- #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
- __STATIC_INLINE void nrf_pwm_subscribe_set(NRF_PWM_Type * p_reg,
- nrf_pwm_task_t task,
- uint8_t channel);
- __STATIC_INLINE void nrf_pwm_subscribe_clear(NRF_PWM_Type * p_reg,
- nrf_pwm_task_t task);
- __STATIC_INLINE void nrf_pwm_publish_set(NRF_PWM_Type * p_reg,
- nrf_pwm_event_t event,
- uint8_t channel);
- __STATIC_INLINE void nrf_pwm_publish_clear(NRF_PWM_Type * p_reg,
- nrf_pwm_event_t event);
- #endif
- __STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg);
- __STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg);
- __STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg,
- uint32_t out_pins[NRF_PWM_CHANNEL_COUNT]);
- __STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg,
- nrf_pwm_clk_t base_clock,
- nrf_pwm_mode_t mode,
- uint16_t top_value);
- __STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,
- uint8_t seq_id,
- nrf_pwm_sequence_t const * p_seq);
- __STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,
- uint8_t seq_id,
- uint16_t const * p_values);
- __STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,
- uint8_t seq_id,
- uint16_t length);
- __STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,
- uint8_t seq_id,
- uint32_t refresh);
- __STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,
- uint8_t seq_id,
- uint32_t end_delay);
- __STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,
- nrf_pwm_dec_load_t dec_load,
- nrf_pwm_dec_step_t dec_step);
- __STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg,
- uint16_t loop_count);
- #ifndef SUPPRESS_INLINE_IMPLEMENTATION
- __STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,
- nrf_pwm_task_t task)
- {
- *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
- }
- __STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,
- nrf_pwm_task_t task)
- {
- return ((uint32_t)p_reg + (uint32_t)task);
- }
- __STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg,
- nrf_pwm_event_t event)
- {
- *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
- #if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
- #endif
- }
- __STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg,
- nrf_pwm_event_t event)
- {
- return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
- }
- __STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,
- nrf_pwm_event_t event)
- {
- return ((uint32_t)p_reg + (uint32_t)event);
- }
- __STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,
- uint32_t mask)
- {
- p_reg->SHORTS |= mask;
- }
- __STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,
- uint32_t mask)
- {
- p_reg->SHORTS &= ~(mask);
- }
- __STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,
- uint32_t mask)
- {
- p_reg->SHORTS = mask;
- }
- __STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg,
- uint32_t mask)
- {
- p_reg->INTENSET = mask;
- }
- __STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg,
- uint32_t mask)
- {
- p_reg->INTENCLR = mask;
- }
- __STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg,
- uint32_t mask)
- {
- p_reg->INTEN = mask;
- }
- __STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg,
- nrf_pwm_int_mask_t pwm_int)
- {
- return (bool)(p_reg->INTENSET & pwm_int);
- }
- #if defined(DPPI_PRESENT)
- __STATIC_INLINE void nrf_pwm_subscribe_set(NRF_PWM_Type * p_reg,
- nrf_pwm_task_t task,
- uint8_t channel)
- {
- *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
- ((uint32_t)channel | PWM_SUBSCRIBE_STOP_EN_Msk);
- }
- __STATIC_INLINE void nrf_pwm_subscribe_clear(NRF_PWM_Type * p_reg,
- nrf_pwm_task_t task)
- {
- *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
- }
- __STATIC_INLINE void nrf_pwm_publish_set(NRF_PWM_Type * p_reg,
- nrf_pwm_event_t event,
- uint8_t channel)
- {
- *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
- ((uint32_t)channel | PWM_PUBLISH_STOPPED_EN_Msk);
- }
- __STATIC_INLINE void nrf_pwm_publish_clear(NRF_PWM_Type * p_reg,
- nrf_pwm_event_t event)
- {
- *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
- }
- #endif
- __STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg)
- {
- p_reg->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);
- }
- __STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg)
- {
- p_reg->ENABLE = (PWM_ENABLE_ENABLE_Disabled << PWM_ENABLE_ENABLE_Pos);
- }
- __STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg,
- uint32_t out_pins[NRF_PWM_CHANNEL_COUNT])
- {
- uint8_t i;
- for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i)
- {
- p_reg->PSEL.OUT[i] = out_pins[i];
- }
- }
- __STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg,
- nrf_pwm_clk_t base_clock,
- nrf_pwm_mode_t mode,
- uint16_t top_value)
- {
- NRFX_ASSERT(top_value <= PWM_COUNTERTOP_COUNTERTOP_Msk);
- p_reg->PRESCALER = base_clock;
- p_reg->MODE = mode;
- p_reg->COUNTERTOP = top_value;
- }
- __STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,
- uint8_t seq_id,
- nrf_pwm_sequence_t const * p_seq)
- {
- NRFX_ASSERT(p_seq != NULL);
- nrf_pwm_seq_ptr_set( p_reg, seq_id, p_seq->values.p_raw);
- nrf_pwm_seq_cnt_set( p_reg, seq_id, p_seq->length);
- nrf_pwm_seq_refresh_set( p_reg, seq_id, p_seq->repeats);
- nrf_pwm_seq_end_delay_set(p_reg, seq_id, p_seq->end_delay);
- }
- __STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,
- uint8_t seq_id,
- uint16_t const * p_values)
- {
- NRFX_ASSERT(seq_id <= 1);
- NRFX_ASSERT(p_values != NULL);
- p_reg->SEQ[seq_id].PTR = (uint32_t)p_values;
- }
- __STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,
- uint8_t seq_id,
- uint16_t length)
- {
- NRFX_ASSERT(seq_id <= 1);
- NRFX_ASSERT(length != 0);
- NRFX_ASSERT(length <= PWM_SEQ_CNT_CNT_Msk);
- p_reg->SEQ[seq_id].CNT = length;
- }
- __STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,
- uint8_t seq_id,
- uint32_t refresh)
- {
- NRFX_ASSERT(seq_id <= 1);
- NRFX_ASSERT(refresh <= PWM_SEQ_REFRESH_CNT_Msk);
- p_reg->SEQ[seq_id].REFRESH = refresh;
- }
- __STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,
- uint8_t seq_id,
- uint32_t end_delay)
- {
- NRFX_ASSERT(seq_id <= 1);
- NRFX_ASSERT(end_delay <= PWM_SEQ_ENDDELAY_CNT_Msk);
- p_reg->SEQ[seq_id].ENDDELAY = end_delay;
- }
- __STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,
- nrf_pwm_dec_load_t dec_load,
- nrf_pwm_dec_step_t dec_step)
- {
- p_reg->DECODER = ((uint32_t)dec_load << PWM_DECODER_LOAD_Pos) |
- ((uint32_t)dec_step << PWM_DECODER_MODE_Pos);
- }
- __STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg,
- uint16_t loop_count)
- {
- p_reg->LOOP = loop_count;
- }
- #endif
- #ifdef __cplusplus
- }
- #endif
- #endif
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