123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269 |
- #include "nrf21540_spi.h"
- #include <string.h>
- #include "nrf_assert.h"
- #include "boards.h"
- #include "nrf_ppi.h"
- #include "nrf21540_defs.h"
- #include "nrf_timer.h"
- #if NRF21540_USE_SPI_MANAGEMENT
- static uint8_t m_spi_tx_data[NRF21540_SPI_LENGTH_BYTES];
- static uint8_t m_spi_rx_data[NRF21540_SPI_LENGTH_BYTES];
- static volatile bool m_spi_xfer_done;
- static struct {
- uint8_t CONFREG0;
- uint8_t CONFREG1;
- } m_confreg_statics;
- static const nrfx_spim_t spi = NRFX_SPIM_INSTANCE(NRF21540_SPIM_NO);
- static inline void wait_for_transfer_end(void)
- {
- while (!m_spi_xfer_done)
- {}
- m_spi_xfer_done = false;
- }
- static void spim_event_handler(nrfx_spim_evt_t const *p_event, void *p_context)
- {
- m_spi_xfer_done = true;
- }
- static uint8_t spi_reg_read(nrf21540_reg_t reg, nrf21540_execution_mode_t mode, bool start_now)
- {
- ASSERT(!(mode == NRF21540_EXEC_MODE_BLOCKING && start_now == false));
- nrfx_spim_xfer_desc_t xfer_desc = NRFX_SPIM_XFER_TRX(m_spi_tx_data,
- NRF21540_SPI_LENGTH_BYTES,
- m_spi_rx_data,
- NRF21540_SPI_LENGTH_BYTES);
- m_spi_tx_data[NRF21540_SPI_COMMAND_ADDR_BYTE] =
- (NRF21540_SPI_COMMAND_READ << NRF21540_SPI_COMMAND_Pos) | (reg << NRF21540_SPI_REG_Pos);
- (void)nrfx_spim_xfer(&spi, &xfer_desc, 0);
- if (mode == NRF21540_EXEC_MODE_BLOCKING)
- {
- wait_for_transfer_end();
- }
- return m_spi_rx_data[NRF21540_SPI_DATA_BYTE];
- }
- static void spi_reg_write(nrf21540_reg_t reg, uint8_t data, nrf21540_execution_mode_t mode, bool start_now)
- {
- ASSERT(!(mode == NRF21540_EXEC_MODE_BLOCKING && start_now == false));
- nrfx_spim_xfer_desc_t xfer_desc = NRFX_SPIM_XFER_TRX(m_spi_tx_data,
- NRF21540_SPI_LENGTH_BYTES,
- m_spi_rx_data,
- NRF21540_SPI_LENGTH_BYTES);
- m_spi_tx_data[NRF21540_SPI_COMMAND_ADDR_BYTE] =
- (NRF21540_SPI_COMMAND_WRITE << NRF21540_SPI_COMMAND_Pos) | (reg << NRF21540_SPI_REG_Pos);
- m_spi_tx_data[NRF21540_SPI_DATA_BYTE] = data;
- uint32_t flags = start_now ? 0 : NRFX_SPIM_FLAG_HOLD_XFER;
- (void)nrfx_spim_xfer(&spi, &xfer_desc, flags);
- if (mode == NRF21540_EXEC_MODE_BLOCKING)
- {
- wait_for_transfer_end();
- }
- }
- static ret_code_t m_confreg_statics_content_update(void)
- {
- ret_code_t ret = nrf21540_pdn_drive(true, NRF21540_EXEC_MODE_BLOCKING);
- if (ret != NRF_SUCCESS)
- {
- return ret;
- }
- m_confreg_statics.CONFREG0 = spi_reg_read(NRF21540_REG_CONFREG0,
- NRF21540_EXEC_MODE_BLOCKING, true);
- m_confreg_statics.CONFREG1 = spi_reg_read(NRF21540_REG_CONFREG1,
- NRF21540_EXEC_MODE_BLOCKING, true);
- return nrf21540_pdn_drive(false, NRF21540_EXEC_MODE_BLOCKING);
- }
- ret_code_t nrf21540_spi_init(void)
- {
- ret_code_t ret;
- nrfx_spim_config_t spi_config = NRFX_SPIM_DEFAULT_CONFIG;
- spi_config.frequency = NRF_SPIM_FREQ_4M;
- spi_config.ss_pin = NRF21540_CS_PIN;
- spi_config.miso_pin = NRF21540_MISO_PIN;
- spi_config.mosi_pin = NRF21540_MOSI_PIN;
- spi_config.sck_pin = NRF21540_CLK_PIN;
- spi_config.ss_active_high = false;
- ret = nrfx_spim_init(&spi, &spi_config, spim_event_handler, NULL);
- if (ret != NRFX_SUCCESS)
- {
- return NRF_ERROR_INTERNAL;
- }
- return m_confreg_statics_content_update();
- }
- static void tx_en_drive(nrf21540_bool_state_t state)
- {
- uint8_t reg_val;
- if (state == NRF21540_ENABLE)
- {
- reg_val = m_confreg_statics.CONFREG0 | NRF21540_BITS_CONFREG0_TX_EN_Enable;
- }
- else
- {
- reg_val = m_confreg_statics.CONFREG0 &(~NRF21540_BITS_CONFREG0_TX_EN_Enable);
- }
- spi_reg_write(NRF21540_REG_CONFREG0, reg_val, NRF21540_EXEC_MODE_NON_BLOCKING, false);
- }
- static void rx_en_drive(nrf21540_bool_state_t state)
- {
- uint8_t reg_val;
- if (state == NRF21540_ENABLE)
- {
- reg_val = m_confreg_statics.CONFREG1 | NRF21540_BITS_CONFREG1_RX_EN_Enable;
- }
- else
- {
- reg_val = m_confreg_statics.CONFREG1 &(~NRF21540_BITS_CONFREG1_RX_EN_Disable);
- }
- spi_reg_write(NRF21540_REG_CONFREG1, reg_val, NRF21540_EXEC_MODE_NON_BLOCKING, false);
- }
- inline uint32_t nrf21540_spim_trx_task_start_address_get(void)
- {
- return nrfx_spim_start_task_get(&spi);
- }
- void nrf21540_spim_for_trx_configure(nrf21540_trx_t dir, nrf21540_bool_state_t required_state)
- {
- if (dir == NRF21540_TX)
- {
- tx_en_drive(required_state);
- }
- else
- {
- rx_en_drive(required_state);
- }
- if (required_state == NRF21540_ENABLE)
- {
- uint32_t task_start_address = nrfx_spim_start_task_get(&spi);
- nrf_ppi_channel_endpoint_setup(NRF21540_TRX_PPI_CHANNEL,
- (uint32_t)nrf_timer_event_address_get(NRF21540_TIMER,
- NRF21540_TIMER_CC_PD_PG_EVENT),
- task_start_address);
- nrf_ppi_channel_enable(NRF21540_TRX_PPI_CHANNEL);
- }
- }
- ret_code_t nrf21540_spi_pwr_mode_set(nrf21540_pwr_mode_t mode)
- {
- if (mode == NRF21540_PWR_MODE_A)
- {
- spi_reg_write(NRF21540_REG_CONFREG0, NRF21540_BITS_CONFREG0_MODE_0,
- NRF21540_EXEC_MODE_BLOCKING, true);
- }
- else if (mode == NRF21540_PWR_MODE_B)
- {
- spi_reg_write(NRF21540_REG_CONFREG0, NRF21540_BITS_CONFREG0_MODE_1,
- NRF21540_EXEC_MODE_BLOCKING, true);
- }
- else
- {
- return NRF_ERROR_INVALID_PARAM;
- }
- return NRF_SUCCESS;
- }
- #endif
|