Nordic Semiconductor
Nordic
nrf5340_network
nrf53
1
nRF53 reference description for system-on-chip with dual ARM 32-bit Cortex-M33 microcontrollers
Copyright (c) 2010 - 2020, Nordic Semiconductor ASA
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
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list of conditions and the following disclaimer.
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Semiconductor ASA integrated circuit in a product or a software update for
such product, must reproduce the above copyright notice, this list of
conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
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4. This software, with or without modification, must only be used with a
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OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8
32
32
0x00000000
0xFFFFFFFF
CM33
r0p4
little
1
0
3
0
30
0
system_nrf5340_network
NRF_
129
FICR_NS
Factory Information Configuration Registers
0x01FF0000
FICR
0
0x1000
registers
FICR
0x20
INFO
Device info
FICR_INFO
read-write
0x200
CONFIGID
Configuration identifier
0x000
read-only
0xFFFFFFFF
HWID
Identification number for the HW
0
15
0x2
0x4
DEVICEID[%s]
Description collection: Device identifier
0x004
read-only
0xFFFFFFFF
DEVICEID
64 bit unique device identifier
0
31
PART
Part code
0x00C
read-only
0x00005340
PART
Part code
0
31
N5340
nRF5340
0x5340
Unspecified
Unspecified
0xFFFFFFFF
VARIANT
Part Variant, Hardware version and Production configuration
0x010
read-only
0xFFFFFFFF
VARIANT
Part Variant, Hardware version and Production configuration, encoded as ASCII
0
31
QKAA
QKAA
0x514B4141
Unspecified
Unspecified
0xFFFFFFFF
PACKAGE
Package option
0x014
read-only
0xFFFFFFFF
PACKAGE
Package option
0
31
QF
QFxx - 94 pin QFN
0x2000
Unspecified
Unspecified
0xFFFFFFFF
RAM
RAM variant
0x018
read-only
0xFFFFFFFF
RAM
RAM variant
0
31
K16
16 kByte RAM
0x10
K32
32 kByte RAM
0x20
K64
64 kByte RAM
0x40
K128
128 kByte RAM
0x80
K256
256 kByte RAM
0x100
K512
512 kByte RAM
0x200
Unspecified
Unspecified
0xFFFFFFFF
FLASH
Flash variant
0x01C
read-only
0xFFFFFFFF
FLASH
Flash variant
0
31
K128
128 kByte FLASH
0x80
K256
256 kByte FLASH
0x100
K512
512 kByte FLASH
0x200
K1024
1 MByte FLASH
0x400
K2048
2 MByte FLASH
0x800
Unspecified
Unspecified
0xFFFFFFFF
CODEPAGESIZE
Code memory page size in bytes
0x020
read-only
0x00000800
CODEPAGESIZE
Code memory page size in bytes
0
31
K2048
2 kByte
0x800
CODESIZE
Code memory size
0x024
read-only
0x00000080
CODESIZE
Code memory size in number of pages
0
31
P128
128 pages
128
DEVICETYPE
Device type
0x028
read-only
0x00000000
DEVICETYPE
Device type
0
31
Die
Device is an physical DIE
0x0000000
FPGA
Device is an FPGA
0xFFFFFFFF
0x4
0x4
ER[%s]
Description collection: Encryption Root, word n
0x280
read-only
0xFFFFFFFF
ER
Encryption Root, word n
0
31
0x4
0x4
IR[%s]
Description collection: Identity Root, word n
0x290
read-only
0xFFFFFFFF
IR
Identity Root, word n
0
31
DEVICEADDRTYPE
Device address type
0x2A0
read-only
0xFFFFFFFF
DEVICEADDRTYPE
Device address type
0
0
Public
Public address
0
Random
Random address
1
0x2
0x4
DEVICEADDR[%s]
Description collection: Device address n
0x2A4
read-only
0xFFFFFFFF
DEVICEADDR
48 bit device address
0
31
32
0x008
TRIMCNF[%s]
Unspecified
FICR_TRIMCNF
read-write
0x300
ADDR
Description cluster: Address
0x000
read-write
0xFFFFFFFF
uint32_t *
Address
Address
0
31
DATA
Description cluster: Data
0x004
read-only
0xFFFFFFFF
Data
Data
0
31
UICR_NS
User Information Configuration Registers
0x01FF8000
UICR
0
0x1000
registers
UICR
0x20
APPROTECT
Access port protection
0x000
read-write
0x00000000
PALL
Blocks debugger read/write access to all CPU registers and memory mapped
addresses Using any value except Unprotected will lead to the protection being enabled.
0
31
Unprotected
Unprotected
0xFFFFFFFF
Protected
Protected
0x00000000
ERASEPROTECT
Erase protection
0x004
read-write
0x00000000
PALL
Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality. Using any value except Unprotected will lead to the protection being enabled.
0
31
Unprotected
Unprotected
0xFFFFFFFF
Protected
Protected
0x00000000
0x20
0x4
NRFFW[%s]
Description collection: Reserved for Nordic firmware design
0x200
read-write
0xFFFFFFFF
NRFFW
Reserved for Nordic firmware design
0
31
0x20
0x4
CUSTOMER[%s]
Description collection: Reserved for customer
0x300
read-write
0xFFFFFFFF
CUSTOMER
Reserved for customer
0
31
CTI_NS
Cross-Trigger Interface control. NOTE: this is not a separate peripheral, but describes CM33 functionality.
0xE0042000
CTI
0
0x1000
registers
CTI
0x20
CTICONTROL
CTI Control register
0x000
read-write
0x00000000
GLBEN
Enables or disables the CTI.
0
0
Disabled
All cross-triggering mapping logic functionality is disabled.
0
Enabled
Cross-triggering mapping logic functionality is enabled.
1
CTIINTACK
CTI Interrupt Acknowledge register
0x010
write-only
0x00000000
DEBUGREQ
Processor debug request
0
0
write
Acknowledge
Clears the ctitrigout.
1
CPURESTART
Processor Restart
1
1
write
Acknowledge
Clears the ctitrigout.
1
UNUSED0
N/A
2
2
write
Acknowledge
Clears the ctitrigout.
1
UNUSED1
N/A
3
3
write
Acknowledge
Clears the ctitrigout.
1
UNUSED2
N/A
4
4
write
Acknowledge
Clears the ctitrigout.
1
UNUSED3
N/A
5
5
write
Acknowledge
Clears the ctitrigout.
1
UNUSED4
N/A
6
6
write
Acknowledge
Clears the ctitrigout.
1
UNUSED5
N/A
7
7
write
Acknowledge
Clears the ctitrigout.
1
CTIAPPSET
CTI Application Trigger Set register
0x014
read-write
0x00000000
APPSET_0
Application trigger event for channel 0.
0
0
read
Inactive
Application trigger 0 is inactive.
0
Active
Application trigger 0 is active.
1
write
Activate
Generate channel event for channel 0.
1
APPSET_1
Application trigger event for channel 1.
1
1
read
Inactive
Application trigger 1 is inactive.
0
Active
Application trigger 1 is active.
1
write
Activate
Generate channel event for channel 1.
1
APPSET_2
Application trigger event for channel 2.
2
2
read
Inactive
Application trigger 2 is inactive.
0
Active
Application trigger 2 is active.
1
write
Activate
Generate channel event for channel 2.
1
APPSET_3
Application trigger event for channel 3.
3
3
read
Inactive
Application trigger 3 is inactive.
0
Active
Application trigger 3 is active.
1
write
Activate
Generate channel event for channel 3.
1
CTIAPPCLEAR
CTI Application Trigger Clear register
0x018
write-only
0x00000000
APPCLEAR_0
Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel.
0
0
write
Clear
Clears the event for channel 0.
1
APPCLEAR_1
Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel.
1
1
write
Clear
Clears the event for channel 1.
1
APPCLEAR_2
Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel.
2
2
write
Clear
Clears the event for channel 2.
1
APPCLEAR_3
Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel.
3
3
write
Clear
Clears the event for channel 3.
1
CTIAPPPULSE
CTI Application Pulse register
0x01C
write-only
0x00000000
APPULSE_0
Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel.
0
0
write
Generate
Generates an event pulse on channel 0.
1
APPULSE_1
Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel.
1
1
write
Generate
Generates an event pulse on channel 1.
1
APPULSE_2
Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel.
2
2
write
Generate
Generates an event pulse on channel 2.
1
APPULSE_3
Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel.
3
3
write
Generate
Generates an event pulse on channel 3.
1
0x8
0x4
CTIINEN[%s]
Description collection: CTI Trigger input
0x020
read-write
0x00000000
TRIGINEN_0
Enables a cross trigger event to channel 0 when a ctitrigin input is activated.
0
0
Disabled
Input trigger n events are ignored by channel 0.
0
Enabled
When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 0.
1
TRIGINEN_1
Enables a cross trigger event to channel 1 when a ctitrigin input is activated.
1
1
Disabled
Input trigger n events are ignored by channel 1.
0
Enabled
When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 1.
1
TRIGINEN_2
Enables a cross trigger event to channel 2 when a ctitrigin input is activated.
2
2
Disabled
Input trigger n events are ignored by channel 2.
0
Enabled
When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 2.
1
TRIGINEN_3
Enables a cross trigger event to channel 3 when a ctitrigin input is activated.
3
3
Disabled
Input trigger n events are ignored by channel 3.
0
Enabled
When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 3.
1
0x8
0x4
CTIOUTEN[%s]
Description collection: CTI Trigger output
0x0A0
read-write
0x00000000
TRIGOUTEN_0
Enables a cross trigger event to ctitrigout when channel 0 is activated.
0
0
Disabled
Channel 0 is ignored by output trigger n.
0
Enabled
When an event occurs on channel 0, generate an event on output event n (ctitrigout[n]).
1
TRIGOUTEN_1
Enables a cross trigger event to ctitrigout when channel 1 is activated.
1
1
Disabled
Channel 1 is ignored by output trigger n.
0
Enabled
When an event occurs on channel 1, generate an event on output event n (ctitrigout[n]).
1
TRIGOUTEN_2
Enables a cross trigger event to ctitrigout when channel 2 is activated.
2
2
Disabled
Channel 2 is ignored by output trigger n.
0
Enabled
When an event occurs on channel 2, generate an event on output event n (ctitrigout[n]).
1
TRIGOUTEN_3
Enables a cross trigger event to ctitrigout when channel 3 is activated.
3
3
Disabled
Channel 3 is ignored by output trigger n.
0
Enabled
When an event occurs on channel 3, generate an event on output event n (ctitrigout[n]).
1
CTITRIGINSTATUS
CTI Trigger In Status register
0x130
read-only
0x00000000
CPUHALTED
Processor Halted
0
0
Active
Ctitrigin 0 is active.
1
Inactive
Ctitrigin 0 is inactive.
0
DWTCOMPOUT0
DWT Comparator Output 0
1
1
Active
Ctitrigin 1 is active.
1
Inactive
Ctitrigin 1 is inactive.
0
DWTCOMPOUT1
DWT Comparator Output 1
2
2
Active
Ctitrigin 2 is active.
1
Inactive
Ctitrigin 2 is inactive.
0
DWTCOMPOUT2
DWT Comparator Output 2
3
3
Active
Ctitrigin 3 is active.
1
Inactive
Ctitrigin 3 is inactive.
0
UNUSED0
N/A
4
4
Active
Ctitrigin 4 is active.
1
Inactive
Ctitrigin 4 is inactive.
0
UNUSED1
N/A
5
5
Active
Ctitrigin 5 is active.
1
Inactive
Ctitrigin 5 is inactive.
0
UNUSED2
N/A
6
6
Active
Ctitrigin 6 is active.
1
Inactive
Ctitrigin 6 is inactive.
0
UNUSED3
N/A
7
7
Active
Ctitrigin 7 is active.
1
Inactive
Ctitrigin 7 is inactive.
0
CTITRIGOUTSTATUS
CTI Trigger Out Status register
0x134
read-only
0x00000000
DEBUGREQ
Processor debug request
0
0
Active
Ctitrigout 0 is active.
1
Inactive
Ctitrigout 0 is inactive.
0
CPURESTART
Processor Restart
1
1
Active
Ctitrigout 1 is active.
1
Inactive
Ctitrigout 1 is inactive.
0
UNUSED0
N/A
2
2
Active
Ctitrigout 2 is active.
1
Inactive
Ctitrigout 2 is inactive.
0
UNUSED1
N/A
3
3
Active
Ctitrigout 3 is active.
1
Inactive
Ctitrigout 3 is inactive.
0
UNUSED2
N/A
4
4
Active
Ctitrigout 4 is active.
1
Inactive
Ctitrigout 4 is inactive.
0
UNUSED3
N/A
5
5
Active
Ctitrigout 5 is active.
1
Inactive
Ctitrigout 5 is inactive.
0
UNUSED4
N/A
6
6
Active
Ctitrigout 6 is active.
1
Inactive
Ctitrigout 6 is inactive.
0
UNUSED5
N/A
7
7
Active
Ctitrigout 7 is active.
1
Inactive
Ctitrigout 7 is inactive.
0
CTICHINSTATUS
CTI Channel In Status register
0x138
read-only
0x00000000
CTICHINSTATUS_0
Shows the status of the ctitrigin 0 input.
0
0
Active
Ctichin 0 is active.
1
Inactive
Ctichin 0 is inactive.
0
CTICHINSTATUS_1
Shows the status of the ctitrigin 1 input.
1
1
Active
Ctichin 1 is active.
1
Inactive
Ctichin 1 is inactive.
0
CTICHINSTATUS_2
Shows the status of the ctitrigin 2 input.
2
2
Active
Ctichin 2 is active.
1
Inactive
Ctichin 2 is inactive.
0
CTICHINSTATUS_3
Shows the status of the ctitrigin 3 input.
3
3
Active
Ctichin 3 is active.
1
Inactive
Ctichin 3 is inactive.
0
CTIGATE
Enable CTI Channel Gate register
0x140
read-write
0x0000000F
CTIGATEEN_0
Enable ctichout0.
0
0
Enabled
Enable ctichout channel 0 propagation.
1
Disabled
Disable ctichout channel 0 propagation.
0
CTIGATEEN_1
Enable ctichout1.
1
1
Enabled
Enable ctichout channel 1 propagation.
1
Disabled
Disable ctichout channel 1 propagation.
0
CTIGATEEN_2
Enable ctichout2.
2
2
Enabled
Enable ctichout channel 2 propagation.
1
Disabled
Disable ctichout channel 2 propagation.
0
CTIGATEEN_3
Enable ctichout3.
3
3
Enabled
Enable ctichout channel 3 propagation.
1
Disabled
Disable ctichout channel 3 propagation.
0
DEVARCH
Device Architecture register
0xFBC
read-only
0x47701A14
Architecture
Contains the CTI device architecture.
0
0
DEVID
Device Configuration register
0xFC8
read-only
0x00040800
EXTMUXNUM
Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl.
The default value of 0b00000 indicates that no multiplexing is present.
0
4
NUMTRIG
Number of ECT triggers available.
8
15
NUMCH
Number of ECT channels available.
16
19
DEVTYPE
Device Type Identifier register
0xFCC
read-only
0x00000014
MAJOR
Major classification of the type of the debug component as specified in the ARM Architecture Specification for this
debug and trace component.
0
3
Controller
Indicates that this component allows a debugger to control other components in a CoreSight SoC-400 system.
0b0100
SUB
Sub-classification of the type of the debug component as specified in the ARM Architecture Specification within
the major classification as specified in the MAJOR field.
4
7
Crosstrigger
Indicates that this component is a sub-triggering component.
0b0001
PIDR4
Peripheral ID4 Register
0xFD0
read-only
0x00000004
DES_2
Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component.
0
3
Code
JEDEC continuation code
0b0100
SIZE
Always 0b0000. Indicates that the device only occupies 4KB of memory.
4
7
PIDR5
Peripheral ID5 register
0xFD4
read-only
PIDR6
Peripheral ID6 register
0xFD8
read-only
PIDR7
Peripheral ID7 register
0xFDC
read-only
PIDR0
Peripheral ID0 Register
0xFE0
read-only
0x00000021
PART_0
Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number.
0
7
PartnumberL
Indicates bits[7:0] of the part number of the component.
0x21
PIDR1
Peripheral ID1 Register
0xFE4
read-only
0x000000BD
PART_1
Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number.
0
3
PartnumberH
Indicates bits[11:8] of the part number of the component.
0b1101
DES_0
Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component.
4
7
Arm
ARM. Bits[3:0] of the JEDEC JEP106 Identity Code
0b1011
PIDR2
Peripheral ID2 Register
0xFE8
read-only
0x0000000B
DES_1
Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component.
0
2
Arm
ARM. Bits[6:4] of the JEDEC JEP106 Identity Code
0b011
JEDEC
Always 1. Indicates that the JEDEC-assigned designer ID is used.
3
3
REVISION
Peripheral revision
4
7
Rev0p0
This device is at r0p0
0b0000
PIDR3
Peripheral ID3 Register
0xFEC
read-only
0x00000000
CMOD
Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases,
this field is 0b0000. Customers change this value when they make authorized modifications to this component.
0
3
Unmodified
Indicates that the customer has not modified this component.
0b000
REVAND
Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after
implementation. In most cases, this field is 0b0000. ARM recommends that the component designers ensure that a
metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000.
4
7
NoErrata
Indicates that there are no errata fixes to this component.
0b000
CIDR0
Component ID0 Register
0xFF0
read-only
0x0000000D
PRMBL_0
Preamble[0]. Contains bits[7:0] of the component identification code.
0
7
Value
Bits[7:0] of the identification code.
0x0D
CIDR1
Component ID1 Register
0xFF4
read-only
0x00000090
PRMBL_1
Preamble[1]. Contains bits[11:8] of the component identification code.
0
3
Value
Bits[11:8] of the identification code.
0b0000
CLASS
Class of the component, for example, whether the component is a ROM table or a generic CoreSight component.
Contains bits[15:12] of the component identification code
4
7
Coresight
Indicates that the component is a CoreSight component.
0b1001
CIDR2
Component ID2 Register
0xFF8
read-only
0x00000005
PRMBL_2
Preamble[2]. Contains bits[23:16] of the component identification code.
0
7
Value
Bits[23:16] of the identification code.
0x05
CIDR3
Component ID3 Register
0xFFC
read-only
0x000000B1
PRMBL_3
Preamble[3]. Contains bits[31:24] of the component identification code.
0
7
Value
Bits[31:24] of the identification code.
0xB1
DCNF_NS
Domain configuration management
0x41000000
DCNF
0
0x1000
registers
DCNF
0x20
CPUID
CPU ID of this subsystem
0x420
read-only
0x00000001
CPUID
CPU ID
0
7
VREQCTRL_NS
Voltage request control
0x41004000
VREQCTRL
0
0x1000
registers
VREQCTRL
0x20
VREGRADIO
Unspecified
VREQCTRL_VREGRADIO
read-write
0x500
VREQH
Request high voltage on RADIO After requesting high voltage, the user must wait until VREQHREADY is set to Ready
0x000
read-write
VREQH
Request high voltage
0
0
Disabled
Disable
0
Enabled
Enable
1
VREQHREADY
High voltage on RADIO is ready
0x008
read-only
READY
RADIO is ready to operate on high voltage
0
0
NotReady
Not ready
0
Ready
Ready
1
CLOCK_NS
Clock management
0x41005000
CLOCK
0
0x1000
registers
CLOCK_POWER
5
CLOCK
0x20
TASKS_HFCLKSTART
Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC
0x000
write-only
TASKS_HFCLKSTART
Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC
0
0
Trigger
Trigger task
1
TASKS_HFCLKSTOP
Stop HFCLK128M/HFCLK64M source
0x004
write-only
TASKS_HFCLKSTOP
Stop HFCLK128M/HFCLK64M source
0
0
Trigger
Trigger task
1
TASKS_LFCLKSTART
Start LFCLK source as selected in LFCLKSRC
0x008
write-only
TASKS_LFCLKSTART
Start LFCLK source as selected in LFCLKSRC
0
0
Trigger
Trigger task
1
TASKS_LFCLKSTOP
Stop LFCLK source
0x00C
write-only
TASKS_LFCLKSTOP
Stop LFCLK source
0
0
Trigger
Trigger task
1
TASKS_CAL
Start calibration of LFRC oscillator
0x010
write-only
TASKS_CAL
Start calibration of LFRC oscillator
0
0
Trigger
Trigger task
1
SUBSCRIBE_HFCLKSTART
Subscribe configuration for task HFCLKSTART
0x080
read-write
CHIDX
DPPI channel that task HFCLKSTART will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_HFCLKSTOP
Subscribe configuration for task HFCLKSTOP
0x084
read-write
CHIDX
DPPI channel that task HFCLKSTOP will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_LFCLKSTART
Subscribe configuration for task LFCLKSTART
0x088
read-write
CHIDX
DPPI channel that task LFCLKSTART will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_LFCLKSTOP
Subscribe configuration for task LFCLKSTOP
0x08C
read-write
CHIDX
DPPI channel that task LFCLKSTOP will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_CAL
Subscribe configuration for task CAL
0x090
read-write
CHIDX
DPPI channel that task CAL will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
EVENTS_HFCLKSTARTED
HFCLK128M/HFCLK64M source started
0x100
read-write
EVENTS_HFCLKSTARTED
HFCLK128M/HFCLK64M source started
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_LFCLKSTARTED
LFCLK source started
0x104
read-write
EVENTS_LFCLKSTARTED
LFCLK source started
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_DONE
Calibration of LFRC oscillator complete event
0x11C
read-write
EVENTS_DONE
Calibration of LFRC oscillator complete event
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
PUBLISH_HFCLKSTARTED
Publish configuration for event HFCLKSTARTED
0x180
read-write
CHIDX
DPPI channel that event HFCLKSTARTED will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_LFCLKSTARTED
Publish configuration for event LFCLKSTARTED
0x184
read-write
CHIDX
DPPI channel that event LFCLKSTARTED will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_DONE
Publish configuration for event DONE
0x19C
read-write
CHIDX
DPPI channel that event DONE will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
INTEN
Enable or disable interrupt
0x300
read-write
HFCLKSTARTED
Enable or disable interrupt for event HFCLKSTARTED
0
0
Disabled
Disable
0
Enabled
Enable
1
LFCLKSTARTED
Enable or disable interrupt for event LFCLKSTARTED
1
1
Disabled
Disable
0
Enabled
Enable
1
DONE
Enable or disable interrupt for event DONE
7
7
Disabled
Disable
0
Enabled
Enable
1
INTENSET
Enable interrupt
0x304
read-write
HFCLKSTARTED
Write '1' to enable interrupt for event HFCLKSTARTED
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
LFCLKSTARTED
Write '1' to enable interrupt for event LFCLKSTARTED
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
DONE
Write '1' to enable interrupt for event DONE
7
7
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
INTENCLR
Disable interrupt
0x308
read-write
HFCLKSTARTED
Write '1' to disable interrupt for event HFCLKSTARTED
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
LFCLKSTARTED
Write '1' to disable interrupt for event LFCLKSTARTED
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
DONE
Write '1' to disable interrupt for event DONE
7
7
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
INTPEND
Pending interrupts
0x30C
read-only
HFCLKSTARTED
Read pending status of interrupt for event HFCLKSTARTED
0
0
read
NotPending
Read: Not pending
0
Pending
Read: Pending
1
LFCLKSTARTED
Read pending status of interrupt for event LFCLKSTARTED
1
1
read
NotPending
Read: Not pending
0
Pending
Read: Pending
1
DONE
Read pending status of interrupt for event DONE
7
7
read
NotPending
Read: Not pending
0
Pending
Read: Pending
1
HFCLKRUN
Status indicating that HFCLKSTART task has been triggered
0x408
read-only
STATUS
HFCLKSTART task triggered or not
0
0
NotTriggered
Task not triggered
0
Triggered
Task triggered
1
HFCLKSTAT
Status indicating which HFCLK128M/HFCLK64M source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance.
0x40C
read-only
SRC
Active clock source
0
0
HFINT
Clock source: HFINT - 128 MHz on-chip oscillator
0
HFXO
Clock source: HFXO - 128 MHz clock derived from external 32 MHz crystal oscillator
1
ALWAYSRUNNING
ALWAYSRUN activated
4
4
NotRunning
Automatic clock control enabled
0
Running
Oscillator is always running
1
STATE
HFCLK state
16
16
NotRunning
HFCLK not running
0
Running
HFCLK running
1
LFCLKRUN
Status indicating that LFCLKSTART task has been triggered
0x414
read-only
STATUS
LFCLKSTART task triggered or not
0
0
NotTriggered
Task not triggered
0
Triggered
Task triggered
1
LFCLKSTAT
Status indicating which LFCLK source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance.
0x418
read-only
SRC
Active clock source
0
1
LFULP
32.768 kHz ultra-low power RC oscillator
0
LFRC
32.768 kHz RC oscillator
1
LFXO
32.768 kHz crystal oscillator
2
LFSYNT
32.768 kHz synthesized from HFCLK
3
ALWAYSRUNNING
ALWAYSRUN activated
4
4
NotRunning
Automatic clock control enabled
0
Running
Oscillator is always running
1
STATE
LFCLK state
16
16
NotRunning
LFCLK not running
0
Running
LFCLK running
1
LFCLKSRCCOPY
Copy of LFCLKSRC register, set when LFCLKSTART task was triggered
0x41C
read-only
0x00000001
SRC
Clock source
0
1
LFULP
32.768 kHz ultra-low power RC oscillator
0
LFRC
32.768 kHz RC oscillator
1
LFXO
32.768 kHz crystal oscillator
2
LFSYNT
32.768 kHz synthesized from HFCLK
3
HFCLKSRC
Clock source for HFCLK128M/HFCLK64M
0x514
read-write
0x00000001
SRC
Select which HFCLK source is started by the HFCLKSTART task
0
0
HFINT
HFCLKSTART task starts HFINT oscillator
0
HFXO
HFCLKSTART task starts HFXO oscillator
1
LFCLKSRC
Clock source for LFCLK
0x518
read-write
0x00000001
SRC
Select which LFCLK source is started by the LFCLKSTART task
0
1
LFULP
32.768 kHz ultra-low power RC oscillator
0
LFRC
32.768 kHz RC oscillator
1
LFXO
32.768 kHz crystal oscillator
2
LFSYNT
32.768 kHz synthesized from HFCLK
3
HFCLKCTRL
HFCLK128M frequency configuration
0x558
read-write
0x00000000
HCLK
High frequency clock HCLK
0
1
Div1
Divide HFCLK by 1
0
Div2
Divide HFCLK by 2
1
HFCLKALWAYSRUN
Automatic or manual control of HFCLK128M/HFCLK64M
0x570
read-write
ALWAYSRUN
Ensure clock is always running
0
0
Automatic
Use automatic clock control
0
AlwaysRun
Ensure clock is always running
1
LFCLKALWAYSRUN
Automatic or manual control of LFCLK
0x574
read-write
ALWAYSRUN
Ensure clock is always running
0
0
Automatic
Use automatic clock control
0
AlwaysRun
Ensure clock is always running
1
POWER_NS
Power control
0x41005000
CLOCK_NS
POWER
0
0x1000
registers
CLOCK_POWER
5
POWER
0x20
TASKS_CONSTLAT
Enable Constant Latency mode
0x78
write-only
TASKS_CONSTLAT
Enable Constant Latency mode
0
0
Trigger
Trigger task
1
TASKS_LOWPWR
Enable Low-Power mode (variable latency)
0x7C
write-only
TASKS_LOWPWR
Enable Low-Power mode (variable latency)
0
0
Trigger
Trigger task
1
SUBSCRIBE_CONSTLAT
Subscribe configuration for task CONSTLAT
0xF8
read-write
CHIDX
DPPI channel that task CONSTLAT will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_LOWPWR
Subscribe configuration for task LOWPWR
0xFC
read-write
CHIDX
DPPI channel that task LOWPWR will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
EVENTS_POFWARN
Power failure warning
0x108
read-write
EVENTS_POFWARN
Power failure warning
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_SLEEPENTER
CPU entered WFI/WFE sleep
0x114
read-write
EVENTS_SLEEPENTER
CPU entered WFI/WFE sleep
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_SLEEPEXIT
CPU exited WFI/WFE sleep
0x118
read-write
EVENTS_SLEEPEXIT
CPU exited WFI/WFE sleep
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
PUBLISH_POFWARN
Publish configuration for event POFWARN
0x188
read-write
CHIDX
DPPI channel that event POFWARN will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_SLEEPENTER
Publish configuration for event SLEEPENTER
0x194
read-write
CHIDX
DPPI channel that event SLEEPENTER will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_SLEEPEXIT
Publish configuration for event SLEEPEXIT
0x198
read-write
CHIDX
DPPI channel that event SLEEPEXIT will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
INTEN
Enable or disable interrupt
0x300
read-write
POFWARN
Enable or disable interrupt for event POFWARN
2
2
Disabled
Disable
0
Enabled
Enable
1
SLEEPENTER
Enable or disable interrupt for event SLEEPENTER
5
5
Disabled
Disable
0
Enabled
Enable
1
SLEEPEXIT
Enable or disable interrupt for event SLEEPEXIT
6
6
Disabled
Disable
0
Enabled
Enable
1
INTENSET
Enable interrupt
0x304
read-write
POFWARN
Write '1' to enable interrupt for event POFWARN
2
2
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
SLEEPENTER
Write '1' to enable interrupt for event SLEEPENTER
5
5
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
SLEEPEXIT
Write '1' to enable interrupt for event SLEEPEXIT
6
6
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
INTENCLR
Disable interrupt
0x308
read-write
POFWARN
Write '1' to disable interrupt for event POFWARN
2
2
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
SLEEPENTER
Write '1' to disable interrupt for event SLEEPENTER
5
5
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
SLEEPEXIT
Write '1' to disable interrupt for event SLEEPEXIT
6
6
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
0x2
0x4
GPREGRET[%s]
Description collection: General purpose retention register
0x51C
read-write
GPREGRET
General purpose retention register
0
7
RESET_NS
Reset control
0x41005000
CLOCK_NS
RESET
0
0x1000
registers
RESET
0x20
RESETREAS
Reset reason
0x400
read-write
RESETPIN
Reset from pin reset detected
0
0
NotDetected
Not detected
0
Detected
Detected
1
DOG0
Reset from application watchdog timer 0 detected
1
1
NotDetected
Not detected
0
Detected
Detected
1
CTRLAP
Reset from application CTRL-AP detected
2
2
NotDetected
Not detected
0
Detected
Detected
1
SREQ
Reset from application soft reset detected
3
3
NotDetected
Not detected
0
Detected
Detected
1
LOCKUP
Reset from application CPU lockup detected
4
4
NotDetected
Not detected
0
Detected
Detected
1
OFF
Reset due to wakeup from System OFF mode when wakeup is triggered by DETECT signal from GPIO
5
5
NotDetected
Not detected
0
Detected
Detected
1
LPCOMP
Reset due to wakeup from System OFF mode when wakeup is triggered by ANADETECT signal from LPCOMP
6
6
NotDetected
Not detected
0
Detected
Detected
1
DIF
Reset due to wakeup from System OFF mode when wakeup is triggered by entering the Debug Interface mode
7
7
NotDetected
Not detected
0
Detected
Detected
1
LSREQ
Reset from network soft reset detected
16
16
NotDetected
Not detected
0
Detected
Detected
1
LLOCKUP
Reset from network CPU lockup detected
17
17
NotDetected
Not detected
0
Detected
Detected
1
LDOG
Reset from network watchdog timer detected
18
18
NotDetected
Not detected
0
Detected
Detected
1
MFORCEOFF
Force-OFF reset from application core detected
23
23
NotDetected
Not detected
0
Detected
Detected
1
NFC
Reset after wakeup from System OFF mode due to NFC field being detected
24
24
NotDetected
Not detected
0
Detected
Detected
1
DOG1
Reset from application watchdog timer 1 detected
25
25
NotDetected
Not detected
0
Detected
Detected
1
VBUS
Reset after wakeup from System OFF mode due to VBUS rising into valid range
26
26
NotDetected
Not detected
0
Detected
Detected
1
LCTRLAP
Reset from network CTRL-AP detected
27
27
NotDetected
Not detected
0
Detected
Detected
1
CTRLAP_NS
Control access port
0x41006000
CTRLAPPERI
0
0x1000
registers
CTRLAPPERI
0x20
MAILBOX
Unspecified
CTRLAPPERI_MAILBOX
read-write
0x400
RXDATA
Data sent from the debugger to the CPU.
0x000
read-only
0x00000000
RXDATA
Data received from debugger
0
31
RXSTATUS
This register shows a status that indicates if data sent from the debugger to the CPU has been read.
0x004
read-only
0x00000000
RXSTATUS
Status of data in register RXDATA
0
0
NoDataPending
No data pending in register RXDATA
0
DataPending
Data pending in register RXDATA
1
TXDATA
Data sent from the CPU to the debugger.
0x80
read-write
0x00000000
TXDATA
Data sent to debugger
0
31
TXSTATUS
This register shows a status that indicates if the data sent from the CPU to the debugger has been read.
0x84
read-only
0x00000000
TXSTATUS
Status of data in register TXDATA
0
0
NoDataPending
No data pending in register TXDATA
0
DataPending
Data pending in register TXDATA
1
ERASEPROTECT
Unspecified
CTRLAPPERI_ERASEPROTECT
read-write
0x500
LOCK
This register locks the ERASEPROTECT.DISABLE register from being written until next reset.
0x000
read-writeonce
0x00000000
LOCK
Lock ERASEPROTECT.DISABLE register from being written until next reset
0
0
Unlocked
Register ERASEPROTECT.DISABLE is writeable
0
Locked
Register ERASEPROTECT.DISABLE is read-only
1
DISABLE
This register disables the ERASEPROTECT register and performs an ERASEALL operation.
0x004
read-write
0x00000000
KEY
The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides.
0
31
APPROTECT
Unspecified
CTRLAPPERI_APPROTECT
read-write
0x540
LOCK
This register locks the APPROTECT.DISABLE register from being written to until next reset.
0x000
read-writeonce
0x00000000
LOCK
Lock the APPROTECT.DISABLE register from being written to until next reset
0
0
Unlocked
Register APPROTECT.DISABLE is writeable
0
Locked
Register APPROTECT.DISABLE is read-only
1
DISABLE
This register disables the APPROTECT register and enables debug access to non-secure mode.
0x004
read-write
0x00000000
KEY
Disable APPROTECT and enable debug access to non-secure mode until the next pin reset if the KEY fields match. The current APPROTECT value as configured from UICR is bypassed if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides.
0
31
STATUS
Status bits for CTRL-AP peripheral
0x600
read-only
0x00000000
APPROTECT
Status bit for access port protection in non-secure mode
0
0
Disabled
Non-secure mode access port protection is currently disabled
0
Enabled
Non-secure mode access port protection is currently enabled
1
DBGIFACEMODE
Status bit for device debug interface mode
2
2
Disabled
No debugger attached
0
Enabled
Debugger is attached and device is in debug interface mode
1
RADIO_NS
2.4 GHz radio
0x41008000
RADIO
0
0x1000
registers
RADIO
8
RADIO
0x20
TASKS_TXEN
Enable RADIO in TX mode
0x000
write-only
TASKS_TXEN
Enable RADIO in TX mode
0
0
Trigger
Trigger task
1
TASKS_RXEN
Enable RADIO in RX mode
0x004
write-only
TASKS_RXEN
Enable RADIO in RX mode
0
0
Trigger
Trigger task
1
TASKS_START
Start RADIO
0x008
write-only
TASKS_START
Start RADIO
0
0
Trigger
Trigger task
1
TASKS_STOP
Stop RADIO
0x00C
write-only
TASKS_STOP
Stop RADIO
0
0
Trigger
Trigger task
1
TASKS_DISABLE
Disable RADIO
0x010
write-only
TASKS_DISABLE
Disable RADIO
0
0
Trigger
Trigger task
1
TASKS_RSSISTART
Start the RSSI and take one single sample of the receive signal strength
0x014
write-only
TASKS_RSSISTART
Start the RSSI and take one single sample of the receive signal strength
0
0
Trigger
Trigger task
1
TASKS_RSSISTOP
Stop the RSSI measurement
0x018
write-only
TASKS_RSSISTOP
Stop the RSSI measurement
0
0
Trigger
Trigger task
1
TASKS_BCSTART
Start the bit counter
0x01C
write-only
TASKS_BCSTART
Start the bit counter
0
0
Trigger
Trigger task
1
TASKS_BCSTOP
Stop the bit counter
0x020
write-only
TASKS_BCSTOP
Stop the bit counter
0
0
Trigger
Trigger task
1
TASKS_EDSTART
Start the energy detect measurement used in IEEE 802.15.4 mode
0x024
write-only
TASKS_EDSTART
Start the energy detect measurement used in IEEE 802.15.4 mode
0
0
Trigger
Trigger task
1
TASKS_EDSTOP
Stop the energy detect measurement
0x028
write-only
TASKS_EDSTOP
Stop the energy detect measurement
0
0
Trigger
Trigger task
1
TASKS_CCASTART
Start the clear channel assessment used in IEEE 802.15.4 mode
0x02C
write-only
TASKS_CCASTART
Start the clear channel assessment used in IEEE 802.15.4 mode
0
0
Trigger
Trigger task
1
TASKS_CCASTOP
Stop the clear channel assessment
0x030
write-only
TASKS_CCASTOP
Stop the clear channel assessment
0
0
Trigger
Trigger task
1
SUBSCRIBE_TXEN
Subscribe configuration for task TXEN
0x080
read-write
CHIDX
DPPI channel that task TXEN will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_RXEN
Subscribe configuration for task RXEN
0x084
read-write
CHIDX
DPPI channel that task RXEN will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_START
Subscribe configuration for task START
0x088
read-write
CHIDX
DPPI channel that task START will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_STOP
Subscribe configuration for task STOP
0x08C
read-write
CHIDX
DPPI channel that task STOP will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_DISABLE
Subscribe configuration for task DISABLE
0x090
read-write
CHIDX
DPPI channel that task DISABLE will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_RSSISTART
Subscribe configuration for task RSSISTART
0x094
read-write
CHIDX
DPPI channel that task RSSISTART will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_RSSISTOP
Subscribe configuration for task RSSISTOP
0x098
read-write
CHIDX
DPPI channel that task RSSISTOP will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_BCSTART
Subscribe configuration for task BCSTART
0x09C
read-write
CHIDX
DPPI channel that task BCSTART will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_BCSTOP
Subscribe configuration for task BCSTOP
0x0A0
read-write
CHIDX
DPPI channel that task BCSTOP will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_EDSTART
Subscribe configuration for task EDSTART
0x0A4
read-write
CHIDX
DPPI channel that task EDSTART will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_EDSTOP
Subscribe configuration for task EDSTOP
0x0A8
read-write
CHIDX
DPPI channel that task EDSTOP will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_CCASTART
Subscribe configuration for task CCASTART
0x0AC
read-write
CHIDX
DPPI channel that task CCASTART will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_CCASTOP
Subscribe configuration for task CCASTOP
0x0B0
read-write
CHIDX
DPPI channel that task CCASTOP will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
EVENTS_READY
RADIO has ramped up and is ready to be started
0x100
read-write
EVENTS_READY
RADIO has ramped up and is ready to be started
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_ADDRESS
Address sent or received
0x104
read-write
EVENTS_ADDRESS
Address sent or received
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_PAYLOAD
Packet payload sent or received
0x108
read-write
EVENTS_PAYLOAD
Packet payload sent or received
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_END
Packet sent or received
0x10C
read-write
EVENTS_END
Packet sent or received
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_DISABLED
RADIO has been disabled
0x110
read-write
EVENTS_DISABLED
RADIO has been disabled
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_DEVMATCH
A device address match occurred on the last received packet
0x114
read-write
EVENTS_DEVMATCH
A device address match occurred on the last received packet
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_DEVMISS
No device address match occurred on the last received packet
0x118
read-write
EVENTS_DEVMISS
No device address match occurred on the last received packet
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_RSSIEND
Sampling of receive signal strength complete
0x11C
read-write
EVENTS_RSSIEND
Sampling of receive signal strength complete
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_BCMATCH
Bit counter reached bit count value
0x128
read-write
EVENTS_BCMATCH
Bit counter reached bit count value
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_CRCOK
Packet received with CRC ok
0x130
read-write
EVENTS_CRCOK
Packet received with CRC ok
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_CRCERROR
Packet received with CRC error
0x134
read-write
EVENTS_CRCERROR
Packet received with CRC error
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_FRAMESTART
IEEE 802.15.4 length field received
0x138
read-write
EVENTS_FRAMESTART
IEEE 802.15.4 length field received
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_EDEND
Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register
0x13C
read-write
EVENTS_EDEND
Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_EDSTOPPED
The sampling of energy detection has stopped
0x140
read-write
EVENTS_EDSTOPPED
The sampling of energy detection has stopped
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_CCAIDLE
Wireless medium in idle - clear to send
0x144
read-write
EVENTS_CCAIDLE
Wireless medium in idle - clear to send
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_CCABUSY
Wireless medium busy - do not send
0x148
read-write
EVENTS_CCABUSY
Wireless medium busy - do not send
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_CCASTOPPED
The CCA has stopped
0x14C
read-write
EVENTS_CCASTOPPED
The CCA has stopped
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_RATEBOOST
Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit.
0x150
read-write
EVENTS_RATEBOOST
Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit.
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_TXREADY
RADIO has ramped up and is ready to be started TX path
0x154
read-write
EVENTS_TXREADY
RADIO has ramped up and is ready to be started TX path
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_RXREADY
RADIO has ramped up and is ready to be started RX path
0x158
read-write
EVENTS_RXREADY
RADIO has ramped up and is ready to be started RX path
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_MHRMATCH
MAC header match found
0x15C
read-write
EVENTS_MHRMATCH
MAC header match found
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_SYNC
Preamble indicator
0x168
read-write
EVENTS_SYNC
Preamble indicator
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_PHYEND
Generated when last bit is sent on air, or received from air
0x16C
read-write
EVENTS_PHYEND
Generated when last bit is sent on air, or received from air
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_CTEPRESENT
CTE is present (early warning right after receiving CTEInfo byte)
0x170
read-write
EVENTS_CTEPRESENT
CTE is present (early warning right after receiving CTEInfo byte)
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
PUBLISH_READY
Publish configuration for event READY
0x180
read-write
CHIDX
DPPI channel that event READY will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_ADDRESS
Publish configuration for event ADDRESS
0x184
read-write
CHIDX
DPPI channel that event ADDRESS will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_PAYLOAD
Publish configuration for event PAYLOAD
0x188
read-write
CHIDX
DPPI channel that event PAYLOAD will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_END
Publish configuration for event END
0x18C
read-write
CHIDX
DPPI channel that event END will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_DISABLED
Publish configuration for event DISABLED
0x190
read-write
CHIDX
DPPI channel that event DISABLED will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_DEVMATCH
Publish configuration for event DEVMATCH
0x194
read-write
CHIDX
DPPI channel that event DEVMATCH will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_DEVMISS
Publish configuration for event DEVMISS
0x198
read-write
CHIDX
DPPI channel that event DEVMISS will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_RSSIEND
Publish configuration for event RSSIEND
0x19C
read-write
CHIDX
DPPI channel that event RSSIEND will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_BCMATCH
Publish configuration for event BCMATCH
0x1A8
read-write
CHIDX
DPPI channel that event BCMATCH will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_CRCOK
Publish configuration for event CRCOK
0x1B0
read-write
CHIDX
DPPI channel that event CRCOK will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_CRCERROR
Publish configuration for event CRCERROR
0x1B4
read-write
CHIDX
DPPI channel that event CRCERROR will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_FRAMESTART
Publish configuration for event FRAMESTART
0x1B8
read-write
CHIDX
DPPI channel that event FRAMESTART will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_EDEND
Publish configuration for event EDEND
0x1BC
read-write
CHIDX
DPPI channel that event EDEND will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_EDSTOPPED
Publish configuration for event EDSTOPPED
0x1C0
read-write
CHIDX
DPPI channel that event EDSTOPPED will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_CCAIDLE
Publish configuration for event CCAIDLE
0x1C4
read-write
CHIDX
DPPI channel that event CCAIDLE will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_CCABUSY
Publish configuration for event CCABUSY
0x1C8
read-write
CHIDX
DPPI channel that event CCABUSY will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_CCASTOPPED
Publish configuration for event CCASTOPPED
0x1CC
read-write
CHIDX
DPPI channel that event CCASTOPPED will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_RATEBOOST
Publish configuration for event RATEBOOST
0x1D0
read-write
CHIDX
DPPI channel that event RATEBOOST will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_TXREADY
Publish configuration for event TXREADY
0x1D4
read-write
CHIDX
DPPI channel that event TXREADY will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_RXREADY
Publish configuration for event RXREADY
0x1D8
read-write
CHIDX
DPPI channel that event RXREADY will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_MHRMATCH
Publish configuration for event MHRMATCH
0x1DC
read-write
CHIDX
DPPI channel that event MHRMATCH will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_SYNC
Publish configuration for event SYNC
0x1E8
read-write
CHIDX
DPPI channel that event SYNC will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_PHYEND
Publish configuration for event PHYEND
0x1EC
read-write
CHIDX
DPPI channel that event PHYEND will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_CTEPRESENT
Publish configuration for event CTEPRESENT
0x1F0
read-write
CHIDX
DPPI channel that event CTEPRESENT will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
SHORTS
Shortcuts between local events and tasks
0x200
read-write
READY_START
Shortcut between event READY and task START
0
0
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
END_DISABLE
Shortcut between event END and task DISABLE
1
1
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
DISABLED_TXEN
Shortcut between event DISABLED and task TXEN
2
2
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
DISABLED_RXEN
Shortcut between event DISABLED and task RXEN
3
3
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
ADDRESS_RSSISTART
Shortcut between event ADDRESS and task RSSISTART
4
4
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
END_START
Shortcut between event END and task START
5
5
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
ADDRESS_BCSTART
Shortcut between event ADDRESS and task BCSTART
6
6
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
DISABLED_RSSISTOP
Shortcut between event DISABLED and task RSSISTOP
8
8
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
RXREADY_CCASTART
Shortcut between event RXREADY and task CCASTART
11
11
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
CCAIDLE_TXEN
Shortcut between event CCAIDLE and task TXEN
12
12
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
CCABUSY_DISABLE
Shortcut between event CCABUSY and task DISABLE
13
13
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
FRAMESTART_BCSTART
Shortcut between event FRAMESTART and task BCSTART
14
14
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
READY_EDSTART
Shortcut between event READY and task EDSTART
15
15
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
EDEND_DISABLE
Shortcut between event EDEND and task DISABLE
16
16
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
CCAIDLE_STOP
Shortcut between event CCAIDLE and task STOP
17
17
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
TXREADY_START
Shortcut between event TXREADY and task START
18
18
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
RXREADY_START
Shortcut between event RXREADY and task START
19
19
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
PHYEND_DISABLE
Shortcut between event PHYEND and task DISABLE
20
20
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
PHYEND_START
Shortcut between event PHYEND and task START
21
21
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
INTENSET
Enable interrupt
0x304
read-write
READY
Write '1' to enable interrupt for event READY
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
ADDRESS
Write '1' to enable interrupt for event ADDRESS
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
PAYLOAD
Write '1' to enable interrupt for event PAYLOAD
2
2
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
END
Write '1' to enable interrupt for event END
3
3
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
DISABLED
Write '1' to enable interrupt for event DISABLED
4
4
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
DEVMATCH
Write '1' to enable interrupt for event DEVMATCH
5
5
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
DEVMISS
Write '1' to enable interrupt for event DEVMISS
6
6
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RSSIEND
Write '1' to enable interrupt for event RSSIEND
7
7
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
BCMATCH
Write '1' to enable interrupt for event BCMATCH
10
10
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
CRCOK
Write '1' to enable interrupt for event CRCOK
12
12
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
CRCERROR
Write '1' to enable interrupt for event CRCERROR
13
13
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
FRAMESTART
Write '1' to enable interrupt for event FRAMESTART
14
14
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
EDEND
Write '1' to enable interrupt for event EDEND
15
15
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
EDSTOPPED
Write '1' to enable interrupt for event EDSTOPPED
16
16
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
CCAIDLE
Write '1' to enable interrupt for event CCAIDLE
17
17
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
CCABUSY
Write '1' to enable interrupt for event CCABUSY
18
18
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
CCASTOPPED
Write '1' to enable interrupt for event CCASTOPPED
19
19
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RATEBOOST
Write '1' to enable interrupt for event RATEBOOST
20
20
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
TXREADY
Write '1' to enable interrupt for event TXREADY
21
21
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RXREADY
Write '1' to enable interrupt for event RXREADY
22
22
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
MHRMATCH
Write '1' to enable interrupt for event MHRMATCH
23
23
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
SYNC
Write '1' to enable interrupt for event SYNC
26
26
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
PHYEND
Write '1' to enable interrupt for event PHYEND
27
27
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
CTEPRESENT
Write '1' to enable interrupt for event CTEPRESENT
28
28
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
INTENCLR
Disable interrupt
0x308
read-write
READY
Write '1' to disable interrupt for event READY
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
ADDRESS
Write '1' to disable interrupt for event ADDRESS
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
PAYLOAD
Write '1' to disable interrupt for event PAYLOAD
2
2
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
END
Write '1' to disable interrupt for event END
3
3
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
DISABLED
Write '1' to disable interrupt for event DISABLED
4
4
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
DEVMATCH
Write '1' to disable interrupt for event DEVMATCH
5
5
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
DEVMISS
Write '1' to disable interrupt for event DEVMISS
6
6
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RSSIEND
Write '1' to disable interrupt for event RSSIEND
7
7
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
BCMATCH
Write '1' to disable interrupt for event BCMATCH
10
10
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
CRCOK
Write '1' to disable interrupt for event CRCOK
12
12
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
CRCERROR
Write '1' to disable interrupt for event CRCERROR
13
13
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
FRAMESTART
Write '1' to disable interrupt for event FRAMESTART
14
14
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
EDEND
Write '1' to disable interrupt for event EDEND
15
15
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
EDSTOPPED
Write '1' to disable interrupt for event EDSTOPPED
16
16
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
CCAIDLE
Write '1' to disable interrupt for event CCAIDLE
17
17
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
CCABUSY
Write '1' to disable interrupt for event CCABUSY
18
18
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
CCASTOPPED
Write '1' to disable interrupt for event CCASTOPPED
19
19
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RATEBOOST
Write '1' to disable interrupt for event RATEBOOST
20
20
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
TXREADY
Write '1' to disable interrupt for event TXREADY
21
21
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RXREADY
Write '1' to disable interrupt for event RXREADY
22
22
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
MHRMATCH
Write '1' to disable interrupt for event MHRMATCH
23
23
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
SYNC
Write '1' to disable interrupt for event SYNC
26
26
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
PHYEND
Write '1' to disable interrupt for event PHYEND
27
27
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
CTEPRESENT
Write '1' to disable interrupt for event CTEPRESENT
28
28
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
CRCSTATUS
CRC status
0x400
read-only
CRCSTATUS
CRC status of packet received
0
0
CRCError
Packet received with CRC error
0
CRCOk
Packet received with CRC ok
1
RXMATCH
Received address
0x408
read-only
RXMATCH
Received address
0
2
RXCRC
CRC field of previously received packet
0x40C
read-only
RXCRC
CRC field of previously received packet
0
23
DAI
Device address match index
0x410
read-only
DAI
Device address match index
0
2
PDUSTAT
Payload status
0x414
read-only
PDUSTAT
Status on payload length vs. PCNF1.MAXLEN
0
0
LessThan
Payload less than PCNF1.MAXLEN
0
GreaterThan
Payload greater than PCNF1.MAXLEN
1
CISTAT
Status on what rate packet is received with in Long Range
1
2
LR125kbit
Frame is received at 125 kbps
0
LR500kbit
Frame is received at 500 kbps
1
CTESTATUS
CTEInfo parsed from received packet
0x44C
read-only
CTETIME
CTETime parsed from packet
0
4
RFU
RFU parsed from packet
5
5
CTETYPE
CTEType parsed from packet
6
7
DFESTATUS
DFE status information
0x458
read-only
SWITCHINGSTATE
Internal state of switching state machine
0
2
Idle
Switching state Idle
0
Offset
Switching state Offset
1
Guard
Switching state Guard
2
Ref
Switching state Ref
3
Switching
Switching state Switching
4
Ending
Switching state Ending
5
SAMPLINGSTATE
Internal state of sampling state machine
4
4
Idle
Sampling state Idle
0
Sampling
Sampling state Sampling
1
PACKETPTR
Packet pointer
0x504
read-write
0x01000000
PACKETPTR
Packet pointer
0
31
FREQUENCY
Frequency
0x508
read-write
0x00000002
FREQUENCY
Radio channel frequency
0
6
MAP
Channel map selection.
8
8
Default
Channel map between 2400 MHZ .. 2500 MHz
0
Low
Channel map between 2360 MHZ .. 2460 MHz
1
TXPOWER
Output power
0x50C
read-write
TXPOWER
RADIO output power
0
7
0dBm
0 dBm
0x0
Neg1dBm
-1 dBm
0xFF
Neg2dBm
-2 dBm
0xFE
Neg3dBm
-3 dBm
0xFD
Neg4dBm
-4 dBm
0xFC
Neg5dBm
-5 dBm
0xFB
Neg6dBm
-6 dBm
0xFA
Neg7dBm
-7 dBm
0xF9
Neg8dBm
-8 dBm
0xF8
Neg12dBm
-12 dBm
0xF4
Neg16dBm
-16 dBm
0xF0
Neg20dBm
-20 dBm
0xEC
Neg30dBm
Deprecated enumerator - -40 dBm
0xE2
Neg40dBm
-40 dBm
0xD8
MODE
Data rate and modulation
0x510
read-write
MODE
Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation.
0
3
Nrf_1Mbit
1 Mbps Nordic proprietary radio mode
0
Nrf_2Mbit
2 Mbps Nordic proprietary radio mode
1
Ble_1Mbit
1 Mbps BLE
3
Ble_2Mbit
2 Mbps BLE
4
Ble_LR125Kbit
Long range 125 kbps TX, 125 kbps and 500 kbps RX
5
Ble_LR500Kbit
Long range 500 kbps TX, 125 kbps and 500 kbps RX
6
Ieee802154_250Kbit
IEEE 802.15.4-2006 250 kbps
15
PCNF0
Packet configuration register 0
0x514
read-write
LFLEN
Length on air of LENGTH field in number of bits.
0
3
S0LEN
Length on air of S0 field in number of bytes.
8
8
S1LEN
Length on air of S1 field in number of bits.
16
19
S1INCL
Include or exclude S1 field in RAM
20
20
Automatic
Include S1 field in RAM only if S1LEN > 0
0
Include
Always include S1 field in RAM independent of S1LEN
1
CILEN
Length of code indicator - long range
22
23
PLEN
Length of preamble on air. Decision point: TASKS_START task
24
25
8bit
8-bit preamble
0
16bit
16-bit preamble
1
32bitZero
32-bit zero preamble - used for IEEE 802.15.4
2
LongRange
Preamble - used for BLE long range
3
CRCINC
Indicates if LENGTH field contains CRC or not
26
26
Exclude
LENGTH does not contain CRC
0
Include
LENGTH includes CRC
1
TERMLEN
Length of TERM field in Long Range operation
29
30
PCNF1
Packet configuration register 1
0x518
read-write
MAXLEN
Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN.
0
7
STATLEN
Static length in number of bytes
8
15
BALEN
Base address length in number of bytes
16
18
ENDIAN
On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields.
24
24
Little
Least significant bit on air first
0
Big
Most significant bit on air first
1
WHITEEN
Enable or disable packet whitening
25
25
Disabled
Disable
0
Enabled
Enable
1
BASE0
Base address 0
0x51C
read-write
BASE0
Base address 0
0
31
BASE1
Base address 1
0x520
read-write
BASE1
Base address 1
0
31
PREFIX0
Prefixes bytes for logical addresses 0-3
0x524
read-write
AP0
Address prefix 0.
0
7
AP1
Address prefix 1.
8
15
AP2
Address prefix 2.
16
23
AP3
Address prefix 3.
24
31
PREFIX1
Prefixes bytes for logical addresses 4-7
0x528
read-write
AP4
Address prefix 4.
0
7
AP5
Address prefix 5.
8
15
AP6
Address prefix 6.
16
23
AP7
Address prefix 7.
24
31
TXADDRESS
Transmit address select
0x52C
read-write
TXADDRESS
Transmit address select
0
2
RXADDRESSES
Receive address select
0x530
read-write
ADDR0
Enable or disable reception on logical address 0.
0
0
Disabled
Disable
0
Enabled
Enable
1
ADDR1
Enable or disable reception on logical address 1.
1
1
Disabled
Disable
0
Enabled
Enable
1
ADDR2
Enable or disable reception on logical address 2.
2
2
Disabled
Disable
0
Enabled
Enable
1
ADDR3
Enable or disable reception on logical address 3.
3
3
Disabled
Disable
0
Enabled
Enable
1
ADDR4
Enable or disable reception on logical address 4.
4
4
Disabled
Disable
0
Enabled
Enable
1
ADDR5
Enable or disable reception on logical address 5.
5
5
Disabled
Disable
0
Enabled
Enable
1
ADDR6
Enable or disable reception on logical address 6.
6
6
Disabled
Disable
0
Enabled
Enable
1
ADDR7
Enable or disable reception on logical address 7.
7
7
Disabled
Disable
0
Enabled
Enable
1
CRCCNF
CRC configuration
0x534
read-write
LEN
CRC length in number of bytes.
0
1
Disabled
CRC length is zero and CRC calculation is disabled
0
One
CRC length is one byte and CRC calculation is enabled
1
Two
CRC length is two bytes and CRC calculation is enabled
2
Three
CRC length is three bytes and CRC calculation is enabled
3
SKIPADDR
Include or exclude packet address field out of CRC calculation.
8
9
Include
CRC calculation includes address field
0
Skip
CRC calculation does not include address field. The CRC calculation will start at the first byte after the address.
1
Ieee802154
CRC calculation as per 802.15.4 standard. Starting at first byte after length field.
2
CRCPOLY
CRC polynomial
0x538
read-write
0x00000000
CRCPOLY
CRC polynomial
0
23
CRCINIT
CRC initial value
0x53C
read-write
CRCINIT
CRC initial value
0
23
TIFS
Interframe spacing in us
0x544
read-write
TIFS
Interframe spacing in us
0
9
RSSISAMPLE
RSSI sample
0x548
read-only
RSSISAMPLE
RSSI sample
0
6
STATE
Current radio state
0x550
read-only
STATE
Current radio state
0
3
Disabled
RADIO is in the Disabled state
0
RxRu
RADIO is in the RXRU state
1
RxIdle
RADIO is in the RXIDLE state
2
Rx
RADIO is in the RX state
3
RxDisable
RADIO is in the RXDISABLED state
4
TxRu
RADIO is in the TXRU state
9
TxIdle
RADIO is in the TXIDLE state
10
Tx
RADIO is in the TX state
11
TxDisable
RADIO is in the TXDISABLED state
12
DATAWHITEIV
Data whitening initial value
0x554
read-write
0x00000040
DATAWHITEIV
Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'.
0
6
BCC
Bit counter compare
0x560
read-write
BCC
Bit counter compare
0
31
0x8
0x4
DAB[%s]
Description collection: Device address base segment n
0x600
read-write
DAB
Device address base segment n
0
31
0x8
0x4
DAP[%s]
Description collection: Device address prefix n
0x620
read-write
DAP
Device address prefix n
0
15
DACNF
Device address match configuration
0x640
read-write
ENA0
Enable or disable device address matching using device address 0
0
0
Disabled
Disabled
0
Enabled
Enabled
1
ENA1
Enable or disable device address matching using device address 1
1
1
Disabled
Disabled
0
Enabled
Enabled
1
ENA2
Enable or disable device address matching using device address 2
2
2
Disabled
Disabled
0
Enabled
Enabled
1
ENA3
Enable or disable device address matching using device address 3
3
3
Disabled
Disabled
0
Enabled
Enabled
1
ENA4
Enable or disable device address matching using device address 4
4
4
Disabled
Disabled
0
Enabled
Enabled
1
ENA5
Enable or disable device address matching using device address 5
5
5
Disabled
Disabled
0
Enabled
Enabled
1
ENA6
Enable or disable device address matching using device address 6
6
6
Disabled
Disabled
0
Enabled
Enabled
1
ENA7
Enable or disable device address matching using device address 7
7
7
Disabled
Disabled
0
Enabled
Enabled
1
TXADD0
TxAdd for device address 0
8
8
TXADD1
TxAdd for device address 1
9
9
TXADD2
TxAdd for device address 2
10
10
TXADD3
TxAdd for device address 3
11
11
TXADD4
TxAdd for device address 4
12
12
TXADD5
TxAdd for device address 5
13
13
TXADD6
TxAdd for device address 6
14
14
TXADD7
TxAdd for device address 7
15
15
MHRMATCHCONF
Search pattern configuration
0x644
read-write
MHRMATCHCONF
Search pattern configuration
0
31
MHRMATCHMAS
Pattern mask
0x648
read-write
MHRMATCHMAS
Pattern mask
0
31
MODECNF0
Radio mode configuration register 0
0x650
read-write
0x00000200
RU
Radio ramp-up time
0
0
Default
Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51
0
Fast
Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information
1
DTX
Default TX value
8
9
B1
Transmit '1'
0
B0
Transmit '0'
1
Center
Transmit center frequency
2
SFD
IEEE 802.15.4 start of frame delimiter
0x660
read-write
0x000000A7
SFD
IEEE 802.15.4 start of frame delimiter
0
7
EDCNT
IEEE 802.15.4 energy detect loop count
0x664
read-write
0x00000000
EDCNT
IEEE 802.15.4 energy detect loop count
0
20
EDSAMPLE
IEEE 802.15.4 energy detect level
0x668
read-only
0x00000000
EDLVL
IEEE 802.15.4 energy detect level
0
7
CCACTRL
IEEE 802.15.4 clear channel assessment control
0x66C
read-write
0x052D0000
CCAMODE
CCA mode of operation
0
2
EdMode
Energy above threshold
0
CarrierMode
Carrier seen
1
CarrierAndEdMode
Energy above threshold AND carrier seen
2
CarrierOrEdMode
Energy above threshold OR carrier seen
3
EdModeTest1
Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging.
4
CCAEDTHRES
CCA energy busy threshold. Used in all the CCA modes except CarrierMode.
8
15
CCACORRTHRES
CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode.
16
23
CCACORRCNT
Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled.
24
31
DFEMODE
Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD)
0x900
read-write
0x00000000
DFEOPMODE
Direction finding operation mode
0
1
Disabled
Direction finding mode disabled
0
AoD
Direction finding mode set to AoD
2
AoA
Direction finding mode set to AoA
3
CTEINLINECONF
Configuration for CTE inline mode
0x904
read-write
0x00002800
CTEINLINECTRLEN
Enable parsing of CTEInfo from received packet in BLE modes
0
0
Enabled
Parsing of CTEInfo is enabled
1
Disabled
Parsing of CTEInfo is disabled
0
CTEINFOINS1
CTEInfo is S1 byte or not
3
3
InS1
CTEInfo is in S1 byte (data PDU)
1
NotInS1
CTEInfo is NOT in S1 byte (advertising PDU)
0
CTEERRORHANDLING
Sampling/switching if CRC is not OK
4
4
Yes
Sampling and antenna switching also when CRC is not OK
1
No
No sampling and antenna switching when CRC is not OK
0
CTETIMEVALIDRANGE
Max range of CTETime
6
7
20
20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20
0
31
31 in 8us unit
1
63
63 in 8us unit
2
CTEINLINERXMODE1US
Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set
10
12
4us
4us
1
2us
2us
2
1us
1us
3
500ns
0.5us
4
250ns
0.25us
5
125ns
0.125us
6
CTEINLINERXMODE2US
Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set
13
15
4us
4us
1
2us
2us
2
1us
1us
3
500ns
0.5us
4
250ns
0.25us
5
125ns
0.125us
6
S0CONF
S0 bit pattern to match
16
23
S0MASK
S0 bit mask to set which bit to match
24
31
DFECTRL1
Various configuration for Direction finding
0x910
read-write
0x00023282
NUMBEROF8US
Length of the AoA/AoD procedure in number of 8 us units
0
5
DFEINEXTENSION
Add CTE extension and do antenna switching/sampling in this extension
7
7
CRC
AoA/AoD procedure triggered at end of CRC
1
Payload
Antenna switching/sampling is done in the packet payload
0
TSWITCHSPACING
Interval between every time the antenna is changed in the SWITCHING state
8
10
4us
4us
1
2us
2us
2
1us
1us
3
TSAMPLESPACINGREF
Interval between samples in the REFERENCE period
12
14
4us
4us
1
2us
2us
2
1us
1us
3
500ns
0.5us
4
250ns
0.25us
5
125ns
0.125us
6
SAMPLETYPE
Whether to sample I/Q or magnitude/phase
15
15
IQ
Complex samples in I and Q
0
MagPhase
Complex samples as magnitude and phase
1
TSAMPLESPACING
Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0
16
18
4us
4us
1
2us
2us
2
1us
1us
3
500ns
0.5us
4
250ns
0.25us
5
125ns
0.125us
6
REPEATPATTERN
Repeat each individual antenna pattern N times sequentially, i.e. P0, P0, P1, P1, P2, P2, P3, P3, etc.
20
23
NoRepeat
Do not repeat (1 time in total)
0
AGCBACKOFFGAIN
Gain will be lowered by the specified number of gain steps at the start of CTE
24
27
DFECTRL2
Start offset for Direction finding
0x914
read-write
0x00000000
TSWITCHOFFSET
Signed value offset after the end of the CRC before starting switching in number of 16M cycles
0
12
TSAMPLEOFFSET
Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 us after switching start
16
27
SWITCHPATTERN
GPIO patterns to be used for each antenna
0x928
read-write
0x00000000
SWITCHPATTERN
Fill array of GPIO patterns for antenna control
0
7
CLEARPATTERN
Clear the GPIO pattern array for antenna control
0x92C
read-write
CLEARPATTERN
Clears GPIO pattern array for antenna control
0
0
oneToClear
Clear
Clear the GPIO pattern
1
PSEL
Unspecified
RADIO_PSEL
read-write
0x930
0x8
0x4
DFEGPIO[%s]
Description collection: Pin select for DFE pin n
0x000
read-write
0xFFFFFFFF
PIN
Pin number
0
4
PORT
Port number
5
5
CONNECT
Connection
31
31
Disconnected
Disconnect
1
Connected
Connect
0
DFEPACKET
DFE packet EasyDMA channel
RADIO_DFEPACKET
read-write
0x950
PTR
Data pointer
0x000
read-write
0x01000000
PTR
Data pointer
0
31
MAXCNT
Maximum number of buffer words to transfer
0x004
read-write
0x00001000
MAXCNT
Maximum number of buffer words to transfer
0
13
AMOUNT
Number of samples transferred in the last transaction
0x008
read-only
AMOUNT
Number of samples transferred in the last transaction
0
15
POWER
Peripheral power control
0xFFC
read-write
0x00000001
POWER
Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again.
0
0
Disabled
Peripheral is powered off
0
Enabled
Peripheral is powered on
1
RNG_NS
Random Number Generator
0x41009000
RNG
0
0x1000
registers
RNG
9
RNG
0x20
TASKS_START
Task starting the random number generator
0x000
write-only
TASKS_START
Task starting the random number generator
0
0
Trigger
Trigger task
1
TASKS_STOP
Task stopping the random number generator
0x004
write-only
TASKS_STOP
Task stopping the random number generator
0
0
Trigger
Trigger task
1
SUBSCRIBE_START
Subscribe configuration for task START
0x080
read-write
CHIDX
DPPI channel that task START will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_STOP
Subscribe configuration for task STOP
0x084
read-write
CHIDX
DPPI channel that task STOP will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
EVENTS_VALRDY
Event being generated for every new random number written to the VALUE register
0x100
read-write
EVENTS_VALRDY
Event being generated for every new random number written to the VALUE register
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
PUBLISH_VALRDY
Publish configuration for event VALRDY
0x180
read-write
CHIDX
DPPI channel that event VALRDY will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
SHORTS
Shortcuts between local events and tasks
0x200
read-write
VALRDY_STOP
Shortcut between event VALRDY and task STOP
0
0
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
INTENSET
Enable interrupt
0x304
read-write
VALRDY
Write '1' to enable interrupt for event VALRDY
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
INTENCLR
Disable interrupt
0x308
read-write
VALRDY
Write '1' to disable interrupt for event VALRDY
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
CONFIG
Configuration register
0x504
read-write
DERCEN
Bias correction
0
0
Disabled
Disabled
0
Enabled
Enabled
1
VALUE
Output random number
0x508
read-only
VALUE
Generated random number
0
7
GPIOTE_NS
GPIO Tasks and Events
0x4100A000
GPIOTE
0
0x1000
registers
GPIOTE
10
GPIOTE
0x20
0x8
0x4
TASKS_OUT[%s]
Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
0x000
write-only
TASKS_OUT
Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
0
0
Trigger
Trigger task
1
0x8
0x4
TASKS_SET[%s]
Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
0x030
write-only
TASKS_SET
Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
0
0
Trigger
Trigger task
1
0x8
0x4
TASKS_CLR[%s]
Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
0x060
write-only
TASKS_CLR
Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
0
0
Trigger
Trigger task
1
0x8
0x4
SUBSCRIBE_OUT[%s]
Description collection: Subscribe configuration for task OUT[n]
0x080
read-write
CHIDX
DPPI channel that task OUT[n] will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
0x8
0x4
SUBSCRIBE_SET[%s]
Description collection: Subscribe configuration for task SET[n]
0x0B0
read-write
CHIDX
DPPI channel that task SET[n] will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
0x8
0x4
SUBSCRIBE_CLR[%s]
Description collection: Subscribe configuration for task CLR[n]
0x0E0
read-write
CHIDX
DPPI channel that task CLR[n] will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
0x8
0x4
EVENTS_IN[%s]
Description collection: Event generated from pin specified in CONFIG[n].PSEL
0x100
read-write
EVENTS_IN
Event generated from pin specified in CONFIG[n].PSEL
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_PORT
Event generated from multiple input GPIO pins with SENSE mechanism enabled
0x17C
read-write
EVENTS_PORT
Event generated from multiple input GPIO pins with SENSE mechanism enabled
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
0x8
0x4
PUBLISH_IN[%s]
Description collection: Publish configuration for event IN[n]
0x180
read-write
CHIDX
DPPI channel that event IN[n] will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_PORT
Publish configuration for event PORT
0x1FC
read-write
CHIDX
DPPI channel that event PORT will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
INTENSET
Enable interrupt
0x304
read-write
IN0
Write '1' to enable interrupt for event IN[0]
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
IN1
Write '1' to enable interrupt for event IN[1]
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
IN2
Write '1' to enable interrupt for event IN[2]
2
2
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
IN3
Write '1' to enable interrupt for event IN[3]
3
3
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
IN4
Write '1' to enable interrupt for event IN[4]
4
4
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
IN5
Write '1' to enable interrupt for event IN[5]
5
5
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
IN6
Write '1' to enable interrupt for event IN[6]
6
6
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
IN7
Write '1' to enable interrupt for event IN[7]
7
7
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
PORT
Write '1' to enable interrupt for event PORT
31
31
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
INTENCLR
Disable interrupt
0x308
read-write
IN0
Write '1' to disable interrupt for event IN[0]
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
IN1
Write '1' to disable interrupt for event IN[1]
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
IN2
Write '1' to disable interrupt for event IN[2]
2
2
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
IN3
Write '1' to disable interrupt for event IN[3]
3
3
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
IN4
Write '1' to disable interrupt for event IN[4]
4
4
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
IN5
Write '1' to disable interrupt for event IN[5]
5
5
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
IN6
Write '1' to disable interrupt for event IN[6]
6
6
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
IN7
Write '1' to disable interrupt for event IN[7]
7
7
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
PORT
Write '1' to disable interrupt for event PORT
31
31
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
LATENCY
Latency selection for Event mode (MODE=Event) with rising or falling edge detection on the pin.
0x504
read-write
0x00000001
LATENCY
Latency setting
0
0
LowPower
Low power setting, for signals with minimum hold time tGPIOTE,HOLD,LP; refer to Electrical specification section
0
LowLatency
Low latency setting, for signals with minimum hold time tGPIOTE,HOLD,LL; refer to Electrical specification section
1
0x8
0x4
CONFIG[%s]
Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event
0x510
read-write
MODE
Mode
0
1
Disabled
Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.
0
Event
Event mode
1
Task
Task mode
3
PSEL
GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event
8
12
PORT
Port number
13
13
POLARITY
When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.
16
17
None
Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.
0
LoToHi
Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.
1
HiToLo
Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.
2
Toggle
Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.
3
OUTINIT
When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.
20
20
Low
Task mode: Initial value of pin before task triggering is low
0
High
Task mode: Initial value of pin before task triggering is high
1
WDT_NS
Watchdog Timer
0x4100B000
WDT
0
0x1000
registers
WDT
11
WDT
0x20
TASKS_START
Start the watchdog
0x000
write-only
TASKS_START
Start the watchdog
0
0
Trigger
Trigger task
1
TASKS_STOP
Stop the watchdog timer.
0x004
write-only
TASKS_STOP
Stop the watchdog timer.
0
0
Trigger
Trigger task
1
SUBSCRIBE_START
Subscribe configuration for task START
0x080
read-write
CHIDX
DPPI channel that task START will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_STOP
Subscribe configuration for task STOP
0x084
read-write
CHIDX
DPPI channel that task STOP will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
EVENTS_TIMEOUT
Watchdog timeout
0x100
read-write
EVENTS_TIMEOUT
Watchdog timeout
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_STOPPED
Watchdog stopped
0x104
read-write
EVENTS_STOPPED
Watchdog stopped
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
PUBLISH_TIMEOUT
Publish configuration for event TIMEOUT
0x180
read-write
CHIDX
DPPI channel that event TIMEOUT will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_STOPPED
Publish configuration for event STOPPED
0x184
read-write
CHIDX
DPPI channel that event STOPPED will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
INTENSET
Enable interrupt
0x304
read-write
TIMEOUT
Write '1' to enable interrupt for event TIMEOUT
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
STOPPED
Write '1' to enable interrupt for event STOPPED
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
INTENCLR
Disable interrupt
0x308
read-write
TIMEOUT
Write '1' to disable interrupt for event TIMEOUT
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
STOPPED
Write '1' to disable interrupt for event STOPPED
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
NMIENSET
Enable interrupt
0x324
read-write
TIMEOUT
Write '1' to enable interrupt for event TIMEOUT
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
STOPPED
Write '1' to enable interrupt for event STOPPED
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
NMIENCLR
Disable interrupt
0x328
read-write
TIMEOUT
Write '1' to disable interrupt for event TIMEOUT
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
STOPPED
Write '1' to disable interrupt for event STOPPED
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RUNSTATUS
Run status
0x400
read-only
RUNSTATUSWDT
Indicates whether or not the watchdog is running
0
0
NotRunning
Watchdog not running
0
Running
Watchdog is running
1
REQSTATUS
Request status
0x404
read-only
0x00000001
RR0
Request status for RR[0] register
0
0
DisabledOrRequested
RR[0] register is not enabled, or are already requesting reload
0
EnabledAndUnrequested
RR[0] register is enabled, and are not yet requesting reload
1
RR1
Request status for RR[1] register
1
1
DisabledOrRequested
RR[1] register is not enabled, or are already requesting reload
0
EnabledAndUnrequested
RR[1] register is enabled, and are not yet requesting reload
1
RR2
Request status for RR[2] register
2
2
DisabledOrRequested
RR[2] register is not enabled, or are already requesting reload
0
EnabledAndUnrequested
RR[2] register is enabled, and are not yet requesting reload
1
RR3
Request status for RR[3] register
3
3
DisabledOrRequested
RR[3] register is not enabled, or are already requesting reload
0
EnabledAndUnrequested
RR[3] register is enabled, and are not yet requesting reload
1
RR4
Request status for RR[4] register
4
4
DisabledOrRequested
RR[4] register is not enabled, or are already requesting reload
0
EnabledAndUnrequested
RR[4] register is enabled, and are not yet requesting reload
1
RR5
Request status for RR[5] register
5
5
DisabledOrRequested
RR[5] register is not enabled, or are already requesting reload
0
EnabledAndUnrequested
RR[5] register is enabled, and are not yet requesting reload
1
RR6
Request status for RR[6] register
6
6
DisabledOrRequested
RR[6] register is not enabled, or are already requesting reload
0
EnabledAndUnrequested
RR[6] register is enabled, and are not yet requesting reload
1
RR7
Request status for RR[7] register
7
7
DisabledOrRequested
RR[7] register is not enabled, or are already requesting reload
0
EnabledAndUnrequested
RR[7] register is enabled, and are not yet requesting reload
1
CRV
Counter reload value
0x504
read-write
0xFFFFFFFF
CRV
Counter reload value in number of cycles of the 32.768 kHz clock
0
31
RREN
Enable register for reload request registers
0x508
read-write
0x00000001
RR0
Enable or disable RR[0] register
0
0
Disabled
Disable RR[0] register
0
Enabled
Enable RR[0] register
1
RR1
Enable or disable RR[1] register
1
1
Disabled
Disable RR[1] register
0
Enabled
Enable RR[1] register
1
RR2
Enable or disable RR[2] register
2
2
Disabled
Disable RR[2] register
0
Enabled
Enable RR[2] register
1
RR3
Enable or disable RR[3] register
3
3
Disabled
Disable RR[3] register
0
Enabled
Enable RR[3] register
1
RR4
Enable or disable RR[4] register
4
4
Disabled
Disable RR[4] register
0
Enabled
Enable RR[4] register
1
RR5
Enable or disable RR[5] register
5
5
Disabled
Disable RR[5] register
0
Enabled
Enable RR[5] register
1
RR6
Enable or disable RR[6] register
6
6
Disabled
Disable RR[6] register
0
Enabled
Enable RR[6] register
1
RR7
Enable or disable RR[7] register
7
7
Disabled
Disable RR[7] register
0
Enabled
Enable RR[7] register
1
CONFIG
Configuration register
0x50C
read-write
0x00000001
SLEEP
Configure the watchdog to either be paused, or kept running, while the CPU is sleeping
0
0
Pause
Pause watchdog while the CPU is sleeping
0
Run
Keep the watchdog running while the CPU is sleeping
1
HALT
Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger
3
3
Pause
Pause watchdog while the CPU is halted by the debugger
0
Run
Keep the watchdog running while the CPU is halted by the debugger
1
STOPEN
Allow stopping the watchdog
6
6
Disable
Do not allow stopping the watchdog
0
Enable
Allow stopping the watchdog
1
TSEN
Task Stop Enable
0x520
write-only
0x00000000
TSEN
Task stop enable register
0
31
Enable
Value to allow stopping the watchdog
0x6E524635
0x8
0x4
RR[%s]
Description collection: Reload request n
0x600
write-only
RR
Reload request register
0
31
Reload
Value to request a reload of the watchdog timer
0x6E524635
TIMER0_NS
Timer/Counter 0
0x4100C000
TIMER
0
0x1000
registers
TIMER0
12
TIMER
0x20
TASKS_START
Start Timer
0x000
write-only
TASKS_START
Start Timer
0
0
Trigger
Trigger task
1
TASKS_STOP
Stop Timer
0x004
write-only
TASKS_STOP
Stop Timer
0
0
Trigger
Trigger task
1
TASKS_COUNT
Increment Timer (Counter mode only)
0x008
write-only
TASKS_COUNT
Increment Timer (Counter mode only)
0
0
Trigger
Trigger task
1
TASKS_CLEAR
Clear time
0x00C
write-only
TASKS_CLEAR
Clear time
0
0
Trigger
Trigger task
1
TASKS_SHUTDOWN
Deprecated register - Shut down timer
0x010
write-only
TASKS_SHUTDOWN
Deprecated field - Shut down timer
0
0
Trigger
Trigger task
1
0x8
0x4
TASKS_CAPTURE[%s]
Description collection: Capture Timer value to CC[n] register
0x040
write-only
TASKS_CAPTURE
Capture Timer value to CC[n] register
0
0
Trigger
Trigger task
1
SUBSCRIBE_START
Subscribe configuration for task START
0x080
read-write
CHIDX
DPPI channel that task START will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_STOP
Subscribe configuration for task STOP
0x084
read-write
CHIDX
DPPI channel that task STOP will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_COUNT
Subscribe configuration for task COUNT
0x088
read-write
CHIDX
DPPI channel that task COUNT will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_CLEAR
Subscribe configuration for task CLEAR
0x08C
read-write
CHIDX
DPPI channel that task CLEAR will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_SHUTDOWN
Deprecated register - Subscribe configuration for task SHUTDOWN
0x090
read-write
CHIDX
DPPI channel that task SHUTDOWN will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
0x8
0x4
SUBSCRIBE_CAPTURE[%s]
Description collection: Subscribe configuration for task CAPTURE[n]
0x0C0
read-write
CHIDX
DPPI channel that task CAPTURE[n] will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
0x8
0x4
EVENTS_COMPARE[%s]
Description collection: Compare event on CC[n] match
0x140
read-write
EVENTS_COMPARE
Compare event on CC[n] match
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
0x8
0x4
PUBLISH_COMPARE[%s]
Description collection: Publish configuration for event COMPARE[n]
0x1C0
read-write
CHIDX
DPPI channel that event COMPARE[n] will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
SHORTS
Shortcuts between local events and tasks
0x200
read-write
COMPARE0_CLEAR
Shortcut between event COMPARE[0] and task CLEAR
0
0
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
COMPARE1_CLEAR
Shortcut between event COMPARE[1] and task CLEAR
1
1
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
COMPARE2_CLEAR
Shortcut between event COMPARE[2] and task CLEAR
2
2
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
COMPARE3_CLEAR
Shortcut between event COMPARE[3] and task CLEAR
3
3
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
COMPARE4_CLEAR
Shortcut between event COMPARE[4] and task CLEAR
4
4
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
COMPARE5_CLEAR
Shortcut between event COMPARE[5] and task CLEAR
5
5
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
COMPARE6_CLEAR
Shortcut between event COMPARE[6] and task CLEAR
6
6
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
COMPARE7_CLEAR
Shortcut between event COMPARE[7] and task CLEAR
7
7
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
COMPARE0_STOP
Shortcut between event COMPARE[0] and task STOP
16
16
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
COMPARE1_STOP
Shortcut between event COMPARE[1] and task STOP
17
17
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
COMPARE2_STOP
Shortcut between event COMPARE[2] and task STOP
18
18
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
COMPARE3_STOP
Shortcut between event COMPARE[3] and task STOP
19
19
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
COMPARE4_STOP
Shortcut between event COMPARE[4] and task STOP
20
20
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
COMPARE5_STOP
Shortcut between event COMPARE[5] and task STOP
21
21
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
COMPARE6_STOP
Shortcut between event COMPARE[6] and task STOP
22
22
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
COMPARE7_STOP
Shortcut between event COMPARE[7] and task STOP
23
23
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
INTEN
Enable or disable interrupt
0x300
read-write
COMPARE0
Enable or disable interrupt for event COMPARE[0]
16
16
Disabled
Disable
0
Enabled
Enable
1
COMPARE1
Enable or disable interrupt for event COMPARE[1]
17
17
Disabled
Disable
0
Enabled
Enable
1
COMPARE2
Enable or disable interrupt for event COMPARE[2]
18
18
Disabled
Disable
0
Enabled
Enable
1
COMPARE3
Enable or disable interrupt for event COMPARE[3]
19
19
Disabled
Disable
0
Enabled
Enable
1
COMPARE4
Enable or disable interrupt for event COMPARE[4]
20
20
Disabled
Disable
0
Enabled
Enable
1
COMPARE5
Enable or disable interrupt for event COMPARE[5]
21
21
Disabled
Disable
0
Enabled
Enable
1
COMPARE6
Enable or disable interrupt for event COMPARE[6]
22
22
Disabled
Disable
0
Enabled
Enable
1
COMPARE7
Enable or disable interrupt for event COMPARE[7]
23
23
Disabled
Disable
0
Enabled
Enable
1
INTENSET
Enable interrupt
0x304
read-write
COMPARE0
Write '1' to enable interrupt for event COMPARE[0]
16
16
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
COMPARE1
Write '1' to enable interrupt for event COMPARE[1]
17
17
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
COMPARE2
Write '1' to enable interrupt for event COMPARE[2]
18
18
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
COMPARE3
Write '1' to enable interrupt for event COMPARE[3]
19
19
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
COMPARE4
Write '1' to enable interrupt for event COMPARE[4]
20
20
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
COMPARE5
Write '1' to enable interrupt for event COMPARE[5]
21
21
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
COMPARE6
Write '1' to enable interrupt for event COMPARE[6]
22
22
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
COMPARE7
Write '1' to enable interrupt for event COMPARE[7]
23
23
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
INTENCLR
Disable interrupt
0x308
read-write
COMPARE0
Write '1' to disable interrupt for event COMPARE[0]
16
16
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
COMPARE1
Write '1' to disable interrupt for event COMPARE[1]
17
17
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
COMPARE2
Write '1' to disable interrupt for event COMPARE[2]
18
18
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
COMPARE3
Write '1' to disable interrupt for event COMPARE[3]
19
19
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
COMPARE4
Write '1' to disable interrupt for event COMPARE[4]
20
20
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
COMPARE5
Write '1' to disable interrupt for event COMPARE[5]
21
21
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
COMPARE6
Write '1' to disable interrupt for event COMPARE[6]
22
22
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
COMPARE7
Write '1' to disable interrupt for event COMPARE[7]
23
23
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
MODE
Timer mode selection
0x504
read-write
MODE
Timer mode
0
1
Timer
Select Timer mode
0
Counter
Deprecated enumerator - Select Counter mode
1
LowPowerCounter
Select Low Power Counter mode
2
BITMODE
Configure the number of bits used by the TIMER
0x508
read-write
BITMODE
Timer bit width
0
1
16Bit
16 bit timer bit width
0
08Bit
8 bit timer bit width
1
24Bit
24 bit timer bit width
2
32Bit
32 bit timer bit width
3
PRESCALER
Timer prescaler register
0x510
read-write
0x00000004
PRESCALER
Prescaler value
0
3
0x8
0x4
CC[%s]
Description collection: Capture/Compare register n
0x540
read-write
CC
Capture/Compare value
0
31
0x8
0x4
ONESHOTEN[%s]
Description collection: Enable one-shot operation for Capture/Compare channel n
0x580
read-write
ONESHOTEN
Enable one-shot operation
0
0
Disable
Disable one-shot operation
0
Enable
Enable one-shot operation
1
ECB_NS
AES ECB Mode Encryption
0x4100D000
ECB
0
0x1000
registers
ECB
13
ECB
0x20
TASKS_STARTECB
Start ECB block encrypt
0x000
write-only
TASKS_STARTECB
Start ECB block encrypt
0
0
Trigger
Trigger task
1
TASKS_STOPECB
Abort a possible executing ECB operation
0x004
write-only
TASKS_STOPECB
Abort a possible executing ECB operation
0
0
Trigger
Trigger task
1
SUBSCRIBE_STARTECB
Subscribe configuration for task STARTECB
0x080
read-write
CHIDX
DPPI channel that task STARTECB will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_STOPECB
Subscribe configuration for task STOPECB
0x084
read-write
CHIDX
DPPI channel that task STOPECB will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
EVENTS_ENDECB
ECB block encrypt complete
0x100
read-write
EVENTS_ENDECB
ECB block encrypt complete
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_ERRORECB
ECB block encrypt aborted because of a STOPECB task or due to an error
0x104
read-write
EVENTS_ERRORECB
ECB block encrypt aborted because of a STOPECB task or due to an error
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
PUBLISH_ENDECB
Publish configuration for event ENDECB
0x180
read-write
CHIDX
DPPI channel that event ENDECB will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_ERRORECB
Publish configuration for event ERRORECB
0x184
read-write
CHIDX
DPPI channel that event ERRORECB will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
INTENSET
Enable interrupt
0x304
read-write
ENDECB
Write '1' to enable interrupt for event ENDECB
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
ERRORECB
Write '1' to enable interrupt for event ERRORECB
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
INTENCLR
Disable interrupt
0x308
read-write
ENDECB
Write '1' to disable interrupt for event ENDECB
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
ERRORECB
Write '1' to disable interrupt for event ERRORECB
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
ECBDATAPTR
ECB block encrypt memory pointers
0x504
read-write
ECBDATAPTR
Pointer to the ECB data structure (see Table 1 ECB data structure overview)
0
31
AAR_NS
Accelerated Address Resolver
0x4100E000
AAR
0
0x1000
registers
AAR_CCM
14
AAR
0x20
TASKS_START
Start resolving addresses based on IRKs specified in the IRK data structure
0x000
write-only
TASKS_START
Start resolving addresses based on IRKs specified in the IRK data structure
0
0
Trigger
Trigger task
1
TASKS_STOP
Stop resolving addresses
0x008
write-only
TASKS_STOP
Stop resolving addresses
0
0
Trigger
Trigger task
1
SUBSCRIBE_START
Subscribe configuration for task START
0x080
read-write
CHIDX
DPPI channel that task START will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_STOP
Subscribe configuration for task STOP
0x088
read-write
CHIDX
DPPI channel that task STOP will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
EVENTS_END
Address resolution procedure complete
0x100
read-write
EVENTS_END
Address resolution procedure complete
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_RESOLVED
Address resolved
0x104
read-write
EVENTS_RESOLVED
Address resolved
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_NOTRESOLVED
Address not resolved
0x108
read-write
EVENTS_NOTRESOLVED
Address not resolved
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
PUBLISH_END
Publish configuration for event END
0x180
read-write
CHIDX
DPPI channel that event END will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_RESOLVED
Publish configuration for event RESOLVED
0x184
read-write
CHIDX
DPPI channel that event RESOLVED will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_NOTRESOLVED
Publish configuration for event NOTRESOLVED
0x188
read-write
CHIDX
DPPI channel that event NOTRESOLVED will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
INTENSET
Enable interrupt
0x304
read-write
END
Write '1' to enable interrupt for event END
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RESOLVED
Write '1' to enable interrupt for event RESOLVED
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
NOTRESOLVED
Write '1' to enable interrupt for event NOTRESOLVED
2
2
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
INTENCLR
Disable interrupt
0x308
read-write
END
Write '1' to disable interrupt for event END
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RESOLVED
Write '1' to disable interrupt for event RESOLVED
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
NOTRESOLVED
Write '1' to disable interrupt for event NOTRESOLVED
2
2
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
STATUS
Resolution status
0x400
read-only
STATUS
The IRK that was used last time an address was resolved
0
3
ENABLE
Enable AAR
0x500
read-write
ENABLE
Enable or disable AAR
0
1
Disabled
Disable
0
Enabled
Enable
3
NIRK
Number of IRKs
0x504
read-write
0x00000001
NIRK
Number of Identity root keys available in the IRK data structure
0
4
IRKPTR
Pointer to IRK data structure
0x508
read-write
IRKPTR
Pointer to the IRK data structure
0
31
ADDRPTR
Pointer to the resolvable address
0x510
read-write
ADDRPTR
Pointer to the resolvable address (6-bytes)
0
31
SCRATCHPTR
Pointer to data area used for temporary storage
0x514
read-write
SCRATCHPTR
Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved.
0
31
CCM_NS
AES CCM mode encryption
0x4100E000
AAR_NS
CCM
0
0x1000
registers
AAR_CCM
14
CCM
0x20
TASKS_KSGEN
Start generation of keystream. This operation will stop by itself when completed.
0x000
write-only
TASKS_KSGEN
Start generation of keystream. This operation will stop by itself when completed.
0
0
Trigger
Trigger task
1
TASKS_CRYPT
Start encryption/decryption. This operation will stop by itself when completed.
0x004
write-only
TASKS_CRYPT
Start encryption/decryption. This operation will stop by itself when completed.
0
0
Trigger
Trigger task
1
TASKS_STOP
Stop encryption/decryption
0x008
write-only
TASKS_STOP
Stop encryption/decryption
0
0
Trigger
Trigger task
1
TASKS_RATEOVERRIDE
Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption
0x00C
write-only
TASKS_RATEOVERRIDE
Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption
0
0
Trigger
Trigger task
1
SUBSCRIBE_KSGEN
Subscribe configuration for task KSGEN
0x080
read-write
CHIDX
DPPI channel that task KSGEN will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_CRYPT
Subscribe configuration for task CRYPT
0x084
read-write
CHIDX
DPPI channel that task CRYPT will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_STOP
Subscribe configuration for task STOP
0x088
read-write
CHIDX
DPPI channel that task STOP will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_RATEOVERRIDE
Subscribe configuration for task RATEOVERRIDE
0x08C
read-write
CHIDX
DPPI channel that task RATEOVERRIDE will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
EVENTS_ENDKSGEN
Keystream generation complete
0x100
read-write
EVENTS_ENDKSGEN
Keystream generation complete
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_ENDCRYPT
Encrypt/decrypt complete
0x104
read-write
EVENTS_ENDCRYPT
Encrypt/decrypt complete
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_ERROR
Deprecated register - CCM error event
0x108
read-write
EVENTS_ERROR
Deprecated field - CCM error event
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
PUBLISH_ENDKSGEN
Publish configuration for event ENDKSGEN
0x180
read-write
CHIDX
DPPI channel that event ENDKSGEN will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_ENDCRYPT
Publish configuration for event ENDCRYPT
0x184
read-write
CHIDX
DPPI channel that event ENDCRYPT will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_ERROR
Deprecated register - Publish configuration for event ERROR
0x188
read-write
CHIDX
DPPI channel that event ERROR will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
SHORTS
Shortcuts between local events and tasks
0x200
read-write
ENDKSGEN_CRYPT
Shortcut between event ENDKSGEN and task CRYPT
0
0
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
INTENSET
Enable interrupt
0x304
read-write
ENDKSGEN
Write '1' to enable interrupt for event ENDKSGEN
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
ENDCRYPT
Write '1' to enable interrupt for event ENDCRYPT
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
ERROR
Deprecated intsetfield - Write '1' to enable interrupt for event ERROR
2
2
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
INTENCLR
Disable interrupt
0x308
read-write
ENDKSGEN
Write '1' to disable interrupt for event ENDKSGEN
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
ENDCRYPT
Write '1' to disable interrupt for event ENDCRYPT
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
ERROR
Deprecated intclrfield - Write '1' to disable interrupt for event ERROR
2
2
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
MICSTATUS
MIC check result
0x400
read-only
MICSTATUS
The result of the MIC check performed during the previous decryption operation
0
0
CheckFailed
MIC check failed
0
CheckPassed
MIC check passed
1
ENABLE
Enable
0x500
read-write
ENABLE
Enable or disable CCM
0
1
Disabled
Disable
0
Enabled
Enable
2
MODE
Operation mode
0x504
read-write
0x00000001
MODE
The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered.
0
0
Encryption
AES CCM packet encryption mode
0
Decryption
AES CCM packet decryption mode
1
DATARATE
Radio data rate that the CCM shall run synchronous with
16
17
1Mbit
1 Mbps
0
2Mbit
2 Mbps
1
125Kbps
125 Kbps
2
500Kbps
500 Kbps
3
LENGTH
Packet length configuration
24
24
Default
Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated.
0
Extended
Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated.
1
CNFPTR
Pointer to data structure holding the AES key and the NONCE vector
0x508
read-write
CNFPTR
Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview)
0
31
INPTR
Input pointer
0x50C
read-write
INPTR
Input pointer
0
31
OUTPTR
Output pointer
0x510
read-write
OUTPTR
Output pointer
0
31
SCRATCHPTR
Pointer to data area used for temporary storage
0x514
read-write
SCRATCHPTR
Pointer to a scratch data area used for temporary storage during keystream generation,
MIC generation and encryption/decryption.
0
31
MAXPACKETSIZE
Length of keystream generated when MODE.LENGTH = Extended
0x518
read-write
0x000000FB
MAXPACKETSIZE
Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted.
0
7
RATEOVERRIDE
Data rate override setting.
0x51C
read-write
0x00000000
RATEOVERRIDE
Data rate override setting
0
1
1Mbit
1 Mbps
0
2Mbit
2 Mbps
1
125Kbps
125 Kbps
2
500Kbps
500 Kbps
3
HEADERMASK
Header (S0) mask.
0x520
read-write
0x000000E3
HEADERMASK
Header (S0) mask
0
7
DPPIC_NS
Distributed programmable peripheral interconnect controller
0x4100F000
DPPIC
0
0x1000
registers
DPPIC
0x20
6
0x008
TASKS_CHG[%s]
Channel group tasks
DPPIC_TASKS_CHG
write-only
0x000
EN
Description cluster: Enable channel group n
0x000
write-only
EN
Enable channel group n
0
0
Trigger
Trigger task
1
DIS
Description cluster: Disable channel group n
0x004
write-only
DIS
Disable channel group n
0
0
Trigger
Trigger task
1
6
0x008
SUBSCRIBE_CHG[%s]
Subscribe configuration for tasks
DPPIC_SUBSCRIBE_CHG
read-write
0x080
EN
Description cluster: Subscribe configuration for task CHG[n].EN
0x000
read-write
CHIDX
DPPI channel that task CHG[n].EN will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
DIS
Description cluster: Subscribe configuration for task CHG[n].DIS
0x004
read-write
CHIDX
DPPI channel that task CHG[n].DIS will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
CHEN
Channel enable register
0x500
read-write
CH0
Enable or disable channel 0
0
0
Disabled
Disable channel
0
Enabled
Enable channel
1
CH1
Enable or disable channel 1
1
1
Disabled
Disable channel
0
Enabled
Enable channel
1
CH2
Enable or disable channel 2
2
2
Disabled
Disable channel
0
Enabled
Enable channel
1
CH3
Enable or disable channel 3
3
3
Disabled
Disable channel
0
Enabled
Enable channel
1
CH4
Enable or disable channel 4
4
4
Disabled
Disable channel
0
Enabled
Enable channel
1
CH5
Enable or disable channel 5
5
5
Disabled
Disable channel
0
Enabled
Enable channel
1
CH6
Enable or disable channel 6
6
6
Disabled
Disable channel
0
Enabled
Enable channel
1
CH7
Enable or disable channel 7
7
7
Disabled
Disable channel
0
Enabled
Enable channel
1
CH8
Enable or disable channel 8
8
8
Disabled
Disable channel
0
Enabled
Enable channel
1
CH9
Enable or disable channel 9
9
9
Disabled
Disable channel
0
Enabled
Enable channel
1
CH10
Enable or disable channel 10
10
10
Disabled
Disable channel
0
Enabled
Enable channel
1
CH11
Enable or disable channel 11
11
11
Disabled
Disable channel
0
Enabled
Enable channel
1
CH12
Enable or disable channel 12
12
12
Disabled
Disable channel
0
Enabled
Enable channel
1
CH13
Enable or disable channel 13
13
13
Disabled
Disable channel
0
Enabled
Enable channel
1
CH14
Enable or disable channel 14
14
14
Disabled
Disable channel
0
Enabled
Enable channel
1
CH15
Enable or disable channel 15
15
15
Disabled
Disable channel
0
Enabled
Enable channel
1
CHENSET
Channel enable set register
0x504
read-write
oneToSet
CH0
Channel 0 enable set register. Writing 0 has no effect.
0
0
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Set
Write: Enable channel
1
CH1
Channel 1 enable set register. Writing 0 has no effect.
1
1
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Set
Write: Enable channel
1
CH2
Channel 2 enable set register. Writing 0 has no effect.
2
2
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Set
Write: Enable channel
1
CH3
Channel 3 enable set register. Writing 0 has no effect.
3
3
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Set
Write: Enable channel
1
CH4
Channel 4 enable set register. Writing 0 has no effect.
4
4
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Set
Write: Enable channel
1
CH5
Channel 5 enable set register. Writing 0 has no effect.
5
5
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Set
Write: Enable channel
1
CH6
Channel 6 enable set register. Writing 0 has no effect.
6
6
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Set
Write: Enable channel
1
CH7
Channel 7 enable set register. Writing 0 has no effect.
7
7
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Set
Write: Enable channel
1
CH8
Channel 8 enable set register. Writing 0 has no effect.
8
8
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Set
Write: Enable channel
1
CH9
Channel 9 enable set register. Writing 0 has no effect.
9
9
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Set
Write: Enable channel
1
CH10
Channel 10 enable set register. Writing 0 has no effect.
10
10
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Set
Write: Enable channel
1
CH11
Channel 11 enable set register. Writing 0 has no effect.
11
11
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Set
Write: Enable channel
1
CH12
Channel 12 enable set register. Writing 0 has no effect.
12
12
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Set
Write: Enable channel
1
CH13
Channel 13 enable set register. Writing 0 has no effect.
13
13
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Set
Write: Enable channel
1
CH14
Channel 14 enable set register. Writing 0 has no effect.
14
14
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Set
Write: Enable channel
1
CH15
Channel 15 enable set register. Writing 0 has no effect.
15
15
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Set
Write: Enable channel
1
CHENCLR
Channel enable clear register
0x508
read-write
oneToClear
CH0
Channel 0 enable clear register. Writing 0 has no effect.
0
0
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Clear
Write: Disable channel
1
CH1
Channel 1 enable clear register. Writing 0 has no effect.
1
1
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Clear
Write: Disable channel
1
CH2
Channel 2 enable clear register. Writing 0 has no effect.
2
2
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Clear
Write: Disable channel
1
CH3
Channel 3 enable clear register. Writing 0 has no effect.
3
3
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Clear
Write: Disable channel
1
CH4
Channel 4 enable clear register. Writing 0 has no effect.
4
4
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Clear
Write: Disable channel
1
CH5
Channel 5 enable clear register. Writing 0 has no effect.
5
5
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Clear
Write: Disable channel
1
CH6
Channel 6 enable clear register. Writing 0 has no effect.
6
6
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Clear
Write: Disable channel
1
CH7
Channel 7 enable clear register. Writing 0 has no effect.
7
7
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Clear
Write: Disable channel
1
CH8
Channel 8 enable clear register. Writing 0 has no effect.
8
8
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Clear
Write: Disable channel
1
CH9
Channel 9 enable clear register. Writing 0 has no effect.
9
9
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Clear
Write: Disable channel
1
CH10
Channel 10 enable clear register. Writing 0 has no effect.
10
10
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Clear
Write: Disable channel
1
CH11
Channel 11 enable clear register. Writing 0 has no effect.
11
11
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Clear
Write: Disable channel
1
CH12
Channel 12 enable clear register. Writing 0 has no effect.
12
12
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Clear
Write: Disable channel
1
CH13
Channel 13 enable clear register. Writing 0 has no effect.
13
13
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Clear
Write: Disable channel
1
CH14
Channel 14 enable clear register. Writing 0 has no effect.
14
14
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Clear
Write: Disable channel
1
CH15
Channel 15 enable clear register. Writing 0 has no effect.
15
15
read
Disabled
Read: Channel disabled
0
Enabled
Read: Channel enabled
1
write
Clear
Write: Disable channel
1
0x6
0x4
CHG[%s]
Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled
0x800
read-write
CH0
Include or exclude channel 0
0
0
Excluded
Exclude
0
Included
Include
1
CH1
Include or exclude channel 1
1
1
Excluded
Exclude
0
Included
Include
1
CH2
Include or exclude channel 2
2
2
Excluded
Exclude
0
Included
Include
1
CH3
Include or exclude channel 3
3
3
Excluded
Exclude
0
Included
Include
1
CH4
Include or exclude channel 4
4
4
Excluded
Exclude
0
Included
Include
1
CH5
Include or exclude channel 5
5
5
Excluded
Exclude
0
Included
Include
1
CH6
Include or exclude channel 6
6
6
Excluded
Exclude
0
Included
Include
1
CH7
Include or exclude channel 7
7
7
Excluded
Exclude
0
Included
Include
1
CH8
Include or exclude channel 8
8
8
Excluded
Exclude
0
Included
Include
1
CH9
Include or exclude channel 9
9
9
Excluded
Exclude
0
Included
Include
1
CH10
Include or exclude channel 10
10
10
Excluded
Exclude
0
Included
Include
1
CH11
Include or exclude channel 11
11
11
Excluded
Exclude
0
Included
Include
1
CH12
Include or exclude channel 12
12
12
Excluded
Exclude
0
Included
Include
1
CH13
Include or exclude channel 13
13
13
Excluded
Exclude
0
Included
Include
1
CH14
Include or exclude channel 14
14
14
Excluded
Exclude
0
Included
Include
1
CH15
Include or exclude channel 15
15
15
Excluded
Exclude
0
Included
Include
1
TEMP_NS
Temperature Sensor
0x41010000
TEMP
0
0x1000
registers
TEMP
16
TEMP
0x20
TASKS_START
Start temperature measurement
0x000
write-only
TASKS_START
Start temperature measurement
0
0
Trigger
Trigger task
1
TASKS_STOP
Stop temperature measurement
0x004
write-only
TASKS_STOP
Stop temperature measurement
0
0
Trigger
Trigger task
1
SUBSCRIBE_START
Subscribe configuration for task START
0x080
read-write
CHIDX
DPPI channel that task START will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_STOP
Subscribe configuration for task STOP
0x084
read-write
CHIDX
DPPI channel that task STOP will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
EVENTS_DATARDY
Temperature measurement complete, data ready
0x100
read-write
EVENTS_DATARDY
Temperature measurement complete, data ready
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
PUBLISH_DATARDY
Publish configuration for event DATARDY
0x180
read-write
CHIDX
DPPI channel that event DATARDY will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
INTENSET
Enable interrupt
0x304
read-write
DATARDY
Write '1' to enable interrupt for event DATARDY
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
INTENCLR
Disable interrupt
0x308
read-write
DATARDY
Write '1' to disable interrupt for event DATARDY
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
TEMP
Temperature in degC (0.25deg steps)
0x508
read-only
int32_t
TEMP
Temperature in degC (0.25deg steps)
0
31
A0
Slope of 1st piece wise linear function
0x520
read-write
0x000002D9
A0
Slope of 1st piece wise linear function
0
11
A1
Slope of 2nd piece wise linear function
0x524
read-write
0x00000322
A1
Slope of 2nd piece wise linear function
0
11
A2
Slope of 3rd piece wise linear function
0x528
read-write
0x00000355
A2
Slope of 3rd piece wise linear function
0
11
A3
Slope of 4th piece wise linear function
0x52C
read-write
0x000003DF
A3
Slope of 4th piece wise linear function
0
11
A4
Slope of 5th piece wise linear function
0x530
read-write
0x0000044E
A4
Slope of 5th piece wise linear function
0
11
A5
Slope of 6th piece wise linear function
0x534
read-write
0x000004B7
A5
Slope of 6th piece wise linear function
0
11
B0
y-intercept of 1st piece wise linear function
0x540
read-write
0x00000FC7
B0
y-intercept of 1st piece wise linear function
0
11
B1
y-intercept of 2nd piece wise linear function
0x544
read-write
0x00000F71
B1
y-intercept of 2nd piece wise linear function
0
11
B2
y-intercept of 3rd piece wise linear function
0x548
read-write
0x00000F6C
B2
y-intercept of 3rd piece wise linear function
0
11
B3
y-intercept of 4th piece wise linear function
0x54C
read-write
0x00000FCB
B3
y-intercept of 4th piece wise linear function
0
11
B4
y-intercept of 5th piece wise linear function
0x550
read-write
0x0000004B
B4
y-intercept of 5th piece wise linear function
0
11
B5
y-intercept of 6th piece wise linear function
0x554
read-write
0x000000F6
B5
y-intercept of 6th piece wise linear function
0
11
T0
End point of 1st piece wise linear function
0x560
read-write
0x000000E1
T0
End point of 1st piece wise linear function
0
7
T1
End point of 2nd piece wise linear function
0x564
read-write
0x000000F9
T1
End point of 2nd piece wise linear function
0
7
T2
End point of 3rd piece wise linear function
0x568
read-write
0x00000010
T2
End point of 3rd piece wise linear function
0
7
T3
End point of 4th piece wise linear function
0x56C
read-write
0x00000026
T3
End point of 4th piece wise linear function
0
7
T4
End point of 5th piece wise linear function
0x570
read-write
0x0000003F
T4
End point of 5th piece wise linear function
0
7
RTC0_NS
Real-time counter 0
0x41011000
RTC
0
0x1000
registers
RTC0
17
RTC
0x20
TASKS_START
Start RTC counter
0x000
write-only
TASKS_START
Start RTC counter
0
0
Trigger
Trigger task
1
TASKS_STOP
Stop RTC counter
0x004
write-only
TASKS_STOP
Stop RTC counter
0
0
Trigger
Trigger task
1
TASKS_CLEAR
Clear RTC counter
0x008
write-only
TASKS_CLEAR
Clear RTC counter
0
0
Trigger
Trigger task
1
TASKS_TRIGOVRFLW
Set counter to 0xFFFFF0
0x00C
write-only
TASKS_TRIGOVRFLW
Set counter to 0xFFFFF0
0
0
Trigger
Trigger task
1
0x4
0x4
TASKS_CAPTURE[%s]
Description collection: Capture RTC counter to CC[n] register
0x040
write-only
TASKS_CAPTURE
Capture RTC counter to CC[n] register
0
0
Trigger
Trigger task
1
SUBSCRIBE_START
Subscribe configuration for task START
0x080
read-write
CHIDX
DPPI channel that task START will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_STOP
Subscribe configuration for task STOP
0x084
read-write
CHIDX
DPPI channel that task STOP will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_CLEAR
Subscribe configuration for task CLEAR
0x088
read-write
CHIDX
DPPI channel that task CLEAR will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_TRIGOVRFLW
Subscribe configuration for task TRIGOVRFLW
0x08C
read-write
CHIDX
DPPI channel that task TRIGOVRFLW will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
0x4
0x4
SUBSCRIBE_CAPTURE[%s]
Description collection: Subscribe configuration for task CAPTURE[n]
0x0C0
read-write
CHIDX
DPPI channel that task CAPTURE[n] will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
EVENTS_TICK
Event on counter increment
0x100
read-write
EVENTS_TICK
Event on counter increment
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_OVRFLW
Event on counter overflow
0x104
read-write
EVENTS_OVRFLW
Event on counter overflow
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
0x4
0x4
EVENTS_COMPARE[%s]
Description collection: Compare event on CC[n] match
0x140
read-write
EVENTS_COMPARE
Compare event on CC[n] match
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
PUBLISH_TICK
Publish configuration for event TICK
0x180
read-write
CHIDX
DPPI channel that event TICK will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_OVRFLW
Publish configuration for event OVRFLW
0x184
read-write
CHIDX
DPPI channel that event OVRFLW will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
0x4
0x4
PUBLISH_COMPARE[%s]
Description collection: Publish configuration for event COMPARE[n]
0x1C0
read-write
CHIDX
DPPI channel that event COMPARE[n] will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
SHORTS
Shortcuts between local events and tasks
0x200
read-write
COMPARE0_CLEAR
Shortcut between event COMPARE[0] and task CLEAR
0
0
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
COMPARE1_CLEAR
Shortcut between event COMPARE[1] and task CLEAR
1
1
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
COMPARE2_CLEAR
Shortcut between event COMPARE[2] and task CLEAR
2
2
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
COMPARE3_CLEAR
Shortcut between event COMPARE[3] and task CLEAR
3
3
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
INTENSET
Enable interrupt
0x304
read-write
TICK
Write '1' to enable interrupt for event TICK
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
OVRFLW
Write '1' to enable interrupt for event OVRFLW
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
COMPARE0
Write '1' to enable interrupt for event COMPARE[0]
16
16
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
COMPARE1
Write '1' to enable interrupt for event COMPARE[1]
17
17
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
COMPARE2
Write '1' to enable interrupt for event COMPARE[2]
18
18
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
COMPARE3
Write '1' to enable interrupt for event COMPARE[3]
19
19
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
INTENCLR
Disable interrupt
0x308
read-write
TICK
Write '1' to disable interrupt for event TICK
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
OVRFLW
Write '1' to disable interrupt for event OVRFLW
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
COMPARE0
Write '1' to disable interrupt for event COMPARE[0]
16
16
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
COMPARE1
Write '1' to disable interrupt for event COMPARE[1]
17
17
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
COMPARE2
Write '1' to disable interrupt for event COMPARE[2]
18
18
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
COMPARE3
Write '1' to disable interrupt for event COMPARE[3]
19
19
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
EVTEN
Enable or disable event routing
0x340
read-write
TICK
Enable or disable event routing for event TICK
0
0
Disabled
Disable
0
Enabled
Enable
1
OVRFLW
Enable or disable event routing for event OVRFLW
1
1
Disabled
Disable
0
Enabled
Enable
1
COMPARE0
Enable or disable event routing for event COMPARE[0]
16
16
Disabled
Disable
0
Enabled
Enable
1
COMPARE1
Enable or disable event routing for event COMPARE[1]
17
17
Disabled
Disable
0
Enabled
Enable
1
COMPARE2
Enable or disable event routing for event COMPARE[2]
18
18
Disabled
Disable
0
Enabled
Enable
1
COMPARE3
Enable or disable event routing for event COMPARE[3]
19
19
Disabled
Disable
0
Enabled
Enable
1
EVTENSET
Enable event routing
0x344
read-write
TICK
Write '1' to enable event routing for event TICK
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
OVRFLW
Write '1' to enable event routing for event OVRFLW
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
COMPARE0
Write '1' to enable event routing for event COMPARE[0]
16
16
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
COMPARE1
Write '1' to enable event routing for event COMPARE[1]
17
17
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
COMPARE2
Write '1' to enable event routing for event COMPARE[2]
18
18
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
COMPARE3
Write '1' to enable event routing for event COMPARE[3]
19
19
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
EVTENCLR
Disable event routing
0x348
read-write
TICK
Write '1' to disable event routing for event TICK
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
OVRFLW
Write '1' to disable event routing for event OVRFLW
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
COMPARE0
Write '1' to disable event routing for event COMPARE[0]
16
16
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
COMPARE1
Write '1' to disable event routing for event COMPARE[1]
17
17
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
COMPARE2
Write '1' to disable event routing for event COMPARE[2]
18
18
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
COMPARE3
Write '1' to disable event routing for event COMPARE[3]
19
19
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
COUNTER
Current counter value
0x504
read-only
COUNTER
Counter value
0
23
PRESCALER
12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped.
0x508
read-write
PRESCALER
Prescaler value
0
11
0x4
0x4
CC[%s]
Description collection: Compare register n
0x540
read-write
COMPARE
Compare value
0
23
IPC_NS
Interprocessor communication
0x41012000
IPC
0
0x1000
registers
IPC
18
IPC
0x20
0x10
0x4
TASKS_SEND[%s]
Description collection: Trigger events on IPC channel enabled in SEND_CNF[n]
0x000
write-only
TASKS_SEND
Trigger events on IPC channel enabled in SEND_CNF[n]
0
0
Trigger
Trigger task
1
0x10
0x4
SUBSCRIBE_SEND[%s]
Description collection: Subscribe configuration for task SEND[n]
0x080
read-write
CHIDX
DPPI channel that task SEND[n] will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
0x10
0x4
EVENTS_RECEIVE[%s]
Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n]
0x100
read-write
EVENTS_RECEIVE
Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n]
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
0x10
0x4
PUBLISH_RECEIVE[%s]
Description collection: Publish configuration for event RECEIVE[n]
0x180
read-write
CHIDX
DPPI channel that event RECEIVE[n] will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
INTEN
Enable or disable interrupt
0x300
read-write
RECEIVE0
Enable or disable interrupt for event RECEIVE[0]
0
0
Disabled
Disable
0
Enabled
Enable
1
RECEIVE1
Enable or disable interrupt for event RECEIVE[1]
1
1
Disabled
Disable
0
Enabled
Enable
1
RECEIVE2
Enable or disable interrupt for event RECEIVE[2]
2
2
Disabled
Disable
0
Enabled
Enable
1
RECEIVE3
Enable or disable interrupt for event RECEIVE[3]
3
3
Disabled
Disable
0
Enabled
Enable
1
RECEIVE4
Enable or disable interrupt for event RECEIVE[4]
4
4
Disabled
Disable
0
Enabled
Enable
1
RECEIVE5
Enable or disable interrupt for event RECEIVE[5]
5
5
Disabled
Disable
0
Enabled
Enable
1
RECEIVE6
Enable or disable interrupt for event RECEIVE[6]
6
6
Disabled
Disable
0
Enabled
Enable
1
RECEIVE7
Enable or disable interrupt for event RECEIVE[7]
7
7
Disabled
Disable
0
Enabled
Enable
1
RECEIVE8
Enable or disable interrupt for event RECEIVE[8]
8
8
Disabled
Disable
0
Enabled
Enable
1
RECEIVE9
Enable or disable interrupt for event RECEIVE[9]
9
9
Disabled
Disable
0
Enabled
Enable
1
RECEIVE10
Enable or disable interrupt for event RECEIVE[10]
10
10
Disabled
Disable
0
Enabled
Enable
1
RECEIVE11
Enable or disable interrupt for event RECEIVE[11]
11
11
Disabled
Disable
0
Enabled
Enable
1
RECEIVE12
Enable or disable interrupt for event RECEIVE[12]
12
12
Disabled
Disable
0
Enabled
Enable
1
RECEIVE13
Enable or disable interrupt for event RECEIVE[13]
13
13
Disabled
Disable
0
Enabled
Enable
1
RECEIVE14
Enable or disable interrupt for event RECEIVE[14]
14
14
Disabled
Disable
0
Enabled
Enable
1
RECEIVE15
Enable or disable interrupt for event RECEIVE[15]
15
15
Disabled
Disable
0
Enabled
Enable
1
INTENSET
Enable interrupt
0x304
read-write
RECEIVE0
Write '1' to enable interrupt for event RECEIVE[0]
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RECEIVE1
Write '1' to enable interrupt for event RECEIVE[1]
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RECEIVE2
Write '1' to enable interrupt for event RECEIVE[2]
2
2
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RECEIVE3
Write '1' to enable interrupt for event RECEIVE[3]
3
3
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RECEIVE4
Write '1' to enable interrupt for event RECEIVE[4]
4
4
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RECEIVE5
Write '1' to enable interrupt for event RECEIVE[5]
5
5
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RECEIVE6
Write '1' to enable interrupt for event RECEIVE[6]
6
6
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RECEIVE7
Write '1' to enable interrupt for event RECEIVE[7]
7
7
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RECEIVE8
Write '1' to enable interrupt for event RECEIVE[8]
8
8
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RECEIVE9
Write '1' to enable interrupt for event RECEIVE[9]
9
9
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RECEIVE10
Write '1' to enable interrupt for event RECEIVE[10]
10
10
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RECEIVE11
Write '1' to enable interrupt for event RECEIVE[11]
11
11
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RECEIVE12
Write '1' to enable interrupt for event RECEIVE[12]
12
12
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RECEIVE13
Write '1' to enable interrupt for event RECEIVE[13]
13
13
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RECEIVE14
Write '1' to enable interrupt for event RECEIVE[14]
14
14
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RECEIVE15
Write '1' to enable interrupt for event RECEIVE[15]
15
15
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
INTENCLR
Disable interrupt
0x308
read-write
RECEIVE0
Write '1' to disable interrupt for event RECEIVE[0]
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RECEIVE1
Write '1' to disable interrupt for event RECEIVE[1]
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RECEIVE2
Write '1' to disable interrupt for event RECEIVE[2]
2
2
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RECEIVE3
Write '1' to disable interrupt for event RECEIVE[3]
3
3
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RECEIVE4
Write '1' to disable interrupt for event RECEIVE[4]
4
4
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RECEIVE5
Write '1' to disable interrupt for event RECEIVE[5]
5
5
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RECEIVE6
Write '1' to disable interrupt for event RECEIVE[6]
6
6
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RECEIVE7
Write '1' to disable interrupt for event RECEIVE[7]
7
7
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RECEIVE8
Write '1' to disable interrupt for event RECEIVE[8]
8
8
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RECEIVE9
Write '1' to disable interrupt for event RECEIVE[9]
9
9
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RECEIVE10
Write '1' to disable interrupt for event RECEIVE[10]
10
10
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RECEIVE11
Write '1' to disable interrupt for event RECEIVE[11]
11
11
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RECEIVE12
Write '1' to disable interrupt for event RECEIVE[12]
12
12
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RECEIVE13
Write '1' to disable interrupt for event RECEIVE[13]
13
13
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RECEIVE14
Write '1' to disable interrupt for event RECEIVE[14]
14
14
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RECEIVE15
Write '1' to disable interrupt for event RECEIVE[15]
15
15
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
INTPEND
Pending interrupts
0x30C
read-only
RECEIVE0
Read pending status of interrupt for event RECEIVE[0]
0
0
read
NotPending
Read: Not pending
0
Pending
Read: Pending
1
RECEIVE1
Read pending status of interrupt for event RECEIVE[1]
1
1
read
NotPending
Read: Not pending
0
Pending
Read: Pending
1
RECEIVE2
Read pending status of interrupt for event RECEIVE[2]
2
2
read
NotPending
Read: Not pending
0
Pending
Read: Pending
1
RECEIVE3
Read pending status of interrupt for event RECEIVE[3]
3
3
read
NotPending
Read: Not pending
0
Pending
Read: Pending
1
RECEIVE4
Read pending status of interrupt for event RECEIVE[4]
4
4
read
NotPending
Read: Not pending
0
Pending
Read: Pending
1
RECEIVE5
Read pending status of interrupt for event RECEIVE[5]
5
5
read
NotPending
Read: Not pending
0
Pending
Read: Pending
1
RECEIVE6
Read pending status of interrupt for event RECEIVE[6]
6
6
read
NotPending
Read: Not pending
0
Pending
Read: Pending
1
RECEIVE7
Read pending status of interrupt for event RECEIVE[7]
7
7
read
NotPending
Read: Not pending
0
Pending
Read: Pending
1
RECEIVE8
Read pending status of interrupt for event RECEIVE[8]
8
8
read
NotPending
Read: Not pending
0
Pending
Read: Pending
1
RECEIVE9
Read pending status of interrupt for event RECEIVE[9]
9
9
read
NotPending
Read: Not pending
0
Pending
Read: Pending
1
RECEIVE10
Read pending status of interrupt for event RECEIVE[10]
10
10
read
NotPending
Read: Not pending
0
Pending
Read: Pending
1
RECEIVE11
Read pending status of interrupt for event RECEIVE[11]
11
11
read
NotPending
Read: Not pending
0
Pending
Read: Pending
1
RECEIVE12
Read pending status of interrupt for event RECEIVE[12]
12
12
read
NotPending
Read: Not pending
0
Pending
Read: Pending
1
RECEIVE13
Read pending status of interrupt for event RECEIVE[13]
13
13
read
NotPending
Read: Not pending
0
Pending
Read: Pending
1
RECEIVE14
Read pending status of interrupt for event RECEIVE[14]
14
14
read
NotPending
Read: Not pending
0
Pending
Read: Pending
1
RECEIVE15
Read pending status of interrupt for event RECEIVE[15]
15
15
read
NotPending
Read: Not pending
0
Pending
Read: Pending
1
0x10
0x4
SEND_CNF[%s]
Description collection: Send event configuration for TASKS_SEND[n]
0x510
read-write
0x00000000
CHEN0
Enable broadcasting on IPC channel 0
0
0
Disable
Disable broadcast
0
Enable
Enable broadcast
1
CHEN1
Enable broadcasting on IPC channel 1
1
1
Disable
Disable broadcast
0
Enable
Enable broadcast
1
CHEN2
Enable broadcasting on IPC channel 2
2
2
Disable
Disable broadcast
0
Enable
Enable broadcast
1
CHEN3
Enable broadcasting on IPC channel 3
3
3
Disable
Disable broadcast
0
Enable
Enable broadcast
1
CHEN4
Enable broadcasting on IPC channel 4
4
4
Disable
Disable broadcast
0
Enable
Enable broadcast
1
CHEN5
Enable broadcasting on IPC channel 5
5
5
Disable
Disable broadcast
0
Enable
Enable broadcast
1
CHEN6
Enable broadcasting on IPC channel 6
6
6
Disable
Disable broadcast
0
Enable
Enable broadcast
1
CHEN7
Enable broadcasting on IPC channel 7
7
7
Disable
Disable broadcast
0
Enable
Enable broadcast
1
CHEN8
Enable broadcasting on IPC channel 8
8
8
Disable
Disable broadcast
0
Enable
Enable broadcast
1
CHEN9
Enable broadcasting on IPC channel 9
9
9
Disable
Disable broadcast
0
Enable
Enable broadcast
1
CHEN10
Enable broadcasting on IPC channel 10
10
10
Disable
Disable broadcast
0
Enable
Enable broadcast
1
CHEN11
Enable broadcasting on IPC channel 11
11
11
Disable
Disable broadcast
0
Enable
Enable broadcast
1
CHEN12
Enable broadcasting on IPC channel 12
12
12
Disable
Disable broadcast
0
Enable
Enable broadcast
1
CHEN13
Enable broadcasting on IPC channel 13
13
13
Disable
Disable broadcast
0
Enable
Enable broadcast
1
CHEN14
Enable broadcasting on IPC channel 14
14
14
Disable
Disable broadcast
0
Enable
Enable broadcast
1
CHEN15
Enable broadcasting on IPC channel 15
15
15
Disable
Disable broadcast
0
Enable
Enable broadcast
1
0x10
0x4
RECEIVE_CNF[%s]
Description collection: Receive event configuration for EVENTS_RECEIVE[n]
0x590
read-write
0x00000000
CHEN0
Enable subscription to IPC channel 0
0
0
Disable
Disable events
0
Enable
Enable events
1
CHEN1
Enable subscription to IPC channel 1
1
1
Disable
Disable events
0
Enable
Enable events
1
CHEN2
Enable subscription to IPC channel 2
2
2
Disable
Disable events
0
Enable
Enable events
1
CHEN3
Enable subscription to IPC channel 3
3
3
Disable
Disable events
0
Enable
Enable events
1
CHEN4
Enable subscription to IPC channel 4
4
4
Disable
Disable events
0
Enable
Enable events
1
CHEN5
Enable subscription to IPC channel 5
5
5
Disable
Disable events
0
Enable
Enable events
1
CHEN6
Enable subscription to IPC channel 6
6
6
Disable
Disable events
0
Enable
Enable events
1
CHEN7
Enable subscription to IPC channel 7
7
7
Disable
Disable events
0
Enable
Enable events
1
CHEN8
Enable subscription to IPC channel 8
8
8
Disable
Disable events
0
Enable
Enable events
1
CHEN9
Enable subscription to IPC channel 9
9
9
Disable
Disable events
0
Enable
Enable events
1
CHEN10
Enable subscription to IPC channel 10
10
10
Disable
Disable events
0
Enable
Enable events
1
CHEN11
Enable subscription to IPC channel 11
11
11
Disable
Disable events
0
Enable
Enable events
1
CHEN12
Enable subscription to IPC channel 12
12
12
Disable
Disable events
0
Enable
Enable events
1
CHEN13
Enable subscription to IPC channel 13
13
13
Disable
Disable events
0
Enable
Enable events
1
CHEN14
Enable subscription to IPC channel 14
14
14
Disable
Disable events
0
Enable
Enable events
1
CHEN15
Enable subscription to IPC channel 15
15
15
Disable
Disable events
0
Enable
Enable events
1
0x2
0x4
GPMEM[%s]
Description collection: General purpose memory
0x610
read-write
0x00000000
GPMEM
General purpose memory
0
31
SPIM0_NS
Serial Peripheral Interface Master with EasyDMA
0x41013000
SPIM
0
0x1000
registers
SPIM0_SPIS0_TWIM0_TWIS0_UARTE0
19
SPIM
0x20
TASKS_START
Start SPI transaction
0x010
write-only
TASKS_START
Start SPI transaction
0
0
Trigger
Trigger task
1
TASKS_STOP
Stop SPI transaction
0x014
write-only
TASKS_STOP
Stop SPI transaction
0
0
Trigger
Trigger task
1
TASKS_SUSPEND
Suspend SPI transaction
0x01C
write-only
TASKS_SUSPEND
Suspend SPI transaction
0
0
Trigger
Trigger task
1
TASKS_RESUME
Resume SPI transaction
0x020
write-only
TASKS_RESUME
Resume SPI transaction
0
0
Trigger
Trigger task
1
SUBSCRIBE_START
Subscribe configuration for task START
0x090
read-write
CHIDX
DPPI channel that task START will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_STOP
Subscribe configuration for task STOP
0x094
read-write
CHIDX
DPPI channel that task STOP will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_SUSPEND
Subscribe configuration for task SUSPEND
0x09C
read-write
CHIDX
DPPI channel that task SUSPEND will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_RESUME
Subscribe configuration for task RESUME
0x0A0
read-write
CHIDX
DPPI channel that task RESUME will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
EVENTS_STOPPED
SPI transaction has stopped
0x104
read-write
EVENTS_STOPPED
SPI transaction has stopped
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_ENDRX
End of RXD buffer reached
0x110
read-write
EVENTS_ENDRX
End of RXD buffer reached
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_END
End of RXD buffer and TXD buffer reached
0x118
read-write
EVENTS_END
End of RXD buffer and TXD buffer reached
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_ENDTX
End of TXD buffer reached
0x120
read-write
EVENTS_ENDTX
End of TXD buffer reached
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_STARTED
Transaction started
0x14C
read-write
EVENTS_STARTED
Transaction started
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
PUBLISH_STOPPED
Publish configuration for event STOPPED
0x184
read-write
CHIDX
DPPI channel that event STOPPED will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_ENDRX
Publish configuration for event ENDRX
0x190
read-write
CHIDX
DPPI channel that event ENDRX will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_END
Publish configuration for event END
0x198
read-write
CHIDX
DPPI channel that event END will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_ENDTX
Publish configuration for event ENDTX
0x1A0
read-write
CHIDX
DPPI channel that event ENDTX will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_STARTED
Publish configuration for event STARTED
0x1CC
read-write
CHIDX
DPPI channel that event STARTED will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
SHORTS
Shortcuts between local events and tasks
0x200
read-write
END_START
Shortcut between event END and task START
17
17
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
INTENSET
Enable interrupt
0x304
read-write
STOPPED
Write '1' to enable interrupt for event STOPPED
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
ENDRX
Write '1' to enable interrupt for event ENDRX
4
4
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
END
Write '1' to enable interrupt for event END
6
6
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
ENDTX
Write '1' to enable interrupt for event ENDTX
8
8
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
STARTED
Write '1' to enable interrupt for event STARTED
19
19
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
INTENCLR
Disable interrupt
0x308
read-write
STOPPED
Write '1' to disable interrupt for event STOPPED
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
ENDRX
Write '1' to disable interrupt for event ENDRX
4
4
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
END
Write '1' to disable interrupt for event END
6
6
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
ENDTX
Write '1' to disable interrupt for event ENDTX
8
8
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
STARTED
Write '1' to disable interrupt for event STARTED
19
19
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
STALLSTAT
Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU.
0x400
read-write
0x00000000
TX
Stall status for EasyDMA RAM reads
0
0
NOSTALL
No stall
0
STALL
A stall has occurred
1
RX
Stall status for EasyDMA RAM writes
1
1
NOSTALL
No stall
0
STALL
A stall has occurred
1
ENABLE
Enable SPIM
0x500
read-write
ENABLE
Enable or disable SPIM
0
3
Disabled
Disable SPIM
0
Enabled
Enable SPIM
7
PSEL
Unspecified
SPIM_PSEL
read-write
0x508
SCK
Pin select for SCK
0x000
read-write
0xFFFFFFFF
PIN
Pin number
0
4
PORT
Port number
5
5
CONNECT
Connection
31
31
Disconnected
Disconnect
1
Connected
Connect
0
MOSI
Pin select for MOSI signal
0x004
read-write
0xFFFFFFFF
PIN
Pin number
0
4
PORT
Port number
5
5
CONNECT
Connection
31
31
Disconnected
Disconnect
1
Connected
Connect
0
MISO
Pin select for MISO signal
0x008
read-write
0xFFFFFFFF
PIN
Pin number
0
4
PORT
Port number
5
5
CONNECT
Connection
31
31
Disconnected
Disconnect
1
Connected
Connect
0
CSN
Pin select for CSN
0x00C
read-write
0xFFFFFFFF
PIN
Pin number
0
4
PORT
Port number
5
5
CONNECT
Connection
31
31
Disconnected
Disconnect
1
Connected
Connect
0
FREQUENCY
SPI frequency. Accuracy depends on the HFCLK source selected.
0x524
read-write
0x04000000
FREQUENCY
SPI master data rate
0
31
K125
125 kbps
0x02000000
K250
250 kbps
0x04000000
K500
500 kbps
0x08000000
M1
1 Mbps
0x10000000
M2
2 Mbps
0x20000000
M4
4 Mbps
0x40000000
M8
8 Mbps
0x80000000
M16
16 Mbps
0x0A000000
M32
32 Mbps
0x14000000
RXD
RXD EasyDMA channel
SPIM_RXD
read-write
0x534
PTR
Data pointer
0x000
read-write
PTR
Data pointer
0
31
MAXCNT
Maximum number of bytes in receive buffer
0x004
read-write
MAXCNT
Maximum number of bytes in receive buffer
0
15
AMOUNT
Number of bytes transferred in the last transaction
0x008
read-only
AMOUNT
Number of bytes transferred in the last transaction
0
15
LIST
EasyDMA list type
0x00C
read-write
LIST
List type
0
1
Disabled
Disable EasyDMA list
0
ArrayList
Use array list
1
TXD
TXD EasyDMA channel
SPIM_TXD
read-write
0x544
PTR
Data pointer
0x000
read-write
PTR
Data pointer
0
31
MAXCNT
Number of bytes in transmit buffer
0x004
read-write
MAXCNT
Maximum number of bytes in transmit buffer
0
15
AMOUNT
Number of bytes transferred in the last transaction
0x008
read-only
AMOUNT
Number of bytes transferred in the last transaction
0
15
LIST
EasyDMA list type
0x00C
read-write
LIST
List type
0
1
Disabled
Disable EasyDMA list
0
ArrayList
Use array list
1
CONFIG
Configuration register
0x554
read-write
ORDER
Bit order
0
0
MsbFirst
Most significant bit shifted out first
0
LsbFirst
Least significant bit shifted out first
1
CPHA
Serial clock (SCK) phase
1
1
Leading
Sample on leading edge of clock, shift serial data on trailing edge
0
Trailing
Sample on trailing edge of clock, shift serial data on leading edge
1
CPOL
Serial clock (SCK) polarity
2
2
ActiveHigh
Active high
0
ActiveLow
Active low
1
IFTIMING
Unspecified
SPIM_IFTIMING
read-write
0x560
RXDELAY
Sample delay for input serial data on MISO
0x000
read-write
0x00000002
RXDELAY
Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK.
0
2
CSNDUR
Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions
0x004
read-write
0x00000002
CSNDUR
Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns).
0
7
CSNPOL
Polarity of CSN output
0x568
read-write
0x00000000
CSNPOL
Polarity of CSN output
0
0
LOW
Active low (idle state high)
0
HIGH
Active high (idle state low)
1
PSELDCX
Pin select for DCX signal
0x56C
read-write
0xFFFFFFFF
PIN
Pin number
0
4
PORT
Port number
5
5
CONNECT
Connection
31
31
Disconnected
Disconnect
1
Connected
Connect
0
DCXCNT
DCX configuration
0x570
read-write
DCXCNT
This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes.
0
3
ORC
Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT
0x5C0
read-write
ORC
Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT.
0
7
SPIS0_NS
SPI Slave
0x41013000
SPIM0_NS
SPIS
0
0x1000
registers
SPIM0_SPIS0_TWIM0_TWIS0_UARTE0
19
SPIS
0x20
TASKS_ACQUIRE
Acquire SPI semaphore
0x024
write-only
TASKS_ACQUIRE
Acquire SPI semaphore
0
0
Trigger
Trigger task
1
TASKS_RELEASE
Release SPI semaphore, enabling the SPI slave to acquire it
0x028
write-only
TASKS_RELEASE
Release SPI semaphore, enabling the SPI slave to acquire it
0
0
Trigger
Trigger task
1
SUBSCRIBE_ACQUIRE
Subscribe configuration for task ACQUIRE
0x0A4
read-write
CHIDX
DPPI channel that task ACQUIRE will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_RELEASE
Subscribe configuration for task RELEASE
0x0A8
read-write
CHIDX
DPPI channel that task RELEASE will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
EVENTS_END
Granted transaction completed
0x104
read-write
EVENTS_END
Granted transaction completed
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_ENDRX
End of RXD buffer reached
0x110
read-write
EVENTS_ENDRX
End of RXD buffer reached
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_ACQUIRED
Semaphore acquired
0x128
read-write
EVENTS_ACQUIRED
Semaphore acquired
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
PUBLISH_END
Publish configuration for event END
0x184
read-write
CHIDX
DPPI channel that event END will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_ENDRX
Publish configuration for event ENDRX
0x190
read-write
CHIDX
DPPI channel that event ENDRX will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_ACQUIRED
Publish configuration for event ACQUIRED
0x1A8
read-write
CHIDX
DPPI channel that event ACQUIRED will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
SHORTS
Shortcuts between local events and tasks
0x200
read-write
END_ACQUIRE
Shortcut between event END and task ACQUIRE
2
2
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
INTENSET
Enable interrupt
0x304
read-write
END
Write '1' to enable interrupt for event END
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
ENDRX
Write '1' to enable interrupt for event ENDRX
4
4
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
ACQUIRED
Write '1' to enable interrupt for event ACQUIRED
10
10
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
INTENCLR
Disable interrupt
0x308
read-write
END
Write '1' to disable interrupt for event END
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
ENDRX
Write '1' to disable interrupt for event ENDRX
4
4
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
ACQUIRED
Write '1' to disable interrupt for event ACQUIRED
10
10
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
SEMSTAT
Semaphore status register
0x400
read-only
0x00000001
SEMSTAT
Semaphore status
0
1
Free
Semaphore is free
0
CPU
Semaphore is assigned to CPU
1
SPIS
Semaphore is assigned to SPI slave
2
CPUPending
Semaphore is assigned to SPI but a handover to the CPU is pending
3
STATUS
Status from last transaction
0x440
read-write
OVERREAD
TX buffer over-read detected, and prevented
0
0
read
NotPresent
Read: error not present
0
Present
Read: error present
1
write
Clear
Write: clear error on writing '1'
1
OVERFLOW
RX buffer overflow detected, and prevented
1
1
read
NotPresent
Read: error not present
0
Present
Read: error present
1
write
Clear
Write: clear error on writing '1'
1
ENABLE
Enable SPI slave
0x500
read-write
ENABLE
Enable or disable SPI slave
0
3
Disabled
Disable SPI slave
0
Enabled
Enable SPI slave
2
PSEL
Unspecified
SPIS_PSEL
read-write
0x508
SCK
Pin select for SCK
0x000
read-write
0xFFFFFFFF
PIN
Pin number
0
4
PORT
Port number
5
5
CONNECT
Connection
31
31
Disconnected
Disconnect
1
Connected
Connect
0
MISO
Pin select for MISO signal
0x004
read-write
0xFFFFFFFF
PIN
Pin number
0
4
PORT
Port number
5
5
CONNECT
Connection
31
31
Disconnected
Disconnect
1
Connected
Connect
0
MOSI
Pin select for MOSI signal
0x008
read-write
0xFFFFFFFF
PIN
Pin number
0
4
PORT
Port number
5
5
CONNECT
Connection
31
31
Disconnected
Disconnect
1
Connected
Connect
0
CSN
Pin select for CSN signal
0x00C
read-write
0xFFFFFFFF
PIN
Pin number
0
4
PORT
Port number
5
5
CONNECT
Connection
31
31
Disconnected
Disconnect
1
Connected
Connect
0
RXD
Unspecified
SPIS_RXD
read-write
0x534
PTR
RXD data pointer
0x000
read-write
PTR
RXD data pointer
0
31
MAXCNT
Maximum number of bytes in receive buffer
0x004
read-write
MAXCNT
Maximum number of bytes in receive buffer
0
15
AMOUNT
Number of bytes received in last granted transaction
0x008
read-only
AMOUNT
Number of bytes received in the last granted transaction
0
15
LIST
EasyDMA list type
0x00C
read-write
LIST
List type
0
1
Disabled
Disable EasyDMA list
0
ArrayList
Use array list
1
TXD
Unspecified
SPIS_TXD
read-write
0x544
PTR
TXD data pointer
0x000
read-write
PTR
TXD data pointer
0
31
MAXCNT
Maximum number of bytes in transmit buffer
0x004
read-write
MAXCNT
Maximum number of bytes in transmit buffer
0
15
AMOUNT
Number of bytes transmitted in last granted transaction
0x008
read-only
AMOUNT
Number of bytes transmitted in last granted transaction
0
15
LIST
EasyDMA list type
0x00C
read-write
LIST
List type
0
1
Disabled
Disable EasyDMA list
0
ArrayList
Use array list
1
CONFIG
Configuration register
0x554
read-write
ORDER
Bit order
0
0
MsbFirst
Most significant bit shifted out first
0
LsbFirst
Least significant bit shifted out first
1
CPHA
Serial clock (SCK) phase
1
1
Leading
Sample on leading edge of clock, shift serial data on trailing edge
0
Trailing
Sample on trailing edge of clock, shift serial data on leading edge
1
CPOL
Serial clock (SCK) polarity
2
2
ActiveHigh
Active high
0
ActiveLow
Active low
1
DEF
Default character. Character clocked out in case of an ignored transaction.
0x55C
read-write
DEF
Default character. Character clocked out in case of an ignored transaction.
0
7
ORC
Over-read character
0x5C0
read-write
ORC
Over-read character. Character clocked out after an over-read of the transmit buffer.
0
7
TWIM0_NS
I2C compatible Two-Wire Master Interface with EasyDMA
0x41013000
SPIM0_NS
TWIM
0
0x1000
registers
SPIM0_SPIS0_TWIM0_TWIS0_UARTE0
19
TWIM
0x20
TASKS_STARTRX
Start TWI receive sequence
0x000
write-only
TASKS_STARTRX
Start TWI receive sequence
0
0
Trigger
Trigger task
1
TASKS_STARTTX
Start TWI transmit sequence
0x008
write-only
TASKS_STARTTX
Start TWI transmit sequence
0
0
Trigger
Trigger task
1
TASKS_STOP
Stop TWI transaction. Must be issued while the TWI master is not suspended.
0x014
write-only
TASKS_STOP
Stop TWI transaction. Must be issued while the TWI master is not suspended.
0
0
Trigger
Trigger task
1
TASKS_SUSPEND
Suspend TWI transaction
0x01C
write-only
TASKS_SUSPEND
Suspend TWI transaction
0
0
Trigger
Trigger task
1
TASKS_RESUME
Resume TWI transaction
0x020
write-only
TASKS_RESUME
Resume TWI transaction
0
0
Trigger
Trigger task
1
SUBSCRIBE_STARTRX
Subscribe configuration for task STARTRX
0x080
read-write
CHIDX
DPPI channel that task STARTRX will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_STARTTX
Subscribe configuration for task STARTTX
0x088
read-write
CHIDX
DPPI channel that task STARTTX will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_STOP
Subscribe configuration for task STOP
0x094
read-write
CHIDX
DPPI channel that task STOP will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_SUSPEND
Subscribe configuration for task SUSPEND
0x09C
read-write
CHIDX
DPPI channel that task SUSPEND will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_RESUME
Subscribe configuration for task RESUME
0x0A0
read-write
CHIDX
DPPI channel that task RESUME will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
EVENTS_STOPPED
TWI stopped
0x104
read-write
EVENTS_STOPPED
TWI stopped
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_ERROR
TWI error
0x124
read-write
EVENTS_ERROR
TWI error
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_SUSPENDED
SUSPEND task has been issued, TWI traffic is now suspended.
0x148
read-write
EVENTS_SUSPENDED
SUSPEND task has been issued, TWI traffic is now suspended.
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_RXSTARTED
Receive sequence started
0x14C
read-write
EVENTS_RXSTARTED
Receive sequence started
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_TXSTARTED
Transmit sequence started
0x150
read-write
EVENTS_TXSTARTED
Transmit sequence started
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_LASTRX
Byte boundary, starting to receive the last byte
0x15C
read-write
EVENTS_LASTRX
Byte boundary, starting to receive the last byte
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_LASTTX
Byte boundary, starting to transmit the last byte
0x160
read-write
EVENTS_LASTTX
Byte boundary, starting to transmit the last byte
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
PUBLISH_STOPPED
Publish configuration for event STOPPED
0x184
read-write
CHIDX
DPPI channel that event STOPPED will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_ERROR
Publish configuration for event ERROR
0x1A4
read-write
CHIDX
DPPI channel that event ERROR will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_SUSPENDED
Publish configuration for event SUSPENDED
0x1C8
read-write
CHIDX
DPPI channel that event SUSPENDED will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_RXSTARTED
Publish configuration for event RXSTARTED
0x1CC
read-write
CHIDX
DPPI channel that event RXSTARTED will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_TXSTARTED
Publish configuration for event TXSTARTED
0x1D0
read-write
CHIDX
DPPI channel that event TXSTARTED will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_LASTRX
Publish configuration for event LASTRX
0x1DC
read-write
CHIDX
DPPI channel that event LASTRX will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_LASTTX
Publish configuration for event LASTTX
0x1E0
read-write
CHIDX
DPPI channel that event LASTTX will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
SHORTS
Shortcuts between local events and tasks
0x200
read-write
LASTTX_STARTRX
Shortcut between event LASTTX and task STARTRX
7
7
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
LASTTX_SUSPEND
Shortcut between event LASTTX and task SUSPEND
8
8
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
LASTTX_STOP
Shortcut between event LASTTX and task STOP
9
9
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
LASTRX_STARTTX
Shortcut between event LASTRX and task STARTTX
10
10
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
LASTRX_SUSPEND
Shortcut between event LASTRX and task SUSPEND
11
11
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
LASTRX_STOP
Shortcut between event LASTRX and task STOP
12
12
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
INTEN
Enable or disable interrupt
0x300
read-write
STOPPED
Enable or disable interrupt for event STOPPED
1
1
Disabled
Disable
0
Enabled
Enable
1
ERROR
Enable or disable interrupt for event ERROR
9
9
Disabled
Disable
0
Enabled
Enable
1
SUSPENDED
Enable or disable interrupt for event SUSPENDED
18
18
Disabled
Disable
0
Enabled
Enable
1
RXSTARTED
Enable or disable interrupt for event RXSTARTED
19
19
Disabled
Disable
0
Enabled
Enable
1
TXSTARTED
Enable or disable interrupt for event TXSTARTED
20
20
Disabled
Disable
0
Enabled
Enable
1
LASTRX
Enable or disable interrupt for event LASTRX
23
23
Disabled
Disable
0
Enabled
Enable
1
LASTTX
Enable or disable interrupt for event LASTTX
24
24
Disabled
Disable
0
Enabled
Enable
1
INTENSET
Enable interrupt
0x304
read-write
STOPPED
Write '1' to enable interrupt for event STOPPED
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
ERROR
Write '1' to enable interrupt for event ERROR
9
9
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
SUSPENDED
Write '1' to enable interrupt for event SUSPENDED
18
18
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RXSTARTED
Write '1' to enable interrupt for event RXSTARTED
19
19
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
TXSTARTED
Write '1' to enable interrupt for event TXSTARTED
20
20
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
LASTRX
Write '1' to enable interrupt for event LASTRX
23
23
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
LASTTX
Write '1' to enable interrupt for event LASTTX
24
24
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
INTENCLR
Disable interrupt
0x308
read-write
STOPPED
Write '1' to disable interrupt for event STOPPED
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
ERROR
Write '1' to disable interrupt for event ERROR
9
9
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
SUSPENDED
Write '1' to disable interrupt for event SUSPENDED
18
18
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RXSTARTED
Write '1' to disable interrupt for event RXSTARTED
19
19
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
TXSTARTED
Write '1' to disable interrupt for event TXSTARTED
20
20
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
LASTRX
Write '1' to disable interrupt for event LASTRX
23
23
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
LASTTX
Write '1' to disable interrupt for event LASTTX
24
24
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
ERRORSRC
Error source
0x4C4
read-write
oneToClear
OVERRUN
Overrun error
0
0
NotReceived
Error did not occur
0
Received
Error occurred
1
ANACK
NACK received after sending the address (write '1' to clear)
1
1
NotReceived
Error did not occur
0
Received
Error occurred
1
DNACK
NACK received after sending a data byte (write '1' to clear)
2
2
NotReceived
Error did not occur
0
Received
Error occurred
1
ENABLE
Enable TWIM
0x500
read-write
ENABLE
Enable or disable TWIM
0
3
Disabled
Disable TWIM
0
Enabled
Enable TWIM
6
PSEL
Unspecified
TWIM_PSEL
read-write
0x508
SCL
Pin select for SCL signal
0x000
read-write
0xFFFFFFFF
PIN
Pin number
0
4
PORT
Port number
5
5
CONNECT
Connection
31
31
Disconnected
Disconnect
1
Connected
Connect
0
SDA
Pin select for SDA signal
0x004
read-write
0xFFFFFFFF
PIN
Pin number
0
4
PORT
Port number
5
5
CONNECT
Connection
31
31
Disconnected
Disconnect
1
Connected
Connect
0
FREQUENCY
TWI frequency. Accuracy depends on the HFCLK source selected.
0x524
read-write
0x04000000
FREQUENCY
TWI master clock frequency
0
31
K100
100 kbps
0x01980000
K250
250 kbps
0x04000000
K400
400 kbps
0x06400000
K1000
1000 kbps
0x0FF00000
RXD
RXD EasyDMA channel
TWIM_RXD
read-write
0x534
PTR
Data pointer
0x000
read-write
PTR
Data pointer
0
31
MAXCNT
Maximum number of bytes in receive buffer
0x004
read-write
MAXCNT
Maximum number of bytes in receive buffer
0
15
AMOUNT
Number of bytes transferred in the last transaction
0x008
read-only
AMOUNT
Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte.
0
15
LIST
EasyDMA list type
0x00C
read-write
LIST
List type
0
2
Disabled
Disable EasyDMA list
0
ArrayList
Use array list
1
TXD
TXD EasyDMA channel
TWIM_TXD
read-write
0x544
PTR
Data pointer
0x000
read-write
PTR
Data pointer
0
31
MAXCNT
Maximum number of bytes in transmit buffer
0x004
read-write
MAXCNT
Maximum number of bytes in transmit buffer
0
15
AMOUNT
Number of bytes transferred in the last transaction
0x008
read-only
AMOUNT
Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte.
0
15
LIST
EasyDMA list type
0x00C
read-write
LIST
List type
0
2
Disabled
Disable EasyDMA list
0
ArrayList
Use array list
1
ADDRESS
Address used in the TWI transfer
0x588
read-write
ADDRESS
Address used in the TWI transfer
0
6
TWIS0_NS
I2C compatible Two-Wire Slave Interface with EasyDMA
0x41013000
SPIM0_NS
TWIS
0
0x1000
registers
SPIM0_SPIS0_TWIM0_TWIS0_UARTE0
19
TWIS
0x20
TASKS_STOP
Stop TWI transaction
0x014
write-only
TASKS_STOP
Stop TWI transaction
0
0
Trigger
Trigger task
1
TASKS_SUSPEND
Suspend TWI transaction
0x01C
write-only
TASKS_SUSPEND
Suspend TWI transaction
0
0
Trigger
Trigger task
1
TASKS_RESUME
Resume TWI transaction
0x020
write-only
TASKS_RESUME
Resume TWI transaction
0
0
Trigger
Trigger task
1
TASKS_PREPARERX
Prepare the TWI slave to respond to a write command
0x030
write-only
TASKS_PREPARERX
Prepare the TWI slave to respond to a write command
0
0
Trigger
Trigger task
1
TASKS_PREPARETX
Prepare the TWI slave to respond to a read command
0x034
write-only
TASKS_PREPARETX
Prepare the TWI slave to respond to a read command
0
0
Trigger
Trigger task
1
SUBSCRIBE_STOP
Subscribe configuration for task STOP
0x094
read-write
CHIDX
DPPI channel that task STOP will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_SUSPEND
Subscribe configuration for task SUSPEND
0x09C
read-write
CHIDX
DPPI channel that task SUSPEND will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_RESUME
Subscribe configuration for task RESUME
0x0A0
read-write
CHIDX
DPPI channel that task RESUME will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_PREPARERX
Subscribe configuration for task PREPARERX
0x0B0
read-write
CHIDX
DPPI channel that task PREPARERX will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_PREPARETX
Subscribe configuration for task PREPARETX
0x0B4
read-write
CHIDX
DPPI channel that task PREPARETX will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
EVENTS_STOPPED
TWI stopped
0x104
read-write
EVENTS_STOPPED
TWI stopped
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_ERROR
TWI error
0x124
read-write
EVENTS_ERROR
TWI error
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_RXSTARTED
Receive sequence started
0x14C
read-write
EVENTS_RXSTARTED
Receive sequence started
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_TXSTARTED
Transmit sequence started
0x150
read-write
EVENTS_TXSTARTED
Transmit sequence started
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_WRITE
Write command received
0x164
read-write
EVENTS_WRITE
Write command received
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_READ
Read command received
0x168
read-write
EVENTS_READ
Read command received
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
PUBLISH_STOPPED
Publish configuration for event STOPPED
0x184
read-write
CHIDX
DPPI channel that event STOPPED will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_ERROR
Publish configuration for event ERROR
0x1A4
read-write
CHIDX
DPPI channel that event ERROR will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_RXSTARTED
Publish configuration for event RXSTARTED
0x1CC
read-write
CHIDX
DPPI channel that event RXSTARTED will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_TXSTARTED
Publish configuration for event TXSTARTED
0x1D0
read-write
CHIDX
DPPI channel that event TXSTARTED will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_WRITE
Publish configuration for event WRITE
0x1E4
read-write
CHIDX
DPPI channel that event WRITE will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_READ
Publish configuration for event READ
0x1E8
read-write
CHIDX
DPPI channel that event READ will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
SHORTS
Shortcuts between local events and tasks
0x200
read-write
WRITE_SUSPEND
Shortcut between event WRITE and task SUSPEND
13
13
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
READ_SUSPEND
Shortcut between event READ and task SUSPEND
14
14
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
INTEN
Enable or disable interrupt
0x300
read-write
STOPPED
Enable or disable interrupt for event STOPPED
1
1
Disabled
Disable
0
Enabled
Enable
1
ERROR
Enable or disable interrupt for event ERROR
9
9
Disabled
Disable
0
Enabled
Enable
1
RXSTARTED
Enable or disable interrupt for event RXSTARTED
19
19
Disabled
Disable
0
Enabled
Enable
1
TXSTARTED
Enable or disable interrupt for event TXSTARTED
20
20
Disabled
Disable
0
Enabled
Enable
1
WRITE
Enable or disable interrupt for event WRITE
25
25
Disabled
Disable
0
Enabled
Enable
1
READ
Enable or disable interrupt for event READ
26
26
Disabled
Disable
0
Enabled
Enable
1
INTENSET
Enable interrupt
0x304
read-write
STOPPED
Write '1' to enable interrupt for event STOPPED
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
ERROR
Write '1' to enable interrupt for event ERROR
9
9
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RXSTARTED
Write '1' to enable interrupt for event RXSTARTED
19
19
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
TXSTARTED
Write '1' to enable interrupt for event TXSTARTED
20
20
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
WRITE
Write '1' to enable interrupt for event WRITE
25
25
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
READ
Write '1' to enable interrupt for event READ
26
26
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
INTENCLR
Disable interrupt
0x308
read-write
STOPPED
Write '1' to disable interrupt for event STOPPED
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
ERROR
Write '1' to disable interrupt for event ERROR
9
9
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RXSTARTED
Write '1' to disable interrupt for event RXSTARTED
19
19
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
TXSTARTED
Write '1' to disable interrupt for event TXSTARTED
20
20
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
WRITE
Write '1' to disable interrupt for event WRITE
25
25
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
READ
Write '1' to disable interrupt for event READ
26
26
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
ERRORSRC
Error source
0x4D0
read-write
oneToClear
OVERFLOW
RX buffer overflow detected, and prevented
0
0
NotDetected
Error did not occur
0
Detected
Error occurred
1
DNACK
NACK sent after receiving a data byte
2
2
NotReceived
Error did not occur
0
Received
Error occurred
1
OVERREAD
TX buffer over-read detected, and prevented
3
3
NotDetected
Error did not occur
0
Detected
Error occurred
1
MATCH
Status register indicating which address had a match
0x4D4
read-only
MATCH
Which of the addresses in {ADDRESS} matched the incoming address
0
0
ENABLE
Enable TWIS
0x500
read-write
ENABLE
Enable or disable TWIS
0
3
Disabled
Disable TWIS
0
Enabled
Enable TWIS
9
PSEL
Unspecified
TWIS_PSEL
read-write
0x508
SCL
Pin select for SCL signal
0x000
read-write
0xFFFFFFFF
PIN
Pin number
0
4
PORT
Port number
5
5
CONNECT
Connection
31
31
Disconnected
Disconnect
1
Connected
Connect
0
SDA
Pin select for SDA signal
0x004
read-write
0xFFFFFFFF
PIN
Pin number
0
4
PORT
Port number
5
5
CONNECT
Connection
31
31
Disconnected
Disconnect
1
Connected
Connect
0
RXD
RXD EasyDMA channel
TWIS_RXD
read-write
0x534
PTR
RXD Data pointer
0x000
read-write
PTR
RXD Data pointer
0
31
MAXCNT
Maximum number of bytes in RXD buffer
0x004
read-write
MAXCNT
Maximum number of bytes in RXD buffer
0
15
AMOUNT
Number of bytes transferred in the last RXD transaction
0x008
read-only
AMOUNT
Number of bytes transferred in the last RXD transaction
0
15
LIST
EasyDMA list type
0x00C
read-write
LIST
List type
0
1
Disabled
Disable EasyDMA list
0
ArrayList
Use array list
1
TXD
TXD EasyDMA channel
TWIS_TXD
read-write
0x544
PTR
TXD Data pointer
0x000
read-write
PTR
TXD Data pointer
0
31
MAXCNT
Maximum number of bytes in TXD buffer
0x004
read-write
MAXCNT
Maximum number of bytes in TXD buffer
0
15
AMOUNT
Number of bytes transferred in the last TXD transaction
0x008
read-only
AMOUNT
Number of bytes transferred in the last TXD transaction
0
15
LIST
EasyDMA list type
0x00C
read-write
LIST
List type
0
1
Disabled
Disable EasyDMA list
0
ArrayList
Use array list
1
0x2
0x4
ADDRESS[%s]
Description collection: TWI slave address n
0x588
read-write
ADDRESS
TWI slave address
0
6
CONFIG
Configuration register for the address match mechanism
0x594
read-write
0x00000001
ADDRESS0
Enable or disable address matching on ADDRESS[0]
0
0
Disabled
Disabled
0
Enabled
Enabled
1
ADDRESS1
Enable or disable address matching on ADDRESS[1]
1
1
Disabled
Disabled
0
Enabled
Enabled
1
ORC
Over-read character. Character sent out in case of an over-read of the transmit buffer.
0x5C0
read-write
ORC
Over-read character. Character sent out in case of an over-read of the transmit buffer.
0
7
UARTE0_NS
UART with EasyDMA
0x41013000
SPIM0_NS
UARTE
0
0x1000
registers
SPIM0_SPIS0_TWIM0_TWIS0_UARTE0
19
UARTE
0x20
TASKS_STARTRX
Start UART receiver
0x000
write-only
TASKS_STARTRX
Start UART receiver
0
0
Trigger
Trigger task
1
TASKS_STOPRX
Stop UART receiver
0x004
write-only
TASKS_STOPRX
Stop UART receiver
0
0
Trigger
Trigger task
1
TASKS_STARTTX
Start UART transmitter
0x008
write-only
TASKS_STARTTX
Start UART transmitter
0
0
Trigger
Trigger task
1
TASKS_STOPTX
Stop UART transmitter
0x00C
write-only
TASKS_STOPTX
Stop UART transmitter
0
0
Trigger
Trigger task
1
TASKS_FLUSHRX
Flush RX FIFO into RX buffer
0x02C
write-only
TASKS_FLUSHRX
Flush RX FIFO into RX buffer
0
0
Trigger
Trigger task
1
SUBSCRIBE_STARTRX
Subscribe configuration for task STARTRX
0x080
read-write
CHIDX
DPPI channel that task STARTRX will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_STOPRX
Subscribe configuration for task STOPRX
0x084
read-write
CHIDX
DPPI channel that task STOPRX will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_STARTTX
Subscribe configuration for task STARTTX
0x088
read-write
CHIDX
DPPI channel that task STARTTX will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_STOPTX
Subscribe configuration for task STOPTX
0x08C
read-write
CHIDX
DPPI channel that task STOPTX will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
SUBSCRIBE_FLUSHRX
Subscribe configuration for task FLUSHRX
0x0AC
read-write
CHIDX
DPPI channel that task FLUSHRX will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
EVENTS_CTS
CTS is activated (set low). Clear To Send.
0x100
read-write
EVENTS_CTS
CTS is activated (set low). Clear To Send.
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_NCTS
CTS is deactivated (set high). Not Clear To Send.
0x104
read-write
EVENTS_NCTS
CTS is deactivated (set high). Not Clear To Send.
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_RXDRDY
Data received in RXD (but potentially not yet transferred to Data RAM)
0x108
read-write
EVENTS_RXDRDY
Data received in RXD (but potentially not yet transferred to Data RAM)
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_ENDRX
Receive buffer is filled up
0x110
read-write
EVENTS_ENDRX
Receive buffer is filled up
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_TXDRDY
Data sent from TXD
0x11C
read-write
EVENTS_TXDRDY
Data sent from TXD
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_ENDTX
Last TX byte transmitted
0x120
read-write
EVENTS_ENDTX
Last TX byte transmitted
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_ERROR
Error detected
0x124
read-write
EVENTS_ERROR
Error detected
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_RXTO
Receiver timeout
0x144
read-write
EVENTS_RXTO
Receiver timeout
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_RXSTARTED
UART receiver has started
0x14C
read-write
EVENTS_RXSTARTED
UART receiver has started
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_TXSTARTED
UART transmitter has started
0x150
read-write
EVENTS_TXSTARTED
UART transmitter has started
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
EVENTS_TXSTOPPED
Transmitter stopped
0x158
read-write
EVENTS_TXSTOPPED
Transmitter stopped
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
PUBLISH_CTS
Publish configuration for event CTS
0x180
read-write
CHIDX
DPPI channel that event CTS will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_NCTS
Publish configuration for event NCTS
0x184
read-write
CHIDX
DPPI channel that event NCTS will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_RXDRDY
Publish configuration for event RXDRDY
0x188
read-write
CHIDX
DPPI channel that event RXDRDY will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_ENDRX
Publish configuration for event ENDRX
0x190
read-write
CHIDX
DPPI channel that event ENDRX will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_TXDRDY
Publish configuration for event TXDRDY
0x19C
read-write
CHIDX
DPPI channel that event TXDRDY will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_ENDTX
Publish configuration for event ENDTX
0x1A0
read-write
CHIDX
DPPI channel that event ENDTX will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_ERROR
Publish configuration for event ERROR
0x1A4
read-write
CHIDX
DPPI channel that event ERROR will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_RXTO
Publish configuration for event RXTO
0x1C4
read-write
CHIDX
DPPI channel that event RXTO will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_RXSTARTED
Publish configuration for event RXSTARTED
0x1CC
read-write
CHIDX
DPPI channel that event RXSTARTED will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_TXSTARTED
Publish configuration for event TXSTARTED
0x1D0
read-write
CHIDX
DPPI channel that event TXSTARTED will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
PUBLISH_TXSTOPPED
Publish configuration for event TXSTOPPED
0x1D8
read-write
CHIDX
DPPI channel that event TXSTOPPED will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
SHORTS
Shortcuts between local events and tasks
0x200
read-write
ENDRX_STARTRX
Shortcut between event ENDRX and task STARTRX
5
5
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
ENDRX_STOPRX
Shortcut between event ENDRX and task STOPRX
6
6
Disabled
Disable shortcut
0
Enabled
Enable shortcut
1
INTEN
Enable or disable interrupt
0x300
read-write
CTS
Enable or disable interrupt for event CTS
0
0
Disabled
Disable
0
Enabled
Enable
1
NCTS
Enable or disable interrupt for event NCTS
1
1
Disabled
Disable
0
Enabled
Enable
1
RXDRDY
Enable or disable interrupt for event RXDRDY
2
2
Disabled
Disable
0
Enabled
Enable
1
ENDRX
Enable or disable interrupt for event ENDRX
4
4
Disabled
Disable
0
Enabled
Enable
1
TXDRDY
Enable or disable interrupt for event TXDRDY
7
7
Disabled
Disable
0
Enabled
Enable
1
ENDTX
Enable or disable interrupt for event ENDTX
8
8
Disabled
Disable
0
Enabled
Enable
1
ERROR
Enable or disable interrupt for event ERROR
9
9
Disabled
Disable
0
Enabled
Enable
1
RXTO
Enable or disable interrupt for event RXTO
17
17
Disabled
Disable
0
Enabled
Enable
1
RXSTARTED
Enable or disable interrupt for event RXSTARTED
19
19
Disabled
Disable
0
Enabled
Enable
1
TXSTARTED
Enable or disable interrupt for event TXSTARTED
20
20
Disabled
Disable
0
Enabled
Enable
1
TXSTOPPED
Enable or disable interrupt for event TXSTOPPED
22
22
Disabled
Disable
0
Enabled
Enable
1
INTENSET
Enable interrupt
0x304
read-write
CTS
Write '1' to enable interrupt for event CTS
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
NCTS
Write '1' to enable interrupt for event NCTS
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RXDRDY
Write '1' to enable interrupt for event RXDRDY
2
2
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
ENDRX
Write '1' to enable interrupt for event ENDRX
4
4
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
TXDRDY
Write '1' to enable interrupt for event TXDRDY
7
7
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
ENDTX
Write '1' to enable interrupt for event ENDTX
8
8
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
ERROR
Write '1' to enable interrupt for event ERROR
9
9
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RXTO
Write '1' to enable interrupt for event RXTO
17
17
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
RXSTARTED
Write '1' to enable interrupt for event RXSTARTED
19
19
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
TXSTARTED
Write '1' to enable interrupt for event TXSTARTED
20
20
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
TXSTOPPED
Write '1' to enable interrupt for event TXSTOPPED
22
22
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
INTENCLR
Disable interrupt
0x308
read-write
CTS
Write '1' to disable interrupt for event CTS
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
NCTS
Write '1' to disable interrupt for event NCTS
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RXDRDY
Write '1' to disable interrupt for event RXDRDY
2
2
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
ENDRX
Write '1' to disable interrupt for event ENDRX
4
4
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
TXDRDY
Write '1' to disable interrupt for event TXDRDY
7
7
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
ENDTX
Write '1' to disable interrupt for event ENDTX
8
8
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
ERROR
Write '1' to disable interrupt for event ERROR
9
9
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RXTO
Write '1' to disable interrupt for event RXTO
17
17
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RXSTARTED
Write '1' to disable interrupt for event RXSTARTED
19
19
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
TXSTARTED
Write '1' to disable interrupt for event TXSTARTED
20
20
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
TXSTOPPED
Write '1' to disable interrupt for event TXSTOPPED
22
22
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
ERRORSRC
Error source Note : this register is read / write one to clear.
0x480
read-write
oneToClear
OVERRUN
Overrun error
0
0
read
NotPresent
Read: error not present
0
Present
Read: error present
1
PARITY
Parity error
1
1
read
NotPresent
Read: error not present
0
Present
Read: error present
1
FRAMING
Framing error occurred
2
2
read
NotPresent
Read: error not present
0
Present
Read: error present
1
BREAK
Break condition
3
3
read
NotPresent
Read: error not present
0
Present
Read: error present
1
ENABLE
Enable UART
0x500
read-write
ENABLE
Enable or disable UARTE
0
3
Disabled
Disable UARTE
0
Enabled
Enable UARTE
8
PSEL
Unspecified
UARTE_PSEL
read-write
0x508
RTS
Pin select for RTS signal
0x000
read-write
0xFFFFFFFF
PIN
Pin number
0
4
PORT
Port number
5
5
CONNECT
Connection
31
31
Disconnected
Disconnect
1
Connected
Connect
0
TXD
Pin select for TXD signal
0x004
read-write
0xFFFFFFFF
PIN
Pin number
0
4
PORT
Port number
5
5
CONNECT
Connection
31
31
Disconnected
Disconnect
1
Connected
Connect
0
CTS
Pin select for CTS signal
0x008
read-write
0xFFFFFFFF
PIN
Pin number
0
4
PORT
Port number
5
5
CONNECT
Connection
31
31
Disconnected
Disconnect
1
Connected
Connect
0
RXD
Pin select for RXD signal
0x00C
read-write
0xFFFFFFFF
PIN
Pin number
0
4
PORT
Port number
5
5
CONNECT
Connection
31
31
Disconnected
Disconnect
1
Connected
Connect
0
BAUDRATE
Baud rate. Accuracy depends on the HFCLK source selected.
0x524
read-write
0x04000000
BAUDRATE
Baud rate
0
31
Baud1200
1200 baud (actual rate: 1205)
0x0004F000
Baud2400
2400 baud (actual rate: 2396)
0x0009D000
Baud4800
4800 baud (actual rate: 4808)
0x0013B000
Baud9600
9600 baud (actual rate: 9598)
0x00275000
Baud14400
14400 baud (actual rate: 14401)
0x003AF000
Baud19200
19200 baud (actual rate: 19208)
0x004EA000
Baud28800
28800 baud (actual rate: 28777)
0x0075C000
Baud31250
31250 baud
0x00800000
Baud38400
38400 baud (actual rate: 38369)
0x009D0000
Baud56000
56000 baud (actual rate: 55944)
0x00E50000
Baud57600
57600 baud (actual rate: 57554)
0x00EB0000
Baud76800
76800 baud (actual rate: 76923)
0x013A9000
Baud115200
115200 baud (actual rate: 115108)
0x01D60000
Baud230400
230400 baud (actual rate: 231884)
0x03B00000
Baud250000
250000 baud
0x04000000
Baud460800
460800 baud (actual rate: 457143)
0x07400000
Baud921600
921600 baud (actual rate: 941176)
0x0F000000
Baud1M
1Mega baud
0x10000000
RXD
RXD EasyDMA channel
UARTE_RXD
read-write
0x534
PTR
Data pointer
0x000
read-write
PTR
Data pointer
0
31
MAXCNT
Maximum number of bytes in receive buffer
0x004
read-write
MAXCNT
Maximum number of bytes in receive buffer
0
15
AMOUNT
Number of bytes transferred in the last transaction
0x008
read-only
AMOUNT
Number of bytes transferred in the last transaction
0
15
TXD
TXD EasyDMA channel
UARTE_TXD
read-write
0x544
PTR
Data pointer
0x000
read-write
PTR
Data pointer
0
31
MAXCNT
Maximum number of bytes in transmit buffer
0x004
read-write
MAXCNT
Maximum number of bytes in transmit buffer
0
15
AMOUNT
Number of bytes transferred in the last transaction
0x008
read-only
AMOUNT
Number of bytes transferred in the last transaction
0
15
CONFIG
Configuration of parity and hardware flow control
0x56C
read-write
HWFC
Hardware flow control
0
0
Disabled
Disabled
0
Enabled
Enabled
1
PARITY
Parity
1
3
Excluded
Exclude parity bit
0x0
Included
Include even parity bit
0x7
STOP
Stop bits
4
4
One
One stop bit
0
Two
Two stop bits
1
PARITYTYPE
Even or odd parity type
8
8
Even
Even parity
0
Odd
Odd parity
1
EGU0_NS
Event generator unit
0x41014000
EGU
0
0x1000
registers
EGU0
20
EGU
0x20
0x10
0x4
TASKS_TRIGGER[%s]
Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event
0x000
write-only
TASKS_TRIGGER
Trigger n for triggering the corresponding TRIGGERED[n] event
0
0
Trigger
Trigger task
1
0x10
0x4
SUBSCRIBE_TRIGGER[%s]
Description collection: Subscribe configuration for task TRIGGER[n]
0x080
read-write
CHIDX
DPPI channel that task TRIGGER[n] will subscribe to
0
7
EN
31
31
Disabled
Disable subscription
0
Enabled
Enable subscription
1
0x10
0x4
EVENTS_TRIGGERED[%s]
Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task
0x100
read-write
EVENTS_TRIGGERED
Event number n generated by triggering the corresponding TRIGGER[n] task
0
0
NotGenerated
Event not generated
0
Generated
Event generated
1
0x10
0x4
PUBLISH_TRIGGERED[%s]
Description collection: Publish configuration for event TRIGGERED[n]
0x180
read-write
CHIDX
DPPI channel that event TRIGGERED[n] will publish to.
0
7
EN
31
31
Disabled
Disable publishing
0
Enabled
Enable publishing
1
INTEN
Enable or disable interrupt
0x300
read-write
TRIGGERED0
Enable or disable interrupt for event TRIGGERED[0]
0
0
Disabled
Disable
0
Enabled
Enable
1
TRIGGERED1
Enable or disable interrupt for event TRIGGERED[1]
1
1
Disabled
Disable
0
Enabled
Enable
1
TRIGGERED2
Enable or disable interrupt for event TRIGGERED[2]
2
2
Disabled
Disable
0
Enabled
Enable
1
TRIGGERED3
Enable or disable interrupt for event TRIGGERED[3]
3
3
Disabled
Disable
0
Enabled
Enable
1
TRIGGERED4
Enable or disable interrupt for event TRIGGERED[4]
4
4
Disabled
Disable
0
Enabled
Enable
1
TRIGGERED5
Enable or disable interrupt for event TRIGGERED[5]
5
5
Disabled
Disable
0
Enabled
Enable
1
TRIGGERED6
Enable or disable interrupt for event TRIGGERED[6]
6
6
Disabled
Disable
0
Enabled
Enable
1
TRIGGERED7
Enable or disable interrupt for event TRIGGERED[7]
7
7
Disabled
Disable
0
Enabled
Enable
1
TRIGGERED8
Enable or disable interrupt for event TRIGGERED[8]
8
8
Disabled
Disable
0
Enabled
Enable
1
TRIGGERED9
Enable or disable interrupt for event TRIGGERED[9]
9
9
Disabled
Disable
0
Enabled
Enable
1
TRIGGERED10
Enable or disable interrupt for event TRIGGERED[10]
10
10
Disabled
Disable
0
Enabled
Enable
1
TRIGGERED11
Enable or disable interrupt for event TRIGGERED[11]
11
11
Disabled
Disable
0
Enabled
Enable
1
TRIGGERED12
Enable or disable interrupt for event TRIGGERED[12]
12
12
Disabled
Disable
0
Enabled
Enable
1
TRIGGERED13
Enable or disable interrupt for event TRIGGERED[13]
13
13
Disabled
Disable
0
Enabled
Enable
1
TRIGGERED14
Enable or disable interrupt for event TRIGGERED[14]
14
14
Disabled
Disable
0
Enabled
Enable
1
TRIGGERED15
Enable or disable interrupt for event TRIGGERED[15]
15
15
Disabled
Disable
0
Enabled
Enable
1
INTENSET
Enable interrupt
0x304
read-write
TRIGGERED0
Write '1' to enable interrupt for event TRIGGERED[0]
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
TRIGGERED1
Write '1' to enable interrupt for event TRIGGERED[1]
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
TRIGGERED2
Write '1' to enable interrupt for event TRIGGERED[2]
2
2
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
TRIGGERED3
Write '1' to enable interrupt for event TRIGGERED[3]
3
3
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
TRIGGERED4
Write '1' to enable interrupt for event TRIGGERED[4]
4
4
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
TRIGGERED5
Write '1' to enable interrupt for event TRIGGERED[5]
5
5
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
TRIGGERED6
Write '1' to enable interrupt for event TRIGGERED[6]
6
6
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
TRIGGERED7
Write '1' to enable interrupt for event TRIGGERED[7]
7
7
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
TRIGGERED8
Write '1' to enable interrupt for event TRIGGERED[8]
8
8
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
TRIGGERED9
Write '1' to enable interrupt for event TRIGGERED[9]
9
9
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
TRIGGERED10
Write '1' to enable interrupt for event TRIGGERED[10]
10
10
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
TRIGGERED11
Write '1' to enable interrupt for event TRIGGERED[11]
11
11
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
TRIGGERED12
Write '1' to enable interrupt for event TRIGGERED[12]
12
12
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
TRIGGERED13
Write '1' to enable interrupt for event TRIGGERED[13]
13
13
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
TRIGGERED14
Write '1' to enable interrupt for event TRIGGERED[14]
14
14
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
TRIGGERED15
Write '1' to enable interrupt for event TRIGGERED[15]
15
15
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Set
Enable
1
INTENCLR
Disable interrupt
0x308
read-write
TRIGGERED0
Write '1' to disable interrupt for event TRIGGERED[0]
0
0
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
TRIGGERED1
Write '1' to disable interrupt for event TRIGGERED[1]
1
1
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
TRIGGERED2
Write '1' to disable interrupt for event TRIGGERED[2]
2
2
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
TRIGGERED3
Write '1' to disable interrupt for event TRIGGERED[3]
3
3
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
TRIGGERED4
Write '1' to disable interrupt for event TRIGGERED[4]
4
4
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
TRIGGERED5
Write '1' to disable interrupt for event TRIGGERED[5]
5
5
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
TRIGGERED6
Write '1' to disable interrupt for event TRIGGERED[6]
6
6
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
TRIGGERED7
Write '1' to disable interrupt for event TRIGGERED[7]
7
7
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
TRIGGERED8
Write '1' to disable interrupt for event TRIGGERED[8]
8
8
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
TRIGGERED9
Write '1' to disable interrupt for event TRIGGERED[9]
9
9
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
TRIGGERED10
Write '1' to disable interrupt for event TRIGGERED[10]
10
10
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
TRIGGERED11
Write '1' to disable interrupt for event TRIGGERED[11]
11
11
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
TRIGGERED12
Write '1' to disable interrupt for event TRIGGERED[12]
12
12
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
TRIGGERED13
Write '1' to disable interrupt for event TRIGGERED[13]
13
13
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
TRIGGERED14
Write '1' to disable interrupt for event TRIGGERED[14]
14
14
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
TRIGGERED15
Write '1' to disable interrupt for event TRIGGERED[15]
15
15
read
Disabled
Read: Disabled
0
Enabled
Read: Enabled
1
write
Clear
Disable
1
RTC1_NS
Real-time counter 1
0x41016000
RTC1
22
TIMER1_NS
Timer/Counter 1
0x41018000
TIMER1
24
TIMER2_NS
Timer/Counter 2
0x41019000
TIMER2
25
SWI0_NS
Software interrupt 0
0x4101A000
SWI
0
0x1000
registers
SWI0
26
SWI
0x20
UNUSED
Unused.
0x000
0x00000000
read-only
SWI1_NS
Software interrupt 1
0x4101B000
SWI1
27
SWI2_NS
Software interrupt 2
0x4101C000
SWI2
28
SWI3_NS
Software interrupt 3
0x4101D000
SWI3
29
APPMUTEX_NS
MUTEX 0
0x40030000
MUTEX
0
0x1000
registers
MUTEX
0x20
0x10
0x4
MUTEX[%s]
Description collection: Mutex register
0x400
read-write
MUTEX
Mutex register n
0
0
Unlocked
Mutex n is in unlocked state
0
Locked
Mutex n is in locked state
1
APPMUTEX_S
MUTEX 1
0x50030000
ACL_NS
Access control lists
0x41080000
ACL
0
0x1000
registers
ACL
0x20
8
0x010
ACL[%s]
Unspecified
ACL_ACL
read-write
0x800
ADDR
Description cluster: Configure the word-aligned start address of region n to protect
0x000
read-writeonce
0x00000000
ADDR
Valid word-aligned start address of region n to protect. Address must point to a flash page boundary.
0
31
SIZE
Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect.
0x004
read-writeonce
0x00000000
SIZE
Size of flash region n in bytes. Must be a multiple of the flash page size.
0
31
PERM
Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE
0x008
read-writeonce
0x00000000
WRITE
Configure write and erase permissions for region n. Write '0' has no effect.
1
1
Enable
Allow write and erase instructions to region n
0
Disable
Block write and erase instructions to region n
1
READ
Configure read permissions for region n. Write '0' has no effect.
2
2
Enable
Allow read instructions to region n
0
Disable
Block read instructions to region n
1
NVMC_NS
Non-volatile memory controller
0x41080000
ACL_NS
NVMC
0
0x1000
registers
NVMC
0x20
READY
Ready flag
0x400
read-only
0x00000001
READY
NVMC is ready or busy
0
0
Busy
NVMC is busy (on-going write or erase operation)
0
Ready
NVMC is ready
1
READYNEXT
Ready flag
0x408
read-only
0x00000001
READYNEXT
NVMC can accept a new write operation
0
0
Busy
NVMC cannot accept any write operation
0
Ready
NVMC is ready
1
CONFIG
Configuration register
0x504
read-write
WEN
Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated.
0
2
Ren
Read only access
0
Wen
Write enabled
1
Een
Erase enabled
2
PEen
Partial erase enabled
4
ERASEALL
Register for erasing all non-volatile user memory
0x50C
write-only
ERASEALL
Erase all non-volatile memory including UICR registers. Note that erasing must be enabled by setting CONFIG.WEN = Een before the non-volatile memory can be erased.
0
0
NoOperation
No operation
0
Erase
Start chip erase
1
ERASEPAGEPARTIALCFG
Register for partial erase configuration
0x51C
read-write
0x0000000A
DURATION
Duration of the partial erase in milliseconds
0
6
ICACHECNF
I-code cache configuration register
0x540
read-write
0x00000000
CACHEEN
Cache enable
0
0
Disabled
Disable cache. Invalidates all cache entries.
0
Enabled
Enable cache
1
CACHEPROFEN
Cache profiling enable
8
8
Disabled
Disable cache profiling
0
Enabled
Enable cache profiling
1
IHIT
I-code cache hit counter
0x548
read-write
HITS
Number of cache hits Write zero to clear
0
31
IMISS
I-code cache miss counter
0x54C
read-write
MISSES
Number of cache misses Write zero to clear
0
31
VMC_NS
Volatile Memory controller
0x41081000
VMC
0
0x1000
registers
VMC
0x20
4
0x010
RAM[%s]
Unspecified
VMC_RAM
read-write
0x600
POWER
Description cluster: RAM[n] power control register
0x000
read-write
0x0000FFFF
S0POWER
Keep RAM section S0 of RAM[n] on or off in System ON mode
0
0
Off
Off
0
On
On
1
S1POWER
Keep RAM section S1 of RAM[n] on or off in System ON mode
1
1
Off
Off
0
On
On
1
S2POWER
Keep RAM section S2 of RAM[n] on or off in System ON mode
2
2
Off
Off
0
On
On
1
S3POWER
Keep RAM section S3 of RAM[n] on or off in System ON mode
3
3
Off
Off
0
On
On
1
S0RETENTION
Keep retention on RAM section S0 of RAM[n] when RAM section is switched off
16
16
Off
Off
0
On
On
1
S1RETENTION
Keep retention on RAM section S1 of RAM[n] when RAM section is switched off
17
17
Off
Off
0
On
On
1
S2RETENTION
Keep retention on RAM section S2 of RAM[n] when RAM section is switched off
18
18
Off
Off
0
On
On
1
S3RETENTION
Keep retention on RAM section S3 of RAM[n] when RAM section is switched off
19
19
Off
Off
0
On
On
1
POWERSET
Description cluster: RAM[n] power control set register
0x004
read-write
0x0000FFFF
S0POWER
Keep RAM section S0 of RAM[n] on or off in System ON mode
0
0
On
On
1
S1POWER
Keep RAM section S1 of RAM[n] on or off in System ON mode
1
1
On
On
1
S2POWER
Keep RAM section S2 of RAM[n] on or off in System ON mode
2
2
On
On
1
S3POWER
Keep RAM section S3 of RAM[n] on or off in System ON mode
3
3
On
On
1
S0RETENTION
Keep retention on RAM section S0 of RAM[n] when RAM section is switched off
16
16
On
On
1
S1RETENTION
Keep retention on RAM section S1 of RAM[n] when RAM section is switched off
17
17
On
On
1
S2RETENTION
Keep retention on RAM section S2 of RAM[n] when RAM section is switched off
18
18
On
On
1
S3RETENTION
Keep retention on RAM section S3 of RAM[n] when RAM section is switched off
19
19
On
On
1
POWERCLR
Description cluster: RAM[n] power control clear register
0x008
read-write
0x0000FFFF
S0POWER
Keep RAM section S0 of RAM[n] on or off in System ON mode
0
0
Off
Off
1
S1POWER
Keep RAM section S1 of RAM[n] on or off in System ON mode
1
1
Off
Off
1
S2POWER
Keep RAM section S2 of RAM[n] on or off in System ON mode
2
2
Off
Off
1
S3POWER
Keep RAM section S3 of RAM[n] on or off in System ON mode
3
3
Off
Off
1
S0RETENTION
Keep retention on RAM section S0 of RAM[n] when RAM section is switched off
16
16
Off
Off
1
S1RETENTION
Keep retention on RAM section S1 of RAM[n] when RAM section is switched off
17
17
Off
Off
1
S2RETENTION
Keep retention on RAM section S2 of RAM[n] when RAM section is switched off
18
18
Off
Off
1
S3RETENTION
Keep retention on RAM section S3 of RAM[n] when RAM section is switched off
19
19
Off
Off
1
P0_NS
GPIO Port 0
0x418C0500
GPIO
0
0x300
registers
GPIO
0x20
OUT
Write GPIO port
0x004
read-write
PIN0
Pin 0
0
0
Low
Pin driver is low
0
High
Pin driver is high
1
PIN1
Pin 1
1
1
Low
Pin driver is low
0
High
Pin driver is high
1
PIN2
Pin 2
2
2
Low
Pin driver is low
0
High
Pin driver is high
1
PIN3
Pin 3
3
3
Low
Pin driver is low
0
High
Pin driver is high
1
PIN4
Pin 4
4
4
Low
Pin driver is low
0
High
Pin driver is high
1
PIN5
Pin 5
5
5
Low
Pin driver is low
0
High
Pin driver is high
1
PIN6
Pin 6
6
6
Low
Pin driver is low
0
High
Pin driver is high
1
PIN7
Pin 7
7
7
Low
Pin driver is low
0
High
Pin driver is high
1
PIN8
Pin 8
8
8
Low
Pin driver is low
0
High
Pin driver is high
1
PIN9
Pin 9
9
9
Low
Pin driver is low
0
High
Pin driver is high
1
PIN10
Pin 10
10
10
Low
Pin driver is low
0
High
Pin driver is high
1
PIN11
Pin 11
11
11
Low
Pin driver is low
0
High
Pin driver is high
1
PIN12
Pin 12
12
12
Low
Pin driver is low
0
High
Pin driver is high
1
PIN13
Pin 13
13
13
Low
Pin driver is low
0
High
Pin driver is high
1
PIN14
Pin 14
14
14
Low
Pin driver is low
0
High
Pin driver is high
1
PIN15
Pin 15
15
15
Low
Pin driver is low
0
High
Pin driver is high
1
PIN16
Pin 16
16
16
Low
Pin driver is low
0
High
Pin driver is high
1
PIN17
Pin 17
17
17
Low
Pin driver is low
0
High
Pin driver is high
1
PIN18
Pin 18
18
18
Low
Pin driver is low
0
High
Pin driver is high
1
PIN19
Pin 19
19
19
Low
Pin driver is low
0
High
Pin driver is high
1
PIN20
Pin 20
20
20
Low
Pin driver is low
0
High
Pin driver is high
1
PIN21
Pin 21
21
21
Low
Pin driver is low
0
High
Pin driver is high
1
PIN22
Pin 22
22
22
Low
Pin driver is low
0
High
Pin driver is high
1
PIN23
Pin 23
23
23
Low
Pin driver is low
0
High
Pin driver is high
1
PIN24
Pin 24
24
24
Low
Pin driver is low
0
High
Pin driver is high
1
PIN25
Pin 25
25
25
Low
Pin driver is low
0
High
Pin driver is high
1
PIN26
Pin 26
26
26
Low
Pin driver is low
0
High
Pin driver is high
1
PIN27
Pin 27
27
27
Low
Pin driver is low
0
High
Pin driver is high
1
PIN28
Pin 28
28
28
Low
Pin driver is low
0
High
Pin driver is high
1
PIN29
Pin 29
29
29
Low
Pin driver is low
0
High
Pin driver is high
1
PIN30
Pin 30
30
30
Low
Pin driver is low
0
High
Pin driver is high
1
PIN31
Pin 31
31
31
Low
Pin driver is low
0
High
Pin driver is high
1
OUTSET
Set individual bits in GPIO port
0x008
read-write
oneToSet
PIN0
Pin 0
0
0
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN1
Pin 1
1
1
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN2
Pin 2
2
2
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN3
Pin 3
3
3
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN4
Pin 4
4
4
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN5
Pin 5
5
5
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN6
Pin 6
6
6
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN7
Pin 7
7
7
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN8
Pin 8
8
8
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN9
Pin 9
9
9
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN10
Pin 10
10
10
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN11
Pin 11
11
11
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN12
Pin 12
12
12
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN13
Pin 13
13
13
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN14
Pin 14
14
14
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN15
Pin 15
15
15
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN16
Pin 16
16
16
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN17
Pin 17
17
17
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN18
Pin 18
18
18
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN19
Pin 19
19
19
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN20
Pin 20
20
20
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN21
Pin 21
21
21
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN22
Pin 22
22
22
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN23
Pin 23
23
23
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN24
Pin 24
24
24
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN25
Pin 25
25
25
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN26
Pin 26
26
26
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN27
Pin 27
27
27
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN28
Pin 28
28
28
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN29
Pin 29
29
29
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN30
Pin 30
30
30
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
PIN31
Pin 31
31
31
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Set
Write: writing a '1' sets the pin high; writing a '0' has no effect
1
OUTCLR
Clear individual bits in GPIO port
0x00C
read-write
oneToClear
PIN0
Pin 0
0
0
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN1
Pin 1
1
1
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN2
Pin 2
2
2
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN3
Pin 3
3
3
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN4
Pin 4
4
4
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN5
Pin 5
5
5
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN6
Pin 6
6
6
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN7
Pin 7
7
7
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN8
Pin 8
8
8
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN9
Pin 9
9
9
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN10
Pin 10
10
10
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN11
Pin 11
11
11
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN12
Pin 12
12
12
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN13
Pin 13
13
13
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN14
Pin 14
14
14
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN15
Pin 15
15
15
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN16
Pin 16
16
16
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN17
Pin 17
17
17
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN18
Pin 18
18
18
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN19
Pin 19
19
19
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN20
Pin 20
20
20
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN21
Pin 21
21
21
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN22
Pin 22
22
22
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN23
Pin 23
23
23
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN24
Pin 24
24
24
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN25
Pin 25
25
25
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN26
Pin 26
26
26
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN27
Pin 27
27
27
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN28
Pin 28
28
28
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN29
Pin 29
29
29
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN30
Pin 30
30
30
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
PIN31
Pin 31
31
31
read
Low
Read: pin driver is low
0
High
Read: pin driver is high
1
write
Clear
Write: writing a '1' sets the pin low; writing a '0' has no effect
1
IN
Read GPIO port
0x010
read-only
PIN0
Pin 0
0
0
Low
Pin input is low
0
High
Pin input is high
1
PIN1
Pin 1
1
1
Low
Pin input is low
0
High
Pin input is high
1
PIN2
Pin 2
2
2
Low
Pin input is low
0
High
Pin input is high
1
PIN3
Pin 3
3
3
Low
Pin input is low
0
High
Pin input is high
1
PIN4
Pin 4
4
4
Low
Pin input is low
0
High
Pin input is high
1
PIN5
Pin 5
5
5
Low
Pin input is low
0
High
Pin input is high
1
PIN6
Pin 6
6
6
Low
Pin input is low
0
High
Pin input is high
1
PIN7
Pin 7
7
7
Low
Pin input is low
0
High
Pin input is high
1
PIN8
Pin 8
8
8
Low
Pin input is low
0
High
Pin input is high
1
PIN9
Pin 9
9
9
Low
Pin input is low
0
High
Pin input is high
1
PIN10
Pin 10
10
10
Low
Pin input is low
0
High
Pin input is high
1
PIN11
Pin 11
11
11
Low
Pin input is low
0
High
Pin input is high
1
PIN12
Pin 12
12
12
Low
Pin input is low
0
High
Pin input is high
1
PIN13
Pin 13
13
13
Low
Pin input is low
0
High
Pin input is high
1
PIN14
Pin 14
14
14
Low
Pin input is low
0
High
Pin input is high
1
PIN15
Pin 15
15
15
Low
Pin input is low
0
High
Pin input is high
1
PIN16
Pin 16
16
16
Low
Pin input is low
0
High
Pin input is high
1
PIN17
Pin 17
17
17
Low
Pin input is low
0
High
Pin input is high
1
PIN18
Pin 18
18
18
Low
Pin input is low
0
High
Pin input is high
1
PIN19
Pin 19
19
19
Low
Pin input is low
0
High
Pin input is high
1
PIN20
Pin 20
20
20
Low
Pin input is low
0
High
Pin input is high
1
PIN21
Pin 21
21
21
Low
Pin input is low
0
High
Pin input is high
1
PIN22
Pin 22
22
22
Low
Pin input is low
0
High
Pin input is high
1
PIN23
Pin 23
23
23
Low
Pin input is low
0
High
Pin input is high
1
PIN24
Pin 24
24
24
Low
Pin input is low
0
High
Pin input is high
1
PIN25
Pin 25
25
25
Low
Pin input is low
0
High
Pin input is high
1
PIN26
Pin 26
26
26
Low
Pin input is low
0
High
Pin input is high
1
PIN27
Pin 27
27
27
Low
Pin input is low
0
High
Pin input is high
1
PIN28
Pin 28
28
28
Low
Pin input is low
0
High
Pin input is high
1
PIN29
Pin 29
29
29
Low
Pin input is low
0
High
Pin input is high
1
PIN30
Pin 30
30
30
Low
Pin input is low
0
High
Pin input is high
1
PIN31
Pin 31
31
31
Low
Pin input is low
0
High
Pin input is high
1
DIR
Direction of GPIO pins
0x014
read-write
PIN0
Pin 0
0
0
Input
Pin set as input
0
Output
Pin set as output
1
PIN1
Pin 1
1
1
Input
Pin set as input
0
Output
Pin set as output
1
PIN2
Pin 2
2
2
Input
Pin set as input
0
Output
Pin set as output
1
PIN3
Pin 3
3
3
Input
Pin set as input
0
Output
Pin set as output
1
PIN4
Pin 4
4
4
Input
Pin set as input
0
Output
Pin set as output
1
PIN5
Pin 5
5
5
Input
Pin set as input
0
Output
Pin set as output
1
PIN6
Pin 6
6
6
Input
Pin set as input
0
Output
Pin set as output
1
PIN7
Pin 7
7
7
Input
Pin set as input
0
Output
Pin set as output
1
PIN8
Pin 8
8
8
Input
Pin set as input
0
Output
Pin set as output
1
PIN9
Pin 9
9
9
Input
Pin set as input
0
Output
Pin set as output
1
PIN10
Pin 10
10
10
Input
Pin set as input
0
Output
Pin set as output
1
PIN11
Pin 11
11
11
Input
Pin set as input
0
Output
Pin set as output
1
PIN12
Pin 12
12
12
Input
Pin set as input
0
Output
Pin set as output
1
PIN13
Pin 13
13
13
Input
Pin set as input
0
Output
Pin set as output
1
PIN14
Pin 14
14
14
Input
Pin set as input
0
Output
Pin set as output
1
PIN15
Pin 15
15
15
Input
Pin set as input
0
Output
Pin set as output
1
PIN16
Pin 16
16
16
Input
Pin set as input
0
Output
Pin set as output
1
PIN17
Pin 17
17
17
Input
Pin set as input
0
Output
Pin set as output
1
PIN18
Pin 18
18
18
Input
Pin set as input
0
Output
Pin set as output
1
PIN19
Pin 19
19
19
Input
Pin set as input
0
Output
Pin set as output
1
PIN20
Pin 20
20
20
Input
Pin set as input
0
Output
Pin set as output
1
PIN21
Pin 21
21
21
Input
Pin set as input
0
Output
Pin set as output
1
PIN22
Pin 22
22
22
Input
Pin set as input
0
Output
Pin set as output
1
PIN23
Pin 23
23
23
Input
Pin set as input
0
Output
Pin set as output
1
PIN24
Pin 24
24
24
Input
Pin set as input
0
Output
Pin set as output
1
PIN25
Pin 25
25
25
Input
Pin set as input
0
Output
Pin set as output
1
PIN26
Pin 26
26
26
Input
Pin set as input
0
Output
Pin set as output
1
PIN27
Pin 27
27
27
Input
Pin set as input
0
Output
Pin set as output
1
PIN28
Pin 28
28
28
Input
Pin set as input
0
Output
Pin set as output
1
PIN29
Pin 29
29
29
Input
Pin set as input
0
Output
Pin set as output
1
PIN30
Pin 30
30
30
Input
Pin set as input
0
Output
Pin set as output
1
PIN31
Pin 31
31
31
Input
Pin set as input
0
Output
Pin set as output
1
DIRSET
DIR set register
0x018
read-write
oneToSet
PIN0
Set as output pin 0
0
0
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN1
Set as output pin 1
1
1
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN2
Set as output pin 2
2
2
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN3
Set as output pin 3
3
3
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN4
Set as output pin 4
4
4
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN5
Set as output pin 5
5
5
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN6
Set as output pin 6
6
6
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN7
Set as output pin 7
7
7
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN8
Set as output pin 8
8
8
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN9
Set as output pin 9
9
9
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN10
Set as output pin 10
10
10
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN11
Set as output pin 11
11
11
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN12
Set as output pin 12
12
12
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN13
Set as output pin 13
13
13
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN14
Set as output pin 14
14
14
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN15
Set as output pin 15
15
15
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN16
Set as output pin 16
16
16
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN17
Set as output pin 17
17
17
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN18
Set as output pin 18
18
18
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN19
Set as output pin 19
19
19
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN20
Set as output pin 20
20
20
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN21
Set as output pin 21
21
21
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN22
Set as output pin 22
22
22
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN23
Set as output pin 23
23
23
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN24
Set as output pin 24
24
24
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN25
Set as output pin 25
25
25
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN26
Set as output pin 26
26
26
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN27
Set as output pin 27
27
27
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN28
Set as output pin 28
28
28
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN29
Set as output pin 29
29
29
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN30
Set as output pin 30
30
30
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
PIN31
Set as output pin 31
31
31
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Set
Write: writing a '1' sets pin to output; writing a '0' has no effect
1
DIRCLR
DIR clear register
0x01C
read-write
oneToClear
PIN0
Set as input pin 0
0
0
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN1
Set as input pin 1
1
1
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN2
Set as input pin 2
2
2
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN3
Set as input pin 3
3
3
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN4
Set as input pin 4
4
4
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN5
Set as input pin 5
5
5
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN6
Set as input pin 6
6
6
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN7
Set as input pin 7
7
7
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN8
Set as input pin 8
8
8
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN9
Set as input pin 9
9
9
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN10
Set as input pin 10
10
10
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN11
Set as input pin 11
11
11
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN12
Set as input pin 12
12
12
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN13
Set as input pin 13
13
13
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN14
Set as input pin 14
14
14
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN15
Set as input pin 15
15
15
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN16
Set as input pin 16
16
16
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN17
Set as input pin 17
17
17
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN18
Set as input pin 18
18
18
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN19
Set as input pin 19
19
19
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN20
Set as input pin 20
20
20
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN21
Set as input pin 21
21
21
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN22
Set as input pin 22
22
22
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN23
Set as input pin 23
23
23
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN24
Set as input pin 24
24
24
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN25
Set as input pin 25
25
25
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN26
Set as input pin 26
26
26
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN27
Set as input pin 27
27
27
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN28
Set as input pin 28
28
28
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN29
Set as input pin 29
29
29
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN30
Set as input pin 30
30
30
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
PIN31
Set as input pin 31
31
31
read
Input
Read: pin set as input
0
Output
Read: pin set as output
1
write
Clear
Write: writing a '1' sets pin to input; writing a '0' has no effect
1
LATCH
Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers
0x020
read-write
PIN0
Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear.
0
0
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN1
Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear.
1
1
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN2
Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear.
2
2
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN3
Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear.
3
3
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN4
Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear.
4
4
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN5
Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear.
5
5
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN6
Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear.
6
6
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN7
Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear.
7
7
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN8
Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear.
8
8
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN9
Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear.
9
9
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN10
Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear.
10
10
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN11
Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear.
11
11
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN12
Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear.
12
12
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN13
Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear.
13
13
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN14
Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear.
14
14
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN15
Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear.
15
15
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN16
Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear.
16
16
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN17
Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear.
17
17
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN18
Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear.
18
18
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN19
Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear.
19
19
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN20
Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear.
20
20
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN21
Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear.
21
21
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN22
Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear.
22
22
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN23
Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear.
23
23
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN24
Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear.
24
24
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN25
Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear.
25
25
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN26
Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear.
26
26
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN27
Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear.
27
27
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN28
Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear.
28
28
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN29
Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear.
29
29
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN30
Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear.
30
30
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
PIN31
Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear.
31
31
NotLatched
Criteria has not been met
0
Latched
Criteria has been met
1
DETECTMODE
Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only)
0x024
read-write
DETECTMODE
Select between default DETECT signal behavior and LDETECT mode
0
0
Default
DETECT directly connected to PIN DETECT signals
0
LDETECT
Use the latched LDETECT behavior
1
DETECTMODE_SEC
Select between default DETECT signal behavior and LDETECT mode (For secure pin only)
0x028
read-write
DETECTMODE
Select between default DETECT signal behavior and LDETECT mode
0
0
Default
DETECT directly connected to PIN DETECT signals
0
LDETECT
Use the latched LDETECT behavior
1
0x20
0x4
PIN_CNF[%s]
Description collection: Configuration of GPIO pins
0x200
read-write
0x00000002
DIR
Pin direction. Same physical register as DIR register
0
0
Input
Configure pin as an input pin
0
Output
Configure pin as an output pin
1
INPUT
Connect or disconnect input buffer
1
1
Connect
Connect input buffer
0
Disconnect
Disconnect input buffer
1
PULL
Pull configuration
2
3
Disabled
No pull
0
Pulldown
Pull down on pin
1
Pullup
Pull up on pin
3
DRIVE
Drive configuration
8
11
S0S1
Standard '0', standard '1'
0
H0S1
High drive '0', standard '1'
1
S0H1
Standard '0', high drive '1'
2
H0H1
High drive '0', high 'drive '1''
3
D0S1
Disconnect '0', standard '1' (normally used for wired-or connections)
4
D0H1
Disconnect '0', high drive '1' (normally used for wired-or connections)
5
S0D1
Standard '0', disconnect '1' (normally used for wired-and connections)
6
H0D1
High drive '0', disconnect '1' (normally used for wired-and connections)
7
E0E1
Extra high drive '0', extra high drive '1'
11
SENSE
Pin sensing mechanism
16
17
Disabled
Disabled
0
High
Sense for high level
2
Low
Sense for low level
3
MCUSEL
Select which MCU/Subsystem controls this pin Note: this field is only accessible from secure code.
28
30
AppMCU
Application MCU
0x0
NetworkMCU
Network MCU
0x1
Peripheral
Peripheral with dedicated pins
0x3
TND
Trace and Debug Subsystem
0x7
P1_NS
GPIO Port 1
0x418C0800