nrfx_coredep.h 6.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180
  1. /**
  2. * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA
  3. *
  4. * All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without modification,
  7. * are permitted provided that the following conditions are met:
  8. *
  9. * 1. Redistributions of source code must retain the above copyright notice, this
  10. * list of conditions and the following disclaimer.
  11. *
  12. * 2. Redistributions in binary form, except as embedded into a Nordic
  13. * Semiconductor ASA integrated circuit in a product or a software update for
  14. * such product, must reproduce the above copyright notice, this list of
  15. * conditions and the following disclaimer in the documentation and/or other
  16. * materials provided with the distribution.
  17. *
  18. * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
  19. * contributors may be used to endorse or promote products derived from this
  20. * software without specific prior written permission.
  21. *
  22. * 4. This software, with or without modification, must only be used with a
  23. * Nordic Semiconductor ASA integrated circuit.
  24. *
  25. * 5. Any software provided in binary form under this license must not be reverse
  26. * engineered, decompiled, modified and/or disassembled.
  27. *
  28. * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
  29. * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  30. * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
  31. * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
  32. * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  33. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  34. * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  37. * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38. *
  39. */
  40. #ifndef NRFX_COREDEP_H__
  41. #define NRFX_COREDEP_H__
  42. /**
  43. * @defgroup nrfx_coredep Core-dependent functionality
  44. * @{
  45. * @ingroup nrfx
  46. * @brief Module containing functions with core-dependent implementation, like delay.
  47. */
  48. #if defined(__NRFX_DOXYGEN__)
  49. /** @brief Core frequency (in MHz). */
  50. #define NRFX_DELAY_CPU_FREQ_MHZ
  51. /** @brief Availability of Data Watchpoint and Trace (DWT) unit in the given SoC. */
  52. #define NRFX_DELAY_DWT_PRESENT
  53. /**
  54. * @brief Number of cycles consumed by one iteration of the internal loop
  55. * in the function @ref nrfx_coredep_delay_us.
  56. *
  57. * This value can be specified externally (for example, when the SoC is emulated).
  58. */
  59. #define NRFX_COREDEP_DELAY_US_LOOP_CYCLES
  60. #elif defined(NRF51)
  61. #define NRFX_DELAY_CPU_FREQ_MHZ 16
  62. #define NRFX_DELAY_DWT_PRESENT 0
  63. #elif defined(NRF52810_XXAA) || defined(NRF52811_XXAA) || defined(NRF52820_XXAA)
  64. #define NRFX_DELAY_CPU_FREQ_MHZ 64
  65. #define NRFX_DELAY_DWT_PRESENT 0
  66. #elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \
  67. defined(NRF52833_XXAA) || defined(NRF52840_XXAA) || \
  68. defined(NRF9160_XXAA)
  69. #define NRFX_DELAY_CPU_FREQ_MHZ 64
  70. #define NRFX_DELAY_DWT_PRESENT 1
  71. #else
  72. #error "Unknown device."
  73. #endif
  74. /**
  75. * @brief Function for delaying execution for a number of microseconds.
  76. *
  77. * The value of @p time_us is multiplied by the frequency in MHz. Therefore, the delay is limited to
  78. * maximum uint32_t capacity divided by frequency. For example:
  79. * - For SoCs working at 64MHz: 0xFFFFFFFF/64 = 0x03FFFFFF (67108863 microseconds)
  80. * - For SoCs working at 16MHz: 0xFFFFFFFF/16 = 0x0FFFFFFF (268435455 microseconds)
  81. *
  82. * @sa NRFX_COREDEP_DELAY_US_LOOP_CYCLES
  83. *
  84. * @param time_us Number of microseconds to wait.
  85. */
  86. __STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us);
  87. /** @} */
  88. #ifndef SUPPRESS_INLINE_IMPLEMENTATION
  89. #if NRFX_CHECK(NRFX_DELAY_DWT_BASED)
  90. #if !NRFX_DELAY_DWT_PRESENT
  91. #error "DWT unit not present in the SoC that is used."
  92. #endif
  93. __STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
  94. {
  95. if (time_us == 0)
  96. {
  97. return;
  98. }
  99. uint32_t time_cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
  100. // Save the current state of the DEMCR register to be able to restore it before exiting
  101. // this function. Enable the trace and debug blocks (including DWT).
  102. uint32_t core_debug = CoreDebug->DEMCR;
  103. CoreDebug->DEMCR = core_debug | CoreDebug_DEMCR_TRCENA_Msk;
  104. // Save the current state of the CTRL register in the DWT block. Make sure
  105. // that the cycle counter is enabled.
  106. uint32_t dwt_ctrl = DWT->CTRL;
  107. DWT->CTRL = dwt_ctrl | DWT_CTRL_CYCCNTENA_Msk;
  108. // Store start value of the cycle counter.
  109. uint32_t cyccnt_initial = DWT->CYCCNT;
  110. // Delay required time.
  111. while ((DWT->CYCCNT - cyccnt_initial) < time_cycles)
  112. {}
  113. // Restore preserved registers.
  114. DWT->CTRL = dwt_ctrl;
  115. CoreDebug->DEMCR = core_debug;
  116. }
  117. #else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)
  118. __STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
  119. {
  120. if (time_us == 0)
  121. {
  122. return;
  123. }
  124. // Allow overriding the number of cycles per loop iteration, in case it is
  125. // needed to adjust this number externally (for example, when the SoC is
  126. // emulated).
  127. #ifndef NRFX_COREDEP_DELAY_US_LOOP_CYCLES
  128. #if defined(NRF51)
  129. // The loop takes 4 cycles: 1 for SUBS, 3 for BHI.
  130. #define NRFX_COREDEP_DELAY_US_LOOP_CYCLES 4
  131. #elif defined(NRF52810_XXAA) || defined(NRF52811_XXAA) || defined(NRF52820_XXAA)
  132. // The loop takes 7 cycles: 1 for SUBS, 2 for BHI, 2 wait states
  133. // for each instruction.
  134. #define NRFX_COREDEP_DELAY_US_LOOP_CYCLES 7
  135. #else
  136. // The loop takes 3 cycles: 1 for SUBS, 2 for BHI.
  137. #define NRFX_COREDEP_DELAY_US_LOOP_CYCLES 3
  138. #endif
  139. #endif // NRFX_COREDEP_DELAY_US_LOOP_CYCLES
  140. // Align the machine code, so that it can be cached properly and no extra
  141. // wait states appear.
  142. __ALIGN(16)
  143. static const uint16_t delay_machine_code[] = {
  144. 0x3800 + NRFX_COREDEP_DELAY_US_LOOP_CYCLES, // SUBS r0, #loop_cycles
  145. 0xd8fd, // BHI .-2
  146. 0x4770 // BX LR
  147. };
  148. typedef void (* delay_func_t)(uint32_t);
  149. const delay_func_t delay_cycles =
  150. // Set LSB to 1 to execute the code in the Thumb mode.
  151. (delay_func_t)((((uint32_t)delay_machine_code) | 1));
  152. uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
  153. delay_cycles(cycles);
  154. }
  155. #endif // !NRFX_CHECK(NRFX_DELAY_DWT_BASED_DELAY)
  156. #endif // SUPPRESS_INLINE_IMPLEMENTATION
  157. #endif // NRFX_COREDEP_H__