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- #ifndef NRF9160_H
- #define NRF9160_H
- #ifdef __cplusplus
- extern "C" {
- #endif
- typedef enum {
- Reset_IRQn = -15,
- NonMaskableInt_IRQn = -14,
- HardFault_IRQn = -13,
- MemoryManagement_IRQn = -12,
- BusFault_IRQn = -11,
- UsageFault_IRQn = -10,
- SecureFault_IRQn = -9,
- SVCall_IRQn = -5,
- DebugMonitor_IRQn = -4,
- PendSV_IRQn = -2,
- SysTick_IRQn = -1,
- SPU_IRQn = 3,
- CLOCK_POWER_IRQn = 5,
- UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQn= 8,
- UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQn= 9,
- UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQn= 10,
- UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQn= 11,
- GPIOTE0_IRQn = 13,
- SAADC_IRQn = 14,
- TIMER0_IRQn = 15,
- TIMER1_IRQn = 16,
- TIMER2_IRQn = 17,
- RTC0_IRQn = 20,
- RTC1_IRQn = 21,
- WDT_IRQn = 24,
- EGU0_IRQn = 27,
- EGU1_IRQn = 28,
- EGU2_IRQn = 29,
- EGU3_IRQn = 30,
- EGU4_IRQn = 31,
- EGU5_IRQn = 32,
- PWM0_IRQn = 33,
- PWM1_IRQn = 34,
- PWM2_IRQn = 35,
- PWM3_IRQn = 36,
- PDM_IRQn = 38,
- I2S_IRQn = 40,
- IPC_IRQn = 42,
- FPU_IRQn = 44,
- GPIOTE1_IRQn = 49,
- KMU_IRQn = 57,
- CRYPTOCELL_IRQn = 64
- } IRQn_Type;
- #define __CM33_REV 0x0004U
- #define __DSP_PRESENT 1
- #define __NVIC_PRIO_BITS 3
- #define __Vendor_SysTickConfig 0
- #define __VTOR_PRESENT 1
- #define __MPU_PRESENT 1
- #define __FPU_PRESENT 1
- #define __FPU_DP 0
- #define __SAUREGION_PRESENT 0
-
- #include "core_cm33.h"
- #include "system_nrf9160.h"
- #ifndef __IM
- #define __IM __I
- #endif
- #ifndef __OM
- #define __OM __O
- #endif
- #ifndef __IOM
- #define __IOM __IO
- #endif
- typedef struct {
- __IM uint32_t RESERVED;
- __IM uint32_t DEVICEID[2];
- __IM uint32_t PART;
- __IM uint32_t VARIANT;
- __IM uint32_t PACKAGE;
- __IM uint32_t RAM;
- __IM uint32_t FLASH;
- __IM uint32_t CODEPAGESIZE;
- __IM uint32_t CODESIZE;
- __IM uint32_t DEVICETYPE;
- } FICR_INFO_Type;
- typedef struct {
- __IM uint32_t ADDR;
- __IM uint32_t DATA;
- } FICR_TRIMCNF_Type;
- typedef struct {
- __IM uint32_t BYTES;
- __IM uint32_t RCCUTOFF;
- __IM uint32_t APCUTOFF;
- __IM uint32_t STARTUP;
- __IM uint32_t ROSC1;
- __IM uint32_t ROSC2;
- __IM uint32_t ROSC3;
- __IM uint32_t ROSC4;
- } FICR_TRNG90B_Type;
- typedef struct {
- __IOM uint32_t DEST;
- __IOM uint32_t PERM;
- } UICR_KEYSLOT_CONFIG_Type;
- typedef struct {
- __IOM uint32_t VALUE[4];
- } UICR_KEYSLOT_KEY_Type;
- typedef struct {
- __IOM UICR_KEYSLOT_CONFIG_Type CONFIG[128];
- __IOM UICR_KEYSLOT_KEY_Type KEY[128];
- } UICR_KEYSLOT_Type;
- typedef struct {
- __IOM uint32_t TRACECLK;
- __IOM uint32_t TRACEDATA0;
- __IOM uint32_t TRACEDATA1;
- __IOM uint32_t TRACEDATA2;
- __IOM uint32_t TRACEDATA3;
- } TAD_PSEL_Type;
- typedef struct {
- __IOM uint32_t PERM;
- } SPU_EXTDOMAIN_Type;
- typedef struct {
- __IOM uint32_t PERM;
- __IOM uint32_t LOCK;
- } SPU_DPPI_Type;
- typedef struct {
- __IOM uint32_t PERM;
- __IOM uint32_t LOCK;
- } SPU_GPIOPORT_Type;
- typedef struct {
- __IOM uint32_t REGION;
- __IOM uint32_t SIZE;
- } SPU_FLASHNSC_Type;
- typedef struct {
- __IOM uint32_t REGION;
- __IOM uint32_t SIZE;
- } SPU_RAMNSC_Type;
- typedef struct {
- __IOM uint32_t PERM;
- } SPU_FLASHREGION_Type;
- typedef struct {
- __IOM uint32_t PERM;
- } SPU_RAMREGION_Type;
- typedef struct {
- __IOM uint32_t PERM;
- } SPU_PERIPHID_Type;
- typedef struct {
- __IM uint32_t RXDATA;
- __IM uint32_t RXSTATUS;
- __IM uint32_t RESERVED[30];
- __IOM uint32_t TXDATA;
- __IM uint32_t TXSTATUS;
- } CTRLAPPERI_MAILBOX_Type;
- typedef struct {
- __IOM uint32_t LOCK;
- __IOM uint32_t DISABLE;
- } CTRLAPPERI_ERASEPROTECT_Type;
- typedef struct {
- __IOM uint32_t SCK;
- __IOM uint32_t MOSI;
- __IOM uint32_t MISO;
- } SPIM_PSEL_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- __IOM uint32_t LIST;
- } SPIM_RXD_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- __IOM uint32_t LIST;
- } SPIM_TXD_Type;
- typedef struct {
- __IOM uint32_t SCK;
- __IOM uint32_t MISO;
- __IOM uint32_t MOSI;
- __IOM uint32_t CSN;
- } SPIS_PSEL_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- __IOM uint32_t LIST;
- } SPIS_RXD_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- __IOM uint32_t LIST;
- } SPIS_TXD_Type;
- typedef struct {
- __IOM uint32_t SCL;
- __IOM uint32_t SDA;
- } TWIM_PSEL_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- __IOM uint32_t LIST;
- } TWIM_RXD_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- __IOM uint32_t LIST;
- } TWIM_TXD_Type;
- typedef struct {
- __IOM uint32_t SCL;
- __IOM uint32_t SDA;
- } TWIS_PSEL_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- __IOM uint32_t LIST;
- } TWIS_RXD_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- __IOM uint32_t LIST;
- } TWIS_TXD_Type;
- typedef struct {
- __IOM uint32_t RTS;
- __IOM uint32_t TXD;
- __IOM uint32_t CTS;
- __IOM uint32_t RXD;
- } UARTE_PSEL_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- } UARTE_RXD_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- } UARTE_TXD_Type;
- typedef struct {
- __IOM uint32_t LIMITH;
- __IOM uint32_t LIMITL;
- } SAADC_EVENTS_CH_Type;
- typedef struct {
- __IOM uint32_t LIMITH;
- __IOM uint32_t LIMITL;
- } SAADC_PUBLISH_CH_Type;
- typedef struct {
- __IOM uint32_t PSELP;
- __IOM uint32_t PSELN;
- __IOM uint32_t CONFIG;
- __IOM uint32_t LIMIT;
- } SAADC_CH_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- } SAADC_RESULT_Type;
- typedef struct {
- __OM uint32_t EN;
- __OM uint32_t DIS;
- } DPPIC_TASKS_CHG_Type;
- typedef struct {
- __IOM uint32_t EN;
- __IOM uint32_t DIS;
- } DPPIC_SUBSCRIBE_CHG_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t CNT;
- __IOM uint32_t REFRESH;
- __IOM uint32_t ENDDELAY;
- __IM uint32_t RESERVED[4];
- } PWM_SEQ_Type;
- typedef struct {
- __IOM uint32_t OUT[4];
- } PWM_PSEL_Type;
- typedef struct {
- __IOM uint32_t CLK;
- __IOM uint32_t DIN;
- } PDM_PSEL_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- } PDM_SAMPLE_Type;
- typedef struct {
- __IOM uint32_t MODE;
- __IOM uint32_t RXEN;
- __IOM uint32_t TXEN;
- __IOM uint32_t MCKEN;
- __IOM uint32_t MCKFREQ;
- __IOM uint32_t RATIO;
- __IOM uint32_t SWIDTH;
- __IOM uint32_t ALIGN;
- __IOM uint32_t FORMAT;
- __IOM uint32_t CHANNELS;
- } I2S_CONFIG_Type;
- typedef struct {
- __IOM uint32_t PTR;
- } I2S_RXD_Type;
- typedef struct {
- __IOM uint32_t PTR;
- } I2S_TXD_Type;
- typedef struct {
- __IOM uint32_t MAXCNT;
- } I2S_RXTXD_Type;
- typedef struct {
- __IOM uint32_t MCK;
- __IOM uint32_t SCK;
- __IOM uint32_t LRCK;
- __IOM uint32_t SDIN;
- __IOM uint32_t SDOUT;
- } I2S_PSEL_Type;
- typedef struct {
- __IOM uint32_t POWER;
- __OM uint32_t POWERSET;
- __OM uint32_t POWERCLR;
- __IM uint32_t RESERVED;
- } VMC_RAM_Type;
-
- typedef struct {
- __IM uint32_t RESERVED[128];
- __IOM FICR_INFO_Type INFO;
- __IM uint32_t RESERVED1[53];
- __IOM FICR_TRIMCNF_Type TRIMCNF[256];
- __IM uint32_t RESERVED2[64];
- __IOM FICR_TRNG90B_Type TRNG90B;
- } NRF_FICR_Type;
- typedef struct {
- __IOM uint32_t APPROTECT;
- __IM uint32_t RESERVED[4];
- __IOM uint32_t XOSC32M;
- __IM uint32_t RESERVED1;
- __IOM uint32_t HFXOSRC;
- __IOM uint32_t HFXOCNT;
- __IM uint32_t RESERVED2[2];
- __IOM uint32_t SECUREAPPROTECT;
- __IOM uint32_t ERASEPROTECT;
- __IM uint32_t RESERVED3[53];
- __IOM uint32_t OTP[190];
- __IOM UICR_KEYSLOT_Type KEYSLOT;
- } NRF_UICR_Type;
- typedef struct {
- __OM uint32_t CLOCKSTART;
- __OM uint32_t CLOCKSTOP;
- __IM uint32_t RESERVED[318];
- __IOM uint32_t ENABLE;
- __IOM TAD_PSEL_Type PSEL;
- __IOM uint32_t TRACEPORTSPEED;
- } NRF_TAD_Type;
- typedef struct {
- __IM uint32_t RESERVED[64];
- __IOM uint32_t EVENTS_RAMACCERR;
- __IOM uint32_t EVENTS_FLASHACCERR;
- __IOM uint32_t EVENTS_PERIPHACCERR;
- __IM uint32_t RESERVED1[29];
- __IOM uint32_t PUBLISH_RAMACCERR;
- __IOM uint32_t PUBLISH_FLASHACCERR;
- __IOM uint32_t PUBLISH_PERIPHACCERR;
- __IM uint32_t RESERVED2[93];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED3[61];
- __IM uint32_t CAP;
- __IM uint32_t RESERVED4[15];
- __IOM SPU_EXTDOMAIN_Type EXTDOMAIN[1];
- __IM uint32_t RESERVED5[15];
- __IOM SPU_DPPI_Type DPPI[1];
- __IM uint32_t RESERVED6[14];
- __IOM SPU_GPIOPORT_Type GPIOPORT[1];
- __IM uint32_t RESERVED7[14];
- __IOM SPU_FLASHNSC_Type FLASHNSC[2];
- __IM uint32_t RESERVED8[12];
- __IOM SPU_RAMNSC_Type RAMNSC[2];
- __IM uint32_t RESERVED9[44];
- __IOM SPU_FLASHREGION_Type FLASHREGION[32];
- __IM uint32_t RESERVED10[32];
- __IOM SPU_RAMREGION_Type RAMREGION[32];
- __IM uint32_t RESERVED11[32];
- __IOM SPU_PERIPHID_Type PERIPHID[67];
- } NRF_SPU_Type;
- typedef struct {
- __IM uint32_t RESERVED[320];
- __OM uint32_t SYSTEMOFF;
- __IM uint32_t RESERVED1[29];
- __IOM uint32_t DCDCEN;
- } NRF_REGULATORS_Type;
- typedef struct {
- __OM uint32_t TASKS_HFCLKSTART;
- __OM uint32_t TASKS_HFCLKSTOP;
- __OM uint32_t TASKS_LFCLKSTART;
- __OM uint32_t TASKS_LFCLKSTOP;
- __IM uint32_t RESERVED[28];
- __IOM uint32_t SUBSCRIBE_HFCLKSTART;
- __IOM uint32_t SUBSCRIBE_HFCLKSTOP;
- __IOM uint32_t SUBSCRIBE_LFCLKSTART;
- __IOM uint32_t SUBSCRIBE_LFCLKSTOP;
- __IM uint32_t RESERVED1[28];
- __IOM uint32_t EVENTS_HFCLKSTARTED;
- __IOM uint32_t EVENTS_LFCLKSTARTED;
- __IM uint32_t RESERVED2[30];
- __IOM uint32_t PUBLISH_HFCLKSTARTED;
- __IOM uint32_t PUBLISH_LFCLKSTARTED;
- __IM uint32_t RESERVED3[94];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t INTPEND;
- __IM uint32_t RESERVED4[62];
- __IM uint32_t HFCLKRUN;
- __IM uint32_t HFCLKSTAT;
- __IM uint32_t RESERVED5;
- __IM uint32_t LFCLKRUN;
- __IM uint32_t LFCLKSTAT;
- __IM uint32_t LFCLKSRCCOPY;
- __IM uint32_t RESERVED6[62];
- __IOM uint32_t LFCLKSRC;
- } NRF_CLOCK_Type;
- typedef struct {
- __IM uint32_t RESERVED[30];
- __OM uint32_t TASKS_CONSTLAT;
- __OM uint32_t TASKS_LOWPWR;
- __IM uint32_t RESERVED1[30];
- __IOM uint32_t SUBSCRIBE_CONSTLAT;
- __IOM uint32_t SUBSCRIBE_LOWPWR;
- __IM uint32_t RESERVED2[2];
- __IOM uint32_t EVENTS_POFWARN;
- __IM uint32_t RESERVED3[2];
- __IOM uint32_t EVENTS_SLEEPENTER;
- __IOM uint32_t EVENTS_SLEEPEXIT;
- __IM uint32_t RESERVED4[27];
- __IOM uint32_t PUBLISH_POFWARN;
- __IM uint32_t RESERVED5[2];
- __IOM uint32_t PUBLISH_SLEEPENTER;
- __IOM uint32_t PUBLISH_SLEEPEXIT;
- __IM uint32_t RESERVED6[89];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED7[61];
- __IOM uint32_t RESETREAS;
- __IM uint32_t RESERVED8[15];
- __IM uint32_t POWERSTATUS;
- __IM uint32_t RESERVED9[54];
- __IOM uint32_t GPREGRET[2];
- } NRF_POWER_Type;
- typedef struct {
- __IM uint32_t RESERVED[256];
- __IOM CTRLAPPERI_MAILBOX_Type MAILBOX;
- __IM uint32_t RESERVED1[30];
- __IOM CTRLAPPERI_ERASEPROTECT_Type ERASEPROTECT;
- } NRF_CTRLAPPERI_Type;
- typedef struct {
- __IM uint32_t RESERVED[4];
- __OM uint32_t TASKS_START;
- __OM uint32_t TASKS_STOP;
- __IM uint32_t RESERVED1;
- __OM uint32_t TASKS_SUSPEND;
- __OM uint32_t TASKS_RESUME;
- __IM uint32_t RESERVED2[27];
- __IOM uint32_t SUBSCRIBE_START;
- __IOM uint32_t SUBSCRIBE_STOP;
- __IM uint32_t RESERVED3;
- __IOM uint32_t SUBSCRIBE_SUSPEND;
- __IOM uint32_t SUBSCRIBE_RESUME;
- __IM uint32_t RESERVED4[24];
- __IOM uint32_t EVENTS_STOPPED;
- __IM uint32_t RESERVED5[2];
- __IOM uint32_t EVENTS_ENDRX;
- __IM uint32_t RESERVED6;
- __IOM uint32_t EVENTS_END;
- __IM uint32_t RESERVED7;
- __IOM uint32_t EVENTS_ENDTX;
- __IM uint32_t RESERVED8[10];
- __IOM uint32_t EVENTS_STARTED;
- __IM uint32_t RESERVED9[13];
- __IOM uint32_t PUBLISH_STOPPED;
- __IM uint32_t RESERVED10[2];
- __IOM uint32_t PUBLISH_ENDRX;
- __IM uint32_t RESERVED11;
- __IOM uint32_t PUBLISH_END;
- __IM uint32_t RESERVED12;
- __IOM uint32_t PUBLISH_ENDTX;
- __IM uint32_t RESERVED13[10];
- __IOM uint32_t PUBLISH_STARTED;
- __IM uint32_t RESERVED14[12];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED15[64];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED16[125];
- __IOM uint32_t ENABLE;
- __IM uint32_t RESERVED17;
- __IOM SPIM_PSEL_Type PSEL;
- __IM uint32_t RESERVED18[4];
- __IOM uint32_t FREQUENCY;
- __IM uint32_t RESERVED19[3];
- __IOM SPIM_RXD_Type RXD;
- __IOM SPIM_TXD_Type TXD;
- __IOM uint32_t CONFIG;
- __IM uint32_t RESERVED20[26];
- __IOM uint32_t ORC;
- } NRF_SPIM_Type;
- typedef struct {
- __IM uint32_t RESERVED[9];
- __OM uint32_t TASKS_ACQUIRE;
- __OM uint32_t TASKS_RELEASE;
- __IM uint32_t RESERVED1[30];
- __IOM uint32_t SUBSCRIBE_ACQUIRE;
- __IOM uint32_t SUBSCRIBE_RELEASE;
- __IM uint32_t RESERVED2[22];
- __IOM uint32_t EVENTS_END;
- __IM uint32_t RESERVED3[2];
- __IOM uint32_t EVENTS_ENDRX;
- __IM uint32_t RESERVED4[5];
- __IOM uint32_t EVENTS_ACQUIRED;
- __IM uint32_t RESERVED5[22];
- __IOM uint32_t PUBLISH_END;
- __IM uint32_t RESERVED6[2];
- __IOM uint32_t PUBLISH_ENDRX;
- __IM uint32_t RESERVED7[5];
- __IOM uint32_t PUBLISH_ACQUIRED;
- __IM uint32_t RESERVED8[21];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED9[64];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED10[61];
- __IM uint32_t SEMSTAT;
- __IM uint32_t RESERVED11[15];
- __IOM uint32_t STATUS;
- __IM uint32_t RESERVED12[47];
- __IOM uint32_t ENABLE;
- __IM uint32_t RESERVED13;
- __IOM SPIS_PSEL_Type PSEL;
- __IM uint32_t RESERVED14[7];
- __IOM SPIS_RXD_Type RXD;
- __IOM SPIS_TXD_Type TXD;
- __IOM uint32_t CONFIG;
- __IM uint32_t RESERVED15;
- __IOM uint32_t DEF;
- __IM uint32_t RESERVED16[24];
- __IOM uint32_t ORC;
- } NRF_SPIS_Type;
- typedef struct {
- __OM uint32_t TASKS_STARTRX;
- __IM uint32_t RESERVED;
- __OM uint32_t TASKS_STARTTX;
- __IM uint32_t RESERVED1[2];
- __OM uint32_t TASKS_STOP;
- __IM uint32_t RESERVED2;
- __OM uint32_t TASKS_SUSPEND;
- __OM uint32_t TASKS_RESUME;
- __IM uint32_t RESERVED3[23];
- __IOM uint32_t SUBSCRIBE_STARTRX;
- __IM uint32_t RESERVED4;
- __IOM uint32_t SUBSCRIBE_STARTTX;
- __IM uint32_t RESERVED5[2];
- __IOM uint32_t SUBSCRIBE_STOP;
- __IM uint32_t RESERVED6;
- __IOM uint32_t SUBSCRIBE_SUSPEND;
- __IOM uint32_t SUBSCRIBE_RESUME;
- __IM uint32_t RESERVED7[24];
- __IOM uint32_t EVENTS_STOPPED;
- __IM uint32_t RESERVED8[7];
- __IOM uint32_t EVENTS_ERROR;
- __IM uint32_t RESERVED9[8];
- __IOM uint32_t EVENTS_SUSPENDED;
- __IOM uint32_t EVENTS_RXSTARTED;
- __IOM uint32_t EVENTS_TXSTARTED;
- __IM uint32_t RESERVED10[2];
- __IOM uint32_t EVENTS_LASTRX;
- __IOM uint32_t EVENTS_LASTTX;
- __IM uint32_t RESERVED11[8];
- __IOM uint32_t PUBLISH_STOPPED;
- __IM uint32_t RESERVED12[7];
- __IOM uint32_t PUBLISH_ERROR;
- __IM uint32_t RESERVED13[8];
- __IOM uint32_t PUBLISH_SUSPENDED;
- __IOM uint32_t PUBLISH_RXSTARTED;
- __IOM uint32_t PUBLISH_TXSTARTED;
- __IM uint32_t RESERVED14[2];
- __IOM uint32_t PUBLISH_LASTRX;
- __IOM uint32_t PUBLISH_LASTTX;
- __IM uint32_t RESERVED15[7];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED16[63];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED17[110];
- __IOM uint32_t ERRORSRC;
- __IM uint32_t RESERVED18[14];
- __IOM uint32_t ENABLE;
- __IM uint32_t RESERVED19;
- __IOM TWIM_PSEL_Type PSEL;
- __IM uint32_t RESERVED20[5];
- __IOM uint32_t FREQUENCY;
- __IM uint32_t RESERVED21[3];
- __IOM TWIM_RXD_Type RXD;
- __IOM TWIM_TXD_Type TXD;
- __IM uint32_t RESERVED22[13];
- __IOM uint32_t ADDRESS;
- } NRF_TWIM_Type;
- typedef struct {
- __IM uint32_t RESERVED[5];
- __OM uint32_t TASKS_STOP;
- __IM uint32_t RESERVED1;
- __OM uint32_t TASKS_SUSPEND;
- __OM uint32_t TASKS_RESUME;
- __IM uint32_t RESERVED2[3];
- __OM uint32_t TASKS_PREPARERX;
- __OM uint32_t TASKS_PREPARETX;
- __IM uint32_t RESERVED3[23];
- __IOM uint32_t SUBSCRIBE_STOP;
- __IM uint32_t RESERVED4;
- __IOM uint32_t SUBSCRIBE_SUSPEND;
- __IOM uint32_t SUBSCRIBE_RESUME;
- __IM uint32_t RESERVED5[3];
- __IOM uint32_t SUBSCRIBE_PREPARERX;
- __IOM uint32_t SUBSCRIBE_PREPARETX;
- __IM uint32_t RESERVED6[19];
- __IOM uint32_t EVENTS_STOPPED;
- __IM uint32_t RESERVED7[7];
- __IOM uint32_t EVENTS_ERROR;
- __IM uint32_t RESERVED8[9];
- __IOM uint32_t EVENTS_RXSTARTED;
- __IOM uint32_t EVENTS_TXSTARTED;
- __IM uint32_t RESERVED9[4];
- __IOM uint32_t EVENTS_WRITE;
- __IOM uint32_t EVENTS_READ;
- __IM uint32_t RESERVED10[6];
- __IOM uint32_t PUBLISH_STOPPED;
- __IM uint32_t RESERVED11[7];
- __IOM uint32_t PUBLISH_ERROR;
- __IM uint32_t RESERVED12[9];
- __IOM uint32_t PUBLISH_RXSTARTED;
- __IOM uint32_t PUBLISH_TXSTARTED;
- __IM uint32_t RESERVED13[4];
- __IOM uint32_t PUBLISH_WRITE;
- __IOM uint32_t PUBLISH_READ;
- __IM uint32_t RESERVED14[5];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED15[63];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED16[113];
- __IOM uint32_t ERRORSRC;
- __IM uint32_t MATCH;
- __IM uint32_t RESERVED17[10];
- __IOM uint32_t ENABLE;
- __IM uint32_t RESERVED18;
- __IOM TWIS_PSEL_Type PSEL;
- __IM uint32_t RESERVED19[9];
- __IOM TWIS_RXD_Type RXD;
- __IOM TWIS_TXD_Type TXD;
- __IM uint32_t RESERVED20[13];
- __IOM uint32_t ADDRESS[2];
- __IM uint32_t RESERVED21;
- __IOM uint32_t CONFIG;
- __IM uint32_t RESERVED22[10];
- __IOM uint32_t ORC;
- } NRF_TWIS_Type;
- typedef struct {
- __OM uint32_t TASKS_STARTRX;
- __OM uint32_t TASKS_STOPRX;
- __OM uint32_t TASKS_STARTTX;
- __OM uint32_t TASKS_STOPTX;
- __IM uint32_t RESERVED[7];
- __OM uint32_t TASKS_FLUSHRX;
- __IM uint32_t RESERVED1[20];
- __IOM uint32_t SUBSCRIBE_STARTRX;
- __IOM uint32_t SUBSCRIBE_STOPRX;
- __IOM uint32_t SUBSCRIBE_STARTTX;
- __IOM uint32_t SUBSCRIBE_STOPTX;
- __IM uint32_t RESERVED2[7];
- __IOM uint32_t SUBSCRIBE_FLUSHRX;
- __IM uint32_t RESERVED3[20];
- __IOM uint32_t EVENTS_CTS;
- __IOM uint32_t EVENTS_NCTS;
- __IOM uint32_t EVENTS_RXDRDY;
- __IM uint32_t RESERVED4;
- __IOM uint32_t EVENTS_ENDRX;
- __IM uint32_t RESERVED5[2];
- __IOM uint32_t EVENTS_TXDRDY;
- __IOM uint32_t EVENTS_ENDTX;
- __IOM uint32_t EVENTS_ERROR;
- __IM uint32_t RESERVED6[7];
- __IOM uint32_t EVENTS_RXTO;
- __IM uint32_t RESERVED7;
- __IOM uint32_t EVENTS_RXSTARTED;
- __IOM uint32_t EVENTS_TXSTARTED;
- __IM uint32_t RESERVED8;
- __IOM uint32_t EVENTS_TXSTOPPED;
- __IM uint32_t RESERVED9[9];
- __IOM uint32_t PUBLISH_CTS;
- __IOM uint32_t PUBLISH_NCTS;
- __IOM uint32_t PUBLISH_RXDRDY;
- __IM uint32_t RESERVED10;
- __IOM uint32_t PUBLISH_ENDRX;
- __IM uint32_t RESERVED11[2];
- __IOM uint32_t PUBLISH_TXDRDY;
- __IOM uint32_t PUBLISH_ENDTX;
- __IOM uint32_t PUBLISH_ERROR;
- __IM uint32_t RESERVED12[7];
- __IOM uint32_t PUBLISH_RXTO;
- __IM uint32_t RESERVED13;
- __IOM uint32_t PUBLISH_RXSTARTED;
- __IOM uint32_t PUBLISH_TXSTARTED;
- __IM uint32_t RESERVED14;
- __IOM uint32_t PUBLISH_TXSTOPPED;
- __IM uint32_t RESERVED15[9];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED16[63];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED17[93];
- __IOM uint32_t ERRORSRC;
- __IM uint32_t RESERVED18[31];
- __IOM uint32_t ENABLE;
- __IM uint32_t RESERVED19;
- __IOM UARTE_PSEL_Type PSEL;
- __IM uint32_t RESERVED20[3];
- __IOM uint32_t BAUDRATE;
- __IM uint32_t RESERVED21[3];
- __IOM UARTE_RXD_Type RXD;
- __IM uint32_t RESERVED22;
- __IOM UARTE_TXD_Type TXD;
- __IM uint32_t RESERVED23[7];
- __IOM uint32_t CONFIG;
- } NRF_UARTE_Type;
- typedef struct {
- __OM uint32_t TASKS_OUT[8];
- __IM uint32_t RESERVED[4];
- __OM uint32_t TASKS_SET[8];
- __IM uint32_t RESERVED1[4];
- __OM uint32_t TASKS_CLR[8];
- __IOM uint32_t SUBSCRIBE_OUT[8];
- __IM uint32_t RESERVED2[4];
- __IOM uint32_t SUBSCRIBE_SET[8];
- __IM uint32_t RESERVED3[4];
- __IOM uint32_t SUBSCRIBE_CLR[8];
- __IOM uint32_t EVENTS_IN[8];
- __IM uint32_t RESERVED4[23];
- __IOM uint32_t EVENTS_PORT;
- __IOM uint32_t PUBLISH_IN[8];
- __IM uint32_t RESERVED5[23];
- __IOM uint32_t PUBLISH_PORT;
- __IM uint32_t RESERVED6[65];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED7[129];
- __IOM uint32_t CONFIG[8];
- } NRF_GPIOTE_Type;
- typedef struct {
- __OM uint32_t TASKS_START;
- __OM uint32_t TASKS_SAMPLE;
- __OM uint32_t TASKS_STOP;
- __OM uint32_t TASKS_CALIBRATEOFFSET;
- __IM uint32_t RESERVED[28];
- __IOM uint32_t SUBSCRIBE_START;
- __IOM uint32_t SUBSCRIBE_SAMPLE;
- __IOM uint32_t SUBSCRIBE_STOP;
- __IOM uint32_t SUBSCRIBE_CALIBRATEOFFSET;
- __IM uint32_t RESERVED1[28];
- __IOM uint32_t EVENTS_STARTED;
- __IOM uint32_t EVENTS_END;
- __IOM uint32_t EVENTS_DONE;
- __IOM uint32_t EVENTS_RESULTDONE;
- __IOM uint32_t EVENTS_CALIBRATEDONE;
- __IOM uint32_t EVENTS_STOPPED;
- __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8];
- __IM uint32_t RESERVED2[10];
- __IOM uint32_t PUBLISH_STARTED;
- __IOM uint32_t PUBLISH_END;
- __IOM uint32_t PUBLISH_DONE;
- __IOM uint32_t PUBLISH_RESULTDONE;
- __IOM uint32_t PUBLISH_CALIBRATEDONE;
- __IOM uint32_t PUBLISH_STOPPED;
- __IOM SAADC_PUBLISH_CH_Type PUBLISH_CH[8];
- __IM uint32_t RESERVED3[74];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED4[61];
- __IM uint32_t STATUS;
- __IM uint32_t RESERVED5[63];
- __IOM uint32_t ENABLE;
- __IM uint32_t RESERVED6[3];
- __IOM SAADC_CH_Type CH[8];
- __IM uint32_t RESERVED7[24];
- __IOM uint32_t RESOLUTION;
- __IOM uint32_t OVERSAMPLE;
- __IOM uint32_t SAMPLERATE;
- __IM uint32_t RESERVED8[12];
- __IOM SAADC_RESULT_Type RESULT;
- } NRF_SAADC_Type;
- typedef struct {
- __OM uint32_t TASKS_START;
- __OM uint32_t TASKS_STOP;
- __OM uint32_t TASKS_COUNT;
- __OM uint32_t TASKS_CLEAR;
- __OM uint32_t TASKS_SHUTDOWN;
- __IM uint32_t RESERVED[11];
- __OM uint32_t TASKS_CAPTURE[6];
- __IM uint32_t RESERVED1[10];
- __IOM uint32_t SUBSCRIBE_START;
- __IOM uint32_t SUBSCRIBE_STOP;
- __IOM uint32_t SUBSCRIBE_COUNT;
- __IOM uint32_t SUBSCRIBE_CLEAR;
- __IOM uint32_t SUBSCRIBE_SHUTDOWN;
- __IM uint32_t RESERVED2[11];
- __IOM uint32_t SUBSCRIBE_CAPTURE[6];
- __IM uint32_t RESERVED3[26];
- __IOM uint32_t EVENTS_COMPARE[6];
- __IM uint32_t RESERVED4[26];
- __IOM uint32_t PUBLISH_COMPARE[6];
- __IM uint32_t RESERVED5[10];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED6[64];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED7[126];
- __IOM uint32_t MODE;
- __IOM uint32_t BITMODE;
- __IM uint32_t RESERVED8;
- __IOM uint32_t PRESCALER;
- __IOM uint32_t ONESHOTEN[6];
- __IM uint32_t RESERVED9[5];
- __IOM uint32_t CC[6];
- } NRF_TIMER_Type;
- typedef struct {
- __OM uint32_t TASKS_START;
- __OM uint32_t TASKS_STOP;
- __OM uint32_t TASKS_CLEAR;
- __OM uint32_t TASKS_TRIGOVRFLW;
- __IM uint32_t RESERVED[28];
- __IOM uint32_t SUBSCRIBE_START;
- __IOM uint32_t SUBSCRIBE_STOP;
- __IOM uint32_t SUBSCRIBE_CLEAR;
- __IOM uint32_t SUBSCRIBE_TRIGOVRFLW;
- __IM uint32_t RESERVED1[28];
- __IOM uint32_t EVENTS_TICK;
- __IOM uint32_t EVENTS_OVRFLW;
- __IM uint32_t RESERVED2[14];
- __IOM uint32_t EVENTS_COMPARE[4];
- __IM uint32_t RESERVED3[12];
- __IOM uint32_t PUBLISH_TICK;
- __IOM uint32_t PUBLISH_OVRFLW;
- __IM uint32_t RESERVED4[14];
- __IOM uint32_t PUBLISH_COMPARE[4];
- __IM uint32_t RESERVED5[77];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED6[13];
- __IOM uint32_t EVTEN;
- __IOM uint32_t EVTENSET;
- __IOM uint32_t EVTENCLR;
- __IM uint32_t RESERVED7[110];
- __IM uint32_t COUNTER;
- __IOM uint32_t PRESCALER;
- __IM uint32_t RESERVED8[13];
- __IOM uint32_t CC[4];
- } NRF_RTC_Type;
- typedef struct {
- __OM DPPIC_TASKS_CHG_Type TASKS_CHG[6];
- __IM uint32_t RESERVED[20];
- __IOM DPPIC_SUBSCRIBE_CHG_Type SUBSCRIBE_CHG[6];
- __IM uint32_t RESERVED1[276];
- __IOM uint32_t CHEN;
- __IOM uint32_t CHENSET;
- __IOM uint32_t CHENCLR;
- __IM uint32_t RESERVED2[189];
- __IOM uint32_t CHG[6];
- } NRF_DPPIC_Type;
- typedef struct {
- __OM uint32_t TASKS_START;
- __IM uint32_t RESERVED[31];
- __IOM uint32_t SUBSCRIBE_START;
- __IM uint32_t RESERVED1[31];
- __IOM uint32_t EVENTS_TIMEOUT;
- __IM uint32_t RESERVED2[31];
- __IOM uint32_t PUBLISH_TIMEOUT;
- __IM uint32_t RESERVED3[96];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED4[61];
- __IM uint32_t RUNSTATUS;
- __IM uint32_t REQSTATUS;
- __IM uint32_t RESERVED5[63];
- __IOM uint32_t CRV;
- __IOM uint32_t RREN;
- __IOM uint32_t CONFIG;
- __IM uint32_t RESERVED6[60];
- __OM uint32_t RR[8];
- } NRF_WDT_Type;
- typedef struct {
- __OM uint32_t TASKS_TRIGGER[16];
- __IM uint32_t RESERVED[16];
- __IOM uint32_t SUBSCRIBE_TRIGGER[16];
- __IM uint32_t RESERVED1[16];
- __IOM uint32_t EVENTS_TRIGGERED[16];
- __IM uint32_t RESERVED2[16];
- __IOM uint32_t PUBLISH_TRIGGERED[16];
- __IM uint32_t RESERVED3[80];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- } NRF_EGU_Type;
- typedef struct {
- __IM uint32_t RESERVED;
- __OM uint32_t TASKS_STOP;
- __OM uint32_t TASKS_SEQSTART[2];
- __OM uint32_t TASKS_NEXTSTEP;
- __IM uint32_t RESERVED1[28];
- __IOM uint32_t SUBSCRIBE_STOP;
- __IOM uint32_t SUBSCRIBE_SEQSTART[2];
- __IOM uint32_t SUBSCRIBE_NEXTSTEP;
- __IM uint32_t RESERVED2[28];
- __IOM uint32_t EVENTS_STOPPED;
- __IOM uint32_t EVENTS_SEQSTARTED[2];
- __IOM uint32_t EVENTS_SEQEND[2];
- __IOM uint32_t EVENTS_PWMPERIODEND;
- __IOM uint32_t EVENTS_LOOPSDONE;
- __IM uint32_t RESERVED3[25];
- __IOM uint32_t PUBLISH_STOPPED;
- __IOM uint32_t PUBLISH_SEQSTARTED[2];
- __IOM uint32_t PUBLISH_SEQEND[2];
- __IOM uint32_t PUBLISH_PWMPERIODEND;
- __IOM uint32_t PUBLISH_LOOPSDONE;
- __IM uint32_t RESERVED4[24];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED5[63];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED6[125];
- __IOM uint32_t ENABLE;
- __IOM uint32_t MODE;
- __IOM uint32_t COUNTERTOP;
- __IOM uint32_t PRESCALER;
- __IOM uint32_t DECODER;
- __IOM uint32_t LOOP;
- __IM uint32_t RESERVED7[2];
- __IOM PWM_SEQ_Type SEQ[2];
- __IOM PWM_PSEL_Type PSEL;
- } NRF_PWM_Type;
- typedef struct {
- __OM uint32_t TASKS_START;
- __OM uint32_t TASKS_STOP;
- __IM uint32_t RESERVED[30];
- __IOM uint32_t SUBSCRIBE_START;
- __IOM uint32_t SUBSCRIBE_STOP;
- __IM uint32_t RESERVED1[30];
- __IOM uint32_t EVENTS_STARTED;
- __IOM uint32_t EVENTS_STOPPED;
- __IOM uint32_t EVENTS_END;
- __IM uint32_t RESERVED2[29];
- __IOM uint32_t PUBLISH_STARTED;
- __IOM uint32_t PUBLISH_STOPPED;
- __IOM uint32_t PUBLISH_END;
- __IM uint32_t RESERVED3[93];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED4[125];
- __IOM uint32_t ENABLE;
- __IOM uint32_t PDMCLKCTRL;
- __IOM uint32_t MODE;
- __IM uint32_t RESERVED5[3];
- __IOM uint32_t GAINL;
- __IOM uint32_t GAINR;
- __IOM uint32_t RATIO;
- __IM uint32_t RESERVED6[7];
- __IOM PDM_PSEL_Type PSEL;
- __IM uint32_t RESERVED7[6];
- __IOM PDM_SAMPLE_Type SAMPLE;
- } NRF_PDM_Type;
- typedef struct {
- __OM uint32_t TASKS_START;
- __OM uint32_t TASKS_STOP;
- __IM uint32_t RESERVED[30];
- __IOM uint32_t SUBSCRIBE_START;
- __IOM uint32_t SUBSCRIBE_STOP;
- __IM uint32_t RESERVED1[31];
- __IOM uint32_t EVENTS_RXPTRUPD;
- __IOM uint32_t EVENTS_STOPPED;
- __IM uint32_t RESERVED2[2];
- __IOM uint32_t EVENTS_TXPTRUPD;
- __IM uint32_t RESERVED3[27];
- __IOM uint32_t PUBLISH_RXPTRUPD;
- __IOM uint32_t PUBLISH_STOPPED;
- __IM uint32_t RESERVED4[2];
- __IOM uint32_t PUBLISH_TXPTRUPD;
- __IM uint32_t RESERVED5[90];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED6[125];
- __IOM uint32_t ENABLE;
- __IOM I2S_CONFIG_Type CONFIG;
- __IM uint32_t RESERVED7[3];
- __IOM I2S_RXD_Type RXD;
- __IM uint32_t RESERVED8;
- __IOM I2S_TXD_Type TXD;
- __IM uint32_t RESERVED9[3];
- __IOM I2S_RXTXD_Type RXTXD;
- __IM uint32_t RESERVED10[3];
- __IOM I2S_PSEL_Type PSEL;
- } NRF_I2S_Type;
- typedef struct {
- __OM uint32_t TASKS_SEND[8];
- __IM uint32_t RESERVED[24];
- __IOM uint32_t SUBSCRIBE_SEND[8];
- __IM uint32_t RESERVED1[24];
- __IOM uint32_t EVENTS_RECEIVE[8];
- __IM uint32_t RESERVED2[24];
- __IOM uint32_t PUBLISH_RECEIVE[8];
- __IM uint32_t RESERVED3[88];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t INTPEND;
- __IM uint32_t RESERVED4[128];
- __IOM uint32_t SEND_CNF[8];
- __IM uint32_t RESERVED5[24];
- __IOM uint32_t RECEIVE_CNF[8];
- __IM uint32_t RESERVED6[24];
- __IOM uint32_t GPMEM[4];
- } NRF_IPC_Type;
- typedef struct {
- __IM uint32_t UNUSED;
- } NRF_FPU_Type;
- typedef struct {
- __OM uint32_t TASKS_PUSH_KEYSLOT;
- __IM uint32_t RESERVED[63];
- __IOM uint32_t EVENTS_KEYSLOT_PUSHED;
- __IOM uint32_t EVENTS_KEYSLOT_REVOKED;
- __IOM uint32_t EVENTS_KEYSLOT_ERROR;
- __IM uint32_t RESERVED1[125];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t INTPEND;
- __IM uint32_t RESERVED2[63];
- __IM uint32_t STATUS;
- __IM uint32_t RESERVED3[60];
- __IOM uint32_t SELECTKEYSLOT;
- } NRF_KMU_Type;
- typedef struct {
- __IM uint32_t RESERVED[256];
- __IM uint32_t READY;
- __IM uint32_t RESERVED1;
- __IM uint32_t READYNEXT;
- __IM uint32_t RESERVED2[62];
- __IOM uint32_t CONFIG;
- __IM uint32_t RESERVED3;
- __OM uint32_t ERASEALL;
- __IM uint32_t RESERVED4[3];
- __IOM uint32_t ERASEPAGEPARTIALCFG;
- __IM uint32_t RESERVED5[8];
- __IOM uint32_t ICACHECNF;
- __IM uint32_t RESERVED6;
- __IOM uint32_t IHIT;
- __IOM uint32_t IMISS;
- __IM uint32_t RESERVED7[13];
- __IOM uint32_t CONFIGNS;
- __OM uint32_t WRITEUICRNS;
- } NRF_NVMC_Type;
- typedef struct {
- __IM uint32_t RESERVED[384];
- __IOM VMC_RAM_Type RAM[8];
- } NRF_VMC_Type;
- typedef struct {
- __IM uint32_t RESERVED[1678];
- __IOM uint32_t HOST_CRYPTOKEY_SEL;
- __IM uint32_t RESERVED1[4];
- __IOM uint32_t HOST_IOT_KPRTL_LOCK;
- __IOM uint32_t HOST_IOT_KDR0;
- __OM uint32_t HOST_IOT_KDR1;
- __OM uint32_t HOST_IOT_KDR2;
- __OM uint32_t HOST_IOT_KDR3;
- __IOM uint32_t HOST_IOT_LCS;
- } NRF_CC_HOST_RGF_Type;
- typedef struct {
- __IM uint32_t RESERVED[320];
- __IOM uint32_t ENABLE;
- } NRF_CRYPTOCELL_Type;
- typedef struct {
- __IM uint32_t RESERVED;
- __IOM uint32_t OUT;
- __IOM uint32_t OUTSET;
- __IOM uint32_t OUTCLR;
- __IM uint32_t IN;
- __IOM uint32_t DIR;
- __IOM uint32_t DIRSET;
- __IOM uint32_t DIRCLR;
- __IOM uint32_t LATCH;
- __IOM uint32_t DETECTMODE;
- __IOM uint32_t DETECTMODE_SEC;
- __IM uint32_t RESERVED1[117];
- __IOM uint32_t PIN_CNF[32];
- } NRF_GPIO_Type;
-
- #define NRF_FICR_S_BASE 0x00FF0000UL
- #define NRF_UICR_S_BASE 0x00FF8000UL
- #define NRF_TAD_S_BASE 0xE0080000UL
- #define NRF_SPU_S_BASE 0x50003000UL
- #define NRF_REGULATORS_NS_BASE 0x40004000UL
- #define NRF_REGULATORS_S_BASE 0x50004000UL
- #define NRF_CLOCK_NS_BASE 0x40005000UL
- #define NRF_POWER_NS_BASE 0x40005000UL
- #define NRF_CLOCK_S_BASE 0x50005000UL
- #define NRF_POWER_S_BASE 0x50005000UL
- #define NRF_CTRL_AP_PERI_S_BASE 0x50006000UL
- #define NRF_SPIM0_NS_BASE 0x40008000UL
- #define NRF_SPIS0_NS_BASE 0x40008000UL
- #define NRF_TWIM0_NS_BASE 0x40008000UL
- #define NRF_TWIS0_NS_BASE 0x40008000UL
- #define NRF_UARTE0_NS_BASE 0x40008000UL
- #define NRF_SPIM0_S_BASE 0x50008000UL
- #define NRF_SPIS0_S_BASE 0x50008000UL
- #define NRF_TWIM0_S_BASE 0x50008000UL
- #define NRF_TWIS0_S_BASE 0x50008000UL
- #define NRF_UARTE0_S_BASE 0x50008000UL
- #define NRF_SPIM1_NS_BASE 0x40009000UL
- #define NRF_SPIS1_NS_BASE 0x40009000UL
- #define NRF_TWIM1_NS_BASE 0x40009000UL
- #define NRF_TWIS1_NS_BASE 0x40009000UL
- #define NRF_UARTE1_NS_BASE 0x40009000UL
- #define NRF_SPIM1_S_BASE 0x50009000UL
- #define NRF_SPIS1_S_BASE 0x50009000UL
- #define NRF_TWIM1_S_BASE 0x50009000UL
- #define NRF_TWIS1_S_BASE 0x50009000UL
- #define NRF_UARTE1_S_BASE 0x50009000UL
- #define NRF_SPIM2_NS_BASE 0x4000A000UL
- #define NRF_SPIS2_NS_BASE 0x4000A000UL
- #define NRF_TWIM2_NS_BASE 0x4000A000UL
- #define NRF_TWIS2_NS_BASE 0x4000A000UL
- #define NRF_UARTE2_NS_BASE 0x4000A000UL
- #define NRF_SPIM2_S_BASE 0x5000A000UL
- #define NRF_SPIS2_S_BASE 0x5000A000UL
- #define NRF_TWIM2_S_BASE 0x5000A000UL
- #define NRF_TWIS2_S_BASE 0x5000A000UL
- #define NRF_UARTE2_S_BASE 0x5000A000UL
- #define NRF_SPIM3_NS_BASE 0x4000B000UL
- #define NRF_SPIS3_NS_BASE 0x4000B000UL
- #define NRF_TWIM3_NS_BASE 0x4000B000UL
- #define NRF_TWIS3_NS_BASE 0x4000B000UL
- #define NRF_UARTE3_NS_BASE 0x4000B000UL
- #define NRF_SPIM3_S_BASE 0x5000B000UL
- #define NRF_SPIS3_S_BASE 0x5000B000UL
- #define NRF_TWIM3_S_BASE 0x5000B000UL
- #define NRF_TWIS3_S_BASE 0x5000B000UL
- #define NRF_UARTE3_S_BASE 0x5000B000UL
- #define NRF_GPIOTE0_S_BASE 0x5000D000UL
- #define NRF_SAADC_NS_BASE 0x4000E000UL
- #define NRF_SAADC_S_BASE 0x5000E000UL
- #define NRF_TIMER0_NS_BASE 0x4000F000UL
- #define NRF_TIMER0_S_BASE 0x5000F000UL
- #define NRF_TIMER1_NS_BASE 0x40010000UL
- #define NRF_TIMER1_S_BASE 0x50010000UL
- #define NRF_TIMER2_NS_BASE 0x40011000UL
- #define NRF_TIMER2_S_BASE 0x50011000UL
- #define NRF_RTC0_NS_BASE 0x40014000UL
- #define NRF_RTC0_S_BASE 0x50014000UL
- #define NRF_RTC1_NS_BASE 0x40015000UL
- #define NRF_RTC1_S_BASE 0x50015000UL
- #define NRF_DPPIC_NS_BASE 0x40017000UL
- #define NRF_DPPIC_S_BASE 0x50017000UL
- #define NRF_WDT_NS_BASE 0x40018000UL
- #define NRF_WDT_S_BASE 0x50018000UL
- #define NRF_EGU0_NS_BASE 0x4001B000UL
- #define NRF_EGU0_S_BASE 0x5001B000UL
- #define NRF_EGU1_NS_BASE 0x4001C000UL
- #define NRF_EGU1_S_BASE 0x5001C000UL
- #define NRF_EGU2_NS_BASE 0x4001D000UL
- #define NRF_EGU2_S_BASE 0x5001D000UL
- #define NRF_EGU3_NS_BASE 0x4001E000UL
- #define NRF_EGU3_S_BASE 0x5001E000UL
- #define NRF_EGU4_NS_BASE 0x4001F000UL
- #define NRF_EGU4_S_BASE 0x5001F000UL
- #define NRF_EGU5_NS_BASE 0x40020000UL
- #define NRF_EGU5_S_BASE 0x50020000UL
- #define NRF_PWM0_NS_BASE 0x40021000UL
- #define NRF_PWM0_S_BASE 0x50021000UL
- #define NRF_PWM1_NS_BASE 0x40022000UL
- #define NRF_PWM1_S_BASE 0x50022000UL
- #define NRF_PWM2_NS_BASE 0x40023000UL
- #define NRF_PWM2_S_BASE 0x50023000UL
- #define NRF_PWM3_NS_BASE 0x40024000UL
- #define NRF_PWM3_S_BASE 0x50024000UL
- #define NRF_PDM_NS_BASE 0x40026000UL
- #define NRF_PDM_S_BASE 0x50026000UL
- #define NRF_I2S_NS_BASE 0x40028000UL
- #define NRF_I2S_S_BASE 0x50028000UL
- #define NRF_IPC_NS_BASE 0x4002A000UL
- #define NRF_IPC_S_BASE 0x5002A000UL
- #define NRF_FPU_NS_BASE 0x4002C000UL
- #define NRF_FPU_S_BASE 0x5002C000UL
- #define NRF_GPIOTE1_NS_BASE 0x40031000UL
- #define NRF_KMU_NS_BASE 0x40039000UL
- #define NRF_NVMC_NS_BASE 0x40039000UL
- #define NRF_KMU_S_BASE 0x50039000UL
- #define NRF_NVMC_S_BASE 0x50039000UL
- #define NRF_VMC_NS_BASE 0x4003A000UL
- #define NRF_VMC_S_BASE 0x5003A000UL
- #define NRF_CC_HOST_RGF_S_BASE 0x50840000UL
- #define NRF_CRYPTOCELL_S_BASE 0x50840000UL
- #define NRF_P0_NS_BASE 0x40842500UL
- #define NRF_P0_S_BASE 0x50842500UL
-
- #define NRF_FICR_S ((NRF_FICR_Type*) NRF_FICR_S_BASE)
- #define NRF_UICR_S ((NRF_UICR_Type*) NRF_UICR_S_BASE)
- #define NRF_TAD_S ((NRF_TAD_Type*) NRF_TAD_S_BASE)
- #define NRF_SPU_S ((NRF_SPU_Type*) NRF_SPU_S_BASE)
- #define NRF_REGULATORS_NS ((NRF_REGULATORS_Type*) NRF_REGULATORS_NS_BASE)
- #define NRF_REGULATORS_S ((NRF_REGULATORS_Type*) NRF_REGULATORS_S_BASE)
- #define NRF_CLOCK_NS ((NRF_CLOCK_Type*) NRF_CLOCK_NS_BASE)
- #define NRF_POWER_NS ((NRF_POWER_Type*) NRF_POWER_NS_BASE)
- #define NRF_CLOCK_S ((NRF_CLOCK_Type*) NRF_CLOCK_S_BASE)
- #define NRF_POWER_S ((NRF_POWER_Type*) NRF_POWER_S_BASE)
- #define NRF_CTRL_AP_PERI_S ((NRF_CTRLAPPERI_Type*) NRF_CTRL_AP_PERI_S_BASE)
- #define NRF_SPIM0_NS ((NRF_SPIM_Type*) NRF_SPIM0_NS_BASE)
- #define NRF_SPIS0_NS ((NRF_SPIS_Type*) NRF_SPIS0_NS_BASE)
- #define NRF_TWIM0_NS ((NRF_TWIM_Type*) NRF_TWIM0_NS_BASE)
- #define NRF_TWIS0_NS ((NRF_TWIS_Type*) NRF_TWIS0_NS_BASE)
- #define NRF_UARTE0_NS ((NRF_UARTE_Type*) NRF_UARTE0_NS_BASE)
- #define NRF_SPIM0_S ((NRF_SPIM_Type*) NRF_SPIM0_S_BASE)
- #define NRF_SPIS0_S ((NRF_SPIS_Type*) NRF_SPIS0_S_BASE)
- #define NRF_TWIM0_S ((NRF_TWIM_Type*) NRF_TWIM0_S_BASE)
- #define NRF_TWIS0_S ((NRF_TWIS_Type*) NRF_TWIS0_S_BASE)
- #define NRF_UARTE0_S ((NRF_UARTE_Type*) NRF_UARTE0_S_BASE)
- #define NRF_SPIM1_NS ((NRF_SPIM_Type*) NRF_SPIM1_NS_BASE)
- #define NRF_SPIS1_NS ((NRF_SPIS_Type*) NRF_SPIS1_NS_BASE)
- #define NRF_TWIM1_NS ((NRF_TWIM_Type*) NRF_TWIM1_NS_BASE)
- #define NRF_TWIS1_NS ((NRF_TWIS_Type*) NRF_TWIS1_NS_BASE)
- #define NRF_UARTE1_NS ((NRF_UARTE_Type*) NRF_UARTE1_NS_BASE)
- #define NRF_SPIM1_S ((NRF_SPIM_Type*) NRF_SPIM1_S_BASE)
- #define NRF_SPIS1_S ((NRF_SPIS_Type*) NRF_SPIS1_S_BASE)
- #define NRF_TWIM1_S ((NRF_TWIM_Type*) NRF_TWIM1_S_BASE)
- #define NRF_TWIS1_S ((NRF_TWIS_Type*) NRF_TWIS1_S_BASE)
- #define NRF_UARTE1_S ((NRF_UARTE_Type*) NRF_UARTE1_S_BASE)
- #define NRF_SPIM2_NS ((NRF_SPIM_Type*) NRF_SPIM2_NS_BASE)
- #define NRF_SPIS2_NS ((NRF_SPIS_Type*) NRF_SPIS2_NS_BASE)
- #define NRF_TWIM2_NS ((NRF_TWIM_Type*) NRF_TWIM2_NS_BASE)
- #define NRF_TWIS2_NS ((NRF_TWIS_Type*) NRF_TWIS2_NS_BASE)
- #define NRF_UARTE2_NS ((NRF_UARTE_Type*) NRF_UARTE2_NS_BASE)
- #define NRF_SPIM2_S ((NRF_SPIM_Type*) NRF_SPIM2_S_BASE)
- #define NRF_SPIS2_S ((NRF_SPIS_Type*) NRF_SPIS2_S_BASE)
- #define NRF_TWIM2_S ((NRF_TWIM_Type*) NRF_TWIM2_S_BASE)
- #define NRF_TWIS2_S ((NRF_TWIS_Type*) NRF_TWIS2_S_BASE)
- #define NRF_UARTE2_S ((NRF_UARTE_Type*) NRF_UARTE2_S_BASE)
- #define NRF_SPIM3_NS ((NRF_SPIM_Type*) NRF_SPIM3_NS_BASE)
- #define NRF_SPIS3_NS ((NRF_SPIS_Type*) NRF_SPIS3_NS_BASE)
- #define NRF_TWIM3_NS ((NRF_TWIM_Type*) NRF_TWIM3_NS_BASE)
- #define NRF_TWIS3_NS ((NRF_TWIS_Type*) NRF_TWIS3_NS_BASE)
- #define NRF_UARTE3_NS ((NRF_UARTE_Type*) NRF_UARTE3_NS_BASE)
- #define NRF_SPIM3_S ((NRF_SPIM_Type*) NRF_SPIM3_S_BASE)
- #define NRF_SPIS3_S ((NRF_SPIS_Type*) NRF_SPIS3_S_BASE)
- #define NRF_TWIM3_S ((NRF_TWIM_Type*) NRF_TWIM3_S_BASE)
- #define NRF_TWIS3_S ((NRF_TWIS_Type*) NRF_TWIS3_S_BASE)
- #define NRF_UARTE3_S ((NRF_UARTE_Type*) NRF_UARTE3_S_BASE)
- #define NRF_GPIOTE0_S ((NRF_GPIOTE_Type*) NRF_GPIOTE0_S_BASE)
- #define NRF_SAADC_NS ((NRF_SAADC_Type*) NRF_SAADC_NS_BASE)
- #define NRF_SAADC_S ((NRF_SAADC_Type*) NRF_SAADC_S_BASE)
- #define NRF_TIMER0_NS ((NRF_TIMER_Type*) NRF_TIMER0_NS_BASE)
- #define NRF_TIMER0_S ((NRF_TIMER_Type*) NRF_TIMER0_S_BASE)
- #define NRF_TIMER1_NS ((NRF_TIMER_Type*) NRF_TIMER1_NS_BASE)
- #define NRF_TIMER1_S ((NRF_TIMER_Type*) NRF_TIMER1_S_BASE)
- #define NRF_TIMER2_NS ((NRF_TIMER_Type*) NRF_TIMER2_NS_BASE)
- #define NRF_TIMER2_S ((NRF_TIMER_Type*) NRF_TIMER2_S_BASE)
- #define NRF_RTC0_NS ((NRF_RTC_Type*) NRF_RTC0_NS_BASE)
- #define NRF_RTC0_S ((NRF_RTC_Type*) NRF_RTC0_S_BASE)
- #define NRF_RTC1_NS ((NRF_RTC_Type*) NRF_RTC1_NS_BASE)
- #define NRF_RTC1_S ((NRF_RTC_Type*) NRF_RTC1_S_BASE)
- #define NRF_DPPIC_NS ((NRF_DPPIC_Type*) NRF_DPPIC_NS_BASE)
- #define NRF_DPPIC_S ((NRF_DPPIC_Type*) NRF_DPPIC_S_BASE)
- #define NRF_WDT_NS ((NRF_WDT_Type*) NRF_WDT_NS_BASE)
- #define NRF_WDT_S ((NRF_WDT_Type*) NRF_WDT_S_BASE)
- #define NRF_EGU0_NS ((NRF_EGU_Type*) NRF_EGU0_NS_BASE)
- #define NRF_EGU0_S ((NRF_EGU_Type*) NRF_EGU0_S_BASE)
- #define NRF_EGU1_NS ((NRF_EGU_Type*) NRF_EGU1_NS_BASE)
- #define NRF_EGU1_S ((NRF_EGU_Type*) NRF_EGU1_S_BASE)
- #define NRF_EGU2_NS ((NRF_EGU_Type*) NRF_EGU2_NS_BASE)
- #define NRF_EGU2_S ((NRF_EGU_Type*) NRF_EGU2_S_BASE)
- #define NRF_EGU3_NS ((NRF_EGU_Type*) NRF_EGU3_NS_BASE)
- #define NRF_EGU3_S ((NRF_EGU_Type*) NRF_EGU3_S_BASE)
- #define NRF_EGU4_NS ((NRF_EGU_Type*) NRF_EGU4_NS_BASE)
- #define NRF_EGU4_S ((NRF_EGU_Type*) NRF_EGU4_S_BASE)
- #define NRF_EGU5_NS ((NRF_EGU_Type*) NRF_EGU5_NS_BASE)
- #define NRF_EGU5_S ((NRF_EGU_Type*) NRF_EGU5_S_BASE)
- #define NRF_PWM0_NS ((NRF_PWM_Type*) NRF_PWM0_NS_BASE)
- #define NRF_PWM0_S ((NRF_PWM_Type*) NRF_PWM0_S_BASE)
- #define NRF_PWM1_NS ((NRF_PWM_Type*) NRF_PWM1_NS_BASE)
- #define NRF_PWM1_S ((NRF_PWM_Type*) NRF_PWM1_S_BASE)
- #define NRF_PWM2_NS ((NRF_PWM_Type*) NRF_PWM2_NS_BASE)
- #define NRF_PWM2_S ((NRF_PWM_Type*) NRF_PWM2_S_BASE)
- #define NRF_PWM3_NS ((NRF_PWM_Type*) NRF_PWM3_NS_BASE)
- #define NRF_PWM3_S ((NRF_PWM_Type*) NRF_PWM3_S_BASE)
- #define NRF_PDM_NS ((NRF_PDM_Type*) NRF_PDM_NS_BASE)
- #define NRF_PDM_S ((NRF_PDM_Type*) NRF_PDM_S_BASE)
- #define NRF_I2S_NS ((NRF_I2S_Type*) NRF_I2S_NS_BASE)
- #define NRF_I2S_S ((NRF_I2S_Type*) NRF_I2S_S_BASE)
- #define NRF_IPC_NS ((NRF_IPC_Type*) NRF_IPC_NS_BASE)
- #define NRF_IPC_S ((NRF_IPC_Type*) NRF_IPC_S_BASE)
- #define NRF_FPU_NS ((NRF_FPU_Type*) NRF_FPU_NS_BASE)
- #define NRF_FPU_S ((NRF_FPU_Type*) NRF_FPU_S_BASE)
- #define NRF_GPIOTE1_NS ((NRF_GPIOTE_Type*) NRF_GPIOTE1_NS_BASE)
- #define NRF_KMU_NS ((NRF_KMU_Type*) NRF_KMU_NS_BASE)
- #define NRF_NVMC_NS ((NRF_NVMC_Type*) NRF_NVMC_NS_BASE)
- #define NRF_KMU_S ((NRF_KMU_Type*) NRF_KMU_S_BASE)
- #define NRF_NVMC_S ((NRF_NVMC_Type*) NRF_NVMC_S_BASE)
- #define NRF_VMC_NS ((NRF_VMC_Type*) NRF_VMC_NS_BASE)
- #define NRF_VMC_S ((NRF_VMC_Type*) NRF_VMC_S_BASE)
- #define NRF_CC_HOST_RGF_S ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_S_BASE)
- #define NRF_CRYPTOCELL_S ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_S_BASE)
- #define NRF_P0_NS ((NRF_GPIO_Type*) NRF_P0_NS_BASE)
- #define NRF_P0_S ((NRF_GPIO_Type*) NRF_P0_S_BASE)
-
- #ifdef __cplusplus
- }
- #endif
- #endif
-
-
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