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- #ifndef __NRF5340_NETWORK_BITS_H
- #define __NRF5340_NETWORK_BITS_H
- #define AAR_TASKS_START_TASKS_START_Pos (0UL)
- #define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos)
- #define AAR_TASKS_START_TASKS_START_Trigger (1UL)
- #define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos)
- #define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define AAR_SUBSCRIBE_START_EN_Pos (31UL)
- #define AAR_SUBSCRIBE_START_EN_Msk (0x1UL << AAR_SUBSCRIBE_START_EN_Pos)
- #define AAR_SUBSCRIBE_START_EN_Disabled (0UL)
- #define AAR_SUBSCRIBE_START_EN_Enabled (1UL)
- #define AAR_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define AAR_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << AAR_SUBSCRIBE_START_CHIDX_Pos)
- #define AAR_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define AAR_SUBSCRIBE_STOP_EN_Msk (0x1UL << AAR_SUBSCRIBE_STOP_EN_Pos)
- #define AAR_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define AAR_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define AAR_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define AAR_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << AAR_SUBSCRIBE_STOP_CHIDX_Pos)
- #define AAR_EVENTS_END_EVENTS_END_Pos (0UL)
- #define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos)
- #define AAR_EVENTS_END_EVENTS_END_NotGenerated (0UL)
- #define AAR_EVENTS_END_EVENTS_END_Generated (1UL)
- #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL)
- #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos)
- #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0UL)
- #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL)
- #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL)
- #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos)
- #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0UL)
- #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL)
- #define AAR_PUBLISH_END_EN_Pos (31UL)
- #define AAR_PUBLISH_END_EN_Msk (0x1UL << AAR_PUBLISH_END_EN_Pos)
- #define AAR_PUBLISH_END_EN_Disabled (0UL)
- #define AAR_PUBLISH_END_EN_Enabled (1UL)
- #define AAR_PUBLISH_END_CHIDX_Pos (0UL)
- #define AAR_PUBLISH_END_CHIDX_Msk (0xFFUL << AAR_PUBLISH_END_CHIDX_Pos)
- #define AAR_PUBLISH_RESOLVED_EN_Pos (31UL)
- #define AAR_PUBLISH_RESOLVED_EN_Msk (0x1UL << AAR_PUBLISH_RESOLVED_EN_Pos)
- #define AAR_PUBLISH_RESOLVED_EN_Disabled (0UL)
- #define AAR_PUBLISH_RESOLVED_EN_Enabled (1UL)
- #define AAR_PUBLISH_RESOLVED_CHIDX_Pos (0UL)
- #define AAR_PUBLISH_RESOLVED_CHIDX_Msk (0xFFUL << AAR_PUBLISH_RESOLVED_CHIDX_Pos)
- #define AAR_PUBLISH_NOTRESOLVED_EN_Pos (31UL)
- #define AAR_PUBLISH_NOTRESOLVED_EN_Msk (0x1UL << AAR_PUBLISH_NOTRESOLVED_EN_Pos)
- #define AAR_PUBLISH_NOTRESOLVED_EN_Disabled (0UL)
- #define AAR_PUBLISH_NOTRESOLVED_EN_Enabled (1UL)
- #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Pos (0UL)
- #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Msk (0xFFUL << AAR_PUBLISH_NOTRESOLVED_CHIDX_Pos)
- #define AAR_INTENSET_NOTRESOLVED_Pos (2UL)
- #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos)
- #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL)
- #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL)
- #define AAR_INTENSET_NOTRESOLVED_Set (1UL)
- #define AAR_INTENSET_RESOLVED_Pos (1UL)
- #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos)
- #define AAR_INTENSET_RESOLVED_Disabled (0UL)
- #define AAR_INTENSET_RESOLVED_Enabled (1UL)
- #define AAR_INTENSET_RESOLVED_Set (1UL)
- #define AAR_INTENSET_END_Pos (0UL)
- #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos)
- #define AAR_INTENSET_END_Disabled (0UL)
- #define AAR_INTENSET_END_Enabled (1UL)
- #define AAR_INTENSET_END_Set (1UL)
- #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL)
- #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos)
- #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL)
- #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL)
- #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL)
- #define AAR_INTENCLR_RESOLVED_Pos (1UL)
- #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos)
- #define AAR_INTENCLR_RESOLVED_Disabled (0UL)
- #define AAR_INTENCLR_RESOLVED_Enabled (1UL)
- #define AAR_INTENCLR_RESOLVED_Clear (1UL)
- #define AAR_INTENCLR_END_Pos (0UL)
- #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos)
- #define AAR_INTENCLR_END_Disabled (0UL)
- #define AAR_INTENCLR_END_Enabled (1UL)
- #define AAR_INTENCLR_END_Clear (1UL)
- #define AAR_STATUS_STATUS_Pos (0UL)
- #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos)
- #define AAR_ENABLE_ENABLE_Pos (0UL)
- #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos)
- #define AAR_ENABLE_ENABLE_Disabled (0UL)
- #define AAR_ENABLE_ENABLE_Enabled (3UL)
- #define AAR_NIRK_NIRK_Pos (0UL)
- #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos)
- #define AAR_IRKPTR_IRKPTR_Pos (0UL)
- #define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos)
- #define AAR_ADDRPTR_ADDRPTR_Pos (0UL)
- #define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos)
- #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL)
- #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos)
- #define ACL_ACL_ADDR_ADDR_Pos (0UL)
- #define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos)
- #define ACL_ACL_SIZE_SIZE_Pos (0UL)
- #define ACL_ACL_SIZE_SIZE_Msk (0xFFFFFFFFUL << ACL_ACL_SIZE_SIZE_Pos)
- #define ACL_ACL_PERM_READ_Pos (2UL)
- #define ACL_ACL_PERM_READ_Msk (0x1UL << ACL_ACL_PERM_READ_Pos)
- #define ACL_ACL_PERM_READ_Enable (0UL)
- #define ACL_ACL_PERM_READ_Disable (1UL)
- #define ACL_ACL_PERM_WRITE_Pos (1UL)
- #define ACL_ACL_PERM_WRITE_Msk (0x1UL << ACL_ACL_PERM_WRITE_Pos)
- #define ACL_ACL_PERM_WRITE_Enable (0UL)
- #define ACL_ACL_PERM_WRITE_Disable (1UL)
- #define MUTEX_MUTEX_MUTEX_Pos (0UL)
- #define MUTEX_MUTEX_MUTEX_Msk (0x1UL << MUTEX_MUTEX_MUTEX_Pos)
- #define MUTEX_MUTEX_MUTEX_Unlocked (0UL)
- #define MUTEX_MUTEX_MUTEX_Locked (1UL)
- #define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL)
- #define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos)
- #define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL)
- #define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL)
- #define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos)
- #define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (1UL)
- #define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos)
- #define CCM_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL)
- #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos)
- #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL)
- #define CCM_SUBSCRIBE_KSGEN_EN_Pos (31UL)
- #define CCM_SUBSCRIBE_KSGEN_EN_Msk (0x1UL << CCM_SUBSCRIBE_KSGEN_EN_Pos)
- #define CCM_SUBSCRIBE_KSGEN_EN_Disabled (0UL)
- #define CCM_SUBSCRIBE_KSGEN_EN_Enabled (1UL)
- #define CCM_SUBSCRIBE_KSGEN_CHIDX_Pos (0UL)
- #define CCM_SUBSCRIBE_KSGEN_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_KSGEN_CHIDX_Pos)
- #define CCM_SUBSCRIBE_CRYPT_EN_Pos (31UL)
- #define CCM_SUBSCRIBE_CRYPT_EN_Msk (0x1UL << CCM_SUBSCRIBE_CRYPT_EN_Pos)
- #define CCM_SUBSCRIBE_CRYPT_EN_Disabled (0UL)
- #define CCM_SUBSCRIBE_CRYPT_EN_Enabled (1UL)
- #define CCM_SUBSCRIBE_CRYPT_CHIDX_Pos (0UL)
- #define CCM_SUBSCRIBE_CRYPT_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_CRYPT_CHIDX_Pos)
- #define CCM_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define CCM_SUBSCRIBE_STOP_EN_Msk (0x1UL << CCM_SUBSCRIBE_STOP_EN_Pos)
- #define CCM_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define CCM_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define CCM_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define CCM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_STOP_CHIDX_Pos)
- #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Pos (31UL)
- #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Msk (0x1UL << CCM_SUBSCRIBE_RATEOVERRIDE_EN_Pos)
- #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Disabled (0UL)
- #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Enabled (1UL)
- #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Pos (0UL)
- #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Pos)
- #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL)
- #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos)
- #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL)
- #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (1UL)
- #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL)
- #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos)
- #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0UL)
- #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (1UL)
- #define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)
- #define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos)
- #define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL)
- #define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL)
- #define CCM_PUBLISH_ENDKSGEN_EN_Pos (31UL)
- #define CCM_PUBLISH_ENDKSGEN_EN_Msk (0x1UL << CCM_PUBLISH_ENDKSGEN_EN_Pos)
- #define CCM_PUBLISH_ENDKSGEN_EN_Disabled (0UL)
- #define CCM_PUBLISH_ENDKSGEN_EN_Enabled (1UL)
- #define CCM_PUBLISH_ENDKSGEN_CHIDX_Pos (0UL)
- #define CCM_PUBLISH_ENDKSGEN_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ENDKSGEN_CHIDX_Pos)
- #define CCM_PUBLISH_ENDCRYPT_EN_Pos (31UL)
- #define CCM_PUBLISH_ENDCRYPT_EN_Msk (0x1UL << CCM_PUBLISH_ENDCRYPT_EN_Pos)
- #define CCM_PUBLISH_ENDCRYPT_EN_Disabled (0UL)
- #define CCM_PUBLISH_ENDCRYPT_EN_Enabled (1UL)
- #define CCM_PUBLISH_ENDCRYPT_CHIDX_Pos (0UL)
- #define CCM_PUBLISH_ENDCRYPT_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ENDCRYPT_CHIDX_Pos)
- #define CCM_PUBLISH_ERROR_EN_Pos (31UL)
- #define CCM_PUBLISH_ERROR_EN_Msk (0x1UL << CCM_PUBLISH_ERROR_EN_Pos)
- #define CCM_PUBLISH_ERROR_EN_Disabled (0UL)
- #define CCM_PUBLISH_ERROR_EN_Enabled (1UL)
- #define CCM_PUBLISH_ERROR_CHIDX_Pos (0UL)
- #define CCM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ERROR_CHIDX_Pos)
- #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL)
- #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos)
- #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL)
- #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL)
- #define CCM_INTENSET_ERROR_Pos (2UL)
- #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos)
- #define CCM_INTENSET_ERROR_Disabled (0UL)
- #define CCM_INTENSET_ERROR_Enabled (1UL)
- #define CCM_INTENSET_ERROR_Set (1UL)
- #define CCM_INTENSET_ENDCRYPT_Pos (1UL)
- #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos)
- #define CCM_INTENSET_ENDCRYPT_Disabled (0UL)
- #define CCM_INTENSET_ENDCRYPT_Enabled (1UL)
- #define CCM_INTENSET_ENDCRYPT_Set (1UL)
- #define CCM_INTENSET_ENDKSGEN_Pos (0UL)
- #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos)
- #define CCM_INTENSET_ENDKSGEN_Disabled (0UL)
- #define CCM_INTENSET_ENDKSGEN_Enabled (1UL)
- #define CCM_INTENSET_ENDKSGEN_Set (1UL)
- #define CCM_INTENCLR_ERROR_Pos (2UL)
- #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos)
- #define CCM_INTENCLR_ERROR_Disabled (0UL)
- #define CCM_INTENCLR_ERROR_Enabled (1UL)
- #define CCM_INTENCLR_ERROR_Clear (1UL)
- #define CCM_INTENCLR_ENDCRYPT_Pos (1UL)
- #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos)
- #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL)
- #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL)
- #define CCM_INTENCLR_ENDCRYPT_Clear (1UL)
- #define CCM_INTENCLR_ENDKSGEN_Pos (0UL)
- #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos)
- #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL)
- #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL)
- #define CCM_INTENCLR_ENDKSGEN_Clear (1UL)
- #define CCM_MICSTATUS_MICSTATUS_Pos (0UL)
- #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos)
- #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL)
- #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL)
- #define CCM_ENABLE_ENABLE_Pos (0UL)
- #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos)
- #define CCM_ENABLE_ENABLE_Disabled (0UL)
- #define CCM_ENABLE_ENABLE_Enabled (2UL)
- #define CCM_MODE_LENGTH_Pos (24UL)
- #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos)
- #define CCM_MODE_LENGTH_Default (0UL)
- #define CCM_MODE_LENGTH_Extended (1UL)
- #define CCM_MODE_DATARATE_Pos (16UL)
- #define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos)
- #define CCM_MODE_DATARATE_1Mbit (0UL)
- #define CCM_MODE_DATARATE_2Mbit (1UL)
- #define CCM_MODE_DATARATE_125Kbps (2UL)
- #define CCM_MODE_DATARATE_500Kbps (3UL)
- #define CCM_MODE_MODE_Pos (0UL)
- #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos)
- #define CCM_MODE_MODE_Encryption (0UL)
- #define CCM_MODE_MODE_Decryption (1UL)
- #define CCM_CNFPTR_CNFPTR_Pos (0UL)
- #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos)
- #define CCM_INPTR_INPTR_Pos (0UL)
- #define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos)
- #define CCM_OUTPTR_OUTPTR_Pos (0UL)
- #define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos)
- #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL)
- #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos)
- #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL)
- #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos)
- #define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL)
- #define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos)
- #define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL)
- #define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL)
- #define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL)
- #define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL)
- #define CCM_HEADERMASK_HEADERMASK_Pos (0UL)
- #define CCM_HEADERMASK_HEADERMASK_Msk (0xFFUL << CCM_HEADERMASK_HEADERMASK_Pos)
- #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL)
- #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos)
- #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL)
- #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL)
- #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos)
- #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL)
- #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL)
- #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos)
- #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL)
- #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL)
- #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos)
- #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL)
- #define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL)
- #define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos)
- #define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos (31UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos)
- #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Disabled (0UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Enabled (1UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos (0UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos)
- #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos (31UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos)
- #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Disabled (0UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Enabled (1UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos (0UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos)
- #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos (31UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos)
- #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (1UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos (0UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos)
- #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos (31UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos)
- #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (1UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos (0UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos)
- #define CLOCK_SUBSCRIBE_CAL_EN_Pos (31UL)
- #define CLOCK_SUBSCRIBE_CAL_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_CAL_EN_Pos)
- #define CLOCK_SUBSCRIBE_CAL_EN_Disabled (0UL)
- #define CLOCK_SUBSCRIBE_CAL_EN_Enabled (1UL)
- #define CLOCK_SUBSCRIBE_CAL_CHIDX_Pos (0UL)
- #define CLOCK_SUBSCRIBE_CAL_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_CAL_CHIDX_Pos)
- #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL)
- #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos)
- #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL)
- #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL)
- #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL)
- #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos)
- #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL)
- #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL)
- #define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL)
- #define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos)
- #define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL)
- #define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL)
- #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos (31UL)
- #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos)
- #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Disabled (0UL)
- #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Enabled (1UL)
- #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos (0UL)
- #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos)
- #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos (31UL)
- #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos)
- #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Disabled (0UL)
- #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (1UL)
- #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos (0UL)
- #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos)
- #define CLOCK_PUBLISH_DONE_EN_Pos (31UL)
- #define CLOCK_PUBLISH_DONE_EN_Msk (0x1UL << CLOCK_PUBLISH_DONE_EN_Pos)
- #define CLOCK_PUBLISH_DONE_EN_Disabled (0UL)
- #define CLOCK_PUBLISH_DONE_EN_Enabled (1UL)
- #define CLOCK_PUBLISH_DONE_CHIDX_Pos (0UL)
- #define CLOCK_PUBLISH_DONE_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_DONE_CHIDX_Pos)
- #define CLOCK_INTEN_DONE_Pos (7UL)
- #define CLOCK_INTEN_DONE_Msk (0x1UL << CLOCK_INTEN_DONE_Pos)
- #define CLOCK_INTEN_DONE_Disabled (0UL)
- #define CLOCK_INTEN_DONE_Enabled (1UL)
- #define CLOCK_INTEN_LFCLKSTARTED_Pos (1UL)
- #define CLOCK_INTEN_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_LFCLKSTARTED_Pos)
- #define CLOCK_INTEN_LFCLKSTARTED_Disabled (0UL)
- #define CLOCK_INTEN_LFCLKSTARTED_Enabled (1UL)
- #define CLOCK_INTEN_HFCLKSTARTED_Pos (0UL)
- #define CLOCK_INTEN_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKSTARTED_Pos)
- #define CLOCK_INTEN_HFCLKSTARTED_Disabled (0UL)
- #define CLOCK_INTEN_HFCLKSTARTED_Enabled (1UL)
- #define CLOCK_INTENSET_DONE_Pos (7UL)
- #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos)
- #define CLOCK_INTENSET_DONE_Disabled (0UL)
- #define CLOCK_INTENSET_DONE_Enabled (1UL)
- #define CLOCK_INTENSET_DONE_Set (1UL)
- #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL)
- #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos)
- #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL)
- #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL)
- #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL)
- #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL)
- #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos)
- #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL)
- #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL)
- #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL)
- #define CLOCK_INTENCLR_DONE_Pos (7UL)
- #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos)
- #define CLOCK_INTENCLR_DONE_Disabled (0UL)
- #define CLOCK_INTENCLR_DONE_Enabled (1UL)
- #define CLOCK_INTENCLR_DONE_Clear (1UL)
- #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL)
- #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos)
- #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL)
- #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL)
- #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL)
- #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL)
- #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos)
- #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL)
- #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL)
- #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL)
- #define CLOCK_INTPEND_DONE_Pos (7UL)
- #define CLOCK_INTPEND_DONE_Msk (0x1UL << CLOCK_INTPEND_DONE_Pos)
- #define CLOCK_INTPEND_DONE_NotPending (0UL)
- #define CLOCK_INTPEND_DONE_Pending (1UL)
- #define CLOCK_INTPEND_LFCLKSTARTED_Pos (1UL)
- #define CLOCK_INTPEND_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_LFCLKSTARTED_Pos)
- #define CLOCK_INTPEND_LFCLKSTARTED_NotPending (0UL)
- #define CLOCK_INTPEND_LFCLKSTARTED_Pending (1UL)
- #define CLOCK_INTPEND_HFCLKSTARTED_Pos (0UL)
- #define CLOCK_INTPEND_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKSTARTED_Pos)
- #define CLOCK_INTPEND_HFCLKSTARTED_NotPending (0UL)
- #define CLOCK_INTPEND_HFCLKSTARTED_Pending (1UL)
- #define CLOCK_HFCLKRUN_STATUS_Pos (0UL)
- #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos)
- #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL)
- #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL)
- #define CLOCK_HFCLKSTAT_STATE_Pos (16UL)
- #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos)
- #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL)
- #define CLOCK_HFCLKSTAT_STATE_Running (1UL)
- #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Pos (4UL)
- #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_HFCLKSTAT_ALWAYSRUNNING_Pos)
- #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_NotRunning (0UL)
- #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Running (1UL)
- #define CLOCK_HFCLKSTAT_SRC_Pos (0UL)
- #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos)
- #define CLOCK_HFCLKSTAT_SRC_HFINT (0UL)
- #define CLOCK_HFCLKSTAT_SRC_HFXO (1UL)
- #define CLOCK_LFCLKRUN_STATUS_Pos (0UL)
- #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos)
- #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL)
- #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL)
- #define CLOCK_LFCLKSTAT_STATE_Pos (16UL)
- #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos)
- #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL)
- #define CLOCK_LFCLKSTAT_STATE_Running (1UL)
- #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos (4UL)
- #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos)
- #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_NotRunning (0UL)
- #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Running (1UL)
- #define CLOCK_LFCLKSTAT_SRC_Pos (0UL)
- #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos)
- #define CLOCK_LFCLKSTAT_SRC_LFULP (0UL)
- #define CLOCK_LFCLKSTAT_SRC_LFRC (1UL)
- #define CLOCK_LFCLKSTAT_SRC_LFXO (2UL)
- #define CLOCK_LFCLKSTAT_SRC_LFSYNT (3UL)
- #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL)
- #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos)
- #define CLOCK_LFCLKSRCCOPY_SRC_LFULP (0UL)
- #define CLOCK_LFCLKSRCCOPY_SRC_LFRC (1UL)
- #define CLOCK_LFCLKSRCCOPY_SRC_LFXO (2UL)
- #define CLOCK_LFCLKSRCCOPY_SRC_LFSYNT (3UL)
- #define CLOCK_HFCLKSRC_SRC_Pos (0UL)
- #define CLOCK_HFCLKSRC_SRC_Msk (0x1UL << CLOCK_HFCLKSRC_SRC_Pos)
- #define CLOCK_HFCLKSRC_SRC_HFINT (0UL)
- #define CLOCK_HFCLKSRC_SRC_HFXO (1UL)
- #define CLOCK_LFCLKSRC_SRC_Pos (0UL)
- #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos)
- #define CLOCK_LFCLKSRC_SRC_LFULP (0UL)
- #define CLOCK_LFCLKSRC_SRC_LFRC (1UL)
- #define CLOCK_LFCLKSRC_SRC_LFXO (2UL)
- #define CLOCK_LFCLKSRC_SRC_LFSYNT (3UL)
- #define CLOCK_HFCLKCTRL_HCLK_Pos (0UL)
- #define CLOCK_HFCLKCTRL_HCLK_Msk (0x3UL << CLOCK_HFCLKCTRL_HCLK_Pos)
- #define CLOCK_HFCLKCTRL_HCLK_Div1 (0UL)
- #define CLOCK_HFCLKCTRL_HCLK_Div2 (1UL)
- #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos (0UL)
- #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos)
- #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Automatic (0UL)
- #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL)
- #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos (0UL)
- #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos)
- #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Automatic (0UL)
- #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL)
- #define CTI_CTICONTROL_GLBEN_Pos (0UL)
- #define CTI_CTICONTROL_GLBEN_Msk (0x1UL << CTI_CTICONTROL_GLBEN_Pos)
- #define CTI_CTICONTROL_GLBEN_Disabled (0UL)
- #define CTI_CTICONTROL_GLBEN_Enabled (1UL)
- #define CTI_CTIINTACK_UNUSED5_Pos (7UL)
- #define CTI_CTIINTACK_UNUSED5_Msk (0x1UL << CTI_CTIINTACK_UNUSED5_Pos)
- #define CTI_CTIINTACK_UNUSED5_Acknowledge (1UL)
- #define CTI_CTIINTACK_UNUSED4_Pos (6UL)
- #define CTI_CTIINTACK_UNUSED4_Msk (0x1UL << CTI_CTIINTACK_UNUSED4_Pos)
- #define CTI_CTIINTACK_UNUSED4_Acknowledge (1UL)
- #define CTI_CTIINTACK_UNUSED3_Pos (5UL)
- #define CTI_CTIINTACK_UNUSED3_Msk (0x1UL << CTI_CTIINTACK_UNUSED3_Pos)
- #define CTI_CTIINTACK_UNUSED3_Acknowledge (1UL)
- #define CTI_CTIINTACK_UNUSED2_Pos (4UL)
- #define CTI_CTIINTACK_UNUSED2_Msk (0x1UL << CTI_CTIINTACK_UNUSED2_Pos)
- #define CTI_CTIINTACK_UNUSED2_Acknowledge (1UL)
- #define CTI_CTIINTACK_UNUSED1_Pos (3UL)
- #define CTI_CTIINTACK_UNUSED1_Msk (0x1UL << CTI_CTIINTACK_UNUSED1_Pos)
- #define CTI_CTIINTACK_UNUSED1_Acknowledge (1UL)
- #define CTI_CTIINTACK_UNUSED0_Pos (2UL)
- #define CTI_CTIINTACK_UNUSED0_Msk (0x1UL << CTI_CTIINTACK_UNUSED0_Pos)
- #define CTI_CTIINTACK_UNUSED0_Acknowledge (1UL)
- #define CTI_CTIINTACK_CPURESTART_Pos (1UL)
- #define CTI_CTIINTACK_CPURESTART_Msk (0x1UL << CTI_CTIINTACK_CPURESTART_Pos)
- #define CTI_CTIINTACK_CPURESTART_Acknowledge (1UL)
- #define CTI_CTIINTACK_DEBUGREQ_Pos (0UL)
- #define CTI_CTIINTACK_DEBUGREQ_Msk (0x1UL << CTI_CTIINTACK_DEBUGREQ_Pos)
- #define CTI_CTIINTACK_DEBUGREQ_Acknowledge (1UL)
- #define CTI_CTIAPPSET_APPSET_3_Pos (3UL)
- #define CTI_CTIAPPSET_APPSET_3_Msk (0x1UL << CTI_CTIAPPSET_APPSET_3_Pos)
- #define CTI_CTIAPPSET_APPSET_3_Inactive (0UL)
- #define CTI_CTIAPPSET_APPSET_3_Active (1UL)
- #define CTI_CTIAPPSET_APPSET_3_Activate (1UL)
- #define CTI_CTIAPPSET_APPSET_2_Pos (2UL)
- #define CTI_CTIAPPSET_APPSET_2_Msk (0x1UL << CTI_CTIAPPSET_APPSET_2_Pos)
- #define CTI_CTIAPPSET_APPSET_2_Inactive (0UL)
- #define CTI_CTIAPPSET_APPSET_2_Active (1UL)
- #define CTI_CTIAPPSET_APPSET_2_Activate (1UL)
- #define CTI_CTIAPPSET_APPSET_1_Pos (1UL)
- #define CTI_CTIAPPSET_APPSET_1_Msk (0x1UL << CTI_CTIAPPSET_APPSET_1_Pos)
- #define CTI_CTIAPPSET_APPSET_1_Inactive (0UL)
- #define CTI_CTIAPPSET_APPSET_1_Active (1UL)
- #define CTI_CTIAPPSET_APPSET_1_Activate (1UL)
- #define CTI_CTIAPPSET_APPSET_0_Pos (0UL)
- #define CTI_CTIAPPSET_APPSET_0_Msk (0x1UL << CTI_CTIAPPSET_APPSET_0_Pos)
- #define CTI_CTIAPPSET_APPSET_0_Inactive (0UL)
- #define CTI_CTIAPPSET_APPSET_0_Active (1UL)
- #define CTI_CTIAPPSET_APPSET_0_Activate (1UL)
- #define CTI_CTIAPPCLEAR_APPCLEAR_3_Pos (3UL)
- #define CTI_CTIAPPCLEAR_APPCLEAR_3_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_3_Pos)
- #define CTI_CTIAPPCLEAR_APPCLEAR_3_Clear (1UL)
- #define CTI_CTIAPPCLEAR_APPCLEAR_2_Pos (2UL)
- #define CTI_CTIAPPCLEAR_APPCLEAR_2_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_2_Pos)
- #define CTI_CTIAPPCLEAR_APPCLEAR_2_Clear (1UL)
- #define CTI_CTIAPPCLEAR_APPCLEAR_1_Pos (1UL)
- #define CTI_CTIAPPCLEAR_APPCLEAR_1_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_1_Pos)
- #define CTI_CTIAPPCLEAR_APPCLEAR_1_Clear (1UL)
- #define CTI_CTIAPPCLEAR_APPCLEAR_0_Pos (0UL)
- #define CTI_CTIAPPCLEAR_APPCLEAR_0_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_0_Pos)
- #define CTI_CTIAPPCLEAR_APPCLEAR_0_Clear (1UL)
- #define CTI_CTIAPPPULSE_APPULSE_3_Pos (3UL)
- #define CTI_CTIAPPPULSE_APPULSE_3_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_3_Pos)
- #define CTI_CTIAPPPULSE_APPULSE_3_Generate (1UL)
- #define CTI_CTIAPPPULSE_APPULSE_2_Pos (2UL)
- #define CTI_CTIAPPPULSE_APPULSE_2_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_2_Pos)
- #define CTI_CTIAPPPULSE_APPULSE_2_Generate (1UL)
- #define CTI_CTIAPPPULSE_APPULSE_1_Pos (1UL)
- #define CTI_CTIAPPPULSE_APPULSE_1_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_1_Pos)
- #define CTI_CTIAPPPULSE_APPULSE_1_Generate (1UL)
- #define CTI_CTIAPPPULSE_APPULSE_0_Pos (0UL)
- #define CTI_CTIAPPPULSE_APPULSE_0_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_0_Pos)
- #define CTI_CTIAPPPULSE_APPULSE_0_Generate (1UL)
- #define CTI_CTIINEN_TRIGINEN_3_Pos (3UL)
- #define CTI_CTIINEN_TRIGINEN_3_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_3_Pos)
- #define CTI_CTIINEN_TRIGINEN_3_Disabled (0UL)
- #define CTI_CTIINEN_TRIGINEN_3_Enabled (1UL)
- #define CTI_CTIINEN_TRIGINEN_2_Pos (2UL)
- #define CTI_CTIINEN_TRIGINEN_2_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_2_Pos)
- #define CTI_CTIINEN_TRIGINEN_2_Disabled (0UL)
- #define CTI_CTIINEN_TRIGINEN_2_Enabled (1UL)
- #define CTI_CTIINEN_TRIGINEN_1_Pos (1UL)
- #define CTI_CTIINEN_TRIGINEN_1_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_1_Pos)
- #define CTI_CTIINEN_TRIGINEN_1_Disabled (0UL)
- #define CTI_CTIINEN_TRIGINEN_1_Enabled (1UL)
- #define CTI_CTIINEN_TRIGINEN_0_Pos (0UL)
- #define CTI_CTIINEN_TRIGINEN_0_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_0_Pos)
- #define CTI_CTIINEN_TRIGINEN_0_Disabled (0UL)
- #define CTI_CTIINEN_TRIGINEN_0_Enabled (1UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_3_Pos (3UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_3_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_3_Pos)
- #define CTI_CTIOUTEN_TRIGOUTEN_3_Disabled (0UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_3_Enabled (1UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_2_Pos (2UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_2_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_2_Pos)
- #define CTI_CTIOUTEN_TRIGOUTEN_2_Disabled (0UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_2_Enabled (1UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_1_Pos (1UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_1_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_1_Pos)
- #define CTI_CTIOUTEN_TRIGOUTEN_1_Disabled (0UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_1_Enabled (1UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_0_Pos (0UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_0_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_0_Pos)
- #define CTI_CTIOUTEN_TRIGOUTEN_0_Disabled (0UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_0_Enabled (1UL)
- #define CTI_CTITRIGINSTATUS_UNUSED3_Pos (7UL)
- #define CTI_CTITRIGINSTATUS_UNUSED3_Msk (0x1UL << CTI_CTITRIGINSTATUS_UNUSED3_Pos)
- #define CTI_CTITRIGINSTATUS_UNUSED3_Inactive (0UL)
- #define CTI_CTITRIGINSTATUS_UNUSED3_Active (1UL)
- #define CTI_CTITRIGINSTATUS_UNUSED2_Pos (6UL)
- #define CTI_CTITRIGINSTATUS_UNUSED2_Msk (0x1UL << CTI_CTITRIGINSTATUS_UNUSED2_Pos)
- #define CTI_CTITRIGINSTATUS_UNUSED2_Inactive (0UL)
- #define CTI_CTITRIGINSTATUS_UNUSED2_Active (1UL)
- #define CTI_CTITRIGINSTATUS_UNUSED1_Pos (5UL)
- #define CTI_CTITRIGINSTATUS_UNUSED1_Msk (0x1UL << CTI_CTITRIGINSTATUS_UNUSED1_Pos)
- #define CTI_CTITRIGINSTATUS_UNUSED1_Inactive (0UL)
- #define CTI_CTITRIGINSTATUS_UNUSED1_Active (1UL)
- #define CTI_CTITRIGINSTATUS_UNUSED0_Pos (4UL)
- #define CTI_CTITRIGINSTATUS_UNUSED0_Msk (0x1UL << CTI_CTITRIGINSTATUS_UNUSED0_Pos)
- #define CTI_CTITRIGINSTATUS_UNUSED0_Inactive (0UL)
- #define CTI_CTITRIGINSTATUS_UNUSED0_Active (1UL)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Pos (3UL)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Msk (0x1UL << CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Pos)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Inactive (0UL)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Active (1UL)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Pos (2UL)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Msk (0x1UL << CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Pos)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Inactive (0UL)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Active (1UL)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Pos (1UL)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Msk (0x1UL << CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Pos)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Inactive (0UL)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Active (1UL)
- #define CTI_CTITRIGINSTATUS_CPUHALTED_Pos (0UL)
- #define CTI_CTITRIGINSTATUS_CPUHALTED_Msk (0x1UL << CTI_CTITRIGINSTATUS_CPUHALTED_Pos)
- #define CTI_CTITRIGINSTATUS_CPUHALTED_Inactive (0UL)
- #define CTI_CTITRIGINSTATUS_CPUHALTED_Active (1UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED5_Pos (7UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED5_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED5_Pos)
- #define CTI_CTITRIGOUTSTATUS_UNUSED5_Inactive (0UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED5_Active (1UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED4_Pos (6UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED4_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED4_Pos)
- #define CTI_CTITRIGOUTSTATUS_UNUSED4_Inactive (0UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED4_Active (1UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED3_Pos (5UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED3_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED3_Pos)
- #define CTI_CTITRIGOUTSTATUS_UNUSED3_Inactive (0UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED3_Active (1UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED2_Pos (4UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED2_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED2_Pos)
- #define CTI_CTITRIGOUTSTATUS_UNUSED2_Inactive (0UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED2_Active (1UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED1_Pos (3UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED1_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED1_Pos)
- #define CTI_CTITRIGOUTSTATUS_UNUSED1_Inactive (0UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED1_Active (1UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED0_Pos (2UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED0_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED0_Pos)
- #define CTI_CTITRIGOUTSTATUS_UNUSED0_Inactive (0UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED0_Active (1UL)
- #define CTI_CTITRIGOUTSTATUS_CPURESTART_Pos (1UL)
- #define CTI_CTITRIGOUTSTATUS_CPURESTART_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_CPURESTART_Pos)
- #define CTI_CTITRIGOUTSTATUS_CPURESTART_Inactive (0UL)
- #define CTI_CTITRIGOUTSTATUS_CPURESTART_Active (1UL)
- #define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Pos (0UL)
- #define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_DEBUGREQ_Pos)
- #define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Inactive (0UL)
- #define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Active (1UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Pos (3UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_3_Pos)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Inactive (0UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Active (1UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Pos (2UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_2_Pos)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Inactive (0UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Active (1UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Pos (1UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_1_Pos)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Inactive (0UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Active (1UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Pos (0UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_0_Pos)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Inactive (0UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Active (1UL)
- #define CTI_CTIGATE_CTIGATEEN_3_Pos (3UL)
- #define CTI_CTIGATE_CTIGATEEN_3_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_3_Pos)
- #define CTI_CTIGATE_CTIGATEEN_3_Disabled (0UL)
- #define CTI_CTIGATE_CTIGATEEN_3_Enabled (1UL)
- #define CTI_CTIGATE_CTIGATEEN_2_Pos (2UL)
- #define CTI_CTIGATE_CTIGATEEN_2_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_2_Pos)
- #define CTI_CTIGATE_CTIGATEEN_2_Disabled (0UL)
- #define CTI_CTIGATE_CTIGATEEN_2_Enabled (1UL)
- #define CTI_CTIGATE_CTIGATEEN_1_Pos (1UL)
- #define CTI_CTIGATE_CTIGATEEN_1_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_1_Pos)
- #define CTI_CTIGATE_CTIGATEEN_1_Disabled (0UL)
- #define CTI_CTIGATE_CTIGATEEN_1_Enabled (1UL)
- #define CTI_CTIGATE_CTIGATEEN_0_Pos (0UL)
- #define CTI_CTIGATE_CTIGATEEN_0_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_0_Pos)
- #define CTI_CTIGATE_CTIGATEEN_0_Disabled (0UL)
- #define CTI_CTIGATE_CTIGATEEN_0_Enabled (1UL)
- #define CTI_DEVARCH_Architecture_Pos (0UL)
- #define CTI_DEVARCH_Architecture_Msk (0x1UL << CTI_DEVARCH_Architecture_Pos)
- #define CTI_DEVID_NUMCH_Pos (16UL)
- #define CTI_DEVID_NUMCH_Msk (0xFUL << CTI_DEVID_NUMCH_Pos)
- #define CTI_DEVID_NUMTRIG_Pos (8UL)
- #define CTI_DEVID_NUMTRIG_Msk (0xFFUL << CTI_DEVID_NUMTRIG_Pos)
- #define CTI_DEVID_EXTMUXNUM_Pos (0UL)
- #define CTI_DEVID_EXTMUXNUM_Msk (0x1FUL << CTI_DEVID_EXTMUXNUM_Pos)
- #define CTI_DEVTYPE_SUB_Pos (4UL)
- #define CTI_DEVTYPE_SUB_Msk (0xFUL << CTI_DEVTYPE_SUB_Pos)
- #define CTI_DEVTYPE_SUB_Crosstrigger (0b0001UL)
- #define CTI_DEVTYPE_MAJOR_Pos (0UL)
- #define CTI_DEVTYPE_MAJOR_Msk (0xFUL << CTI_DEVTYPE_MAJOR_Pos)
- #define CTI_DEVTYPE_MAJOR_Controller (0b0100UL)
- #define CTI_PIDR4_SIZE_Pos (4UL)
- #define CTI_PIDR4_SIZE_Msk (0xFUL << CTI_PIDR4_SIZE_Pos)
- #define CTI_PIDR4_DES_2_Pos (0UL)
- #define CTI_PIDR4_DES_2_Msk (0xFUL << CTI_PIDR4_DES_2_Pos)
- #define CTI_PIDR4_DES_2_Code (0b0100UL)
- #define CTI_PIDR0_PART_0_Pos (0UL)
- #define CTI_PIDR0_PART_0_Msk (0xFFUL << CTI_PIDR0_PART_0_Pos)
- #define CTI_PIDR0_PART_0_PartnumberL (0x21UL)
- #define CTI_PIDR1_DES_0_Pos (4UL)
- #define CTI_PIDR1_DES_0_Msk (0xFUL << CTI_PIDR1_DES_0_Pos)
- #define CTI_PIDR1_DES_0_Arm (0b1011UL)
- #define CTI_PIDR1_PART_1_Pos (0UL)
- #define CTI_PIDR1_PART_1_Msk (0xFUL << CTI_PIDR1_PART_1_Pos)
- #define CTI_PIDR1_PART_1_PartnumberH (0b1101UL)
- #define CTI_PIDR2_REVISION_Pos (4UL)
- #define CTI_PIDR2_REVISION_Msk (0xFUL << CTI_PIDR2_REVISION_Pos)
- #define CTI_PIDR2_REVISION_Rev0p0 (0b0000UL)
- #define CTI_PIDR2_JEDEC_Pos (3UL)
- #define CTI_PIDR2_JEDEC_Msk (0x1UL << CTI_PIDR2_JEDEC_Pos)
- #define CTI_PIDR2_DES_1_Pos (0UL)
- #define CTI_PIDR2_DES_1_Msk (0x7UL << CTI_PIDR2_DES_1_Pos)
- #define CTI_PIDR2_DES_1_Arm (0b011UL)
- #define CTI_PIDR3_REVAND_Pos (4UL)
- #define CTI_PIDR3_REVAND_Msk (0xFUL << CTI_PIDR3_REVAND_Pos)
- #define CTI_PIDR3_REVAND_NoErrata (0b000UL)
- #define CTI_PIDR3_CMOD_Pos (0UL)
- #define CTI_PIDR3_CMOD_Msk (0xFUL << CTI_PIDR3_CMOD_Pos)
- #define CTI_PIDR3_CMOD_Unmodified (0b000UL)
- #define CTI_CIDR0_PRMBL_0_Pos (0UL)
- #define CTI_CIDR0_PRMBL_0_Msk (0xFFUL << CTI_CIDR0_PRMBL_0_Pos)
- #define CTI_CIDR0_PRMBL_0_Value (0x0DUL)
- #define CTI_CIDR1_CLASS_Pos (4UL)
- #define CTI_CIDR1_CLASS_Msk (0xFUL << CTI_CIDR1_CLASS_Pos)
- #define CTI_CIDR1_CLASS_Coresight (0b1001UL)
- #define CTI_CIDR1_PRMBL_1_Pos (0UL)
- #define CTI_CIDR1_PRMBL_1_Msk (0xFUL << CTI_CIDR1_PRMBL_1_Pos)
- #define CTI_CIDR1_PRMBL_1_Value (0b0000UL)
- #define CTI_CIDR2_PRMBL_2_Pos (0UL)
- #define CTI_CIDR2_PRMBL_2_Msk (0xFFUL << CTI_CIDR2_PRMBL_2_Pos)
- #define CTI_CIDR2_PRMBL_2_Value (0x05UL)
- #define CTI_CIDR3_PRMBL_3_Pos (0UL)
- #define CTI_CIDR3_PRMBL_3_Msk (0xFFUL << CTI_CIDR3_PRMBL_3_Pos)
- #define CTI_CIDR3_PRMBL_3_Value (0xB1UL)
- #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos (0UL)
- #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos)
- #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos (0UL)
- #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos)
- #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_NoDataPending (0UL)
- #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (1UL)
- #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos (0UL)
- #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos)
- #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos (0UL)
- #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos)
- #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_NoDataPending (0UL)
- #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (1UL)
- #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos (0UL)
- #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos)
- #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked (0UL)
- #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked (1UL)
- #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos (0UL)
- #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos)
- #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Pos (0UL)
- #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_APPROTECT_LOCK_LOCK_Pos)
- #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Unlocked (0UL)
- #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Locked (1UL)
- #define CTRLAPPERI_APPROTECT_DISABLE_KEY_Pos (0UL)
- #define CTRLAPPERI_APPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_APPROTECT_DISABLE_KEY_Pos)
- #define CTRLAPPERI_STATUS_DBGIFACEMODE_Pos (2UL)
- #define CTRLAPPERI_STATUS_DBGIFACEMODE_Msk (0x1UL << CTRLAPPERI_STATUS_DBGIFACEMODE_Pos)
- #define CTRLAPPERI_STATUS_DBGIFACEMODE_Disabled (0UL)
- #define CTRLAPPERI_STATUS_DBGIFACEMODE_Enabled (1UL)
- #define CTRLAPPERI_STATUS_APPROTECT_Pos (0UL)
- #define CTRLAPPERI_STATUS_APPROTECT_Msk (0x1UL << CTRLAPPERI_STATUS_APPROTECT_Pos)
- #define CTRLAPPERI_STATUS_APPROTECT_Disabled (0UL)
- #define CTRLAPPERI_STATUS_APPROTECT_Enabled (1UL)
- #define DCNF_CPUID_CPUID_Pos (0UL)
- #define DCNF_CPUID_CPUID_Msk (0xFFUL << DCNF_CPUID_CPUID_Pos)
- #define DPPIC_TASKS_CHG_EN_EN_Pos (0UL)
- #define DPPIC_TASKS_CHG_EN_EN_Msk (0x1UL << DPPIC_TASKS_CHG_EN_EN_Pos)
- #define DPPIC_TASKS_CHG_EN_EN_Trigger (1UL)
- #define DPPIC_TASKS_CHG_DIS_DIS_Pos (0UL)
- #define DPPIC_TASKS_CHG_DIS_DIS_Msk (0x1UL << DPPIC_TASKS_CHG_DIS_DIS_Pos)
- #define DPPIC_TASKS_CHG_DIS_DIS_Trigger (1UL)
- #define DPPIC_SUBSCRIBE_CHG_EN_EN_Pos (31UL)
- #define DPPIC_SUBSCRIBE_CHG_EN_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_EN_EN_Pos)
- #define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0UL)
- #define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (1UL)
- #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL)
- #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos)
- #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos (31UL)
- #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos)
- #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0UL)
- #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (1UL)
- #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL)
- #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos)
- #define DPPIC_CHEN_CH15_Pos (15UL)
- #define DPPIC_CHEN_CH15_Msk (0x1UL << DPPIC_CHEN_CH15_Pos)
- #define DPPIC_CHEN_CH15_Disabled (0UL)
- #define DPPIC_CHEN_CH15_Enabled (1UL)
- #define DPPIC_CHEN_CH14_Pos (14UL)
- #define DPPIC_CHEN_CH14_Msk (0x1UL << DPPIC_CHEN_CH14_Pos)
- #define DPPIC_CHEN_CH14_Disabled (0UL)
- #define DPPIC_CHEN_CH14_Enabled (1UL)
- #define DPPIC_CHEN_CH13_Pos (13UL)
- #define DPPIC_CHEN_CH13_Msk (0x1UL << DPPIC_CHEN_CH13_Pos)
- #define DPPIC_CHEN_CH13_Disabled (0UL)
- #define DPPIC_CHEN_CH13_Enabled (1UL)
- #define DPPIC_CHEN_CH12_Pos (12UL)
- #define DPPIC_CHEN_CH12_Msk (0x1UL << DPPIC_CHEN_CH12_Pos)
- #define DPPIC_CHEN_CH12_Disabled (0UL)
- #define DPPIC_CHEN_CH12_Enabled (1UL)
- #define DPPIC_CHEN_CH11_Pos (11UL)
- #define DPPIC_CHEN_CH11_Msk (0x1UL << DPPIC_CHEN_CH11_Pos)
- #define DPPIC_CHEN_CH11_Disabled (0UL)
- #define DPPIC_CHEN_CH11_Enabled (1UL)
- #define DPPIC_CHEN_CH10_Pos (10UL)
- #define DPPIC_CHEN_CH10_Msk (0x1UL << DPPIC_CHEN_CH10_Pos)
- #define DPPIC_CHEN_CH10_Disabled (0UL)
- #define DPPIC_CHEN_CH10_Enabled (1UL)
- #define DPPIC_CHEN_CH9_Pos (9UL)
- #define DPPIC_CHEN_CH9_Msk (0x1UL << DPPIC_CHEN_CH9_Pos)
- #define DPPIC_CHEN_CH9_Disabled (0UL)
- #define DPPIC_CHEN_CH9_Enabled (1UL)
- #define DPPIC_CHEN_CH8_Pos (8UL)
- #define DPPIC_CHEN_CH8_Msk (0x1UL << DPPIC_CHEN_CH8_Pos)
- #define DPPIC_CHEN_CH8_Disabled (0UL)
- #define DPPIC_CHEN_CH8_Enabled (1UL)
- #define DPPIC_CHEN_CH7_Pos (7UL)
- #define DPPIC_CHEN_CH7_Msk (0x1UL << DPPIC_CHEN_CH7_Pos)
- #define DPPIC_CHEN_CH7_Disabled (0UL)
- #define DPPIC_CHEN_CH7_Enabled (1UL)
- #define DPPIC_CHEN_CH6_Pos (6UL)
- #define DPPIC_CHEN_CH6_Msk (0x1UL << DPPIC_CHEN_CH6_Pos)
- #define DPPIC_CHEN_CH6_Disabled (0UL)
- #define DPPIC_CHEN_CH6_Enabled (1UL)
- #define DPPIC_CHEN_CH5_Pos (5UL)
- #define DPPIC_CHEN_CH5_Msk (0x1UL << DPPIC_CHEN_CH5_Pos)
- #define DPPIC_CHEN_CH5_Disabled (0UL)
- #define DPPIC_CHEN_CH5_Enabled (1UL)
- #define DPPIC_CHEN_CH4_Pos (4UL)
- #define DPPIC_CHEN_CH4_Msk (0x1UL << DPPIC_CHEN_CH4_Pos)
- #define DPPIC_CHEN_CH4_Disabled (0UL)
- #define DPPIC_CHEN_CH4_Enabled (1UL)
- #define DPPIC_CHEN_CH3_Pos (3UL)
- #define DPPIC_CHEN_CH3_Msk (0x1UL << DPPIC_CHEN_CH3_Pos)
- #define DPPIC_CHEN_CH3_Disabled (0UL)
- #define DPPIC_CHEN_CH3_Enabled (1UL)
- #define DPPIC_CHEN_CH2_Pos (2UL)
- #define DPPIC_CHEN_CH2_Msk (0x1UL << DPPIC_CHEN_CH2_Pos)
- #define DPPIC_CHEN_CH2_Disabled (0UL)
- #define DPPIC_CHEN_CH2_Enabled (1UL)
- #define DPPIC_CHEN_CH1_Pos (1UL)
- #define DPPIC_CHEN_CH1_Msk (0x1UL << DPPIC_CHEN_CH1_Pos)
- #define DPPIC_CHEN_CH1_Disabled (0UL)
- #define DPPIC_CHEN_CH1_Enabled (1UL)
- #define DPPIC_CHEN_CH0_Pos (0UL)
- #define DPPIC_CHEN_CH0_Msk (0x1UL << DPPIC_CHEN_CH0_Pos)
- #define DPPIC_CHEN_CH0_Disabled (0UL)
- #define DPPIC_CHEN_CH0_Enabled (1UL)
- #define DPPIC_CHENSET_CH15_Pos (15UL)
- #define DPPIC_CHENSET_CH15_Msk (0x1UL << DPPIC_CHENSET_CH15_Pos)
- #define DPPIC_CHENSET_CH15_Disabled (0UL)
- #define DPPIC_CHENSET_CH15_Enabled (1UL)
- #define DPPIC_CHENSET_CH15_Set (1UL)
- #define DPPIC_CHENSET_CH14_Pos (14UL)
- #define DPPIC_CHENSET_CH14_Msk (0x1UL << DPPIC_CHENSET_CH14_Pos)
- #define DPPIC_CHENSET_CH14_Disabled (0UL)
- #define DPPIC_CHENSET_CH14_Enabled (1UL)
- #define DPPIC_CHENSET_CH14_Set (1UL)
- #define DPPIC_CHENSET_CH13_Pos (13UL)
- #define DPPIC_CHENSET_CH13_Msk (0x1UL << DPPIC_CHENSET_CH13_Pos)
- #define DPPIC_CHENSET_CH13_Disabled (0UL)
- #define DPPIC_CHENSET_CH13_Enabled (1UL)
- #define DPPIC_CHENSET_CH13_Set (1UL)
- #define DPPIC_CHENSET_CH12_Pos (12UL)
- #define DPPIC_CHENSET_CH12_Msk (0x1UL << DPPIC_CHENSET_CH12_Pos)
- #define DPPIC_CHENSET_CH12_Disabled (0UL)
- #define DPPIC_CHENSET_CH12_Enabled (1UL)
- #define DPPIC_CHENSET_CH12_Set (1UL)
- #define DPPIC_CHENSET_CH11_Pos (11UL)
- #define DPPIC_CHENSET_CH11_Msk (0x1UL << DPPIC_CHENSET_CH11_Pos)
- #define DPPIC_CHENSET_CH11_Disabled (0UL)
- #define DPPIC_CHENSET_CH11_Enabled (1UL)
- #define DPPIC_CHENSET_CH11_Set (1UL)
- #define DPPIC_CHENSET_CH10_Pos (10UL)
- #define DPPIC_CHENSET_CH10_Msk (0x1UL << DPPIC_CHENSET_CH10_Pos)
- #define DPPIC_CHENSET_CH10_Disabled (0UL)
- #define DPPIC_CHENSET_CH10_Enabled (1UL)
- #define DPPIC_CHENSET_CH10_Set (1UL)
- #define DPPIC_CHENSET_CH9_Pos (9UL)
- #define DPPIC_CHENSET_CH9_Msk (0x1UL << DPPIC_CHENSET_CH9_Pos)
- #define DPPIC_CHENSET_CH9_Disabled (0UL)
- #define DPPIC_CHENSET_CH9_Enabled (1UL)
- #define DPPIC_CHENSET_CH9_Set (1UL)
- #define DPPIC_CHENSET_CH8_Pos (8UL)
- #define DPPIC_CHENSET_CH8_Msk (0x1UL << DPPIC_CHENSET_CH8_Pos)
- #define DPPIC_CHENSET_CH8_Disabled (0UL)
- #define DPPIC_CHENSET_CH8_Enabled (1UL)
- #define DPPIC_CHENSET_CH8_Set (1UL)
- #define DPPIC_CHENSET_CH7_Pos (7UL)
- #define DPPIC_CHENSET_CH7_Msk (0x1UL << DPPIC_CHENSET_CH7_Pos)
- #define DPPIC_CHENSET_CH7_Disabled (0UL)
- #define DPPIC_CHENSET_CH7_Enabled (1UL)
- #define DPPIC_CHENSET_CH7_Set (1UL)
- #define DPPIC_CHENSET_CH6_Pos (6UL)
- #define DPPIC_CHENSET_CH6_Msk (0x1UL << DPPIC_CHENSET_CH6_Pos)
- #define DPPIC_CHENSET_CH6_Disabled (0UL)
- #define DPPIC_CHENSET_CH6_Enabled (1UL)
- #define DPPIC_CHENSET_CH6_Set (1UL)
- #define DPPIC_CHENSET_CH5_Pos (5UL)
- #define DPPIC_CHENSET_CH5_Msk (0x1UL << DPPIC_CHENSET_CH5_Pos)
- #define DPPIC_CHENSET_CH5_Disabled (0UL)
- #define DPPIC_CHENSET_CH5_Enabled (1UL)
- #define DPPIC_CHENSET_CH5_Set (1UL)
- #define DPPIC_CHENSET_CH4_Pos (4UL)
- #define DPPIC_CHENSET_CH4_Msk (0x1UL << DPPIC_CHENSET_CH4_Pos)
- #define DPPIC_CHENSET_CH4_Disabled (0UL)
- #define DPPIC_CHENSET_CH4_Enabled (1UL)
- #define DPPIC_CHENSET_CH4_Set (1UL)
- #define DPPIC_CHENSET_CH3_Pos (3UL)
- #define DPPIC_CHENSET_CH3_Msk (0x1UL << DPPIC_CHENSET_CH3_Pos)
- #define DPPIC_CHENSET_CH3_Disabled (0UL)
- #define DPPIC_CHENSET_CH3_Enabled (1UL)
- #define DPPIC_CHENSET_CH3_Set (1UL)
- #define DPPIC_CHENSET_CH2_Pos (2UL)
- #define DPPIC_CHENSET_CH2_Msk (0x1UL << DPPIC_CHENSET_CH2_Pos)
- #define DPPIC_CHENSET_CH2_Disabled (0UL)
- #define DPPIC_CHENSET_CH2_Enabled (1UL)
- #define DPPIC_CHENSET_CH2_Set (1UL)
- #define DPPIC_CHENSET_CH1_Pos (1UL)
- #define DPPIC_CHENSET_CH1_Msk (0x1UL << DPPIC_CHENSET_CH1_Pos)
- #define DPPIC_CHENSET_CH1_Disabled (0UL)
- #define DPPIC_CHENSET_CH1_Enabled (1UL)
- #define DPPIC_CHENSET_CH1_Set (1UL)
- #define DPPIC_CHENSET_CH0_Pos (0UL)
- #define DPPIC_CHENSET_CH0_Msk (0x1UL << DPPIC_CHENSET_CH0_Pos)
- #define DPPIC_CHENSET_CH0_Disabled (0UL)
- #define DPPIC_CHENSET_CH0_Enabled (1UL)
- #define DPPIC_CHENSET_CH0_Set (1UL)
- #define DPPIC_CHENCLR_CH15_Pos (15UL)
- #define DPPIC_CHENCLR_CH15_Msk (0x1UL << DPPIC_CHENCLR_CH15_Pos)
- #define DPPIC_CHENCLR_CH15_Disabled (0UL)
- #define DPPIC_CHENCLR_CH15_Enabled (1UL)
- #define DPPIC_CHENCLR_CH15_Clear (1UL)
- #define DPPIC_CHENCLR_CH14_Pos (14UL)
- #define DPPIC_CHENCLR_CH14_Msk (0x1UL << DPPIC_CHENCLR_CH14_Pos)
- #define DPPIC_CHENCLR_CH14_Disabled (0UL)
- #define DPPIC_CHENCLR_CH14_Enabled (1UL)
- #define DPPIC_CHENCLR_CH14_Clear (1UL)
- #define DPPIC_CHENCLR_CH13_Pos (13UL)
- #define DPPIC_CHENCLR_CH13_Msk (0x1UL << DPPIC_CHENCLR_CH13_Pos)
- #define DPPIC_CHENCLR_CH13_Disabled (0UL)
- #define DPPIC_CHENCLR_CH13_Enabled (1UL)
- #define DPPIC_CHENCLR_CH13_Clear (1UL)
- #define DPPIC_CHENCLR_CH12_Pos (12UL)
- #define DPPIC_CHENCLR_CH12_Msk (0x1UL << DPPIC_CHENCLR_CH12_Pos)
- #define DPPIC_CHENCLR_CH12_Disabled (0UL)
- #define DPPIC_CHENCLR_CH12_Enabled (1UL)
- #define DPPIC_CHENCLR_CH12_Clear (1UL)
- #define DPPIC_CHENCLR_CH11_Pos (11UL)
- #define DPPIC_CHENCLR_CH11_Msk (0x1UL << DPPIC_CHENCLR_CH11_Pos)
- #define DPPIC_CHENCLR_CH11_Disabled (0UL)
- #define DPPIC_CHENCLR_CH11_Enabled (1UL)
- #define DPPIC_CHENCLR_CH11_Clear (1UL)
- #define DPPIC_CHENCLR_CH10_Pos (10UL)
- #define DPPIC_CHENCLR_CH10_Msk (0x1UL << DPPIC_CHENCLR_CH10_Pos)
- #define DPPIC_CHENCLR_CH10_Disabled (0UL)
- #define DPPIC_CHENCLR_CH10_Enabled (1UL)
- #define DPPIC_CHENCLR_CH10_Clear (1UL)
- #define DPPIC_CHENCLR_CH9_Pos (9UL)
- #define DPPIC_CHENCLR_CH9_Msk (0x1UL << DPPIC_CHENCLR_CH9_Pos)
- #define DPPIC_CHENCLR_CH9_Disabled (0UL)
- #define DPPIC_CHENCLR_CH9_Enabled (1UL)
- #define DPPIC_CHENCLR_CH9_Clear (1UL)
- #define DPPIC_CHENCLR_CH8_Pos (8UL)
- #define DPPIC_CHENCLR_CH8_Msk (0x1UL << DPPIC_CHENCLR_CH8_Pos)
- #define DPPIC_CHENCLR_CH8_Disabled (0UL)
- #define DPPIC_CHENCLR_CH8_Enabled (1UL)
- #define DPPIC_CHENCLR_CH8_Clear (1UL)
- #define DPPIC_CHENCLR_CH7_Pos (7UL)
- #define DPPIC_CHENCLR_CH7_Msk (0x1UL << DPPIC_CHENCLR_CH7_Pos)
- #define DPPIC_CHENCLR_CH7_Disabled (0UL)
- #define DPPIC_CHENCLR_CH7_Enabled (1UL)
- #define DPPIC_CHENCLR_CH7_Clear (1UL)
- #define DPPIC_CHENCLR_CH6_Pos (6UL)
- #define DPPIC_CHENCLR_CH6_Msk (0x1UL << DPPIC_CHENCLR_CH6_Pos)
- #define DPPIC_CHENCLR_CH6_Disabled (0UL)
- #define DPPIC_CHENCLR_CH6_Enabled (1UL)
- #define DPPIC_CHENCLR_CH6_Clear (1UL)
- #define DPPIC_CHENCLR_CH5_Pos (5UL)
- #define DPPIC_CHENCLR_CH5_Msk (0x1UL << DPPIC_CHENCLR_CH5_Pos)
- #define DPPIC_CHENCLR_CH5_Disabled (0UL)
- #define DPPIC_CHENCLR_CH5_Enabled (1UL)
- #define DPPIC_CHENCLR_CH5_Clear (1UL)
- #define DPPIC_CHENCLR_CH4_Pos (4UL)
- #define DPPIC_CHENCLR_CH4_Msk (0x1UL << DPPIC_CHENCLR_CH4_Pos)
- #define DPPIC_CHENCLR_CH4_Disabled (0UL)
- #define DPPIC_CHENCLR_CH4_Enabled (1UL)
- #define DPPIC_CHENCLR_CH4_Clear (1UL)
- #define DPPIC_CHENCLR_CH3_Pos (3UL)
- #define DPPIC_CHENCLR_CH3_Msk (0x1UL << DPPIC_CHENCLR_CH3_Pos)
- #define DPPIC_CHENCLR_CH3_Disabled (0UL)
- #define DPPIC_CHENCLR_CH3_Enabled (1UL)
- #define DPPIC_CHENCLR_CH3_Clear (1UL)
- #define DPPIC_CHENCLR_CH2_Pos (2UL)
- #define DPPIC_CHENCLR_CH2_Msk (0x1UL << DPPIC_CHENCLR_CH2_Pos)
- #define DPPIC_CHENCLR_CH2_Disabled (0UL)
- #define DPPIC_CHENCLR_CH2_Enabled (1UL)
- #define DPPIC_CHENCLR_CH2_Clear (1UL)
- #define DPPIC_CHENCLR_CH1_Pos (1UL)
- #define DPPIC_CHENCLR_CH1_Msk (0x1UL << DPPIC_CHENCLR_CH1_Pos)
- #define DPPIC_CHENCLR_CH1_Disabled (0UL)
- #define DPPIC_CHENCLR_CH1_Enabled (1UL)
- #define DPPIC_CHENCLR_CH1_Clear (1UL)
- #define DPPIC_CHENCLR_CH0_Pos (0UL)
- #define DPPIC_CHENCLR_CH0_Msk (0x1UL << DPPIC_CHENCLR_CH0_Pos)
- #define DPPIC_CHENCLR_CH0_Disabled (0UL)
- #define DPPIC_CHENCLR_CH0_Enabled (1UL)
- #define DPPIC_CHENCLR_CH0_Clear (1UL)
- #define DPPIC_CHG_CH15_Pos (15UL)
- #define DPPIC_CHG_CH15_Msk (0x1UL << DPPIC_CHG_CH15_Pos)
- #define DPPIC_CHG_CH15_Excluded (0UL)
- #define DPPIC_CHG_CH15_Included (1UL)
- #define DPPIC_CHG_CH14_Pos (14UL)
- #define DPPIC_CHG_CH14_Msk (0x1UL << DPPIC_CHG_CH14_Pos)
- #define DPPIC_CHG_CH14_Excluded (0UL)
- #define DPPIC_CHG_CH14_Included (1UL)
- #define DPPIC_CHG_CH13_Pos (13UL)
- #define DPPIC_CHG_CH13_Msk (0x1UL << DPPIC_CHG_CH13_Pos)
- #define DPPIC_CHG_CH13_Excluded (0UL)
- #define DPPIC_CHG_CH13_Included (1UL)
- #define DPPIC_CHG_CH12_Pos (12UL)
- #define DPPIC_CHG_CH12_Msk (0x1UL << DPPIC_CHG_CH12_Pos)
- #define DPPIC_CHG_CH12_Excluded (0UL)
- #define DPPIC_CHG_CH12_Included (1UL)
- #define DPPIC_CHG_CH11_Pos (11UL)
- #define DPPIC_CHG_CH11_Msk (0x1UL << DPPIC_CHG_CH11_Pos)
- #define DPPIC_CHG_CH11_Excluded (0UL)
- #define DPPIC_CHG_CH11_Included (1UL)
- #define DPPIC_CHG_CH10_Pos (10UL)
- #define DPPIC_CHG_CH10_Msk (0x1UL << DPPIC_CHG_CH10_Pos)
- #define DPPIC_CHG_CH10_Excluded (0UL)
- #define DPPIC_CHG_CH10_Included (1UL)
- #define DPPIC_CHG_CH9_Pos (9UL)
- #define DPPIC_CHG_CH9_Msk (0x1UL << DPPIC_CHG_CH9_Pos)
- #define DPPIC_CHG_CH9_Excluded (0UL)
- #define DPPIC_CHG_CH9_Included (1UL)
- #define DPPIC_CHG_CH8_Pos (8UL)
- #define DPPIC_CHG_CH8_Msk (0x1UL << DPPIC_CHG_CH8_Pos)
- #define DPPIC_CHG_CH8_Excluded (0UL)
- #define DPPIC_CHG_CH8_Included (1UL)
- #define DPPIC_CHG_CH7_Pos (7UL)
- #define DPPIC_CHG_CH7_Msk (0x1UL << DPPIC_CHG_CH7_Pos)
- #define DPPIC_CHG_CH7_Excluded (0UL)
- #define DPPIC_CHG_CH7_Included (1UL)
- #define DPPIC_CHG_CH6_Pos (6UL)
- #define DPPIC_CHG_CH6_Msk (0x1UL << DPPIC_CHG_CH6_Pos)
- #define DPPIC_CHG_CH6_Excluded (0UL)
- #define DPPIC_CHG_CH6_Included (1UL)
- #define DPPIC_CHG_CH5_Pos (5UL)
- #define DPPIC_CHG_CH5_Msk (0x1UL << DPPIC_CHG_CH5_Pos)
- #define DPPIC_CHG_CH5_Excluded (0UL)
- #define DPPIC_CHG_CH5_Included (1UL)
- #define DPPIC_CHG_CH4_Pos (4UL)
- #define DPPIC_CHG_CH4_Msk (0x1UL << DPPIC_CHG_CH4_Pos)
- #define DPPIC_CHG_CH4_Excluded (0UL)
- #define DPPIC_CHG_CH4_Included (1UL)
- #define DPPIC_CHG_CH3_Pos (3UL)
- #define DPPIC_CHG_CH3_Msk (0x1UL << DPPIC_CHG_CH3_Pos)
- #define DPPIC_CHG_CH3_Excluded (0UL)
- #define DPPIC_CHG_CH3_Included (1UL)
- #define DPPIC_CHG_CH2_Pos (2UL)
- #define DPPIC_CHG_CH2_Msk (0x1UL << DPPIC_CHG_CH2_Pos)
- #define DPPIC_CHG_CH2_Excluded (0UL)
- #define DPPIC_CHG_CH2_Included (1UL)
- #define DPPIC_CHG_CH1_Pos (1UL)
- #define DPPIC_CHG_CH1_Msk (0x1UL << DPPIC_CHG_CH1_Pos)
- #define DPPIC_CHG_CH1_Excluded (0UL)
- #define DPPIC_CHG_CH1_Included (1UL)
- #define DPPIC_CHG_CH0_Pos (0UL)
- #define DPPIC_CHG_CH0_Msk (0x1UL << DPPIC_CHG_CH0_Pos)
- #define DPPIC_CHG_CH0_Excluded (0UL)
- #define DPPIC_CHG_CH0_Included (1UL)
- #define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL)
- #define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos)
- #define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (1UL)
- #define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL)
- #define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos)
- #define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (1UL)
- #define ECB_SUBSCRIBE_STARTECB_EN_Pos (31UL)
- #define ECB_SUBSCRIBE_STARTECB_EN_Msk (0x1UL << ECB_SUBSCRIBE_STARTECB_EN_Pos)
- #define ECB_SUBSCRIBE_STARTECB_EN_Disabled (0UL)
- #define ECB_SUBSCRIBE_STARTECB_EN_Enabled (1UL)
- #define ECB_SUBSCRIBE_STARTECB_CHIDX_Pos (0UL)
- #define ECB_SUBSCRIBE_STARTECB_CHIDX_Msk (0xFFUL << ECB_SUBSCRIBE_STARTECB_CHIDX_Pos)
- #define ECB_SUBSCRIBE_STOPECB_EN_Pos (31UL)
- #define ECB_SUBSCRIBE_STOPECB_EN_Msk (0x1UL << ECB_SUBSCRIBE_STOPECB_EN_Pos)
- #define ECB_SUBSCRIBE_STOPECB_EN_Disabled (0UL)
- #define ECB_SUBSCRIBE_STOPECB_EN_Enabled (1UL)
- #define ECB_SUBSCRIBE_STOPECB_CHIDX_Pos (0UL)
- #define ECB_SUBSCRIBE_STOPECB_CHIDX_Msk (0xFFUL << ECB_SUBSCRIBE_STOPECB_CHIDX_Pos)
- #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL)
- #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos)
- #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0UL)
- #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (1UL)
- #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL)
- #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos)
- #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0UL)
- #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (1UL)
- #define ECB_PUBLISH_ENDECB_EN_Pos (31UL)
- #define ECB_PUBLISH_ENDECB_EN_Msk (0x1UL << ECB_PUBLISH_ENDECB_EN_Pos)
- #define ECB_PUBLISH_ENDECB_EN_Disabled (0UL)
- #define ECB_PUBLISH_ENDECB_EN_Enabled (1UL)
- #define ECB_PUBLISH_ENDECB_CHIDX_Pos (0UL)
- #define ECB_PUBLISH_ENDECB_CHIDX_Msk (0xFFUL << ECB_PUBLISH_ENDECB_CHIDX_Pos)
- #define ECB_PUBLISH_ERRORECB_EN_Pos (31UL)
- #define ECB_PUBLISH_ERRORECB_EN_Msk (0x1UL << ECB_PUBLISH_ERRORECB_EN_Pos)
- #define ECB_PUBLISH_ERRORECB_EN_Disabled (0UL)
- #define ECB_PUBLISH_ERRORECB_EN_Enabled (1UL)
- #define ECB_PUBLISH_ERRORECB_CHIDX_Pos (0UL)
- #define ECB_PUBLISH_ERRORECB_CHIDX_Msk (0xFFUL << ECB_PUBLISH_ERRORECB_CHIDX_Pos)
- #define ECB_INTENSET_ERRORECB_Pos (1UL)
- #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos)
- #define ECB_INTENSET_ERRORECB_Disabled (0UL)
- #define ECB_INTENSET_ERRORECB_Enabled (1UL)
- #define ECB_INTENSET_ERRORECB_Set (1UL)
- #define ECB_INTENSET_ENDECB_Pos (0UL)
- #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos)
- #define ECB_INTENSET_ENDECB_Disabled (0UL)
- #define ECB_INTENSET_ENDECB_Enabled (1UL)
- #define ECB_INTENSET_ENDECB_Set (1UL)
- #define ECB_INTENCLR_ERRORECB_Pos (1UL)
- #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos)
- #define ECB_INTENCLR_ERRORECB_Disabled (0UL)
- #define ECB_INTENCLR_ERRORECB_Enabled (1UL)
- #define ECB_INTENCLR_ERRORECB_Clear (1UL)
- #define ECB_INTENCLR_ENDECB_Pos (0UL)
- #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos)
- #define ECB_INTENCLR_ENDECB_Disabled (0UL)
- #define ECB_INTENCLR_ENDECB_Enabled (1UL)
- #define ECB_INTENCLR_ENDECB_Clear (1UL)
- #define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL)
- #define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos)
- #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL)
- #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos)
- #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL)
- #define EGU_SUBSCRIBE_TRIGGER_EN_Pos (31UL)
- #define EGU_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << EGU_SUBSCRIBE_TRIGGER_EN_Pos)
- #define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0UL)
- #define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (1UL)
- #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL)
- #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos)
- #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL)
- #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos)
- #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL)
- #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL)
- #define EGU_PUBLISH_TRIGGERED_EN_Pos (31UL)
- #define EGU_PUBLISH_TRIGGERED_EN_Msk (0x1UL << EGU_PUBLISH_TRIGGERED_EN_Pos)
- #define EGU_PUBLISH_TRIGGERED_EN_Disabled (0UL)
- #define EGU_PUBLISH_TRIGGERED_EN_Enabled (1UL)
- #define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL)
- #define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos)
- #define EGU_INTEN_TRIGGERED15_Pos (15UL)
- #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos)
- #define EGU_INTEN_TRIGGERED15_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED15_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED14_Pos (14UL)
- #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos)
- #define EGU_INTEN_TRIGGERED14_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED14_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED13_Pos (13UL)
- #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos)
- #define EGU_INTEN_TRIGGERED13_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED13_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED12_Pos (12UL)
- #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos)
- #define EGU_INTEN_TRIGGERED12_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED12_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED11_Pos (11UL)
- #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos)
- #define EGU_INTEN_TRIGGERED11_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED11_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED10_Pos (10UL)
- #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos)
- #define EGU_INTEN_TRIGGERED10_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED10_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED9_Pos (9UL)
- #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos)
- #define EGU_INTEN_TRIGGERED9_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED9_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED8_Pos (8UL)
- #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos)
- #define EGU_INTEN_TRIGGERED8_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED8_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED7_Pos (7UL)
- #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos)
- #define EGU_INTEN_TRIGGERED7_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED7_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED6_Pos (6UL)
- #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos)
- #define EGU_INTEN_TRIGGERED6_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED6_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED5_Pos (5UL)
- #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos)
- #define EGU_INTEN_TRIGGERED5_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED5_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED4_Pos (4UL)
- #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos)
- #define EGU_INTEN_TRIGGERED4_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED4_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED3_Pos (3UL)
- #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos)
- #define EGU_INTEN_TRIGGERED3_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED3_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED2_Pos (2UL)
- #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos)
- #define EGU_INTEN_TRIGGERED2_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED2_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED1_Pos (1UL)
- #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos)
- #define EGU_INTEN_TRIGGERED1_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED1_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED0_Pos (0UL)
- #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos)
- #define EGU_INTEN_TRIGGERED0_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED0_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED15_Pos (15UL)
- #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos)
- #define EGU_INTENSET_TRIGGERED15_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED15_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED15_Set (1UL)
- #define EGU_INTENSET_TRIGGERED14_Pos (14UL)
- #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos)
- #define EGU_INTENSET_TRIGGERED14_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED14_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED14_Set (1UL)
- #define EGU_INTENSET_TRIGGERED13_Pos (13UL)
- #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos)
- #define EGU_INTENSET_TRIGGERED13_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED13_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED13_Set (1UL)
- #define EGU_INTENSET_TRIGGERED12_Pos (12UL)
- #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos)
- #define EGU_INTENSET_TRIGGERED12_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED12_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED12_Set (1UL)
- #define EGU_INTENSET_TRIGGERED11_Pos (11UL)
- #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos)
- #define EGU_INTENSET_TRIGGERED11_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED11_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED11_Set (1UL)
- #define EGU_INTENSET_TRIGGERED10_Pos (10UL)
- #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos)
- #define EGU_INTENSET_TRIGGERED10_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED10_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED10_Set (1UL)
- #define EGU_INTENSET_TRIGGERED9_Pos (9UL)
- #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos)
- #define EGU_INTENSET_TRIGGERED9_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED9_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED9_Set (1UL)
- #define EGU_INTENSET_TRIGGERED8_Pos (8UL)
- #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos)
- #define EGU_INTENSET_TRIGGERED8_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED8_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED8_Set (1UL)
- #define EGU_INTENSET_TRIGGERED7_Pos (7UL)
- #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos)
- #define EGU_INTENSET_TRIGGERED7_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED7_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED7_Set (1UL)
- #define EGU_INTENSET_TRIGGERED6_Pos (6UL)
- #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos)
- #define EGU_INTENSET_TRIGGERED6_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED6_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED6_Set (1UL)
- #define EGU_INTENSET_TRIGGERED5_Pos (5UL)
- #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos)
- #define EGU_INTENSET_TRIGGERED5_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED5_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED5_Set (1UL)
- #define EGU_INTENSET_TRIGGERED4_Pos (4UL)
- #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos)
- #define EGU_INTENSET_TRIGGERED4_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED4_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED4_Set (1UL)
- #define EGU_INTENSET_TRIGGERED3_Pos (3UL)
- #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos)
- #define EGU_INTENSET_TRIGGERED3_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED3_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED3_Set (1UL)
- #define EGU_INTENSET_TRIGGERED2_Pos (2UL)
- #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos)
- #define EGU_INTENSET_TRIGGERED2_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED2_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED2_Set (1UL)
- #define EGU_INTENSET_TRIGGERED1_Pos (1UL)
- #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos)
- #define EGU_INTENSET_TRIGGERED1_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED1_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED1_Set (1UL)
- #define EGU_INTENSET_TRIGGERED0_Pos (0UL)
- #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos)
- #define EGU_INTENSET_TRIGGERED0_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED0_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED0_Set (1UL)
- #define EGU_INTENCLR_TRIGGERED15_Pos (15UL)
- #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos)
- #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED15_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED14_Pos (14UL)
- #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos)
- #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED14_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED13_Pos (13UL)
- #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos)
- #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED13_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED12_Pos (12UL)
- #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos)
- #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED12_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED11_Pos (11UL)
- #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos)
- #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED11_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED10_Pos (10UL)
- #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos)
- #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED10_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED9_Pos (9UL)
- #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos)
- #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED9_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED8_Pos (8UL)
- #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos)
- #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED8_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED7_Pos (7UL)
- #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos)
- #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED7_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED6_Pos (6UL)
- #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos)
- #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED6_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED5_Pos (5UL)
- #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos)
- #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED5_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED4_Pos (4UL)
- #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos)
- #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED4_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED3_Pos (3UL)
- #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos)
- #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED3_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED2_Pos (2UL)
- #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos)
- #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED2_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED1_Pos (1UL)
- #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos)
- #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED1_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED0_Pos (0UL)
- #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos)
- #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED0_Clear (1UL)
- #define FICR_INFO_CONFIGID_HWID_Pos (0UL)
- #define FICR_INFO_CONFIGID_HWID_Msk (0xFFFFUL << FICR_INFO_CONFIGID_HWID_Pos)
- #define FICR_INFO_DEVICEID_DEVICEID_Pos (0UL)
- #define FICR_INFO_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICEID_DEVICEID_Pos)
- #define FICR_INFO_PART_PART_Pos (0UL)
- #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos)
- #define FICR_INFO_PART_PART_N5340 (0x5340UL)
- #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL)
- #define FICR_INFO_VARIANT_VARIANT_Pos (0UL)
- #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos)
- #define FICR_INFO_VARIANT_VARIANT_QKAA (0x514B4141UL)
- #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL)
- #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL)
- #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos)
- #define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL)
- #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL)
- #define FICR_INFO_RAM_RAM_Pos (0UL)
- #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos)
- #define FICR_INFO_RAM_RAM_K16 (0x10UL)
- #define FICR_INFO_RAM_RAM_K32 (0x20UL)
- #define FICR_INFO_RAM_RAM_K64 (0x40UL)
- #define FICR_INFO_RAM_RAM_K128 (0x80UL)
- #define FICR_INFO_RAM_RAM_K256 (0x100UL)
- #define FICR_INFO_RAM_RAM_K512 (0x200UL)
- #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL)
- #define FICR_INFO_FLASH_FLASH_Pos (0UL)
- #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos)
- #define FICR_INFO_FLASH_FLASH_K128 (0x80UL)
- #define FICR_INFO_FLASH_FLASH_K256 (0x100UL)
- #define FICR_INFO_FLASH_FLASH_K512 (0x200UL)
- #define FICR_INFO_FLASH_FLASH_K1024 (0x400UL)
- #define FICR_INFO_FLASH_FLASH_K2048 (0x800UL)
- #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL)
- #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL)
- #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos)
- #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_K2048 (0x800UL)
- #define FICR_INFO_CODESIZE_CODESIZE_Pos (0UL)
- #define FICR_INFO_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODESIZE_CODESIZE_Pos)
- #define FICR_INFO_CODESIZE_CODESIZE_P128 (128UL)
- #define FICR_INFO_DEVICETYPE_DEVICETYPE_Pos (0UL)
- #define FICR_INFO_DEVICETYPE_DEVICETYPE_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICETYPE_DEVICETYPE_Pos)
- #define FICR_INFO_DEVICETYPE_DEVICETYPE_Die (0x0000000UL)
- #define FICR_INFO_DEVICETYPE_DEVICETYPE_FPGA (0xFFFFFFFFUL)
- #define FICR_ER_ER_Pos (0UL)
- #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos)
- #define FICR_IR_IR_Pos (0UL)
- #define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos)
- #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL)
- #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos)
- #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL)
- #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL)
- #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL)
- #define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos)
- #define FICR_TRIMCNF_ADDR_Address_Pos (0UL)
- #define FICR_TRIMCNF_ADDR_Address_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_ADDR_Address_Pos)
- #define FICR_TRIMCNF_DATA_Data_Pos (0UL)
- #define FICR_TRIMCNF_DATA_Data_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_DATA_Data_Pos)
- #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL)
- #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos)
- #define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL)
- #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL)
- #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos)
- #define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL)
- #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL)
- #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos)
- #define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL)
- #define GPIOTE_SUBSCRIBE_OUT_EN_Pos (31UL)
- #define GPIOTE_SUBSCRIBE_OUT_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_OUT_EN_Pos)
- #define GPIOTE_SUBSCRIBE_OUT_EN_Disabled (0UL)
- #define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (1UL)
- #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos (0UL)
- #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos)
- #define GPIOTE_SUBSCRIBE_SET_EN_Pos (31UL)
- #define GPIOTE_SUBSCRIBE_SET_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_SET_EN_Pos)
- #define GPIOTE_SUBSCRIBE_SET_EN_Disabled (0UL)
- #define GPIOTE_SUBSCRIBE_SET_EN_Enabled (1UL)
- #define GPIOTE_SUBSCRIBE_SET_CHIDX_Pos (0UL)
- #define GPIOTE_SUBSCRIBE_SET_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_SET_CHIDX_Pos)
- #define GPIOTE_SUBSCRIBE_CLR_EN_Pos (31UL)
- #define GPIOTE_SUBSCRIBE_CLR_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_CLR_EN_Pos)
- #define GPIOTE_SUBSCRIBE_CLR_EN_Disabled (0UL)
- #define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (1UL)
- #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos (0UL)
- #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos)
- #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL)
- #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos)
- #define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL)
- #define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL)
- #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL)
- #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos)
- #define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL)
- #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL)
- #define GPIOTE_PUBLISH_IN_EN_Pos (31UL)
- #define GPIOTE_PUBLISH_IN_EN_Msk (0x1UL << GPIOTE_PUBLISH_IN_EN_Pos)
- #define GPIOTE_PUBLISH_IN_EN_Disabled (0UL)
- #define GPIOTE_PUBLISH_IN_EN_Enabled (1UL)
- #define GPIOTE_PUBLISH_IN_CHIDX_Pos (0UL)
- #define GPIOTE_PUBLISH_IN_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_IN_CHIDX_Pos)
- #define GPIOTE_PUBLISH_PORT_EN_Pos (31UL)
- #define GPIOTE_PUBLISH_PORT_EN_Msk (0x1UL << GPIOTE_PUBLISH_PORT_EN_Pos)
- #define GPIOTE_PUBLISH_PORT_EN_Disabled (0UL)
- #define GPIOTE_PUBLISH_PORT_EN_Enabled (1UL)
- #define GPIOTE_PUBLISH_PORT_CHIDX_Pos (0UL)
- #define GPIOTE_PUBLISH_PORT_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_PORT_CHIDX_Pos)
- #define GPIOTE_INTENSET_PORT_Pos (31UL)
- #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos)
- #define GPIOTE_INTENSET_PORT_Disabled (0UL)
- #define GPIOTE_INTENSET_PORT_Enabled (1UL)
- #define GPIOTE_INTENSET_PORT_Set (1UL)
- #define GPIOTE_INTENSET_IN7_Pos (7UL)
- #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos)
- #define GPIOTE_INTENSET_IN7_Disabled (0UL)
- #define GPIOTE_INTENSET_IN7_Enabled (1UL)
- #define GPIOTE_INTENSET_IN7_Set (1UL)
- #define GPIOTE_INTENSET_IN6_Pos (6UL)
- #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos)
- #define GPIOTE_INTENSET_IN6_Disabled (0UL)
- #define GPIOTE_INTENSET_IN6_Enabled (1UL)
- #define GPIOTE_INTENSET_IN6_Set (1UL)
- #define GPIOTE_INTENSET_IN5_Pos (5UL)
- #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos)
- #define GPIOTE_INTENSET_IN5_Disabled (0UL)
- #define GPIOTE_INTENSET_IN5_Enabled (1UL)
- #define GPIOTE_INTENSET_IN5_Set (1UL)
- #define GPIOTE_INTENSET_IN4_Pos (4UL)
- #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos)
- #define GPIOTE_INTENSET_IN4_Disabled (0UL)
- #define GPIOTE_INTENSET_IN4_Enabled (1UL)
- #define GPIOTE_INTENSET_IN4_Set (1UL)
- #define GPIOTE_INTENSET_IN3_Pos (3UL)
- #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos)
- #define GPIOTE_INTENSET_IN3_Disabled (0UL)
- #define GPIOTE_INTENSET_IN3_Enabled (1UL)
- #define GPIOTE_INTENSET_IN3_Set (1UL)
- #define GPIOTE_INTENSET_IN2_Pos (2UL)
- #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos)
- #define GPIOTE_INTENSET_IN2_Disabled (0UL)
- #define GPIOTE_INTENSET_IN2_Enabled (1UL)
- #define GPIOTE_INTENSET_IN2_Set (1UL)
- #define GPIOTE_INTENSET_IN1_Pos (1UL)
- #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos)
- #define GPIOTE_INTENSET_IN1_Disabled (0UL)
- #define GPIOTE_INTENSET_IN1_Enabled (1UL)
- #define GPIOTE_INTENSET_IN1_Set (1UL)
- #define GPIOTE_INTENSET_IN0_Pos (0UL)
- #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos)
- #define GPIOTE_INTENSET_IN0_Disabled (0UL)
- #define GPIOTE_INTENSET_IN0_Enabled (1UL)
- #define GPIOTE_INTENSET_IN0_Set (1UL)
- #define GPIOTE_INTENCLR_PORT_Pos (31UL)
- #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos)
- #define GPIOTE_INTENCLR_PORT_Disabled (0UL)
- #define GPIOTE_INTENCLR_PORT_Enabled (1UL)
- #define GPIOTE_INTENCLR_PORT_Clear (1UL)
- #define GPIOTE_INTENCLR_IN7_Pos (7UL)
- #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos)
- #define GPIOTE_INTENCLR_IN7_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN7_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN7_Clear (1UL)
- #define GPIOTE_INTENCLR_IN6_Pos (6UL)
- #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos)
- #define GPIOTE_INTENCLR_IN6_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN6_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN6_Clear (1UL)
- #define GPIOTE_INTENCLR_IN5_Pos (5UL)
- #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos)
- #define GPIOTE_INTENCLR_IN5_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN5_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN5_Clear (1UL)
- #define GPIOTE_INTENCLR_IN4_Pos (4UL)
- #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos)
- #define GPIOTE_INTENCLR_IN4_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN4_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN4_Clear (1UL)
- #define GPIOTE_INTENCLR_IN3_Pos (3UL)
- #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos)
- #define GPIOTE_INTENCLR_IN3_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN3_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN3_Clear (1UL)
- #define GPIOTE_INTENCLR_IN2_Pos (2UL)
- #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos)
- #define GPIOTE_INTENCLR_IN2_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN2_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN2_Clear (1UL)
- #define GPIOTE_INTENCLR_IN1_Pos (1UL)
- #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos)
- #define GPIOTE_INTENCLR_IN1_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN1_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN1_Clear (1UL)
- #define GPIOTE_INTENCLR_IN0_Pos (0UL)
- #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos)
- #define GPIOTE_INTENCLR_IN0_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN0_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN0_Clear (1UL)
- #define GPIOTE_LATENCY_LATENCY_Pos (0UL)
- #define GPIOTE_LATENCY_LATENCY_Msk (0x1UL << GPIOTE_LATENCY_LATENCY_Pos)
- #define GPIOTE_LATENCY_LATENCY_LowPower (0UL)
- #define GPIOTE_LATENCY_LATENCY_LowLatency (1UL)
- #define GPIOTE_CONFIG_OUTINIT_Pos (20UL)
- #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos)
- #define GPIOTE_CONFIG_OUTINIT_Low (0UL)
- #define GPIOTE_CONFIG_OUTINIT_High (1UL)
- #define GPIOTE_CONFIG_POLARITY_Pos (16UL)
- #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos)
- #define GPIOTE_CONFIG_POLARITY_None (0UL)
- #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL)
- #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL)
- #define GPIOTE_CONFIG_POLARITY_Toggle (3UL)
- #define GPIOTE_CONFIG_PORT_Pos (13UL)
- #define GPIOTE_CONFIG_PORT_Msk (0x1UL << GPIOTE_CONFIG_PORT_Pos)
- #define GPIOTE_CONFIG_PSEL_Pos (8UL)
- #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos)
- #define GPIOTE_CONFIG_MODE_Pos (0UL)
- #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos)
- #define GPIOTE_CONFIG_MODE_Disabled (0UL)
- #define GPIOTE_CONFIG_MODE_Event (1UL)
- #define GPIOTE_CONFIG_MODE_Task (3UL)
- #define IPC_TASKS_SEND_TASKS_SEND_Pos (0UL)
- #define IPC_TASKS_SEND_TASKS_SEND_Msk (0x1UL << IPC_TASKS_SEND_TASKS_SEND_Pos)
- #define IPC_TASKS_SEND_TASKS_SEND_Trigger (1UL)
- #define IPC_SUBSCRIBE_SEND_EN_Pos (31UL)
- #define IPC_SUBSCRIBE_SEND_EN_Msk (0x1UL << IPC_SUBSCRIBE_SEND_EN_Pos)
- #define IPC_SUBSCRIBE_SEND_EN_Disabled (0UL)
- #define IPC_SUBSCRIBE_SEND_EN_Enabled (1UL)
- #define IPC_SUBSCRIBE_SEND_CHIDX_Pos (0UL)
- #define IPC_SUBSCRIBE_SEND_CHIDX_Msk (0xFFUL << IPC_SUBSCRIBE_SEND_CHIDX_Pos)
- #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos (0UL)
- #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Msk (0x1UL << IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos)
- #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_NotGenerated (0UL)
- #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Generated (1UL)
- #define IPC_PUBLISH_RECEIVE_EN_Pos (31UL)
- #define IPC_PUBLISH_RECEIVE_EN_Msk (0x1UL << IPC_PUBLISH_RECEIVE_EN_Pos)
- #define IPC_PUBLISH_RECEIVE_EN_Disabled (0UL)
- #define IPC_PUBLISH_RECEIVE_EN_Enabled (1UL)
- #define IPC_PUBLISH_RECEIVE_CHIDX_Pos (0UL)
- #define IPC_PUBLISH_RECEIVE_CHIDX_Msk (0xFFUL << IPC_PUBLISH_RECEIVE_CHIDX_Pos)
- #define IPC_INTEN_RECEIVE15_Pos (15UL)
- #define IPC_INTEN_RECEIVE15_Msk (0x1UL << IPC_INTEN_RECEIVE15_Pos)
- #define IPC_INTEN_RECEIVE15_Disabled (0UL)
- #define IPC_INTEN_RECEIVE15_Enabled (1UL)
- #define IPC_INTEN_RECEIVE14_Pos (14UL)
- #define IPC_INTEN_RECEIVE14_Msk (0x1UL << IPC_INTEN_RECEIVE14_Pos)
- #define IPC_INTEN_RECEIVE14_Disabled (0UL)
- #define IPC_INTEN_RECEIVE14_Enabled (1UL)
- #define IPC_INTEN_RECEIVE13_Pos (13UL)
- #define IPC_INTEN_RECEIVE13_Msk (0x1UL << IPC_INTEN_RECEIVE13_Pos)
- #define IPC_INTEN_RECEIVE13_Disabled (0UL)
- #define IPC_INTEN_RECEIVE13_Enabled (1UL)
- #define IPC_INTEN_RECEIVE12_Pos (12UL)
- #define IPC_INTEN_RECEIVE12_Msk (0x1UL << IPC_INTEN_RECEIVE12_Pos)
- #define IPC_INTEN_RECEIVE12_Disabled (0UL)
- #define IPC_INTEN_RECEIVE12_Enabled (1UL)
- #define IPC_INTEN_RECEIVE11_Pos (11UL)
- #define IPC_INTEN_RECEIVE11_Msk (0x1UL << IPC_INTEN_RECEIVE11_Pos)
- #define IPC_INTEN_RECEIVE11_Disabled (0UL)
- #define IPC_INTEN_RECEIVE11_Enabled (1UL)
- #define IPC_INTEN_RECEIVE10_Pos (10UL)
- #define IPC_INTEN_RECEIVE10_Msk (0x1UL << IPC_INTEN_RECEIVE10_Pos)
- #define IPC_INTEN_RECEIVE10_Disabled (0UL)
- #define IPC_INTEN_RECEIVE10_Enabled (1UL)
- #define IPC_INTEN_RECEIVE9_Pos (9UL)
- #define IPC_INTEN_RECEIVE9_Msk (0x1UL << IPC_INTEN_RECEIVE9_Pos)
- #define IPC_INTEN_RECEIVE9_Disabled (0UL)
- #define IPC_INTEN_RECEIVE9_Enabled (1UL)
- #define IPC_INTEN_RECEIVE8_Pos (8UL)
- #define IPC_INTEN_RECEIVE8_Msk (0x1UL << IPC_INTEN_RECEIVE8_Pos)
- #define IPC_INTEN_RECEIVE8_Disabled (0UL)
- #define IPC_INTEN_RECEIVE8_Enabled (1UL)
- #define IPC_INTEN_RECEIVE7_Pos (7UL)
- #define IPC_INTEN_RECEIVE7_Msk (0x1UL << IPC_INTEN_RECEIVE7_Pos)
- #define IPC_INTEN_RECEIVE7_Disabled (0UL)
- #define IPC_INTEN_RECEIVE7_Enabled (1UL)
- #define IPC_INTEN_RECEIVE6_Pos (6UL)
- #define IPC_INTEN_RECEIVE6_Msk (0x1UL << IPC_INTEN_RECEIVE6_Pos)
- #define IPC_INTEN_RECEIVE6_Disabled (0UL)
- #define IPC_INTEN_RECEIVE6_Enabled (1UL)
- #define IPC_INTEN_RECEIVE5_Pos (5UL)
- #define IPC_INTEN_RECEIVE5_Msk (0x1UL << IPC_INTEN_RECEIVE5_Pos)
- #define IPC_INTEN_RECEIVE5_Disabled (0UL)
- #define IPC_INTEN_RECEIVE5_Enabled (1UL)
- #define IPC_INTEN_RECEIVE4_Pos (4UL)
- #define IPC_INTEN_RECEIVE4_Msk (0x1UL << IPC_INTEN_RECEIVE4_Pos)
- #define IPC_INTEN_RECEIVE4_Disabled (0UL)
- #define IPC_INTEN_RECEIVE4_Enabled (1UL)
- #define IPC_INTEN_RECEIVE3_Pos (3UL)
- #define IPC_INTEN_RECEIVE3_Msk (0x1UL << IPC_INTEN_RECEIVE3_Pos)
- #define IPC_INTEN_RECEIVE3_Disabled (0UL)
- #define IPC_INTEN_RECEIVE3_Enabled (1UL)
- #define IPC_INTEN_RECEIVE2_Pos (2UL)
- #define IPC_INTEN_RECEIVE2_Msk (0x1UL << IPC_INTEN_RECEIVE2_Pos)
- #define IPC_INTEN_RECEIVE2_Disabled (0UL)
- #define IPC_INTEN_RECEIVE2_Enabled (1UL)
- #define IPC_INTEN_RECEIVE1_Pos (1UL)
- #define IPC_INTEN_RECEIVE1_Msk (0x1UL << IPC_INTEN_RECEIVE1_Pos)
- #define IPC_INTEN_RECEIVE1_Disabled (0UL)
- #define IPC_INTEN_RECEIVE1_Enabled (1UL)
- #define IPC_INTEN_RECEIVE0_Pos (0UL)
- #define IPC_INTEN_RECEIVE0_Msk (0x1UL << IPC_INTEN_RECEIVE0_Pos)
- #define IPC_INTEN_RECEIVE0_Disabled (0UL)
- #define IPC_INTEN_RECEIVE0_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE15_Pos (15UL)
- #define IPC_INTENSET_RECEIVE15_Msk (0x1UL << IPC_INTENSET_RECEIVE15_Pos)
- #define IPC_INTENSET_RECEIVE15_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE15_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE15_Set (1UL)
- #define IPC_INTENSET_RECEIVE14_Pos (14UL)
- #define IPC_INTENSET_RECEIVE14_Msk (0x1UL << IPC_INTENSET_RECEIVE14_Pos)
- #define IPC_INTENSET_RECEIVE14_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE14_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE14_Set (1UL)
- #define IPC_INTENSET_RECEIVE13_Pos (13UL)
- #define IPC_INTENSET_RECEIVE13_Msk (0x1UL << IPC_INTENSET_RECEIVE13_Pos)
- #define IPC_INTENSET_RECEIVE13_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE13_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE13_Set (1UL)
- #define IPC_INTENSET_RECEIVE12_Pos (12UL)
- #define IPC_INTENSET_RECEIVE12_Msk (0x1UL << IPC_INTENSET_RECEIVE12_Pos)
- #define IPC_INTENSET_RECEIVE12_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE12_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE12_Set (1UL)
- #define IPC_INTENSET_RECEIVE11_Pos (11UL)
- #define IPC_INTENSET_RECEIVE11_Msk (0x1UL << IPC_INTENSET_RECEIVE11_Pos)
- #define IPC_INTENSET_RECEIVE11_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE11_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE11_Set (1UL)
- #define IPC_INTENSET_RECEIVE10_Pos (10UL)
- #define IPC_INTENSET_RECEIVE10_Msk (0x1UL << IPC_INTENSET_RECEIVE10_Pos)
- #define IPC_INTENSET_RECEIVE10_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE10_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE10_Set (1UL)
- #define IPC_INTENSET_RECEIVE9_Pos (9UL)
- #define IPC_INTENSET_RECEIVE9_Msk (0x1UL << IPC_INTENSET_RECEIVE9_Pos)
- #define IPC_INTENSET_RECEIVE9_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE9_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE9_Set (1UL)
- #define IPC_INTENSET_RECEIVE8_Pos (8UL)
- #define IPC_INTENSET_RECEIVE8_Msk (0x1UL << IPC_INTENSET_RECEIVE8_Pos)
- #define IPC_INTENSET_RECEIVE8_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE8_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE8_Set (1UL)
- #define IPC_INTENSET_RECEIVE7_Pos (7UL)
- #define IPC_INTENSET_RECEIVE7_Msk (0x1UL << IPC_INTENSET_RECEIVE7_Pos)
- #define IPC_INTENSET_RECEIVE7_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE7_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE7_Set (1UL)
- #define IPC_INTENSET_RECEIVE6_Pos (6UL)
- #define IPC_INTENSET_RECEIVE6_Msk (0x1UL << IPC_INTENSET_RECEIVE6_Pos)
- #define IPC_INTENSET_RECEIVE6_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE6_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE6_Set (1UL)
- #define IPC_INTENSET_RECEIVE5_Pos (5UL)
- #define IPC_INTENSET_RECEIVE5_Msk (0x1UL << IPC_INTENSET_RECEIVE5_Pos)
- #define IPC_INTENSET_RECEIVE5_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE5_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE5_Set (1UL)
- #define IPC_INTENSET_RECEIVE4_Pos (4UL)
- #define IPC_INTENSET_RECEIVE4_Msk (0x1UL << IPC_INTENSET_RECEIVE4_Pos)
- #define IPC_INTENSET_RECEIVE4_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE4_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE4_Set (1UL)
- #define IPC_INTENSET_RECEIVE3_Pos (3UL)
- #define IPC_INTENSET_RECEIVE3_Msk (0x1UL << IPC_INTENSET_RECEIVE3_Pos)
- #define IPC_INTENSET_RECEIVE3_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE3_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE3_Set (1UL)
- #define IPC_INTENSET_RECEIVE2_Pos (2UL)
- #define IPC_INTENSET_RECEIVE2_Msk (0x1UL << IPC_INTENSET_RECEIVE2_Pos)
- #define IPC_INTENSET_RECEIVE2_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE2_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE2_Set (1UL)
- #define IPC_INTENSET_RECEIVE1_Pos (1UL)
- #define IPC_INTENSET_RECEIVE1_Msk (0x1UL << IPC_INTENSET_RECEIVE1_Pos)
- #define IPC_INTENSET_RECEIVE1_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE1_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE1_Set (1UL)
- #define IPC_INTENSET_RECEIVE0_Pos (0UL)
- #define IPC_INTENSET_RECEIVE0_Msk (0x1UL << IPC_INTENSET_RECEIVE0_Pos)
- #define IPC_INTENSET_RECEIVE0_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE0_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE0_Set (1UL)
- #define IPC_INTENCLR_RECEIVE15_Pos (15UL)
- #define IPC_INTENCLR_RECEIVE15_Msk (0x1UL << IPC_INTENCLR_RECEIVE15_Pos)
- #define IPC_INTENCLR_RECEIVE15_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE15_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE15_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE14_Pos (14UL)
- #define IPC_INTENCLR_RECEIVE14_Msk (0x1UL << IPC_INTENCLR_RECEIVE14_Pos)
- #define IPC_INTENCLR_RECEIVE14_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE14_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE14_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE13_Pos (13UL)
- #define IPC_INTENCLR_RECEIVE13_Msk (0x1UL << IPC_INTENCLR_RECEIVE13_Pos)
- #define IPC_INTENCLR_RECEIVE13_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE13_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE13_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE12_Pos (12UL)
- #define IPC_INTENCLR_RECEIVE12_Msk (0x1UL << IPC_INTENCLR_RECEIVE12_Pos)
- #define IPC_INTENCLR_RECEIVE12_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE12_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE12_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE11_Pos (11UL)
- #define IPC_INTENCLR_RECEIVE11_Msk (0x1UL << IPC_INTENCLR_RECEIVE11_Pos)
- #define IPC_INTENCLR_RECEIVE11_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE11_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE11_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE10_Pos (10UL)
- #define IPC_INTENCLR_RECEIVE10_Msk (0x1UL << IPC_INTENCLR_RECEIVE10_Pos)
- #define IPC_INTENCLR_RECEIVE10_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE10_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE10_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE9_Pos (9UL)
- #define IPC_INTENCLR_RECEIVE9_Msk (0x1UL << IPC_INTENCLR_RECEIVE9_Pos)
- #define IPC_INTENCLR_RECEIVE9_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE9_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE9_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE8_Pos (8UL)
- #define IPC_INTENCLR_RECEIVE8_Msk (0x1UL << IPC_INTENCLR_RECEIVE8_Pos)
- #define IPC_INTENCLR_RECEIVE8_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE8_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE8_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE7_Pos (7UL)
- #define IPC_INTENCLR_RECEIVE7_Msk (0x1UL << IPC_INTENCLR_RECEIVE7_Pos)
- #define IPC_INTENCLR_RECEIVE7_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE7_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE7_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE6_Pos (6UL)
- #define IPC_INTENCLR_RECEIVE6_Msk (0x1UL << IPC_INTENCLR_RECEIVE6_Pos)
- #define IPC_INTENCLR_RECEIVE6_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE6_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE6_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE5_Pos (5UL)
- #define IPC_INTENCLR_RECEIVE5_Msk (0x1UL << IPC_INTENCLR_RECEIVE5_Pos)
- #define IPC_INTENCLR_RECEIVE5_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE5_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE5_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE4_Pos (4UL)
- #define IPC_INTENCLR_RECEIVE4_Msk (0x1UL << IPC_INTENCLR_RECEIVE4_Pos)
- #define IPC_INTENCLR_RECEIVE4_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE4_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE4_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE3_Pos (3UL)
- #define IPC_INTENCLR_RECEIVE3_Msk (0x1UL << IPC_INTENCLR_RECEIVE3_Pos)
- #define IPC_INTENCLR_RECEIVE3_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE3_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE3_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE2_Pos (2UL)
- #define IPC_INTENCLR_RECEIVE2_Msk (0x1UL << IPC_INTENCLR_RECEIVE2_Pos)
- #define IPC_INTENCLR_RECEIVE2_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE2_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE2_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE1_Pos (1UL)
- #define IPC_INTENCLR_RECEIVE1_Msk (0x1UL << IPC_INTENCLR_RECEIVE1_Pos)
- #define IPC_INTENCLR_RECEIVE1_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE1_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE1_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE0_Pos (0UL)
- #define IPC_INTENCLR_RECEIVE0_Msk (0x1UL << IPC_INTENCLR_RECEIVE0_Pos)
- #define IPC_INTENCLR_RECEIVE0_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE0_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE0_Clear (1UL)
- #define IPC_INTPEND_RECEIVE15_Pos (15UL)
- #define IPC_INTPEND_RECEIVE15_Msk (0x1UL << IPC_INTPEND_RECEIVE15_Pos)
- #define IPC_INTPEND_RECEIVE15_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE15_Pending (1UL)
- #define IPC_INTPEND_RECEIVE14_Pos (14UL)
- #define IPC_INTPEND_RECEIVE14_Msk (0x1UL << IPC_INTPEND_RECEIVE14_Pos)
- #define IPC_INTPEND_RECEIVE14_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE14_Pending (1UL)
- #define IPC_INTPEND_RECEIVE13_Pos (13UL)
- #define IPC_INTPEND_RECEIVE13_Msk (0x1UL << IPC_INTPEND_RECEIVE13_Pos)
- #define IPC_INTPEND_RECEIVE13_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE13_Pending (1UL)
- #define IPC_INTPEND_RECEIVE12_Pos (12UL)
- #define IPC_INTPEND_RECEIVE12_Msk (0x1UL << IPC_INTPEND_RECEIVE12_Pos)
- #define IPC_INTPEND_RECEIVE12_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE12_Pending (1UL)
- #define IPC_INTPEND_RECEIVE11_Pos (11UL)
- #define IPC_INTPEND_RECEIVE11_Msk (0x1UL << IPC_INTPEND_RECEIVE11_Pos)
- #define IPC_INTPEND_RECEIVE11_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE11_Pending (1UL)
- #define IPC_INTPEND_RECEIVE10_Pos (10UL)
- #define IPC_INTPEND_RECEIVE10_Msk (0x1UL << IPC_INTPEND_RECEIVE10_Pos)
- #define IPC_INTPEND_RECEIVE10_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE10_Pending (1UL)
- #define IPC_INTPEND_RECEIVE9_Pos (9UL)
- #define IPC_INTPEND_RECEIVE9_Msk (0x1UL << IPC_INTPEND_RECEIVE9_Pos)
- #define IPC_INTPEND_RECEIVE9_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE9_Pending (1UL)
- #define IPC_INTPEND_RECEIVE8_Pos (8UL)
- #define IPC_INTPEND_RECEIVE8_Msk (0x1UL << IPC_INTPEND_RECEIVE8_Pos)
- #define IPC_INTPEND_RECEIVE8_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE8_Pending (1UL)
- #define IPC_INTPEND_RECEIVE7_Pos (7UL)
- #define IPC_INTPEND_RECEIVE7_Msk (0x1UL << IPC_INTPEND_RECEIVE7_Pos)
- #define IPC_INTPEND_RECEIVE7_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE7_Pending (1UL)
- #define IPC_INTPEND_RECEIVE6_Pos (6UL)
- #define IPC_INTPEND_RECEIVE6_Msk (0x1UL << IPC_INTPEND_RECEIVE6_Pos)
- #define IPC_INTPEND_RECEIVE6_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE6_Pending (1UL)
- #define IPC_INTPEND_RECEIVE5_Pos (5UL)
- #define IPC_INTPEND_RECEIVE5_Msk (0x1UL << IPC_INTPEND_RECEIVE5_Pos)
- #define IPC_INTPEND_RECEIVE5_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE5_Pending (1UL)
- #define IPC_INTPEND_RECEIVE4_Pos (4UL)
- #define IPC_INTPEND_RECEIVE4_Msk (0x1UL << IPC_INTPEND_RECEIVE4_Pos)
- #define IPC_INTPEND_RECEIVE4_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE4_Pending (1UL)
- #define IPC_INTPEND_RECEIVE3_Pos (3UL)
- #define IPC_INTPEND_RECEIVE3_Msk (0x1UL << IPC_INTPEND_RECEIVE3_Pos)
- #define IPC_INTPEND_RECEIVE3_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE3_Pending (1UL)
- #define IPC_INTPEND_RECEIVE2_Pos (2UL)
- #define IPC_INTPEND_RECEIVE2_Msk (0x1UL << IPC_INTPEND_RECEIVE2_Pos)
- #define IPC_INTPEND_RECEIVE2_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE2_Pending (1UL)
- #define IPC_INTPEND_RECEIVE1_Pos (1UL)
- #define IPC_INTPEND_RECEIVE1_Msk (0x1UL << IPC_INTPEND_RECEIVE1_Pos)
- #define IPC_INTPEND_RECEIVE1_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE1_Pending (1UL)
- #define IPC_INTPEND_RECEIVE0_Pos (0UL)
- #define IPC_INTPEND_RECEIVE0_Msk (0x1UL << IPC_INTPEND_RECEIVE0_Pos)
- #define IPC_INTPEND_RECEIVE0_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE0_Pending (1UL)
- #define IPC_SEND_CNF_CHEN15_Pos (15UL)
- #define IPC_SEND_CNF_CHEN15_Msk (0x1UL << IPC_SEND_CNF_CHEN15_Pos)
- #define IPC_SEND_CNF_CHEN15_Disable (0UL)
- #define IPC_SEND_CNF_CHEN15_Enable (1UL)
- #define IPC_SEND_CNF_CHEN14_Pos (14UL)
- #define IPC_SEND_CNF_CHEN14_Msk (0x1UL << IPC_SEND_CNF_CHEN14_Pos)
- #define IPC_SEND_CNF_CHEN14_Disable (0UL)
- #define IPC_SEND_CNF_CHEN14_Enable (1UL)
- #define IPC_SEND_CNF_CHEN13_Pos (13UL)
- #define IPC_SEND_CNF_CHEN13_Msk (0x1UL << IPC_SEND_CNF_CHEN13_Pos)
- #define IPC_SEND_CNF_CHEN13_Disable (0UL)
- #define IPC_SEND_CNF_CHEN13_Enable (1UL)
- #define IPC_SEND_CNF_CHEN12_Pos (12UL)
- #define IPC_SEND_CNF_CHEN12_Msk (0x1UL << IPC_SEND_CNF_CHEN12_Pos)
- #define IPC_SEND_CNF_CHEN12_Disable (0UL)
- #define IPC_SEND_CNF_CHEN12_Enable (1UL)
- #define IPC_SEND_CNF_CHEN11_Pos (11UL)
- #define IPC_SEND_CNF_CHEN11_Msk (0x1UL << IPC_SEND_CNF_CHEN11_Pos)
- #define IPC_SEND_CNF_CHEN11_Disable (0UL)
- #define IPC_SEND_CNF_CHEN11_Enable (1UL)
- #define IPC_SEND_CNF_CHEN10_Pos (10UL)
- #define IPC_SEND_CNF_CHEN10_Msk (0x1UL << IPC_SEND_CNF_CHEN10_Pos)
- #define IPC_SEND_CNF_CHEN10_Disable (0UL)
- #define IPC_SEND_CNF_CHEN10_Enable (1UL)
- #define IPC_SEND_CNF_CHEN9_Pos (9UL)
- #define IPC_SEND_CNF_CHEN9_Msk (0x1UL << IPC_SEND_CNF_CHEN9_Pos)
- #define IPC_SEND_CNF_CHEN9_Disable (0UL)
- #define IPC_SEND_CNF_CHEN9_Enable (1UL)
- #define IPC_SEND_CNF_CHEN8_Pos (8UL)
- #define IPC_SEND_CNF_CHEN8_Msk (0x1UL << IPC_SEND_CNF_CHEN8_Pos)
- #define IPC_SEND_CNF_CHEN8_Disable (0UL)
- #define IPC_SEND_CNF_CHEN8_Enable (1UL)
- #define IPC_SEND_CNF_CHEN7_Pos (7UL)
- #define IPC_SEND_CNF_CHEN7_Msk (0x1UL << IPC_SEND_CNF_CHEN7_Pos)
- #define IPC_SEND_CNF_CHEN7_Disable (0UL)
- #define IPC_SEND_CNF_CHEN7_Enable (1UL)
- #define IPC_SEND_CNF_CHEN6_Pos (6UL)
- #define IPC_SEND_CNF_CHEN6_Msk (0x1UL << IPC_SEND_CNF_CHEN6_Pos)
- #define IPC_SEND_CNF_CHEN6_Disable (0UL)
- #define IPC_SEND_CNF_CHEN6_Enable (1UL)
- #define IPC_SEND_CNF_CHEN5_Pos (5UL)
- #define IPC_SEND_CNF_CHEN5_Msk (0x1UL << IPC_SEND_CNF_CHEN5_Pos)
- #define IPC_SEND_CNF_CHEN5_Disable (0UL)
- #define IPC_SEND_CNF_CHEN5_Enable (1UL)
- #define IPC_SEND_CNF_CHEN4_Pos (4UL)
- #define IPC_SEND_CNF_CHEN4_Msk (0x1UL << IPC_SEND_CNF_CHEN4_Pos)
- #define IPC_SEND_CNF_CHEN4_Disable (0UL)
- #define IPC_SEND_CNF_CHEN4_Enable (1UL)
- #define IPC_SEND_CNF_CHEN3_Pos (3UL)
- #define IPC_SEND_CNF_CHEN3_Msk (0x1UL << IPC_SEND_CNF_CHEN3_Pos)
- #define IPC_SEND_CNF_CHEN3_Disable (0UL)
- #define IPC_SEND_CNF_CHEN3_Enable (1UL)
- #define IPC_SEND_CNF_CHEN2_Pos (2UL)
- #define IPC_SEND_CNF_CHEN2_Msk (0x1UL << IPC_SEND_CNF_CHEN2_Pos)
- #define IPC_SEND_CNF_CHEN2_Disable (0UL)
- #define IPC_SEND_CNF_CHEN2_Enable (1UL)
- #define IPC_SEND_CNF_CHEN1_Pos (1UL)
- #define IPC_SEND_CNF_CHEN1_Msk (0x1UL << IPC_SEND_CNF_CHEN1_Pos)
- #define IPC_SEND_CNF_CHEN1_Disable (0UL)
- #define IPC_SEND_CNF_CHEN1_Enable (1UL)
- #define IPC_SEND_CNF_CHEN0_Pos (0UL)
- #define IPC_SEND_CNF_CHEN0_Msk (0x1UL << IPC_SEND_CNF_CHEN0_Pos)
- #define IPC_SEND_CNF_CHEN0_Disable (0UL)
- #define IPC_SEND_CNF_CHEN0_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN15_Pos (15UL)
- #define IPC_RECEIVE_CNF_CHEN15_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN15_Pos)
- #define IPC_RECEIVE_CNF_CHEN15_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN15_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN14_Pos (14UL)
- #define IPC_RECEIVE_CNF_CHEN14_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN14_Pos)
- #define IPC_RECEIVE_CNF_CHEN14_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN14_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN13_Pos (13UL)
- #define IPC_RECEIVE_CNF_CHEN13_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN13_Pos)
- #define IPC_RECEIVE_CNF_CHEN13_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN13_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN12_Pos (12UL)
- #define IPC_RECEIVE_CNF_CHEN12_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN12_Pos)
- #define IPC_RECEIVE_CNF_CHEN12_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN12_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN11_Pos (11UL)
- #define IPC_RECEIVE_CNF_CHEN11_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN11_Pos)
- #define IPC_RECEIVE_CNF_CHEN11_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN11_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN10_Pos (10UL)
- #define IPC_RECEIVE_CNF_CHEN10_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN10_Pos)
- #define IPC_RECEIVE_CNF_CHEN10_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN10_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN9_Pos (9UL)
- #define IPC_RECEIVE_CNF_CHEN9_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN9_Pos)
- #define IPC_RECEIVE_CNF_CHEN9_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN9_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN8_Pos (8UL)
- #define IPC_RECEIVE_CNF_CHEN8_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN8_Pos)
- #define IPC_RECEIVE_CNF_CHEN8_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN8_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN7_Pos (7UL)
- #define IPC_RECEIVE_CNF_CHEN7_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN7_Pos)
- #define IPC_RECEIVE_CNF_CHEN7_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN7_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN6_Pos (6UL)
- #define IPC_RECEIVE_CNF_CHEN6_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN6_Pos)
- #define IPC_RECEIVE_CNF_CHEN6_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN6_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN5_Pos (5UL)
- #define IPC_RECEIVE_CNF_CHEN5_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN5_Pos)
- #define IPC_RECEIVE_CNF_CHEN5_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN5_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN4_Pos (4UL)
- #define IPC_RECEIVE_CNF_CHEN4_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN4_Pos)
- #define IPC_RECEIVE_CNF_CHEN4_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN4_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN3_Pos (3UL)
- #define IPC_RECEIVE_CNF_CHEN3_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN3_Pos)
- #define IPC_RECEIVE_CNF_CHEN3_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN3_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN2_Pos (2UL)
- #define IPC_RECEIVE_CNF_CHEN2_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN2_Pos)
- #define IPC_RECEIVE_CNF_CHEN2_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN2_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN1_Pos (1UL)
- #define IPC_RECEIVE_CNF_CHEN1_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN1_Pos)
- #define IPC_RECEIVE_CNF_CHEN1_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN1_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN0_Pos (0UL)
- #define IPC_RECEIVE_CNF_CHEN0_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN0_Pos)
- #define IPC_RECEIVE_CNF_CHEN0_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN0_Enable (1UL)
- #define IPC_GPMEM_GPMEM_Pos (0UL)
- #define IPC_GPMEM_GPMEM_Msk (0xFFFFFFFFUL << IPC_GPMEM_GPMEM_Pos)
- #define NVMC_READY_READY_Pos (0UL)
- #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos)
- #define NVMC_READY_READY_Busy (0UL)
- #define NVMC_READY_READY_Ready (1UL)
- #define NVMC_READYNEXT_READYNEXT_Pos (0UL)
- #define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos)
- #define NVMC_READYNEXT_READYNEXT_Busy (0UL)
- #define NVMC_READYNEXT_READYNEXT_Ready (1UL)
- #define NVMC_CONFIG_WEN_Pos (0UL)
- #define NVMC_CONFIG_WEN_Msk (0x7UL << NVMC_CONFIG_WEN_Pos)
- #define NVMC_CONFIG_WEN_Ren (0UL)
- #define NVMC_CONFIG_WEN_Wen (1UL)
- #define NVMC_CONFIG_WEN_Een (2UL)
- #define NVMC_CONFIG_WEN_PEen (4UL)
- #define NVMC_ERASEALL_ERASEALL_Pos (0UL)
- #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos)
- #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL)
- #define NVMC_ERASEALL_ERASEALL_Erase (1UL)
- #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL)
- #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos)
- #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL)
- #define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos)
- #define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL)
- #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL)
- #define NVMC_ICACHECNF_CACHEEN_Pos (0UL)
- #define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos)
- #define NVMC_ICACHECNF_CACHEEN_Disabled (0UL)
- #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL)
- #define NVMC_IHIT_HITS_Pos (0UL)
- #define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos)
- #define NVMC_IMISS_MISSES_Pos (0UL)
- #define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos)
- #define GPIO_OUT_PIN31_Pos (31UL)
- #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos)
- #define GPIO_OUT_PIN31_Low (0UL)
- #define GPIO_OUT_PIN31_High (1UL)
- #define GPIO_OUT_PIN30_Pos (30UL)
- #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos)
- #define GPIO_OUT_PIN30_Low (0UL)
- #define GPIO_OUT_PIN30_High (1UL)
- #define GPIO_OUT_PIN29_Pos (29UL)
- #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos)
- #define GPIO_OUT_PIN29_Low (0UL)
- #define GPIO_OUT_PIN29_High (1UL)
- #define GPIO_OUT_PIN28_Pos (28UL)
- #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos)
- #define GPIO_OUT_PIN28_Low (0UL)
- #define GPIO_OUT_PIN28_High (1UL)
- #define GPIO_OUT_PIN27_Pos (27UL)
- #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos)
- #define GPIO_OUT_PIN27_Low (0UL)
- #define GPIO_OUT_PIN27_High (1UL)
- #define GPIO_OUT_PIN26_Pos (26UL)
- #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos)
- #define GPIO_OUT_PIN26_Low (0UL)
- #define GPIO_OUT_PIN26_High (1UL)
- #define GPIO_OUT_PIN25_Pos (25UL)
- #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos)
- #define GPIO_OUT_PIN25_Low (0UL)
- #define GPIO_OUT_PIN25_High (1UL)
- #define GPIO_OUT_PIN24_Pos (24UL)
- #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos)
- #define GPIO_OUT_PIN24_Low (0UL)
- #define GPIO_OUT_PIN24_High (1UL)
- #define GPIO_OUT_PIN23_Pos (23UL)
- #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos)
- #define GPIO_OUT_PIN23_Low (0UL)
- #define GPIO_OUT_PIN23_High (1UL)
- #define GPIO_OUT_PIN22_Pos (22UL)
- #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos)
- #define GPIO_OUT_PIN22_Low (0UL)
- #define GPIO_OUT_PIN22_High (1UL)
- #define GPIO_OUT_PIN21_Pos (21UL)
- #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos)
- #define GPIO_OUT_PIN21_Low (0UL)
- #define GPIO_OUT_PIN21_High (1UL)
- #define GPIO_OUT_PIN20_Pos (20UL)
- #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos)
- #define GPIO_OUT_PIN20_Low (0UL)
- #define GPIO_OUT_PIN20_High (1UL)
- #define GPIO_OUT_PIN19_Pos (19UL)
- #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos)
- #define GPIO_OUT_PIN19_Low (0UL)
- #define GPIO_OUT_PIN19_High (1UL)
- #define GPIO_OUT_PIN18_Pos (18UL)
- #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos)
- #define GPIO_OUT_PIN18_Low (0UL)
- #define GPIO_OUT_PIN18_High (1UL)
- #define GPIO_OUT_PIN17_Pos (17UL)
- #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos)
- #define GPIO_OUT_PIN17_Low (0UL)
- #define GPIO_OUT_PIN17_High (1UL)
- #define GPIO_OUT_PIN16_Pos (16UL)
- #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos)
- #define GPIO_OUT_PIN16_Low (0UL)
- #define GPIO_OUT_PIN16_High (1UL)
- #define GPIO_OUT_PIN15_Pos (15UL)
- #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos)
- #define GPIO_OUT_PIN15_Low (0UL)
- #define GPIO_OUT_PIN15_High (1UL)
- #define GPIO_OUT_PIN14_Pos (14UL)
- #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos)
- #define GPIO_OUT_PIN14_Low (0UL)
- #define GPIO_OUT_PIN14_High (1UL)
- #define GPIO_OUT_PIN13_Pos (13UL)
- #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos)
- #define GPIO_OUT_PIN13_Low (0UL)
- #define GPIO_OUT_PIN13_High (1UL)
- #define GPIO_OUT_PIN12_Pos (12UL)
- #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos)
- #define GPIO_OUT_PIN12_Low (0UL)
- #define GPIO_OUT_PIN12_High (1UL)
- #define GPIO_OUT_PIN11_Pos (11UL)
- #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos)
- #define GPIO_OUT_PIN11_Low (0UL)
- #define GPIO_OUT_PIN11_High (1UL)
- #define GPIO_OUT_PIN10_Pos (10UL)
- #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos)
- #define GPIO_OUT_PIN10_Low (0UL)
- #define GPIO_OUT_PIN10_High (1UL)
- #define GPIO_OUT_PIN9_Pos (9UL)
- #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos)
- #define GPIO_OUT_PIN9_Low (0UL)
- #define GPIO_OUT_PIN9_High (1UL)
- #define GPIO_OUT_PIN8_Pos (8UL)
- #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos)
- #define GPIO_OUT_PIN8_Low (0UL)
- #define GPIO_OUT_PIN8_High (1UL)
- #define GPIO_OUT_PIN7_Pos (7UL)
- #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos)
- #define GPIO_OUT_PIN7_Low (0UL)
- #define GPIO_OUT_PIN7_High (1UL)
- #define GPIO_OUT_PIN6_Pos (6UL)
- #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos)
- #define GPIO_OUT_PIN6_Low (0UL)
- #define GPIO_OUT_PIN6_High (1UL)
- #define GPIO_OUT_PIN5_Pos (5UL)
- #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos)
- #define GPIO_OUT_PIN5_Low (0UL)
- #define GPIO_OUT_PIN5_High (1UL)
- #define GPIO_OUT_PIN4_Pos (4UL)
- #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos)
- #define GPIO_OUT_PIN4_Low (0UL)
- #define GPIO_OUT_PIN4_High (1UL)
- #define GPIO_OUT_PIN3_Pos (3UL)
- #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos)
- #define GPIO_OUT_PIN3_Low (0UL)
- #define GPIO_OUT_PIN3_High (1UL)
- #define GPIO_OUT_PIN2_Pos (2UL)
- #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos)
- #define GPIO_OUT_PIN2_Low (0UL)
- #define GPIO_OUT_PIN2_High (1UL)
- #define GPIO_OUT_PIN1_Pos (1UL)
- #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos)
- #define GPIO_OUT_PIN1_Low (0UL)
- #define GPIO_OUT_PIN1_High (1UL)
- #define GPIO_OUT_PIN0_Pos (0UL)
- #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos)
- #define GPIO_OUT_PIN0_Low (0UL)
- #define GPIO_OUT_PIN0_High (1UL)
- #define GPIO_OUTSET_PIN31_Pos (31UL)
- #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos)
- #define GPIO_OUTSET_PIN31_Low (0UL)
- #define GPIO_OUTSET_PIN31_High (1UL)
- #define GPIO_OUTSET_PIN31_Set (1UL)
- #define GPIO_OUTSET_PIN30_Pos (30UL)
- #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos)
- #define GPIO_OUTSET_PIN30_Low (0UL)
- #define GPIO_OUTSET_PIN30_High (1UL)
- #define GPIO_OUTSET_PIN30_Set (1UL)
- #define GPIO_OUTSET_PIN29_Pos (29UL)
- #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos)
- #define GPIO_OUTSET_PIN29_Low (0UL)
- #define GPIO_OUTSET_PIN29_High (1UL)
- #define GPIO_OUTSET_PIN29_Set (1UL)
- #define GPIO_OUTSET_PIN28_Pos (28UL)
- #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos)
- #define GPIO_OUTSET_PIN28_Low (0UL)
- #define GPIO_OUTSET_PIN28_High (1UL)
- #define GPIO_OUTSET_PIN28_Set (1UL)
- #define GPIO_OUTSET_PIN27_Pos (27UL)
- #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos)
- #define GPIO_OUTSET_PIN27_Low (0UL)
- #define GPIO_OUTSET_PIN27_High (1UL)
- #define GPIO_OUTSET_PIN27_Set (1UL)
- #define GPIO_OUTSET_PIN26_Pos (26UL)
- #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos)
- #define GPIO_OUTSET_PIN26_Low (0UL)
- #define GPIO_OUTSET_PIN26_High (1UL)
- #define GPIO_OUTSET_PIN26_Set (1UL)
- #define GPIO_OUTSET_PIN25_Pos (25UL)
- #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos)
- #define GPIO_OUTSET_PIN25_Low (0UL)
- #define GPIO_OUTSET_PIN25_High (1UL)
- #define GPIO_OUTSET_PIN25_Set (1UL)
- #define GPIO_OUTSET_PIN24_Pos (24UL)
- #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos)
- #define GPIO_OUTSET_PIN24_Low (0UL)
- #define GPIO_OUTSET_PIN24_High (1UL)
- #define GPIO_OUTSET_PIN24_Set (1UL)
- #define GPIO_OUTSET_PIN23_Pos (23UL)
- #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos)
- #define GPIO_OUTSET_PIN23_Low (0UL)
- #define GPIO_OUTSET_PIN23_High (1UL)
- #define GPIO_OUTSET_PIN23_Set (1UL)
- #define GPIO_OUTSET_PIN22_Pos (22UL)
- #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos)
- #define GPIO_OUTSET_PIN22_Low (0UL)
- #define GPIO_OUTSET_PIN22_High (1UL)
- #define GPIO_OUTSET_PIN22_Set (1UL)
- #define GPIO_OUTSET_PIN21_Pos (21UL)
- #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos)
- #define GPIO_OUTSET_PIN21_Low (0UL)
- #define GPIO_OUTSET_PIN21_High (1UL)
- #define GPIO_OUTSET_PIN21_Set (1UL)
- #define GPIO_OUTSET_PIN20_Pos (20UL)
- #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos)
- #define GPIO_OUTSET_PIN20_Low (0UL)
- #define GPIO_OUTSET_PIN20_High (1UL)
- #define GPIO_OUTSET_PIN20_Set (1UL)
- #define GPIO_OUTSET_PIN19_Pos (19UL)
- #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos)
- #define GPIO_OUTSET_PIN19_Low (0UL)
- #define GPIO_OUTSET_PIN19_High (1UL)
- #define GPIO_OUTSET_PIN19_Set (1UL)
- #define GPIO_OUTSET_PIN18_Pos (18UL)
- #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos)
- #define GPIO_OUTSET_PIN18_Low (0UL)
- #define GPIO_OUTSET_PIN18_High (1UL)
- #define GPIO_OUTSET_PIN18_Set (1UL)
- #define GPIO_OUTSET_PIN17_Pos (17UL)
- #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos)
- #define GPIO_OUTSET_PIN17_Low (0UL)
- #define GPIO_OUTSET_PIN17_High (1UL)
- #define GPIO_OUTSET_PIN17_Set (1UL)
- #define GPIO_OUTSET_PIN16_Pos (16UL)
- #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos)
- #define GPIO_OUTSET_PIN16_Low (0UL)
- #define GPIO_OUTSET_PIN16_High (1UL)
- #define GPIO_OUTSET_PIN16_Set (1UL)
- #define GPIO_OUTSET_PIN15_Pos (15UL)
- #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos)
- #define GPIO_OUTSET_PIN15_Low (0UL)
- #define GPIO_OUTSET_PIN15_High (1UL)
- #define GPIO_OUTSET_PIN15_Set (1UL)
- #define GPIO_OUTSET_PIN14_Pos (14UL)
- #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos)
- #define GPIO_OUTSET_PIN14_Low (0UL)
- #define GPIO_OUTSET_PIN14_High (1UL)
- #define GPIO_OUTSET_PIN14_Set (1UL)
- #define GPIO_OUTSET_PIN13_Pos (13UL)
- #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos)
- #define GPIO_OUTSET_PIN13_Low (0UL)
- #define GPIO_OUTSET_PIN13_High (1UL)
- #define GPIO_OUTSET_PIN13_Set (1UL)
- #define GPIO_OUTSET_PIN12_Pos (12UL)
- #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos)
- #define GPIO_OUTSET_PIN12_Low (0UL)
- #define GPIO_OUTSET_PIN12_High (1UL)
- #define GPIO_OUTSET_PIN12_Set (1UL)
- #define GPIO_OUTSET_PIN11_Pos (11UL)
- #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos)
- #define GPIO_OUTSET_PIN11_Low (0UL)
- #define GPIO_OUTSET_PIN11_High (1UL)
- #define GPIO_OUTSET_PIN11_Set (1UL)
- #define GPIO_OUTSET_PIN10_Pos (10UL)
- #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos)
- #define GPIO_OUTSET_PIN10_Low (0UL)
- #define GPIO_OUTSET_PIN10_High (1UL)
- #define GPIO_OUTSET_PIN10_Set (1UL)
- #define GPIO_OUTSET_PIN9_Pos (9UL)
- #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos)
- #define GPIO_OUTSET_PIN9_Low (0UL)
- #define GPIO_OUTSET_PIN9_High (1UL)
- #define GPIO_OUTSET_PIN9_Set (1UL)
- #define GPIO_OUTSET_PIN8_Pos (8UL)
- #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos)
- #define GPIO_OUTSET_PIN8_Low (0UL)
- #define GPIO_OUTSET_PIN8_High (1UL)
- #define GPIO_OUTSET_PIN8_Set (1UL)
- #define GPIO_OUTSET_PIN7_Pos (7UL)
- #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos)
- #define GPIO_OUTSET_PIN7_Low (0UL)
- #define GPIO_OUTSET_PIN7_High (1UL)
- #define GPIO_OUTSET_PIN7_Set (1UL)
- #define GPIO_OUTSET_PIN6_Pos (6UL)
- #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos)
- #define GPIO_OUTSET_PIN6_Low (0UL)
- #define GPIO_OUTSET_PIN6_High (1UL)
- #define GPIO_OUTSET_PIN6_Set (1UL)
- #define GPIO_OUTSET_PIN5_Pos (5UL)
- #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos)
- #define GPIO_OUTSET_PIN5_Low (0UL)
- #define GPIO_OUTSET_PIN5_High (1UL)
- #define GPIO_OUTSET_PIN5_Set (1UL)
- #define GPIO_OUTSET_PIN4_Pos (4UL)
- #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos)
- #define GPIO_OUTSET_PIN4_Low (0UL)
- #define GPIO_OUTSET_PIN4_High (1UL)
- #define GPIO_OUTSET_PIN4_Set (1UL)
- #define GPIO_OUTSET_PIN3_Pos (3UL)
- #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos)
- #define GPIO_OUTSET_PIN3_Low (0UL)
- #define GPIO_OUTSET_PIN3_High (1UL)
- #define GPIO_OUTSET_PIN3_Set (1UL)
- #define GPIO_OUTSET_PIN2_Pos (2UL)
- #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos)
- #define GPIO_OUTSET_PIN2_Low (0UL)
- #define GPIO_OUTSET_PIN2_High (1UL)
- #define GPIO_OUTSET_PIN2_Set (1UL)
- #define GPIO_OUTSET_PIN1_Pos (1UL)
- #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos)
- #define GPIO_OUTSET_PIN1_Low (0UL)
- #define GPIO_OUTSET_PIN1_High (1UL)
- #define GPIO_OUTSET_PIN1_Set (1UL)
- #define GPIO_OUTSET_PIN0_Pos (0UL)
- #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos)
- #define GPIO_OUTSET_PIN0_Low (0UL)
- #define GPIO_OUTSET_PIN0_High (1UL)
- #define GPIO_OUTSET_PIN0_Set (1UL)
- #define GPIO_OUTCLR_PIN31_Pos (31UL)
- #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos)
- #define GPIO_OUTCLR_PIN31_Low (0UL)
- #define GPIO_OUTCLR_PIN31_High (1UL)
- #define GPIO_OUTCLR_PIN31_Clear (1UL)
- #define GPIO_OUTCLR_PIN30_Pos (30UL)
- #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos)
- #define GPIO_OUTCLR_PIN30_Low (0UL)
- #define GPIO_OUTCLR_PIN30_High (1UL)
- #define GPIO_OUTCLR_PIN30_Clear (1UL)
- #define GPIO_OUTCLR_PIN29_Pos (29UL)
- #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos)
- #define GPIO_OUTCLR_PIN29_Low (0UL)
- #define GPIO_OUTCLR_PIN29_High (1UL)
- #define GPIO_OUTCLR_PIN29_Clear (1UL)
- #define GPIO_OUTCLR_PIN28_Pos (28UL)
- #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos)
- #define GPIO_OUTCLR_PIN28_Low (0UL)
- #define GPIO_OUTCLR_PIN28_High (1UL)
- #define GPIO_OUTCLR_PIN28_Clear (1UL)
- #define GPIO_OUTCLR_PIN27_Pos (27UL)
- #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos)
- #define GPIO_OUTCLR_PIN27_Low (0UL)
- #define GPIO_OUTCLR_PIN27_High (1UL)
- #define GPIO_OUTCLR_PIN27_Clear (1UL)
- #define GPIO_OUTCLR_PIN26_Pos (26UL)
- #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos)
- #define GPIO_OUTCLR_PIN26_Low (0UL)
- #define GPIO_OUTCLR_PIN26_High (1UL)
- #define GPIO_OUTCLR_PIN26_Clear (1UL)
- #define GPIO_OUTCLR_PIN25_Pos (25UL)
- #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos)
- #define GPIO_OUTCLR_PIN25_Low (0UL)
- #define GPIO_OUTCLR_PIN25_High (1UL)
- #define GPIO_OUTCLR_PIN25_Clear (1UL)
- #define GPIO_OUTCLR_PIN24_Pos (24UL)
- #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos)
- #define GPIO_OUTCLR_PIN24_Low (0UL)
- #define GPIO_OUTCLR_PIN24_High (1UL)
- #define GPIO_OUTCLR_PIN24_Clear (1UL)
- #define GPIO_OUTCLR_PIN23_Pos (23UL)
- #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos)
- #define GPIO_OUTCLR_PIN23_Low (0UL)
- #define GPIO_OUTCLR_PIN23_High (1UL)
- #define GPIO_OUTCLR_PIN23_Clear (1UL)
- #define GPIO_OUTCLR_PIN22_Pos (22UL)
- #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos)
- #define GPIO_OUTCLR_PIN22_Low (0UL)
- #define GPIO_OUTCLR_PIN22_High (1UL)
- #define GPIO_OUTCLR_PIN22_Clear (1UL)
- #define GPIO_OUTCLR_PIN21_Pos (21UL)
- #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos)
- #define GPIO_OUTCLR_PIN21_Low (0UL)
- #define GPIO_OUTCLR_PIN21_High (1UL)
- #define GPIO_OUTCLR_PIN21_Clear (1UL)
- #define GPIO_OUTCLR_PIN20_Pos (20UL)
- #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos)
- #define GPIO_OUTCLR_PIN20_Low (0UL)
- #define GPIO_OUTCLR_PIN20_High (1UL)
- #define GPIO_OUTCLR_PIN20_Clear (1UL)
- #define GPIO_OUTCLR_PIN19_Pos (19UL)
- #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos)
- #define GPIO_OUTCLR_PIN19_Low (0UL)
- #define GPIO_OUTCLR_PIN19_High (1UL)
- #define GPIO_OUTCLR_PIN19_Clear (1UL)
- #define GPIO_OUTCLR_PIN18_Pos (18UL)
- #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos)
- #define GPIO_OUTCLR_PIN18_Low (0UL)
- #define GPIO_OUTCLR_PIN18_High (1UL)
- #define GPIO_OUTCLR_PIN18_Clear (1UL)
- #define GPIO_OUTCLR_PIN17_Pos (17UL)
- #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos)
- #define GPIO_OUTCLR_PIN17_Low (0UL)
- #define GPIO_OUTCLR_PIN17_High (1UL)
- #define GPIO_OUTCLR_PIN17_Clear (1UL)
- #define GPIO_OUTCLR_PIN16_Pos (16UL)
- #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos)
- #define GPIO_OUTCLR_PIN16_Low (0UL)
- #define GPIO_OUTCLR_PIN16_High (1UL)
- #define GPIO_OUTCLR_PIN16_Clear (1UL)
- #define GPIO_OUTCLR_PIN15_Pos (15UL)
- #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos)
- #define GPIO_OUTCLR_PIN15_Low (0UL)
- #define GPIO_OUTCLR_PIN15_High (1UL)
- #define GPIO_OUTCLR_PIN15_Clear (1UL)
- #define GPIO_OUTCLR_PIN14_Pos (14UL)
- #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos)
- #define GPIO_OUTCLR_PIN14_Low (0UL)
- #define GPIO_OUTCLR_PIN14_High (1UL)
- #define GPIO_OUTCLR_PIN14_Clear (1UL)
- #define GPIO_OUTCLR_PIN13_Pos (13UL)
- #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos)
- #define GPIO_OUTCLR_PIN13_Low (0UL)
- #define GPIO_OUTCLR_PIN13_High (1UL)
- #define GPIO_OUTCLR_PIN13_Clear (1UL)
- #define GPIO_OUTCLR_PIN12_Pos (12UL)
- #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos)
- #define GPIO_OUTCLR_PIN12_Low (0UL)
- #define GPIO_OUTCLR_PIN12_High (1UL)
- #define GPIO_OUTCLR_PIN12_Clear (1UL)
- #define GPIO_OUTCLR_PIN11_Pos (11UL)
- #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos)
- #define GPIO_OUTCLR_PIN11_Low (0UL)
- #define GPIO_OUTCLR_PIN11_High (1UL)
- #define GPIO_OUTCLR_PIN11_Clear (1UL)
- #define GPIO_OUTCLR_PIN10_Pos (10UL)
- #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos)
- #define GPIO_OUTCLR_PIN10_Low (0UL)
- #define GPIO_OUTCLR_PIN10_High (1UL)
- #define GPIO_OUTCLR_PIN10_Clear (1UL)
- #define GPIO_OUTCLR_PIN9_Pos (9UL)
- #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos)
- #define GPIO_OUTCLR_PIN9_Low (0UL)
- #define GPIO_OUTCLR_PIN9_High (1UL)
- #define GPIO_OUTCLR_PIN9_Clear (1UL)
- #define GPIO_OUTCLR_PIN8_Pos (8UL)
- #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos)
- #define GPIO_OUTCLR_PIN8_Low (0UL)
- #define GPIO_OUTCLR_PIN8_High (1UL)
- #define GPIO_OUTCLR_PIN8_Clear (1UL)
- #define GPIO_OUTCLR_PIN7_Pos (7UL)
- #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos)
- #define GPIO_OUTCLR_PIN7_Low (0UL)
- #define GPIO_OUTCLR_PIN7_High (1UL)
- #define GPIO_OUTCLR_PIN7_Clear (1UL)
- #define GPIO_OUTCLR_PIN6_Pos (6UL)
- #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos)
- #define GPIO_OUTCLR_PIN6_Low (0UL)
- #define GPIO_OUTCLR_PIN6_High (1UL)
- #define GPIO_OUTCLR_PIN6_Clear (1UL)
- #define GPIO_OUTCLR_PIN5_Pos (5UL)
- #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos)
- #define GPIO_OUTCLR_PIN5_Low (0UL)
- #define GPIO_OUTCLR_PIN5_High (1UL)
- #define GPIO_OUTCLR_PIN5_Clear (1UL)
- #define GPIO_OUTCLR_PIN4_Pos (4UL)
- #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos)
- #define GPIO_OUTCLR_PIN4_Low (0UL)
- #define GPIO_OUTCLR_PIN4_High (1UL)
- #define GPIO_OUTCLR_PIN4_Clear (1UL)
- #define GPIO_OUTCLR_PIN3_Pos (3UL)
- #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos)
- #define GPIO_OUTCLR_PIN3_Low (0UL)
- #define GPIO_OUTCLR_PIN3_High (1UL)
- #define GPIO_OUTCLR_PIN3_Clear (1UL)
- #define GPIO_OUTCLR_PIN2_Pos (2UL)
- #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos)
- #define GPIO_OUTCLR_PIN2_Low (0UL)
- #define GPIO_OUTCLR_PIN2_High (1UL)
- #define GPIO_OUTCLR_PIN2_Clear (1UL)
- #define GPIO_OUTCLR_PIN1_Pos (1UL)
- #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos)
- #define GPIO_OUTCLR_PIN1_Low (0UL)
- #define GPIO_OUTCLR_PIN1_High (1UL)
- #define GPIO_OUTCLR_PIN1_Clear (1UL)
- #define GPIO_OUTCLR_PIN0_Pos (0UL)
- #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos)
- #define GPIO_OUTCLR_PIN0_Low (0UL)
- #define GPIO_OUTCLR_PIN0_High (1UL)
- #define GPIO_OUTCLR_PIN0_Clear (1UL)
- #define GPIO_IN_PIN31_Pos (31UL)
- #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos)
- #define GPIO_IN_PIN31_Low (0UL)
- #define GPIO_IN_PIN31_High (1UL)
- #define GPIO_IN_PIN30_Pos (30UL)
- #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos)
- #define GPIO_IN_PIN30_Low (0UL)
- #define GPIO_IN_PIN30_High (1UL)
- #define GPIO_IN_PIN29_Pos (29UL)
- #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos)
- #define GPIO_IN_PIN29_Low (0UL)
- #define GPIO_IN_PIN29_High (1UL)
- #define GPIO_IN_PIN28_Pos (28UL)
- #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos)
- #define GPIO_IN_PIN28_Low (0UL)
- #define GPIO_IN_PIN28_High (1UL)
- #define GPIO_IN_PIN27_Pos (27UL)
- #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos)
- #define GPIO_IN_PIN27_Low (0UL)
- #define GPIO_IN_PIN27_High (1UL)
- #define GPIO_IN_PIN26_Pos (26UL)
- #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos)
- #define GPIO_IN_PIN26_Low (0UL)
- #define GPIO_IN_PIN26_High (1UL)
- #define GPIO_IN_PIN25_Pos (25UL)
- #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos)
- #define GPIO_IN_PIN25_Low (0UL)
- #define GPIO_IN_PIN25_High (1UL)
- #define GPIO_IN_PIN24_Pos (24UL)
- #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos)
- #define GPIO_IN_PIN24_Low (0UL)
- #define GPIO_IN_PIN24_High (1UL)
- #define GPIO_IN_PIN23_Pos (23UL)
- #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos)
- #define GPIO_IN_PIN23_Low (0UL)
- #define GPIO_IN_PIN23_High (1UL)
- #define GPIO_IN_PIN22_Pos (22UL)
- #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos)
- #define GPIO_IN_PIN22_Low (0UL)
- #define GPIO_IN_PIN22_High (1UL)
- #define GPIO_IN_PIN21_Pos (21UL)
- #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos)
- #define GPIO_IN_PIN21_Low (0UL)
- #define GPIO_IN_PIN21_High (1UL)
- #define GPIO_IN_PIN20_Pos (20UL)
- #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos)
- #define GPIO_IN_PIN20_Low (0UL)
- #define GPIO_IN_PIN20_High (1UL)
- #define GPIO_IN_PIN19_Pos (19UL)
- #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos)
- #define GPIO_IN_PIN19_Low (0UL)
- #define GPIO_IN_PIN19_High (1UL)
- #define GPIO_IN_PIN18_Pos (18UL)
- #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos)
- #define GPIO_IN_PIN18_Low (0UL)
- #define GPIO_IN_PIN18_High (1UL)
- #define GPIO_IN_PIN17_Pos (17UL)
- #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos)
- #define GPIO_IN_PIN17_Low (0UL)
- #define GPIO_IN_PIN17_High (1UL)
- #define GPIO_IN_PIN16_Pos (16UL)
- #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos)
- #define GPIO_IN_PIN16_Low (0UL)
- #define GPIO_IN_PIN16_High (1UL)
- #define GPIO_IN_PIN15_Pos (15UL)
- #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos)
- #define GPIO_IN_PIN15_Low (0UL)
- #define GPIO_IN_PIN15_High (1UL)
- #define GPIO_IN_PIN14_Pos (14UL)
- #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos)
- #define GPIO_IN_PIN14_Low (0UL)
- #define GPIO_IN_PIN14_High (1UL)
- #define GPIO_IN_PIN13_Pos (13UL)
- #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos)
- #define GPIO_IN_PIN13_Low (0UL)
- #define GPIO_IN_PIN13_High (1UL)
- #define GPIO_IN_PIN12_Pos (12UL)
- #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos)
- #define GPIO_IN_PIN12_Low (0UL)
- #define GPIO_IN_PIN12_High (1UL)
- #define GPIO_IN_PIN11_Pos (11UL)
- #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos)
- #define GPIO_IN_PIN11_Low (0UL)
- #define GPIO_IN_PIN11_High (1UL)
- #define GPIO_IN_PIN10_Pos (10UL)
- #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos)
- #define GPIO_IN_PIN10_Low (0UL)
- #define GPIO_IN_PIN10_High (1UL)
- #define GPIO_IN_PIN9_Pos (9UL)
- #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos)
- #define GPIO_IN_PIN9_Low (0UL)
- #define GPIO_IN_PIN9_High (1UL)
- #define GPIO_IN_PIN8_Pos (8UL)
- #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos)
- #define GPIO_IN_PIN8_Low (0UL)
- #define GPIO_IN_PIN8_High (1UL)
- #define GPIO_IN_PIN7_Pos (7UL)
- #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos)
- #define GPIO_IN_PIN7_Low (0UL)
- #define GPIO_IN_PIN7_High (1UL)
- #define GPIO_IN_PIN6_Pos (6UL)
- #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos)
- #define GPIO_IN_PIN6_Low (0UL)
- #define GPIO_IN_PIN6_High (1UL)
- #define GPIO_IN_PIN5_Pos (5UL)
- #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos)
- #define GPIO_IN_PIN5_Low (0UL)
- #define GPIO_IN_PIN5_High (1UL)
- #define GPIO_IN_PIN4_Pos (4UL)
- #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos)
- #define GPIO_IN_PIN4_Low (0UL)
- #define GPIO_IN_PIN4_High (1UL)
- #define GPIO_IN_PIN3_Pos (3UL)
- #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos)
- #define GPIO_IN_PIN3_Low (0UL)
- #define GPIO_IN_PIN3_High (1UL)
- #define GPIO_IN_PIN2_Pos (2UL)
- #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos)
- #define GPIO_IN_PIN2_Low (0UL)
- #define GPIO_IN_PIN2_High (1UL)
- #define GPIO_IN_PIN1_Pos (1UL)
- #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos)
- #define GPIO_IN_PIN1_Low (0UL)
- #define GPIO_IN_PIN1_High (1UL)
- #define GPIO_IN_PIN0_Pos (0UL)
- #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos)
- #define GPIO_IN_PIN0_Low (0UL)
- #define GPIO_IN_PIN0_High (1UL)
- #define GPIO_DIR_PIN31_Pos (31UL)
- #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos)
- #define GPIO_DIR_PIN31_Input (0UL)
- #define GPIO_DIR_PIN31_Output (1UL)
- #define GPIO_DIR_PIN30_Pos (30UL)
- #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos)
- #define GPIO_DIR_PIN30_Input (0UL)
- #define GPIO_DIR_PIN30_Output (1UL)
- #define GPIO_DIR_PIN29_Pos (29UL)
- #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos)
- #define GPIO_DIR_PIN29_Input (0UL)
- #define GPIO_DIR_PIN29_Output (1UL)
- #define GPIO_DIR_PIN28_Pos (28UL)
- #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos)
- #define GPIO_DIR_PIN28_Input (0UL)
- #define GPIO_DIR_PIN28_Output (1UL)
- #define GPIO_DIR_PIN27_Pos (27UL)
- #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos)
- #define GPIO_DIR_PIN27_Input (0UL)
- #define GPIO_DIR_PIN27_Output (1UL)
- #define GPIO_DIR_PIN26_Pos (26UL)
- #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos)
- #define GPIO_DIR_PIN26_Input (0UL)
- #define GPIO_DIR_PIN26_Output (1UL)
- #define GPIO_DIR_PIN25_Pos (25UL)
- #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos)
- #define GPIO_DIR_PIN25_Input (0UL)
- #define GPIO_DIR_PIN25_Output (1UL)
- #define GPIO_DIR_PIN24_Pos (24UL)
- #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos)
- #define GPIO_DIR_PIN24_Input (0UL)
- #define GPIO_DIR_PIN24_Output (1UL)
- #define GPIO_DIR_PIN23_Pos (23UL)
- #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos)
- #define GPIO_DIR_PIN23_Input (0UL)
- #define GPIO_DIR_PIN23_Output (1UL)
- #define GPIO_DIR_PIN22_Pos (22UL)
- #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos)
- #define GPIO_DIR_PIN22_Input (0UL)
- #define GPIO_DIR_PIN22_Output (1UL)
- #define GPIO_DIR_PIN21_Pos (21UL)
- #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos)
- #define GPIO_DIR_PIN21_Input (0UL)
- #define GPIO_DIR_PIN21_Output (1UL)
- #define GPIO_DIR_PIN20_Pos (20UL)
- #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos)
- #define GPIO_DIR_PIN20_Input (0UL)
- #define GPIO_DIR_PIN20_Output (1UL)
- #define GPIO_DIR_PIN19_Pos (19UL)
- #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos)
- #define GPIO_DIR_PIN19_Input (0UL)
- #define GPIO_DIR_PIN19_Output (1UL)
- #define GPIO_DIR_PIN18_Pos (18UL)
- #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos)
- #define GPIO_DIR_PIN18_Input (0UL)
- #define GPIO_DIR_PIN18_Output (1UL)
- #define GPIO_DIR_PIN17_Pos (17UL)
- #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos)
- #define GPIO_DIR_PIN17_Input (0UL)
- #define GPIO_DIR_PIN17_Output (1UL)
- #define GPIO_DIR_PIN16_Pos (16UL)
- #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos)
- #define GPIO_DIR_PIN16_Input (0UL)
- #define GPIO_DIR_PIN16_Output (1UL)
- #define GPIO_DIR_PIN15_Pos (15UL)
- #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos)
- #define GPIO_DIR_PIN15_Input (0UL)
- #define GPIO_DIR_PIN15_Output (1UL)
- #define GPIO_DIR_PIN14_Pos (14UL)
- #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos)
- #define GPIO_DIR_PIN14_Input (0UL)
- #define GPIO_DIR_PIN14_Output (1UL)
- #define GPIO_DIR_PIN13_Pos (13UL)
- #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos)
- #define GPIO_DIR_PIN13_Input (0UL)
- #define GPIO_DIR_PIN13_Output (1UL)
- #define GPIO_DIR_PIN12_Pos (12UL)
- #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos)
- #define GPIO_DIR_PIN12_Input (0UL)
- #define GPIO_DIR_PIN12_Output (1UL)
- #define GPIO_DIR_PIN11_Pos (11UL)
- #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos)
- #define GPIO_DIR_PIN11_Input (0UL)
- #define GPIO_DIR_PIN11_Output (1UL)
- #define GPIO_DIR_PIN10_Pos (10UL)
- #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos)
- #define GPIO_DIR_PIN10_Input (0UL)
- #define GPIO_DIR_PIN10_Output (1UL)
- #define GPIO_DIR_PIN9_Pos (9UL)
- #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos)
- #define GPIO_DIR_PIN9_Input (0UL)
- #define GPIO_DIR_PIN9_Output (1UL)
- #define GPIO_DIR_PIN8_Pos (8UL)
- #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos)
- #define GPIO_DIR_PIN8_Input (0UL)
- #define GPIO_DIR_PIN8_Output (1UL)
- #define GPIO_DIR_PIN7_Pos (7UL)
- #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos)
- #define GPIO_DIR_PIN7_Input (0UL)
- #define GPIO_DIR_PIN7_Output (1UL)
- #define GPIO_DIR_PIN6_Pos (6UL)
- #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos)
- #define GPIO_DIR_PIN6_Input (0UL)
- #define GPIO_DIR_PIN6_Output (1UL)
- #define GPIO_DIR_PIN5_Pos (5UL)
- #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos)
- #define GPIO_DIR_PIN5_Input (0UL)
- #define GPIO_DIR_PIN5_Output (1UL)
- #define GPIO_DIR_PIN4_Pos (4UL)
- #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos)
- #define GPIO_DIR_PIN4_Input (0UL)
- #define GPIO_DIR_PIN4_Output (1UL)
- #define GPIO_DIR_PIN3_Pos (3UL)
- #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos)
- #define GPIO_DIR_PIN3_Input (0UL)
- #define GPIO_DIR_PIN3_Output (1UL)
- #define GPIO_DIR_PIN2_Pos (2UL)
- #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos)
- #define GPIO_DIR_PIN2_Input (0UL)
- #define GPIO_DIR_PIN2_Output (1UL)
- #define GPIO_DIR_PIN1_Pos (1UL)
- #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos)
- #define GPIO_DIR_PIN1_Input (0UL)
- #define GPIO_DIR_PIN1_Output (1UL)
- #define GPIO_DIR_PIN0_Pos (0UL)
- #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos)
- #define GPIO_DIR_PIN0_Input (0UL)
- #define GPIO_DIR_PIN0_Output (1UL)
- #define GPIO_DIRSET_PIN31_Pos (31UL)
- #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos)
- #define GPIO_DIRSET_PIN31_Input (0UL)
- #define GPIO_DIRSET_PIN31_Output (1UL)
- #define GPIO_DIRSET_PIN31_Set (1UL)
- #define GPIO_DIRSET_PIN30_Pos (30UL)
- #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos)
- #define GPIO_DIRSET_PIN30_Input (0UL)
- #define GPIO_DIRSET_PIN30_Output (1UL)
- #define GPIO_DIRSET_PIN30_Set (1UL)
- #define GPIO_DIRSET_PIN29_Pos (29UL)
- #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos)
- #define GPIO_DIRSET_PIN29_Input (0UL)
- #define GPIO_DIRSET_PIN29_Output (1UL)
- #define GPIO_DIRSET_PIN29_Set (1UL)
- #define GPIO_DIRSET_PIN28_Pos (28UL)
- #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos)
- #define GPIO_DIRSET_PIN28_Input (0UL)
- #define GPIO_DIRSET_PIN28_Output (1UL)
- #define GPIO_DIRSET_PIN28_Set (1UL)
- #define GPIO_DIRSET_PIN27_Pos (27UL)
- #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos)
- #define GPIO_DIRSET_PIN27_Input (0UL)
- #define GPIO_DIRSET_PIN27_Output (1UL)
- #define GPIO_DIRSET_PIN27_Set (1UL)
- #define GPIO_DIRSET_PIN26_Pos (26UL)
- #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos)
- #define GPIO_DIRSET_PIN26_Input (0UL)
- #define GPIO_DIRSET_PIN26_Output (1UL)
- #define GPIO_DIRSET_PIN26_Set (1UL)
- #define GPIO_DIRSET_PIN25_Pos (25UL)
- #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos)
- #define GPIO_DIRSET_PIN25_Input (0UL)
- #define GPIO_DIRSET_PIN25_Output (1UL)
- #define GPIO_DIRSET_PIN25_Set (1UL)
- #define GPIO_DIRSET_PIN24_Pos (24UL)
- #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos)
- #define GPIO_DIRSET_PIN24_Input (0UL)
- #define GPIO_DIRSET_PIN24_Output (1UL)
- #define GPIO_DIRSET_PIN24_Set (1UL)
- #define GPIO_DIRSET_PIN23_Pos (23UL)
- #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos)
- #define GPIO_DIRSET_PIN23_Input (0UL)
- #define GPIO_DIRSET_PIN23_Output (1UL)
- #define GPIO_DIRSET_PIN23_Set (1UL)
- #define GPIO_DIRSET_PIN22_Pos (22UL)
- #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos)
- #define GPIO_DIRSET_PIN22_Input (0UL)
- #define GPIO_DIRSET_PIN22_Output (1UL)
- #define GPIO_DIRSET_PIN22_Set (1UL)
- #define GPIO_DIRSET_PIN21_Pos (21UL)
- #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos)
- #define GPIO_DIRSET_PIN21_Input (0UL)
- #define GPIO_DIRSET_PIN21_Output (1UL)
- #define GPIO_DIRSET_PIN21_Set (1UL)
- #define GPIO_DIRSET_PIN20_Pos (20UL)
- #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos)
- #define GPIO_DIRSET_PIN20_Input (0UL)
- #define GPIO_DIRSET_PIN20_Output (1UL)
- #define GPIO_DIRSET_PIN20_Set (1UL)
- #define GPIO_DIRSET_PIN19_Pos (19UL)
- #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos)
- #define GPIO_DIRSET_PIN19_Input (0UL)
- #define GPIO_DIRSET_PIN19_Output (1UL)
- #define GPIO_DIRSET_PIN19_Set (1UL)
- #define GPIO_DIRSET_PIN18_Pos (18UL)
- #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos)
- #define GPIO_DIRSET_PIN18_Input (0UL)
- #define GPIO_DIRSET_PIN18_Output (1UL)
- #define GPIO_DIRSET_PIN18_Set (1UL)
- #define GPIO_DIRSET_PIN17_Pos (17UL)
- #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos)
- #define GPIO_DIRSET_PIN17_Input (0UL)
- #define GPIO_DIRSET_PIN17_Output (1UL)
- #define GPIO_DIRSET_PIN17_Set (1UL)
- #define GPIO_DIRSET_PIN16_Pos (16UL)
- #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos)
- #define GPIO_DIRSET_PIN16_Input (0UL)
- #define GPIO_DIRSET_PIN16_Output (1UL)
- #define GPIO_DIRSET_PIN16_Set (1UL)
- #define GPIO_DIRSET_PIN15_Pos (15UL)
- #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos)
- #define GPIO_DIRSET_PIN15_Input (0UL)
- #define GPIO_DIRSET_PIN15_Output (1UL)
- #define GPIO_DIRSET_PIN15_Set (1UL)
- #define GPIO_DIRSET_PIN14_Pos (14UL)
- #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos)
- #define GPIO_DIRSET_PIN14_Input (0UL)
- #define GPIO_DIRSET_PIN14_Output (1UL)
- #define GPIO_DIRSET_PIN14_Set (1UL)
- #define GPIO_DIRSET_PIN13_Pos (13UL)
- #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos)
- #define GPIO_DIRSET_PIN13_Input (0UL)
- #define GPIO_DIRSET_PIN13_Output (1UL)
- #define GPIO_DIRSET_PIN13_Set (1UL)
- #define GPIO_DIRSET_PIN12_Pos (12UL)
- #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos)
- #define GPIO_DIRSET_PIN12_Input (0UL)
- #define GPIO_DIRSET_PIN12_Output (1UL)
- #define GPIO_DIRSET_PIN12_Set (1UL)
- #define GPIO_DIRSET_PIN11_Pos (11UL)
- #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos)
- #define GPIO_DIRSET_PIN11_Input (0UL)
- #define GPIO_DIRSET_PIN11_Output (1UL)
- #define GPIO_DIRSET_PIN11_Set (1UL)
- #define GPIO_DIRSET_PIN10_Pos (10UL)
- #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos)
- #define GPIO_DIRSET_PIN10_Input (0UL)
- #define GPIO_DIRSET_PIN10_Output (1UL)
- #define GPIO_DIRSET_PIN10_Set (1UL)
- #define GPIO_DIRSET_PIN9_Pos (9UL)
- #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos)
- #define GPIO_DIRSET_PIN9_Input (0UL)
- #define GPIO_DIRSET_PIN9_Output (1UL)
- #define GPIO_DIRSET_PIN9_Set (1UL)
- #define GPIO_DIRSET_PIN8_Pos (8UL)
- #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos)
- #define GPIO_DIRSET_PIN8_Input (0UL)
- #define GPIO_DIRSET_PIN8_Output (1UL)
- #define GPIO_DIRSET_PIN8_Set (1UL)
- #define GPIO_DIRSET_PIN7_Pos (7UL)
- #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos)
- #define GPIO_DIRSET_PIN7_Input (0UL)
- #define GPIO_DIRSET_PIN7_Output (1UL)
- #define GPIO_DIRSET_PIN7_Set (1UL)
- #define GPIO_DIRSET_PIN6_Pos (6UL)
- #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos)
- #define GPIO_DIRSET_PIN6_Input (0UL)
- #define GPIO_DIRSET_PIN6_Output (1UL)
- #define GPIO_DIRSET_PIN6_Set (1UL)
- #define GPIO_DIRSET_PIN5_Pos (5UL)
- #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos)
- #define GPIO_DIRSET_PIN5_Input (0UL)
- #define GPIO_DIRSET_PIN5_Output (1UL)
- #define GPIO_DIRSET_PIN5_Set (1UL)
- #define GPIO_DIRSET_PIN4_Pos (4UL)
- #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos)
- #define GPIO_DIRSET_PIN4_Input (0UL)
- #define GPIO_DIRSET_PIN4_Output (1UL)
- #define GPIO_DIRSET_PIN4_Set (1UL)
- #define GPIO_DIRSET_PIN3_Pos (3UL)
- #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos)
- #define GPIO_DIRSET_PIN3_Input (0UL)
- #define GPIO_DIRSET_PIN3_Output (1UL)
- #define GPIO_DIRSET_PIN3_Set (1UL)
- #define GPIO_DIRSET_PIN2_Pos (2UL)
- #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos)
- #define GPIO_DIRSET_PIN2_Input (0UL)
- #define GPIO_DIRSET_PIN2_Output (1UL)
- #define GPIO_DIRSET_PIN2_Set (1UL)
- #define GPIO_DIRSET_PIN1_Pos (1UL)
- #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos)
- #define GPIO_DIRSET_PIN1_Input (0UL)
- #define GPIO_DIRSET_PIN1_Output (1UL)
- #define GPIO_DIRSET_PIN1_Set (1UL)
- #define GPIO_DIRSET_PIN0_Pos (0UL)
- #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos)
- #define GPIO_DIRSET_PIN0_Input (0UL)
- #define GPIO_DIRSET_PIN0_Output (1UL)
- #define GPIO_DIRSET_PIN0_Set (1UL)
- #define GPIO_DIRCLR_PIN31_Pos (31UL)
- #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos)
- #define GPIO_DIRCLR_PIN31_Input (0UL)
- #define GPIO_DIRCLR_PIN31_Output (1UL)
- #define GPIO_DIRCLR_PIN31_Clear (1UL)
- #define GPIO_DIRCLR_PIN30_Pos (30UL)
- #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos)
- #define GPIO_DIRCLR_PIN30_Input (0UL)
- #define GPIO_DIRCLR_PIN30_Output (1UL)
- #define GPIO_DIRCLR_PIN30_Clear (1UL)
- #define GPIO_DIRCLR_PIN29_Pos (29UL)
- #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos)
- #define GPIO_DIRCLR_PIN29_Input (0UL)
- #define GPIO_DIRCLR_PIN29_Output (1UL)
- #define GPIO_DIRCLR_PIN29_Clear (1UL)
- #define GPIO_DIRCLR_PIN28_Pos (28UL)
- #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos)
- #define GPIO_DIRCLR_PIN28_Input (0UL)
- #define GPIO_DIRCLR_PIN28_Output (1UL)
- #define GPIO_DIRCLR_PIN28_Clear (1UL)
- #define GPIO_DIRCLR_PIN27_Pos (27UL)
- #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos)
- #define GPIO_DIRCLR_PIN27_Input (0UL)
- #define GPIO_DIRCLR_PIN27_Output (1UL)
- #define GPIO_DIRCLR_PIN27_Clear (1UL)
- #define GPIO_DIRCLR_PIN26_Pos (26UL)
- #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos)
- #define GPIO_DIRCLR_PIN26_Input (0UL)
- #define GPIO_DIRCLR_PIN26_Output (1UL)
- #define GPIO_DIRCLR_PIN26_Clear (1UL)
- #define GPIO_DIRCLR_PIN25_Pos (25UL)
- #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos)
- #define GPIO_DIRCLR_PIN25_Input (0UL)
- #define GPIO_DIRCLR_PIN25_Output (1UL)
- #define GPIO_DIRCLR_PIN25_Clear (1UL)
- #define GPIO_DIRCLR_PIN24_Pos (24UL)
- #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos)
- #define GPIO_DIRCLR_PIN24_Input (0UL)
- #define GPIO_DIRCLR_PIN24_Output (1UL)
- #define GPIO_DIRCLR_PIN24_Clear (1UL)
- #define GPIO_DIRCLR_PIN23_Pos (23UL)
- #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos)
- #define GPIO_DIRCLR_PIN23_Input (0UL)
- #define GPIO_DIRCLR_PIN23_Output (1UL)
- #define GPIO_DIRCLR_PIN23_Clear (1UL)
- #define GPIO_DIRCLR_PIN22_Pos (22UL)
- #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos)
- #define GPIO_DIRCLR_PIN22_Input (0UL)
- #define GPIO_DIRCLR_PIN22_Output (1UL)
- #define GPIO_DIRCLR_PIN22_Clear (1UL)
- #define GPIO_DIRCLR_PIN21_Pos (21UL)
- #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos)
- #define GPIO_DIRCLR_PIN21_Input (0UL)
- #define GPIO_DIRCLR_PIN21_Output (1UL)
- #define GPIO_DIRCLR_PIN21_Clear (1UL)
- #define GPIO_DIRCLR_PIN20_Pos (20UL)
- #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos)
- #define GPIO_DIRCLR_PIN20_Input (0UL)
- #define GPIO_DIRCLR_PIN20_Output (1UL)
- #define GPIO_DIRCLR_PIN20_Clear (1UL)
- #define GPIO_DIRCLR_PIN19_Pos (19UL)
- #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos)
- #define GPIO_DIRCLR_PIN19_Input (0UL)
- #define GPIO_DIRCLR_PIN19_Output (1UL)
- #define GPIO_DIRCLR_PIN19_Clear (1UL)
- #define GPIO_DIRCLR_PIN18_Pos (18UL)
- #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos)
- #define GPIO_DIRCLR_PIN18_Input (0UL)
- #define GPIO_DIRCLR_PIN18_Output (1UL)
- #define GPIO_DIRCLR_PIN18_Clear (1UL)
- #define GPIO_DIRCLR_PIN17_Pos (17UL)
- #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos)
- #define GPIO_DIRCLR_PIN17_Input (0UL)
- #define GPIO_DIRCLR_PIN17_Output (1UL)
- #define GPIO_DIRCLR_PIN17_Clear (1UL)
- #define GPIO_DIRCLR_PIN16_Pos (16UL)
- #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos)
- #define GPIO_DIRCLR_PIN16_Input (0UL)
- #define GPIO_DIRCLR_PIN16_Output (1UL)
- #define GPIO_DIRCLR_PIN16_Clear (1UL)
- #define GPIO_DIRCLR_PIN15_Pos (15UL)
- #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos)
- #define GPIO_DIRCLR_PIN15_Input (0UL)
- #define GPIO_DIRCLR_PIN15_Output (1UL)
- #define GPIO_DIRCLR_PIN15_Clear (1UL)
- #define GPIO_DIRCLR_PIN14_Pos (14UL)
- #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos)
- #define GPIO_DIRCLR_PIN14_Input (0UL)
- #define GPIO_DIRCLR_PIN14_Output (1UL)
- #define GPIO_DIRCLR_PIN14_Clear (1UL)
- #define GPIO_DIRCLR_PIN13_Pos (13UL)
- #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos)
- #define GPIO_DIRCLR_PIN13_Input (0UL)
- #define GPIO_DIRCLR_PIN13_Output (1UL)
- #define GPIO_DIRCLR_PIN13_Clear (1UL)
- #define GPIO_DIRCLR_PIN12_Pos (12UL)
- #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos)
- #define GPIO_DIRCLR_PIN12_Input (0UL)
- #define GPIO_DIRCLR_PIN12_Output (1UL)
- #define GPIO_DIRCLR_PIN12_Clear (1UL)
- #define GPIO_DIRCLR_PIN11_Pos (11UL)
- #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos)
- #define GPIO_DIRCLR_PIN11_Input (0UL)
- #define GPIO_DIRCLR_PIN11_Output (1UL)
- #define GPIO_DIRCLR_PIN11_Clear (1UL)
- #define GPIO_DIRCLR_PIN10_Pos (10UL)
- #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos)
- #define GPIO_DIRCLR_PIN10_Input (0UL)
- #define GPIO_DIRCLR_PIN10_Output (1UL)
- #define GPIO_DIRCLR_PIN10_Clear (1UL)
- #define GPIO_DIRCLR_PIN9_Pos (9UL)
- #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos)
- #define GPIO_DIRCLR_PIN9_Input (0UL)
- #define GPIO_DIRCLR_PIN9_Output (1UL)
- #define GPIO_DIRCLR_PIN9_Clear (1UL)
- #define GPIO_DIRCLR_PIN8_Pos (8UL)
- #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos)
- #define GPIO_DIRCLR_PIN8_Input (0UL)
- #define GPIO_DIRCLR_PIN8_Output (1UL)
- #define GPIO_DIRCLR_PIN8_Clear (1UL)
- #define GPIO_DIRCLR_PIN7_Pos (7UL)
- #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos)
- #define GPIO_DIRCLR_PIN7_Input (0UL)
- #define GPIO_DIRCLR_PIN7_Output (1UL)
- #define GPIO_DIRCLR_PIN7_Clear (1UL)
- #define GPIO_DIRCLR_PIN6_Pos (6UL)
- #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos)
- #define GPIO_DIRCLR_PIN6_Input (0UL)
- #define GPIO_DIRCLR_PIN6_Output (1UL)
- #define GPIO_DIRCLR_PIN6_Clear (1UL)
- #define GPIO_DIRCLR_PIN5_Pos (5UL)
- #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos)
- #define GPIO_DIRCLR_PIN5_Input (0UL)
- #define GPIO_DIRCLR_PIN5_Output (1UL)
- #define GPIO_DIRCLR_PIN5_Clear (1UL)
- #define GPIO_DIRCLR_PIN4_Pos (4UL)
- #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos)
- #define GPIO_DIRCLR_PIN4_Input (0UL)
- #define GPIO_DIRCLR_PIN4_Output (1UL)
- #define GPIO_DIRCLR_PIN4_Clear (1UL)
- #define GPIO_DIRCLR_PIN3_Pos (3UL)
- #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos)
- #define GPIO_DIRCLR_PIN3_Input (0UL)
- #define GPIO_DIRCLR_PIN3_Output (1UL)
- #define GPIO_DIRCLR_PIN3_Clear (1UL)
- #define GPIO_DIRCLR_PIN2_Pos (2UL)
- #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos)
- #define GPIO_DIRCLR_PIN2_Input (0UL)
- #define GPIO_DIRCLR_PIN2_Output (1UL)
- #define GPIO_DIRCLR_PIN2_Clear (1UL)
- #define GPIO_DIRCLR_PIN1_Pos (1UL)
- #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos)
- #define GPIO_DIRCLR_PIN1_Input (0UL)
- #define GPIO_DIRCLR_PIN1_Output (1UL)
- #define GPIO_DIRCLR_PIN1_Clear (1UL)
- #define GPIO_DIRCLR_PIN0_Pos (0UL)
- #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos)
- #define GPIO_DIRCLR_PIN0_Input (0UL)
- #define GPIO_DIRCLR_PIN0_Output (1UL)
- #define GPIO_DIRCLR_PIN0_Clear (1UL)
- #define GPIO_LATCH_PIN31_Pos (31UL)
- #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos)
- #define GPIO_LATCH_PIN31_NotLatched (0UL)
- #define GPIO_LATCH_PIN31_Latched (1UL)
- #define GPIO_LATCH_PIN30_Pos (30UL)
- #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos)
- #define GPIO_LATCH_PIN30_NotLatched (0UL)
- #define GPIO_LATCH_PIN30_Latched (1UL)
- #define GPIO_LATCH_PIN29_Pos (29UL)
- #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos)
- #define GPIO_LATCH_PIN29_NotLatched (0UL)
- #define GPIO_LATCH_PIN29_Latched (1UL)
- #define GPIO_LATCH_PIN28_Pos (28UL)
- #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos)
- #define GPIO_LATCH_PIN28_NotLatched (0UL)
- #define GPIO_LATCH_PIN28_Latched (1UL)
- #define GPIO_LATCH_PIN27_Pos (27UL)
- #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos)
- #define GPIO_LATCH_PIN27_NotLatched (0UL)
- #define GPIO_LATCH_PIN27_Latched (1UL)
- #define GPIO_LATCH_PIN26_Pos (26UL)
- #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos)
- #define GPIO_LATCH_PIN26_NotLatched (0UL)
- #define GPIO_LATCH_PIN26_Latched (1UL)
- #define GPIO_LATCH_PIN25_Pos (25UL)
- #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos)
- #define GPIO_LATCH_PIN25_NotLatched (0UL)
- #define GPIO_LATCH_PIN25_Latched (1UL)
- #define GPIO_LATCH_PIN24_Pos (24UL)
- #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos)
- #define GPIO_LATCH_PIN24_NotLatched (0UL)
- #define GPIO_LATCH_PIN24_Latched (1UL)
- #define GPIO_LATCH_PIN23_Pos (23UL)
- #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos)
- #define GPIO_LATCH_PIN23_NotLatched (0UL)
- #define GPIO_LATCH_PIN23_Latched (1UL)
- #define GPIO_LATCH_PIN22_Pos (22UL)
- #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos)
- #define GPIO_LATCH_PIN22_NotLatched (0UL)
- #define GPIO_LATCH_PIN22_Latched (1UL)
- #define GPIO_LATCH_PIN21_Pos (21UL)
- #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos)
- #define GPIO_LATCH_PIN21_NotLatched (0UL)
- #define GPIO_LATCH_PIN21_Latched (1UL)
- #define GPIO_LATCH_PIN20_Pos (20UL)
- #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos)
- #define GPIO_LATCH_PIN20_NotLatched (0UL)
- #define GPIO_LATCH_PIN20_Latched (1UL)
- #define GPIO_LATCH_PIN19_Pos (19UL)
- #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos)
- #define GPIO_LATCH_PIN19_NotLatched (0UL)
- #define GPIO_LATCH_PIN19_Latched (1UL)
- #define GPIO_LATCH_PIN18_Pos (18UL)
- #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos)
- #define GPIO_LATCH_PIN18_NotLatched (0UL)
- #define GPIO_LATCH_PIN18_Latched (1UL)
- #define GPIO_LATCH_PIN17_Pos (17UL)
- #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos)
- #define GPIO_LATCH_PIN17_NotLatched (0UL)
- #define GPIO_LATCH_PIN17_Latched (1UL)
- #define GPIO_LATCH_PIN16_Pos (16UL)
- #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos)
- #define GPIO_LATCH_PIN16_NotLatched (0UL)
- #define GPIO_LATCH_PIN16_Latched (1UL)
- #define GPIO_LATCH_PIN15_Pos (15UL)
- #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos)
- #define GPIO_LATCH_PIN15_NotLatched (0UL)
- #define GPIO_LATCH_PIN15_Latched (1UL)
- #define GPIO_LATCH_PIN14_Pos (14UL)
- #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos)
- #define GPIO_LATCH_PIN14_NotLatched (0UL)
- #define GPIO_LATCH_PIN14_Latched (1UL)
- #define GPIO_LATCH_PIN13_Pos (13UL)
- #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos)
- #define GPIO_LATCH_PIN13_NotLatched (0UL)
- #define GPIO_LATCH_PIN13_Latched (1UL)
- #define GPIO_LATCH_PIN12_Pos (12UL)
- #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos)
- #define GPIO_LATCH_PIN12_NotLatched (0UL)
- #define GPIO_LATCH_PIN12_Latched (1UL)
- #define GPIO_LATCH_PIN11_Pos (11UL)
- #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos)
- #define GPIO_LATCH_PIN11_NotLatched (0UL)
- #define GPIO_LATCH_PIN11_Latched (1UL)
- #define GPIO_LATCH_PIN10_Pos (10UL)
- #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos)
- #define GPIO_LATCH_PIN10_NotLatched (0UL)
- #define GPIO_LATCH_PIN10_Latched (1UL)
- #define GPIO_LATCH_PIN9_Pos (9UL)
- #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos)
- #define GPIO_LATCH_PIN9_NotLatched (0UL)
- #define GPIO_LATCH_PIN9_Latched (1UL)
- #define GPIO_LATCH_PIN8_Pos (8UL)
- #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos)
- #define GPIO_LATCH_PIN8_NotLatched (0UL)
- #define GPIO_LATCH_PIN8_Latched (1UL)
- #define GPIO_LATCH_PIN7_Pos (7UL)
- #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos)
- #define GPIO_LATCH_PIN7_NotLatched (0UL)
- #define GPIO_LATCH_PIN7_Latched (1UL)
- #define GPIO_LATCH_PIN6_Pos (6UL)
- #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos)
- #define GPIO_LATCH_PIN6_NotLatched (0UL)
- #define GPIO_LATCH_PIN6_Latched (1UL)
- #define GPIO_LATCH_PIN5_Pos (5UL)
- #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos)
- #define GPIO_LATCH_PIN5_NotLatched (0UL)
- #define GPIO_LATCH_PIN5_Latched (1UL)
- #define GPIO_LATCH_PIN4_Pos (4UL)
- #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos)
- #define GPIO_LATCH_PIN4_NotLatched (0UL)
- #define GPIO_LATCH_PIN4_Latched (1UL)
- #define GPIO_LATCH_PIN3_Pos (3UL)
- #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos)
- #define GPIO_LATCH_PIN3_NotLatched (0UL)
- #define GPIO_LATCH_PIN3_Latched (1UL)
- #define GPIO_LATCH_PIN2_Pos (2UL)
- #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos)
- #define GPIO_LATCH_PIN2_NotLatched (0UL)
- #define GPIO_LATCH_PIN2_Latched (1UL)
- #define GPIO_LATCH_PIN1_Pos (1UL)
- #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos)
- #define GPIO_LATCH_PIN1_NotLatched (0UL)
- #define GPIO_LATCH_PIN1_Latched (1UL)
- #define GPIO_LATCH_PIN0_Pos (0UL)
- #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos)
- #define GPIO_LATCH_PIN0_NotLatched (0UL)
- #define GPIO_LATCH_PIN0_Latched (1UL)
- #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL)
- #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos)
- #define GPIO_DETECTMODE_DETECTMODE_Default (0UL)
- #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL)
- #define GPIO_DETECTMODE_SEC_DETECTMODE_Pos (0UL)
- #define GPIO_DETECTMODE_SEC_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_SEC_DETECTMODE_Pos)
- #define GPIO_DETECTMODE_SEC_DETECTMODE_Default (0UL)
- #define GPIO_DETECTMODE_SEC_DETECTMODE_LDETECT (1UL)
- #define GPIO_PIN_CNF_MCUSEL_Pos (28UL)
- #define GPIO_PIN_CNF_MCUSEL_Msk (0x7UL << GPIO_PIN_CNF_MCUSEL_Pos)
- #define GPIO_PIN_CNF_MCUSEL_AppMCU (0x0UL)
- #define GPIO_PIN_CNF_MCUSEL_NetworkMCU (0x1UL)
- #define GPIO_PIN_CNF_MCUSEL_Peripheral (0x3UL)
- #define GPIO_PIN_CNF_MCUSEL_TND (0x7UL)
- #define GPIO_PIN_CNF_SENSE_Pos (16UL)
- #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos)
- #define GPIO_PIN_CNF_SENSE_Disabled (0UL)
- #define GPIO_PIN_CNF_SENSE_High (2UL)
- #define GPIO_PIN_CNF_SENSE_Low (3UL)
- #define GPIO_PIN_CNF_DRIVE_Pos (8UL)
- #define GPIO_PIN_CNF_DRIVE_Msk (0xFUL << GPIO_PIN_CNF_DRIVE_Pos)
- #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL)
- #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL)
- #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL)
- #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL)
- #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL)
- #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL)
- #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL)
- #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL)
- #define GPIO_PIN_CNF_DRIVE_E0E1 (11UL)
- #define GPIO_PIN_CNF_PULL_Pos (2UL)
- #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos)
- #define GPIO_PIN_CNF_PULL_Disabled (0UL)
- #define GPIO_PIN_CNF_PULL_Pulldown (1UL)
- #define GPIO_PIN_CNF_PULL_Pullup (3UL)
- #define GPIO_PIN_CNF_INPUT_Pos (1UL)
- #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos)
- #define GPIO_PIN_CNF_INPUT_Connect (0UL)
- #define GPIO_PIN_CNF_INPUT_Disconnect (1UL)
- #define GPIO_PIN_CNF_DIR_Pos (0UL)
- #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos)
- #define GPIO_PIN_CNF_DIR_Input (0UL)
- #define GPIO_PIN_CNF_DIR_Output (1UL)
- #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL)
- #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos)
- #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL)
- #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL)
- #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos)
- #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL)
- #define POWER_SUBSCRIBE_CONSTLAT_EN_Pos (31UL)
- #define POWER_SUBSCRIBE_CONSTLAT_EN_Msk (0x1UL << POWER_SUBSCRIBE_CONSTLAT_EN_Pos)
- #define POWER_SUBSCRIBE_CONSTLAT_EN_Disabled (0UL)
- #define POWER_SUBSCRIBE_CONSTLAT_EN_Enabled (1UL)
- #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos (0UL)
- #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos)
- #define POWER_SUBSCRIBE_LOWPWR_EN_Pos (31UL)
- #define POWER_SUBSCRIBE_LOWPWR_EN_Msk (0x1UL << POWER_SUBSCRIBE_LOWPWR_EN_Pos)
- #define POWER_SUBSCRIBE_LOWPWR_EN_Disabled (0UL)
- #define POWER_SUBSCRIBE_LOWPWR_EN_Enabled (1UL)
- #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos (0UL)
- #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos)
- #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL)
- #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos)
- #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL)
- #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL)
- #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL)
- #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos)
- #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL)
- #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL)
- #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL)
- #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos)
- #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL)
- #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL)
- #define POWER_PUBLISH_POFWARN_EN_Pos (31UL)
- #define POWER_PUBLISH_POFWARN_EN_Msk (0x1UL << POWER_PUBLISH_POFWARN_EN_Pos)
- #define POWER_PUBLISH_POFWARN_EN_Disabled (0UL)
- #define POWER_PUBLISH_POFWARN_EN_Enabled (1UL)
- #define POWER_PUBLISH_POFWARN_CHIDX_Pos (0UL)
- #define POWER_PUBLISH_POFWARN_CHIDX_Msk (0xFFUL << POWER_PUBLISH_POFWARN_CHIDX_Pos)
- #define POWER_PUBLISH_SLEEPENTER_EN_Pos (31UL)
- #define POWER_PUBLISH_SLEEPENTER_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPENTER_EN_Pos)
- #define POWER_PUBLISH_SLEEPENTER_EN_Disabled (0UL)
- #define POWER_PUBLISH_SLEEPENTER_EN_Enabled (1UL)
- #define POWER_PUBLISH_SLEEPENTER_CHIDX_Pos (0UL)
- #define POWER_PUBLISH_SLEEPENTER_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPENTER_CHIDX_Pos)
- #define POWER_PUBLISH_SLEEPEXIT_EN_Pos (31UL)
- #define POWER_PUBLISH_SLEEPEXIT_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPEXIT_EN_Pos)
- #define POWER_PUBLISH_SLEEPEXIT_EN_Disabled (0UL)
- #define POWER_PUBLISH_SLEEPEXIT_EN_Enabled (1UL)
- #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos (0UL)
- #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos)
- #define POWER_INTEN_SLEEPEXIT_Pos (6UL)
- #define POWER_INTEN_SLEEPEXIT_Msk (0x1UL << POWER_INTEN_SLEEPEXIT_Pos)
- #define POWER_INTEN_SLEEPEXIT_Disabled (0UL)
- #define POWER_INTEN_SLEEPEXIT_Enabled (1UL)
- #define POWER_INTEN_SLEEPENTER_Pos (5UL)
- #define POWER_INTEN_SLEEPENTER_Msk (0x1UL << POWER_INTEN_SLEEPENTER_Pos)
- #define POWER_INTEN_SLEEPENTER_Disabled (0UL)
- #define POWER_INTEN_SLEEPENTER_Enabled (1UL)
- #define POWER_INTEN_POFWARN_Pos (2UL)
- #define POWER_INTEN_POFWARN_Msk (0x1UL << POWER_INTEN_POFWARN_Pos)
- #define POWER_INTEN_POFWARN_Disabled (0UL)
- #define POWER_INTEN_POFWARN_Enabled (1UL)
- #define POWER_INTENSET_SLEEPEXIT_Pos (6UL)
- #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos)
- #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL)
- #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL)
- #define POWER_INTENSET_SLEEPEXIT_Set (1UL)
- #define POWER_INTENSET_SLEEPENTER_Pos (5UL)
- #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos)
- #define POWER_INTENSET_SLEEPENTER_Disabled (0UL)
- #define POWER_INTENSET_SLEEPENTER_Enabled (1UL)
- #define POWER_INTENSET_SLEEPENTER_Set (1UL)
- #define POWER_INTENSET_POFWARN_Pos (2UL)
- #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos)
- #define POWER_INTENSET_POFWARN_Disabled (0UL)
- #define POWER_INTENSET_POFWARN_Enabled (1UL)
- #define POWER_INTENSET_POFWARN_Set (1UL)
- #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL)
- #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos)
- #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL)
- #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL)
- #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL)
- #define POWER_INTENCLR_SLEEPENTER_Pos (5UL)
- #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos)
- #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL)
- #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL)
- #define POWER_INTENCLR_SLEEPENTER_Clear (1UL)
- #define POWER_INTENCLR_POFWARN_Pos (2UL)
- #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos)
- #define POWER_INTENCLR_POFWARN_Disabled (0UL)
- #define POWER_INTENCLR_POFWARN_Enabled (1UL)
- #define POWER_INTENCLR_POFWARN_Clear (1UL)
- #define POWER_GPREGRET_GPREGRET_Pos (0UL)
- #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos)
- #define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL)
- #define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos)
- #define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (1UL)
- #define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL)
- #define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos)
- #define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (1UL)
- #define RADIO_TASKS_START_TASKS_START_Pos (0UL)
- #define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos)
- #define RADIO_TASKS_START_TASKS_START_Trigger (1UL)
- #define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos)
- #define RADIO_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL)
- #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos)
- #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL)
- #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL)
- #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos)
- #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (1UL)
- #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL)
- #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos)
- #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Trigger (1UL)
- #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL)
- #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos)
- #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (1UL)
- #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL)
- #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos)
- #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (1UL)
- #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos (0UL)
- #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk (0x1UL << RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos)
- #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Trigger (1UL)
- #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos (0UL)
- #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk (0x1UL << RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos)
- #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Trigger (1UL)
- #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos (0UL)
- #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk (0x1UL << RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos)
- #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Trigger (1UL)
- #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos (0UL)
- #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk (0x1UL << RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos)
- #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Trigger (1UL)
- #define RADIO_SUBSCRIBE_TXEN_EN_Pos (31UL)
- #define RADIO_SUBSCRIBE_TXEN_EN_Msk (0x1UL << RADIO_SUBSCRIBE_TXEN_EN_Pos)
- #define RADIO_SUBSCRIBE_TXEN_EN_Disabled (0UL)
- #define RADIO_SUBSCRIBE_TXEN_EN_Enabled (1UL)
- #define RADIO_SUBSCRIBE_TXEN_CHIDX_Pos (0UL)
- #define RADIO_SUBSCRIBE_TXEN_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_TXEN_CHIDX_Pos)
- #define RADIO_SUBSCRIBE_RXEN_EN_Pos (31UL)
- #define RADIO_SUBSCRIBE_RXEN_EN_Msk (0x1UL << RADIO_SUBSCRIBE_RXEN_EN_Pos)
- #define RADIO_SUBSCRIBE_RXEN_EN_Disabled (0UL)
- #define RADIO_SUBSCRIBE_RXEN_EN_Enabled (1UL)
- #define RADIO_SUBSCRIBE_RXEN_CHIDX_Pos (0UL)
- #define RADIO_SUBSCRIBE_RXEN_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RXEN_CHIDX_Pos)
- #define RADIO_SUBSCRIBE_START_EN_Pos (31UL)
- #define RADIO_SUBSCRIBE_START_EN_Msk (0x1UL << RADIO_SUBSCRIBE_START_EN_Pos)
- #define RADIO_SUBSCRIBE_START_EN_Disabled (0UL)
- #define RADIO_SUBSCRIBE_START_EN_Enabled (1UL)
- #define RADIO_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define RADIO_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_START_CHIDX_Pos)
- #define RADIO_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define RADIO_SUBSCRIBE_STOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_STOP_EN_Pos)
- #define RADIO_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define RADIO_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define RADIO_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define RADIO_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_STOP_CHIDX_Pos)
- #define RADIO_SUBSCRIBE_DISABLE_EN_Pos (31UL)
- #define RADIO_SUBSCRIBE_DISABLE_EN_Msk (0x1UL << RADIO_SUBSCRIBE_DISABLE_EN_Pos)
- #define RADIO_SUBSCRIBE_DISABLE_EN_Disabled (0UL)
- #define RADIO_SUBSCRIBE_DISABLE_EN_Enabled (1UL)
- #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Pos (0UL)
- #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_DISABLE_CHIDX_Pos)
- #define RADIO_SUBSCRIBE_RSSISTART_EN_Pos (31UL)
- #define RADIO_SUBSCRIBE_RSSISTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_RSSISTART_EN_Pos)
- #define RADIO_SUBSCRIBE_RSSISTART_EN_Disabled (0UL)
- #define RADIO_SUBSCRIBE_RSSISTART_EN_Enabled (1UL)
- #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Pos (0UL)
- #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RSSISTART_CHIDX_Pos)
- #define RADIO_SUBSCRIBE_RSSISTOP_EN_Pos (31UL)
- #define RADIO_SUBSCRIBE_RSSISTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_RSSISTOP_EN_Pos)
- #define RADIO_SUBSCRIBE_RSSISTOP_EN_Disabled (0UL)
- #define RADIO_SUBSCRIBE_RSSISTOP_EN_Enabled (1UL)
- #define RADIO_SUBSCRIBE_RSSISTOP_CHIDX_Pos (0UL)
- #define RADIO_SUBSCRIBE_RSSISTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RSSISTOP_CHIDX_Pos)
- #define RADIO_SUBSCRIBE_BCSTART_EN_Pos (31UL)
- #define RADIO_SUBSCRIBE_BCSTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_BCSTART_EN_Pos)
- #define RADIO_SUBSCRIBE_BCSTART_EN_Disabled (0UL)
- #define RADIO_SUBSCRIBE_BCSTART_EN_Enabled (1UL)
- #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Pos (0UL)
- #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_BCSTART_CHIDX_Pos)
- #define RADIO_SUBSCRIBE_BCSTOP_EN_Pos (31UL)
- #define RADIO_SUBSCRIBE_BCSTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_BCSTOP_EN_Pos)
- #define RADIO_SUBSCRIBE_BCSTOP_EN_Disabled (0UL)
- #define RADIO_SUBSCRIBE_BCSTOP_EN_Enabled (1UL)
- #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Pos (0UL)
- #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_BCSTOP_CHIDX_Pos)
- #define RADIO_SUBSCRIBE_EDSTART_EN_Pos (31UL)
- #define RADIO_SUBSCRIBE_EDSTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_EDSTART_EN_Pos)
- #define RADIO_SUBSCRIBE_EDSTART_EN_Disabled (0UL)
- #define RADIO_SUBSCRIBE_EDSTART_EN_Enabled (1UL)
- #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Pos (0UL)
- #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_EDSTART_CHIDX_Pos)
- #define RADIO_SUBSCRIBE_EDSTOP_EN_Pos (31UL)
- #define RADIO_SUBSCRIBE_EDSTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_EDSTOP_EN_Pos)
- #define RADIO_SUBSCRIBE_EDSTOP_EN_Disabled (0UL)
- #define RADIO_SUBSCRIBE_EDSTOP_EN_Enabled (1UL)
- #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Pos (0UL)
- #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_EDSTOP_CHIDX_Pos)
- #define RADIO_SUBSCRIBE_CCASTART_EN_Pos (31UL)
- #define RADIO_SUBSCRIBE_CCASTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_CCASTART_EN_Pos)
- #define RADIO_SUBSCRIBE_CCASTART_EN_Disabled (0UL)
- #define RADIO_SUBSCRIBE_CCASTART_EN_Enabled (1UL)
- #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Pos (0UL)
- #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_CCASTART_CHIDX_Pos)
- #define RADIO_SUBSCRIBE_CCASTOP_EN_Pos (31UL)
- #define RADIO_SUBSCRIBE_CCASTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_CCASTOP_EN_Pos)
- #define RADIO_SUBSCRIBE_CCASTOP_EN_Disabled (0UL)
- #define RADIO_SUBSCRIBE_CCASTOP_EN_Enabled (1UL)
- #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Pos (0UL)
- #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_CCASTOP_CHIDX_Pos)
- #define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL)
- #define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos)
- #define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0UL)
- #define RADIO_EVENTS_READY_EVENTS_READY_Generated (1UL)
- #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL)
- #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos)
- #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0UL)
- #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (1UL)
- #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL)
- #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos)
- #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0UL)
- #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (1UL)
- #define RADIO_EVENTS_END_EVENTS_END_Pos (0UL)
- #define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos)
- #define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0UL)
- #define RADIO_EVENTS_END_EVENTS_END_Generated (1UL)
- #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL)
- #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos)
- #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0UL)
- #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (1UL)
- #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL)
- #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos)
- #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0UL)
- #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (1UL)
- #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL)
- #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos)
- #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0UL)
- #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (1UL)
- #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL)
- #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos)
- #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_NotGenerated (0UL)
- #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Generated (1UL)
- #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL)
- #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos)
- #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0UL)
- #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (1UL)
- #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL)
- #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos)
- #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0UL)
- #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (1UL)
- #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL)
- #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos)
- #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0UL)
- #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (1UL)
- #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL)
- #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos)
- #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0UL)
- #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL)
- #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL)
- #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos)
- #define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0UL)
- #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Generated (1UL)
- #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos (0UL)
- #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Msk (0x1UL << RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos)
- #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_NotGenerated (0UL)
- #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Generated (1UL)
- #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos (0UL)
- #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Msk (0x1UL << RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos)
- #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_NotGenerated (0UL)
- #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Generated (1UL)
- #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos (0UL)
- #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Msk (0x1UL << RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos)
- #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_NotGenerated (0UL)
- #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Generated (1UL)
- #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos (0UL)
- #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Msk (0x1UL << RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos)
- #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_NotGenerated (0UL)
- #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Generated (1UL)
- #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos (0UL)
- #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Msk (0x1UL << RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos)
- #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_NotGenerated (0UL)
- #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Generated (1UL)
- #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL)
- #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos)
- #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_NotGenerated (0UL)
- #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Generated (1UL)
- #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL)
- #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos)
- #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0UL)
- #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (1UL)
- #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL)
- #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos)
- #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0UL)
- #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (1UL)
- #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos (0UL)
- #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Msk (0x1UL << RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos)
- #define RADIO_EVENTS_SYNC_EVENTS_SYNC_NotGenerated (0UL)
- #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Generated (1UL)
- #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL)
- #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos)
- #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0UL)
- #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (1UL)
- #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos (0UL)
- #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Msk (0x1UL << RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos)
- #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_NotGenerated (0UL)
- #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Generated (1UL)
- #define RADIO_PUBLISH_READY_EN_Pos (31UL)
- #define RADIO_PUBLISH_READY_EN_Msk (0x1UL << RADIO_PUBLISH_READY_EN_Pos)
- #define RADIO_PUBLISH_READY_EN_Disabled (0UL)
- #define RADIO_PUBLISH_READY_EN_Enabled (1UL)
- #define RADIO_PUBLISH_READY_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_READY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_READY_CHIDX_Pos)
- #define RADIO_PUBLISH_ADDRESS_EN_Pos (31UL)
- #define RADIO_PUBLISH_ADDRESS_EN_Msk (0x1UL << RADIO_PUBLISH_ADDRESS_EN_Pos)
- #define RADIO_PUBLISH_ADDRESS_EN_Disabled (0UL)
- #define RADIO_PUBLISH_ADDRESS_EN_Enabled (1UL)
- #define RADIO_PUBLISH_ADDRESS_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_ADDRESS_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_ADDRESS_CHIDX_Pos)
- #define RADIO_PUBLISH_PAYLOAD_EN_Pos (31UL)
- #define RADIO_PUBLISH_PAYLOAD_EN_Msk (0x1UL << RADIO_PUBLISH_PAYLOAD_EN_Pos)
- #define RADIO_PUBLISH_PAYLOAD_EN_Disabled (0UL)
- #define RADIO_PUBLISH_PAYLOAD_EN_Enabled (1UL)
- #define RADIO_PUBLISH_PAYLOAD_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_PAYLOAD_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_PAYLOAD_CHIDX_Pos)
- #define RADIO_PUBLISH_END_EN_Pos (31UL)
- #define RADIO_PUBLISH_END_EN_Msk (0x1UL << RADIO_PUBLISH_END_EN_Pos)
- #define RADIO_PUBLISH_END_EN_Disabled (0UL)
- #define RADIO_PUBLISH_END_EN_Enabled (1UL)
- #define RADIO_PUBLISH_END_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_END_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_END_CHIDX_Pos)
- #define RADIO_PUBLISH_DISABLED_EN_Pos (31UL)
- #define RADIO_PUBLISH_DISABLED_EN_Msk (0x1UL << RADIO_PUBLISH_DISABLED_EN_Pos)
- #define RADIO_PUBLISH_DISABLED_EN_Disabled (0UL)
- #define RADIO_PUBLISH_DISABLED_EN_Enabled (1UL)
- #define RADIO_PUBLISH_DISABLED_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_DISABLED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DISABLED_CHIDX_Pos)
- #define RADIO_PUBLISH_DEVMATCH_EN_Pos (31UL)
- #define RADIO_PUBLISH_DEVMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_DEVMATCH_EN_Pos)
- #define RADIO_PUBLISH_DEVMATCH_EN_Disabled (0UL)
- #define RADIO_PUBLISH_DEVMATCH_EN_Enabled (1UL)
- #define RADIO_PUBLISH_DEVMATCH_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_DEVMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DEVMATCH_CHIDX_Pos)
- #define RADIO_PUBLISH_DEVMISS_EN_Pos (31UL)
- #define RADIO_PUBLISH_DEVMISS_EN_Msk (0x1UL << RADIO_PUBLISH_DEVMISS_EN_Pos)
- #define RADIO_PUBLISH_DEVMISS_EN_Disabled (0UL)
- #define RADIO_PUBLISH_DEVMISS_EN_Enabled (1UL)
- #define RADIO_PUBLISH_DEVMISS_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_DEVMISS_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DEVMISS_CHIDX_Pos)
- #define RADIO_PUBLISH_RSSIEND_EN_Pos (31UL)
- #define RADIO_PUBLISH_RSSIEND_EN_Msk (0x1UL << RADIO_PUBLISH_RSSIEND_EN_Pos)
- #define RADIO_PUBLISH_RSSIEND_EN_Disabled (0UL)
- #define RADIO_PUBLISH_RSSIEND_EN_Enabled (1UL)
- #define RADIO_PUBLISH_RSSIEND_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_RSSIEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RSSIEND_CHIDX_Pos)
- #define RADIO_PUBLISH_BCMATCH_EN_Pos (31UL)
- #define RADIO_PUBLISH_BCMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_BCMATCH_EN_Pos)
- #define RADIO_PUBLISH_BCMATCH_EN_Disabled (0UL)
- #define RADIO_PUBLISH_BCMATCH_EN_Enabled (1UL)
- #define RADIO_PUBLISH_BCMATCH_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_BCMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_BCMATCH_CHIDX_Pos)
- #define RADIO_PUBLISH_CRCOK_EN_Pos (31UL)
- #define RADIO_PUBLISH_CRCOK_EN_Msk (0x1UL << RADIO_PUBLISH_CRCOK_EN_Pos)
- #define RADIO_PUBLISH_CRCOK_EN_Disabled (0UL)
- #define RADIO_PUBLISH_CRCOK_EN_Enabled (1UL)
- #define RADIO_PUBLISH_CRCOK_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_CRCOK_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CRCOK_CHIDX_Pos)
- #define RADIO_PUBLISH_CRCERROR_EN_Pos (31UL)
- #define RADIO_PUBLISH_CRCERROR_EN_Msk (0x1UL << RADIO_PUBLISH_CRCERROR_EN_Pos)
- #define RADIO_PUBLISH_CRCERROR_EN_Disabled (0UL)
- #define RADIO_PUBLISH_CRCERROR_EN_Enabled (1UL)
- #define RADIO_PUBLISH_CRCERROR_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_CRCERROR_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CRCERROR_CHIDX_Pos)
- #define RADIO_PUBLISH_FRAMESTART_EN_Pos (31UL)
- #define RADIO_PUBLISH_FRAMESTART_EN_Msk (0x1UL << RADIO_PUBLISH_FRAMESTART_EN_Pos)
- #define RADIO_PUBLISH_FRAMESTART_EN_Disabled (0UL)
- #define RADIO_PUBLISH_FRAMESTART_EN_Enabled (1UL)
- #define RADIO_PUBLISH_FRAMESTART_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_FRAMESTART_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_FRAMESTART_CHIDX_Pos)
- #define RADIO_PUBLISH_EDEND_EN_Pos (31UL)
- #define RADIO_PUBLISH_EDEND_EN_Msk (0x1UL << RADIO_PUBLISH_EDEND_EN_Pos)
- #define RADIO_PUBLISH_EDEND_EN_Disabled (0UL)
- #define RADIO_PUBLISH_EDEND_EN_Enabled (1UL)
- #define RADIO_PUBLISH_EDEND_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_EDEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_EDEND_CHIDX_Pos)
- #define RADIO_PUBLISH_EDSTOPPED_EN_Pos (31UL)
- #define RADIO_PUBLISH_EDSTOPPED_EN_Msk (0x1UL << RADIO_PUBLISH_EDSTOPPED_EN_Pos)
- #define RADIO_PUBLISH_EDSTOPPED_EN_Disabled (0UL)
- #define RADIO_PUBLISH_EDSTOPPED_EN_Enabled (1UL)
- #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_EDSTOPPED_CHIDX_Pos)
- #define RADIO_PUBLISH_CCAIDLE_EN_Pos (31UL)
- #define RADIO_PUBLISH_CCAIDLE_EN_Msk (0x1UL << RADIO_PUBLISH_CCAIDLE_EN_Pos)
- #define RADIO_PUBLISH_CCAIDLE_EN_Disabled (0UL)
- #define RADIO_PUBLISH_CCAIDLE_EN_Enabled (1UL)
- #define RADIO_PUBLISH_CCAIDLE_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_CCAIDLE_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCAIDLE_CHIDX_Pos)
- #define RADIO_PUBLISH_CCABUSY_EN_Pos (31UL)
- #define RADIO_PUBLISH_CCABUSY_EN_Msk (0x1UL << RADIO_PUBLISH_CCABUSY_EN_Pos)
- #define RADIO_PUBLISH_CCABUSY_EN_Disabled (0UL)
- #define RADIO_PUBLISH_CCABUSY_EN_Enabled (1UL)
- #define RADIO_PUBLISH_CCABUSY_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_CCABUSY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCABUSY_CHIDX_Pos)
- #define RADIO_PUBLISH_CCASTOPPED_EN_Pos (31UL)
- #define RADIO_PUBLISH_CCASTOPPED_EN_Msk (0x1UL << RADIO_PUBLISH_CCASTOPPED_EN_Pos)
- #define RADIO_PUBLISH_CCASTOPPED_EN_Disabled (0UL)
- #define RADIO_PUBLISH_CCASTOPPED_EN_Enabled (1UL)
- #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCASTOPPED_CHIDX_Pos)
- #define RADIO_PUBLISH_RATEBOOST_EN_Pos (31UL)
- #define RADIO_PUBLISH_RATEBOOST_EN_Msk (0x1UL << RADIO_PUBLISH_RATEBOOST_EN_Pos)
- #define RADIO_PUBLISH_RATEBOOST_EN_Disabled (0UL)
- #define RADIO_PUBLISH_RATEBOOST_EN_Enabled (1UL)
- #define RADIO_PUBLISH_RATEBOOST_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_RATEBOOST_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RATEBOOST_CHIDX_Pos)
- #define RADIO_PUBLISH_TXREADY_EN_Pos (31UL)
- #define RADIO_PUBLISH_TXREADY_EN_Msk (0x1UL << RADIO_PUBLISH_TXREADY_EN_Pos)
- #define RADIO_PUBLISH_TXREADY_EN_Disabled (0UL)
- #define RADIO_PUBLISH_TXREADY_EN_Enabled (1UL)
- #define RADIO_PUBLISH_TXREADY_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_TXREADY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_TXREADY_CHIDX_Pos)
- #define RADIO_PUBLISH_RXREADY_EN_Pos (31UL)
- #define RADIO_PUBLISH_RXREADY_EN_Msk (0x1UL << RADIO_PUBLISH_RXREADY_EN_Pos)
- #define RADIO_PUBLISH_RXREADY_EN_Disabled (0UL)
- #define RADIO_PUBLISH_RXREADY_EN_Enabled (1UL)
- #define RADIO_PUBLISH_RXREADY_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_RXREADY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RXREADY_CHIDX_Pos)
- #define RADIO_PUBLISH_MHRMATCH_EN_Pos (31UL)
- #define RADIO_PUBLISH_MHRMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_MHRMATCH_EN_Pos)
- #define RADIO_PUBLISH_MHRMATCH_EN_Disabled (0UL)
- #define RADIO_PUBLISH_MHRMATCH_EN_Enabled (1UL)
- #define RADIO_PUBLISH_MHRMATCH_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_MHRMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_MHRMATCH_CHIDX_Pos)
- #define RADIO_PUBLISH_SYNC_EN_Pos (31UL)
- #define RADIO_PUBLISH_SYNC_EN_Msk (0x1UL << RADIO_PUBLISH_SYNC_EN_Pos)
- #define RADIO_PUBLISH_SYNC_EN_Disabled (0UL)
- #define RADIO_PUBLISH_SYNC_EN_Enabled (1UL)
- #define RADIO_PUBLISH_SYNC_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_SYNC_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_SYNC_CHIDX_Pos)
- #define RADIO_PUBLISH_PHYEND_EN_Pos (31UL)
- #define RADIO_PUBLISH_PHYEND_EN_Msk (0x1UL << RADIO_PUBLISH_PHYEND_EN_Pos)
- #define RADIO_PUBLISH_PHYEND_EN_Disabled (0UL)
- #define RADIO_PUBLISH_PHYEND_EN_Enabled (1UL)
- #define RADIO_PUBLISH_PHYEND_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_PHYEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_PHYEND_CHIDX_Pos)
- #define RADIO_PUBLISH_CTEPRESENT_EN_Pos (31UL)
- #define RADIO_PUBLISH_CTEPRESENT_EN_Msk (0x1UL << RADIO_PUBLISH_CTEPRESENT_EN_Pos)
- #define RADIO_PUBLISH_CTEPRESENT_EN_Disabled (0UL)
- #define RADIO_PUBLISH_CTEPRESENT_EN_Enabled (1UL)
- #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Pos (0UL)
- #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CTEPRESENT_CHIDX_Pos)
- #define RADIO_SHORTS_PHYEND_START_Pos (21UL)
- #define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos)
- #define RADIO_SHORTS_PHYEND_START_Disabled (0UL)
- #define RADIO_SHORTS_PHYEND_START_Enabled (1UL)
- #define RADIO_SHORTS_PHYEND_DISABLE_Pos (20UL)
- #define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos)
- #define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0UL)
- #define RADIO_SHORTS_PHYEND_DISABLE_Enabled (1UL)
- #define RADIO_SHORTS_RXREADY_START_Pos (19UL)
- #define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos)
- #define RADIO_SHORTS_RXREADY_START_Disabled (0UL)
- #define RADIO_SHORTS_RXREADY_START_Enabled (1UL)
- #define RADIO_SHORTS_TXREADY_START_Pos (18UL)
- #define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos)
- #define RADIO_SHORTS_TXREADY_START_Disabled (0UL)
- #define RADIO_SHORTS_TXREADY_START_Enabled (1UL)
- #define RADIO_SHORTS_CCAIDLE_STOP_Pos (17UL)
- #define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos)
- #define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0UL)
- #define RADIO_SHORTS_CCAIDLE_STOP_Enabled (1UL)
- #define RADIO_SHORTS_EDEND_DISABLE_Pos (16UL)
- #define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos)
- #define RADIO_SHORTS_EDEND_DISABLE_Disabled (0UL)
- #define RADIO_SHORTS_EDEND_DISABLE_Enabled (1UL)
- #define RADIO_SHORTS_READY_EDSTART_Pos (15UL)
- #define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos)
- #define RADIO_SHORTS_READY_EDSTART_Disabled (0UL)
- #define RADIO_SHORTS_READY_EDSTART_Enabled (1UL)
- #define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (14UL)
- #define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos)
- #define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0UL)
- #define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (1UL)
- #define RADIO_SHORTS_CCABUSY_DISABLE_Pos (13UL)
- #define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos)
- #define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0UL)
- #define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (1UL)
- #define RADIO_SHORTS_CCAIDLE_TXEN_Pos (12UL)
- #define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos)
- #define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0UL)
- #define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (1UL)
- #define RADIO_SHORTS_RXREADY_CCASTART_Pos (11UL)
- #define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos)
- #define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0UL)
- #define RADIO_SHORTS_RXREADY_CCASTART_Enabled (1UL)
- #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL)
- #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos)
- #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL)
- #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL)
- #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL)
- #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos)
- #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL)
- #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL)
- #define RADIO_SHORTS_END_START_Pos (5UL)
- #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos)
- #define RADIO_SHORTS_END_START_Disabled (0UL)
- #define RADIO_SHORTS_END_START_Enabled (1UL)
- #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL)
- #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos)
- #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL)
- #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL)
- #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL)
- #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos)
- #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL)
- #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL)
- #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL)
- #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos)
- #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL)
- #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL)
- #define RADIO_SHORTS_END_DISABLE_Pos (1UL)
- #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos)
- #define RADIO_SHORTS_END_DISABLE_Disabled (0UL)
- #define RADIO_SHORTS_END_DISABLE_Enabled (1UL)
- #define RADIO_SHORTS_READY_START_Pos (0UL)
- #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos)
- #define RADIO_SHORTS_READY_START_Disabled (0UL)
- #define RADIO_SHORTS_READY_START_Enabled (1UL)
- #define RADIO_INTENSET_CTEPRESENT_Pos (28UL)
- #define RADIO_INTENSET_CTEPRESENT_Msk (0x1UL << RADIO_INTENSET_CTEPRESENT_Pos)
- #define RADIO_INTENSET_CTEPRESENT_Disabled (0UL)
- #define RADIO_INTENSET_CTEPRESENT_Enabled (1UL)
- #define RADIO_INTENSET_CTEPRESENT_Set (1UL)
- #define RADIO_INTENSET_PHYEND_Pos (27UL)
- #define RADIO_INTENSET_PHYEND_Msk (0x1UL << RADIO_INTENSET_PHYEND_Pos)
- #define RADIO_INTENSET_PHYEND_Disabled (0UL)
- #define RADIO_INTENSET_PHYEND_Enabled (1UL)
- #define RADIO_INTENSET_PHYEND_Set (1UL)
- #define RADIO_INTENSET_SYNC_Pos (26UL)
- #define RADIO_INTENSET_SYNC_Msk (0x1UL << RADIO_INTENSET_SYNC_Pos)
- #define RADIO_INTENSET_SYNC_Disabled (0UL)
- #define RADIO_INTENSET_SYNC_Enabled (1UL)
- #define RADIO_INTENSET_SYNC_Set (1UL)
- #define RADIO_INTENSET_MHRMATCH_Pos (23UL)
- #define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos)
- #define RADIO_INTENSET_MHRMATCH_Disabled (0UL)
- #define RADIO_INTENSET_MHRMATCH_Enabled (1UL)
- #define RADIO_INTENSET_MHRMATCH_Set (1UL)
- #define RADIO_INTENSET_RXREADY_Pos (22UL)
- #define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos)
- #define RADIO_INTENSET_RXREADY_Disabled (0UL)
- #define RADIO_INTENSET_RXREADY_Enabled (1UL)
- #define RADIO_INTENSET_RXREADY_Set (1UL)
- #define RADIO_INTENSET_TXREADY_Pos (21UL)
- #define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos)
- #define RADIO_INTENSET_TXREADY_Disabled (0UL)
- #define RADIO_INTENSET_TXREADY_Enabled (1UL)
- #define RADIO_INTENSET_TXREADY_Set (1UL)
- #define RADIO_INTENSET_RATEBOOST_Pos (20UL)
- #define RADIO_INTENSET_RATEBOOST_Msk (0x1UL << RADIO_INTENSET_RATEBOOST_Pos)
- #define RADIO_INTENSET_RATEBOOST_Disabled (0UL)
- #define RADIO_INTENSET_RATEBOOST_Enabled (1UL)
- #define RADIO_INTENSET_RATEBOOST_Set (1UL)
- #define RADIO_INTENSET_CCASTOPPED_Pos (19UL)
- #define RADIO_INTENSET_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET_CCASTOPPED_Pos)
- #define RADIO_INTENSET_CCASTOPPED_Disabled (0UL)
- #define RADIO_INTENSET_CCASTOPPED_Enabled (1UL)
- #define RADIO_INTENSET_CCASTOPPED_Set (1UL)
- #define RADIO_INTENSET_CCABUSY_Pos (18UL)
- #define RADIO_INTENSET_CCABUSY_Msk (0x1UL << RADIO_INTENSET_CCABUSY_Pos)
- #define RADIO_INTENSET_CCABUSY_Disabled (0UL)
- #define RADIO_INTENSET_CCABUSY_Enabled (1UL)
- #define RADIO_INTENSET_CCABUSY_Set (1UL)
- #define RADIO_INTENSET_CCAIDLE_Pos (17UL)
- #define RADIO_INTENSET_CCAIDLE_Msk (0x1UL << RADIO_INTENSET_CCAIDLE_Pos)
- #define RADIO_INTENSET_CCAIDLE_Disabled (0UL)
- #define RADIO_INTENSET_CCAIDLE_Enabled (1UL)
- #define RADIO_INTENSET_CCAIDLE_Set (1UL)
- #define RADIO_INTENSET_EDSTOPPED_Pos (16UL)
- #define RADIO_INTENSET_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET_EDSTOPPED_Pos)
- #define RADIO_INTENSET_EDSTOPPED_Disabled (0UL)
- #define RADIO_INTENSET_EDSTOPPED_Enabled (1UL)
- #define RADIO_INTENSET_EDSTOPPED_Set (1UL)
- #define RADIO_INTENSET_EDEND_Pos (15UL)
- #define RADIO_INTENSET_EDEND_Msk (0x1UL << RADIO_INTENSET_EDEND_Pos)
- #define RADIO_INTENSET_EDEND_Disabled (0UL)
- #define RADIO_INTENSET_EDEND_Enabled (1UL)
- #define RADIO_INTENSET_EDEND_Set (1UL)
- #define RADIO_INTENSET_FRAMESTART_Pos (14UL)
- #define RADIO_INTENSET_FRAMESTART_Msk (0x1UL << RADIO_INTENSET_FRAMESTART_Pos)
- #define RADIO_INTENSET_FRAMESTART_Disabled (0UL)
- #define RADIO_INTENSET_FRAMESTART_Enabled (1UL)
- #define RADIO_INTENSET_FRAMESTART_Set (1UL)
- #define RADIO_INTENSET_CRCERROR_Pos (13UL)
- #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos)
- #define RADIO_INTENSET_CRCERROR_Disabled (0UL)
- #define RADIO_INTENSET_CRCERROR_Enabled (1UL)
- #define RADIO_INTENSET_CRCERROR_Set (1UL)
- #define RADIO_INTENSET_CRCOK_Pos (12UL)
- #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos)
- #define RADIO_INTENSET_CRCOK_Disabled (0UL)
- #define RADIO_INTENSET_CRCOK_Enabled (1UL)
- #define RADIO_INTENSET_CRCOK_Set (1UL)
- #define RADIO_INTENSET_BCMATCH_Pos (10UL)
- #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos)
- #define RADIO_INTENSET_BCMATCH_Disabled (0UL)
- #define RADIO_INTENSET_BCMATCH_Enabled (1UL)
- #define RADIO_INTENSET_BCMATCH_Set (1UL)
- #define RADIO_INTENSET_RSSIEND_Pos (7UL)
- #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos)
- #define RADIO_INTENSET_RSSIEND_Disabled (0UL)
- #define RADIO_INTENSET_RSSIEND_Enabled (1UL)
- #define RADIO_INTENSET_RSSIEND_Set (1UL)
- #define RADIO_INTENSET_DEVMISS_Pos (6UL)
- #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos)
- #define RADIO_INTENSET_DEVMISS_Disabled (0UL)
- #define RADIO_INTENSET_DEVMISS_Enabled (1UL)
- #define RADIO_INTENSET_DEVMISS_Set (1UL)
- #define RADIO_INTENSET_DEVMATCH_Pos (5UL)
- #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos)
- #define RADIO_INTENSET_DEVMATCH_Disabled (0UL)
- #define RADIO_INTENSET_DEVMATCH_Enabled (1UL)
- #define RADIO_INTENSET_DEVMATCH_Set (1UL)
- #define RADIO_INTENSET_DISABLED_Pos (4UL)
- #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos)
- #define RADIO_INTENSET_DISABLED_Disabled (0UL)
- #define RADIO_INTENSET_DISABLED_Enabled (1UL)
- #define RADIO_INTENSET_DISABLED_Set (1UL)
- #define RADIO_INTENSET_END_Pos (3UL)
- #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos)
- #define RADIO_INTENSET_END_Disabled (0UL)
- #define RADIO_INTENSET_END_Enabled (1UL)
- #define RADIO_INTENSET_END_Set (1UL)
- #define RADIO_INTENSET_PAYLOAD_Pos (2UL)
- #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos)
- #define RADIO_INTENSET_PAYLOAD_Disabled (0UL)
- #define RADIO_INTENSET_PAYLOAD_Enabled (1UL)
- #define RADIO_INTENSET_PAYLOAD_Set (1UL)
- #define RADIO_INTENSET_ADDRESS_Pos (1UL)
- #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos)
- #define RADIO_INTENSET_ADDRESS_Disabled (0UL)
- #define RADIO_INTENSET_ADDRESS_Enabled (1UL)
- #define RADIO_INTENSET_ADDRESS_Set (1UL)
- #define RADIO_INTENSET_READY_Pos (0UL)
- #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos)
- #define RADIO_INTENSET_READY_Disabled (0UL)
- #define RADIO_INTENSET_READY_Enabled (1UL)
- #define RADIO_INTENSET_READY_Set (1UL)
- #define RADIO_INTENCLR_CTEPRESENT_Pos (28UL)
- #define RADIO_INTENCLR_CTEPRESENT_Msk (0x1UL << RADIO_INTENCLR_CTEPRESENT_Pos)
- #define RADIO_INTENCLR_CTEPRESENT_Disabled (0UL)
- #define RADIO_INTENCLR_CTEPRESENT_Enabled (1UL)
- #define RADIO_INTENCLR_CTEPRESENT_Clear (1UL)
- #define RADIO_INTENCLR_PHYEND_Pos (27UL)
- #define RADIO_INTENCLR_PHYEND_Msk (0x1UL << RADIO_INTENCLR_PHYEND_Pos)
- #define RADIO_INTENCLR_PHYEND_Disabled (0UL)
- #define RADIO_INTENCLR_PHYEND_Enabled (1UL)
- #define RADIO_INTENCLR_PHYEND_Clear (1UL)
- #define RADIO_INTENCLR_SYNC_Pos (26UL)
- #define RADIO_INTENCLR_SYNC_Msk (0x1UL << RADIO_INTENCLR_SYNC_Pos)
- #define RADIO_INTENCLR_SYNC_Disabled (0UL)
- #define RADIO_INTENCLR_SYNC_Enabled (1UL)
- #define RADIO_INTENCLR_SYNC_Clear (1UL)
- #define RADIO_INTENCLR_MHRMATCH_Pos (23UL)
- #define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos)
- #define RADIO_INTENCLR_MHRMATCH_Disabled (0UL)
- #define RADIO_INTENCLR_MHRMATCH_Enabled (1UL)
- #define RADIO_INTENCLR_MHRMATCH_Clear (1UL)
- #define RADIO_INTENCLR_RXREADY_Pos (22UL)
- #define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos)
- #define RADIO_INTENCLR_RXREADY_Disabled (0UL)
- #define RADIO_INTENCLR_RXREADY_Enabled (1UL)
- #define RADIO_INTENCLR_RXREADY_Clear (1UL)
- #define RADIO_INTENCLR_TXREADY_Pos (21UL)
- #define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos)
- #define RADIO_INTENCLR_TXREADY_Disabled (0UL)
- #define RADIO_INTENCLR_TXREADY_Enabled (1UL)
- #define RADIO_INTENCLR_TXREADY_Clear (1UL)
- #define RADIO_INTENCLR_RATEBOOST_Pos (20UL)
- #define RADIO_INTENCLR_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR_RATEBOOST_Pos)
- #define RADIO_INTENCLR_RATEBOOST_Disabled (0UL)
- #define RADIO_INTENCLR_RATEBOOST_Enabled (1UL)
- #define RADIO_INTENCLR_RATEBOOST_Clear (1UL)
- #define RADIO_INTENCLR_CCASTOPPED_Pos (19UL)
- #define RADIO_INTENCLR_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR_CCASTOPPED_Pos)
- #define RADIO_INTENCLR_CCASTOPPED_Disabled (0UL)
- #define RADIO_INTENCLR_CCASTOPPED_Enabled (1UL)
- #define RADIO_INTENCLR_CCASTOPPED_Clear (1UL)
- #define RADIO_INTENCLR_CCABUSY_Pos (18UL)
- #define RADIO_INTENCLR_CCABUSY_Msk (0x1UL << RADIO_INTENCLR_CCABUSY_Pos)
- #define RADIO_INTENCLR_CCABUSY_Disabled (0UL)
- #define RADIO_INTENCLR_CCABUSY_Enabled (1UL)
- #define RADIO_INTENCLR_CCABUSY_Clear (1UL)
- #define RADIO_INTENCLR_CCAIDLE_Pos (17UL)
- #define RADIO_INTENCLR_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR_CCAIDLE_Pos)
- #define RADIO_INTENCLR_CCAIDLE_Disabled (0UL)
- #define RADIO_INTENCLR_CCAIDLE_Enabled (1UL)
- #define RADIO_INTENCLR_CCAIDLE_Clear (1UL)
- #define RADIO_INTENCLR_EDSTOPPED_Pos (16UL)
- #define RADIO_INTENCLR_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR_EDSTOPPED_Pos)
- #define RADIO_INTENCLR_EDSTOPPED_Disabled (0UL)
- #define RADIO_INTENCLR_EDSTOPPED_Enabled (1UL)
- #define RADIO_INTENCLR_EDSTOPPED_Clear (1UL)
- #define RADIO_INTENCLR_EDEND_Pos (15UL)
- #define RADIO_INTENCLR_EDEND_Msk (0x1UL << RADIO_INTENCLR_EDEND_Pos)
- #define RADIO_INTENCLR_EDEND_Disabled (0UL)
- #define RADIO_INTENCLR_EDEND_Enabled (1UL)
- #define RADIO_INTENCLR_EDEND_Clear (1UL)
- #define RADIO_INTENCLR_FRAMESTART_Pos (14UL)
- #define RADIO_INTENCLR_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR_FRAMESTART_Pos)
- #define RADIO_INTENCLR_FRAMESTART_Disabled (0UL)
- #define RADIO_INTENCLR_FRAMESTART_Enabled (1UL)
- #define RADIO_INTENCLR_FRAMESTART_Clear (1UL)
- #define RADIO_INTENCLR_CRCERROR_Pos (13UL)
- #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos)
- #define RADIO_INTENCLR_CRCERROR_Disabled (0UL)
- #define RADIO_INTENCLR_CRCERROR_Enabled (1UL)
- #define RADIO_INTENCLR_CRCERROR_Clear (1UL)
- #define RADIO_INTENCLR_CRCOK_Pos (12UL)
- #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos)
- #define RADIO_INTENCLR_CRCOK_Disabled (0UL)
- #define RADIO_INTENCLR_CRCOK_Enabled (1UL)
- #define RADIO_INTENCLR_CRCOK_Clear (1UL)
- #define RADIO_INTENCLR_BCMATCH_Pos (10UL)
- #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos)
- #define RADIO_INTENCLR_BCMATCH_Disabled (0UL)
- #define RADIO_INTENCLR_BCMATCH_Enabled (1UL)
- #define RADIO_INTENCLR_BCMATCH_Clear (1UL)
- #define RADIO_INTENCLR_RSSIEND_Pos (7UL)
- #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos)
- #define RADIO_INTENCLR_RSSIEND_Disabled (0UL)
- #define RADIO_INTENCLR_RSSIEND_Enabled (1UL)
- #define RADIO_INTENCLR_RSSIEND_Clear (1UL)
- #define RADIO_INTENCLR_DEVMISS_Pos (6UL)
- #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos)
- #define RADIO_INTENCLR_DEVMISS_Disabled (0UL)
- #define RADIO_INTENCLR_DEVMISS_Enabled (1UL)
- #define RADIO_INTENCLR_DEVMISS_Clear (1UL)
- #define RADIO_INTENCLR_DEVMATCH_Pos (5UL)
- #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos)
- #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL)
- #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL)
- #define RADIO_INTENCLR_DEVMATCH_Clear (1UL)
- #define RADIO_INTENCLR_DISABLED_Pos (4UL)
- #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos)
- #define RADIO_INTENCLR_DISABLED_Disabled (0UL)
- #define RADIO_INTENCLR_DISABLED_Enabled (1UL)
- #define RADIO_INTENCLR_DISABLED_Clear (1UL)
- #define RADIO_INTENCLR_END_Pos (3UL)
- #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos)
- #define RADIO_INTENCLR_END_Disabled (0UL)
- #define RADIO_INTENCLR_END_Enabled (1UL)
- #define RADIO_INTENCLR_END_Clear (1UL)
- #define RADIO_INTENCLR_PAYLOAD_Pos (2UL)
- #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos)
- #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL)
- #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL)
- #define RADIO_INTENCLR_PAYLOAD_Clear (1UL)
- #define RADIO_INTENCLR_ADDRESS_Pos (1UL)
- #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos)
- #define RADIO_INTENCLR_ADDRESS_Disabled (0UL)
- #define RADIO_INTENCLR_ADDRESS_Enabled (1UL)
- #define RADIO_INTENCLR_ADDRESS_Clear (1UL)
- #define RADIO_INTENCLR_READY_Pos (0UL)
- #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos)
- #define RADIO_INTENCLR_READY_Disabled (0UL)
- #define RADIO_INTENCLR_READY_Enabled (1UL)
- #define RADIO_INTENCLR_READY_Clear (1UL)
- #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL)
- #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos)
- #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL)
- #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL)
- #define RADIO_RXMATCH_RXMATCH_Pos (0UL)
- #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos)
- #define RADIO_RXCRC_RXCRC_Pos (0UL)
- #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos)
- #define RADIO_DAI_DAI_Pos (0UL)
- #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos)
- #define RADIO_PDUSTAT_CISTAT_Pos (1UL)
- #define RADIO_PDUSTAT_CISTAT_Msk (0x3UL << RADIO_PDUSTAT_CISTAT_Pos)
- #define RADIO_PDUSTAT_CISTAT_LR125kbit (0UL)
- #define RADIO_PDUSTAT_CISTAT_LR500kbit (1UL)
- #define RADIO_PDUSTAT_PDUSTAT_Pos (0UL)
- #define RADIO_PDUSTAT_PDUSTAT_Msk (0x1UL << RADIO_PDUSTAT_PDUSTAT_Pos)
- #define RADIO_PDUSTAT_PDUSTAT_LessThan (0UL)
- #define RADIO_PDUSTAT_PDUSTAT_GreaterThan (1UL)
- #define RADIO_CTESTATUS_CTETYPE_Pos (6UL)
- #define RADIO_CTESTATUS_CTETYPE_Msk (0x3UL << RADIO_CTESTATUS_CTETYPE_Pos)
- #define RADIO_CTESTATUS_RFU_Pos (5UL)
- #define RADIO_CTESTATUS_RFU_Msk (0x1UL << RADIO_CTESTATUS_RFU_Pos)
- #define RADIO_CTESTATUS_CTETIME_Pos (0UL)
- #define RADIO_CTESTATUS_CTETIME_Msk (0x1FUL << RADIO_CTESTATUS_CTETIME_Pos)
- #define RADIO_DFESTATUS_SAMPLINGSTATE_Pos (4UL)
- #define RADIO_DFESTATUS_SAMPLINGSTATE_Msk (0x1UL << RADIO_DFESTATUS_SAMPLINGSTATE_Pos)
- #define RADIO_DFESTATUS_SAMPLINGSTATE_Idle (0UL)
- #define RADIO_DFESTATUS_SAMPLINGSTATE_Sampling (1UL)
- #define RADIO_DFESTATUS_SWITCHINGSTATE_Pos (0UL)
- #define RADIO_DFESTATUS_SWITCHINGSTATE_Msk (0x7UL << RADIO_DFESTATUS_SWITCHINGSTATE_Pos)
- #define RADIO_DFESTATUS_SWITCHINGSTATE_Idle (0UL)
- #define RADIO_DFESTATUS_SWITCHINGSTATE_Offset (1UL)
- #define RADIO_DFESTATUS_SWITCHINGSTATE_Guard (2UL)
- #define RADIO_DFESTATUS_SWITCHINGSTATE_Ref (3UL)
- #define RADIO_DFESTATUS_SWITCHINGSTATE_Switching (4UL)
- #define RADIO_DFESTATUS_SWITCHINGSTATE_Ending (5UL)
- #define RADIO_PACKETPTR_PACKETPTR_Pos (0UL)
- #define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos)
- #define RADIO_FREQUENCY_MAP_Pos (8UL)
- #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos)
- #define RADIO_FREQUENCY_MAP_Default (0UL)
- #define RADIO_FREQUENCY_MAP_Low (1UL)
- #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL)
- #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos)
- #define RADIO_TXPOWER_TXPOWER_Pos (0UL)
- #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos)
- #define RADIO_TXPOWER_TXPOWER_0dBm (0x0UL)
- #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL)
- #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xE2UL)
- #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL)
- #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL)
- #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL)
- #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL)
- #define RADIO_TXPOWER_TXPOWER_Neg7dBm (0xF9UL)
- #define RADIO_TXPOWER_TXPOWER_Neg6dBm (0xFAUL)
- #define RADIO_TXPOWER_TXPOWER_Neg5dBm (0xFBUL)
- #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL)
- #define RADIO_TXPOWER_TXPOWER_Neg3dBm (0xFDUL)
- #define RADIO_TXPOWER_TXPOWER_Neg2dBm (0xFEUL)
- #define RADIO_TXPOWER_TXPOWER_Neg1dBm (0xFFUL)
- #define RADIO_MODE_MODE_Pos (0UL)
- #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos)
- #define RADIO_MODE_MODE_Nrf_1Mbit (0UL)
- #define RADIO_MODE_MODE_Nrf_2Mbit (1UL)
- #define RADIO_MODE_MODE_Ble_1Mbit (3UL)
- #define RADIO_MODE_MODE_Ble_2Mbit (4UL)
- #define RADIO_MODE_MODE_Ble_LR125Kbit (5UL)
- #define RADIO_MODE_MODE_Ble_LR500Kbit (6UL)
- #define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL)
- #define RADIO_PCNF0_TERMLEN_Pos (29UL)
- #define RADIO_PCNF0_TERMLEN_Msk (0x3UL << RADIO_PCNF0_TERMLEN_Pos)
- #define RADIO_PCNF0_CRCINC_Pos (26UL)
- #define RADIO_PCNF0_CRCINC_Msk (0x1UL << RADIO_PCNF0_CRCINC_Pos)
- #define RADIO_PCNF0_CRCINC_Exclude (0UL)
- #define RADIO_PCNF0_CRCINC_Include (1UL)
- #define RADIO_PCNF0_PLEN_Pos (24UL)
- #define RADIO_PCNF0_PLEN_Msk (0x3UL << RADIO_PCNF0_PLEN_Pos)
- #define RADIO_PCNF0_PLEN_8bit (0UL)
- #define RADIO_PCNF0_PLEN_16bit (1UL)
- #define RADIO_PCNF0_PLEN_32bitZero (2UL)
- #define RADIO_PCNF0_PLEN_LongRange (3UL)
- #define RADIO_PCNF0_CILEN_Pos (22UL)
- #define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos)
- #define RADIO_PCNF0_S1INCL_Pos (20UL)
- #define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos)
- #define RADIO_PCNF0_S1INCL_Automatic (0UL)
- #define RADIO_PCNF0_S1INCL_Include (1UL)
- #define RADIO_PCNF0_S1LEN_Pos (16UL)
- #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos)
- #define RADIO_PCNF0_S0LEN_Pos (8UL)
- #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos)
- #define RADIO_PCNF0_LFLEN_Pos (0UL)
- #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos)
- #define RADIO_PCNF1_WHITEEN_Pos (25UL)
- #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos)
- #define RADIO_PCNF1_WHITEEN_Disabled (0UL)
- #define RADIO_PCNF1_WHITEEN_Enabled (1UL)
- #define RADIO_PCNF1_ENDIAN_Pos (24UL)
- #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos)
- #define RADIO_PCNF1_ENDIAN_Little (0UL)
- #define RADIO_PCNF1_ENDIAN_Big (1UL)
- #define RADIO_PCNF1_BALEN_Pos (16UL)
- #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos)
- #define RADIO_PCNF1_STATLEN_Pos (8UL)
- #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos)
- #define RADIO_PCNF1_MAXLEN_Pos (0UL)
- #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos)
- #define RADIO_BASE0_BASE0_Pos (0UL)
- #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos)
- #define RADIO_BASE1_BASE1_Pos (0UL)
- #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos)
- #define RADIO_PREFIX0_AP3_Pos (24UL)
- #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos)
- #define RADIO_PREFIX0_AP2_Pos (16UL)
- #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos)
- #define RADIO_PREFIX0_AP1_Pos (8UL)
- #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos)
- #define RADIO_PREFIX0_AP0_Pos (0UL)
- #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos)
- #define RADIO_PREFIX1_AP7_Pos (24UL)
- #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos)
- #define RADIO_PREFIX1_AP6_Pos (16UL)
- #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos)
- #define RADIO_PREFIX1_AP5_Pos (8UL)
- #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos)
- #define RADIO_PREFIX1_AP4_Pos (0UL)
- #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos)
- #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL)
- #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos)
- #define RADIO_RXADDRESSES_ADDR7_Pos (7UL)
- #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos)
- #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL)
- #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL)
- #define RADIO_RXADDRESSES_ADDR6_Pos (6UL)
- #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos)
- #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL)
- #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL)
- #define RADIO_RXADDRESSES_ADDR5_Pos (5UL)
- #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos)
- #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL)
- #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL)
- #define RADIO_RXADDRESSES_ADDR4_Pos (4UL)
- #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos)
- #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL)
- #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL)
- #define RADIO_RXADDRESSES_ADDR3_Pos (3UL)
- #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos)
- #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL)
- #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL)
- #define RADIO_RXADDRESSES_ADDR2_Pos (2UL)
- #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos)
- #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL)
- #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL)
- #define RADIO_RXADDRESSES_ADDR1_Pos (1UL)
- #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos)
- #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL)
- #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL)
- #define RADIO_RXADDRESSES_ADDR0_Pos (0UL)
- #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos)
- #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL)
- #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL)
- #define RADIO_CRCCNF_SKIPADDR_Pos (8UL)
- #define RADIO_CRCCNF_SKIPADDR_Msk (0x3UL << RADIO_CRCCNF_SKIPADDR_Pos)
- #define RADIO_CRCCNF_SKIPADDR_Include (0UL)
- #define RADIO_CRCCNF_SKIPADDR_Skip (1UL)
- #define RADIO_CRCCNF_SKIPADDR_Ieee802154 (2UL)
- #define RADIO_CRCCNF_LEN_Pos (0UL)
- #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos)
- #define RADIO_CRCCNF_LEN_Disabled (0UL)
- #define RADIO_CRCCNF_LEN_One (1UL)
- #define RADIO_CRCCNF_LEN_Two (2UL)
- #define RADIO_CRCCNF_LEN_Three (3UL)
- #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL)
- #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos)
- #define RADIO_CRCINIT_CRCINIT_Pos (0UL)
- #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos)
- #define RADIO_TIFS_TIFS_Pos (0UL)
- #define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos)
- #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL)
- #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos)
- #define RADIO_STATE_STATE_Pos (0UL)
- #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos)
- #define RADIO_STATE_STATE_Disabled (0UL)
- #define RADIO_STATE_STATE_RxRu (1UL)
- #define RADIO_STATE_STATE_RxIdle (2UL)
- #define RADIO_STATE_STATE_Rx (3UL)
- #define RADIO_STATE_STATE_RxDisable (4UL)
- #define RADIO_STATE_STATE_TxRu (9UL)
- #define RADIO_STATE_STATE_TxIdle (10UL)
- #define RADIO_STATE_STATE_Tx (11UL)
- #define RADIO_STATE_STATE_TxDisable (12UL)
- #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL)
- #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos)
- #define RADIO_BCC_BCC_Pos (0UL)
- #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos)
- #define RADIO_DAB_DAB_Pos (0UL)
- #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos)
- #define RADIO_DAP_DAP_Pos (0UL)
- #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos)
- #define RADIO_DACNF_TXADD7_Pos (15UL)
- #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos)
- #define RADIO_DACNF_TXADD6_Pos (14UL)
- #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos)
- #define RADIO_DACNF_TXADD5_Pos (13UL)
- #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos)
- #define RADIO_DACNF_TXADD4_Pos (12UL)
- #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos)
- #define RADIO_DACNF_TXADD3_Pos (11UL)
- #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos)
- #define RADIO_DACNF_TXADD2_Pos (10UL)
- #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos)
- #define RADIO_DACNF_TXADD1_Pos (9UL)
- #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos)
- #define RADIO_DACNF_TXADD0_Pos (8UL)
- #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos)
- #define RADIO_DACNF_ENA7_Pos (7UL)
- #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos)
- #define RADIO_DACNF_ENA7_Disabled (0UL)
- #define RADIO_DACNF_ENA7_Enabled (1UL)
- #define RADIO_DACNF_ENA6_Pos (6UL)
- #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos)
- #define RADIO_DACNF_ENA6_Disabled (0UL)
- #define RADIO_DACNF_ENA6_Enabled (1UL)
- #define RADIO_DACNF_ENA5_Pos (5UL)
- #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos)
- #define RADIO_DACNF_ENA5_Disabled (0UL)
- #define RADIO_DACNF_ENA5_Enabled (1UL)
- #define RADIO_DACNF_ENA4_Pos (4UL)
- #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos)
- #define RADIO_DACNF_ENA4_Disabled (0UL)
- #define RADIO_DACNF_ENA4_Enabled (1UL)
- #define RADIO_DACNF_ENA3_Pos (3UL)
- #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos)
- #define RADIO_DACNF_ENA3_Disabled (0UL)
- #define RADIO_DACNF_ENA3_Enabled (1UL)
- #define RADIO_DACNF_ENA2_Pos (2UL)
- #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos)
- #define RADIO_DACNF_ENA2_Disabled (0UL)
- #define RADIO_DACNF_ENA2_Enabled (1UL)
- #define RADIO_DACNF_ENA1_Pos (1UL)
- #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos)
- #define RADIO_DACNF_ENA1_Disabled (0UL)
- #define RADIO_DACNF_ENA1_Enabled (1UL)
- #define RADIO_DACNF_ENA0_Pos (0UL)
- #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos)
- #define RADIO_DACNF_ENA0_Disabled (0UL)
- #define RADIO_DACNF_ENA0_Enabled (1UL)
- #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos (0UL)
- #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos)
- #define RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos (0UL)
- #define RADIO_MHRMATCHMAS_MHRMATCHMAS_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos)
- #define RADIO_MODECNF0_DTX_Pos (8UL)
- #define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos)
- #define RADIO_MODECNF0_DTX_B1 (0UL)
- #define RADIO_MODECNF0_DTX_B0 (1UL)
- #define RADIO_MODECNF0_DTX_Center (2UL)
- #define RADIO_MODECNF0_RU_Pos (0UL)
- #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos)
- #define RADIO_MODECNF0_RU_Default (0UL)
- #define RADIO_MODECNF0_RU_Fast (1UL)
- #define RADIO_SFD_SFD_Pos (0UL)
- #define RADIO_SFD_SFD_Msk (0xFFUL << RADIO_SFD_SFD_Pos)
- #define RADIO_EDCNT_EDCNT_Pos (0UL)
- #define RADIO_EDCNT_EDCNT_Msk (0x1FFFFFUL << RADIO_EDCNT_EDCNT_Pos)
- #define RADIO_EDSAMPLE_EDLVL_Pos (0UL)
- #define RADIO_EDSAMPLE_EDLVL_Msk (0xFFUL << RADIO_EDSAMPLE_EDLVL_Pos)
- #define RADIO_CCACTRL_CCACORRCNT_Pos (24UL)
- #define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos)
- #define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL)
- #define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos)
- #define RADIO_CCACTRL_CCAEDTHRES_Pos (8UL)
- #define RADIO_CCACTRL_CCAEDTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCAEDTHRES_Pos)
- #define RADIO_CCACTRL_CCAMODE_Pos (0UL)
- #define RADIO_CCACTRL_CCAMODE_Msk (0x7UL << RADIO_CCACTRL_CCAMODE_Pos)
- #define RADIO_CCACTRL_CCAMODE_EdMode (0UL)
- #define RADIO_CCACTRL_CCAMODE_CarrierMode (1UL)
- #define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (2UL)
- #define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (3UL)
- #define RADIO_CCACTRL_CCAMODE_EdModeTest1 (4UL)
- #define RADIO_DFEMODE_DFEOPMODE_Pos (0UL)
- #define RADIO_DFEMODE_DFEOPMODE_Msk (0x3UL << RADIO_DFEMODE_DFEOPMODE_Pos)
- #define RADIO_DFEMODE_DFEOPMODE_Disabled (0UL)
- #define RADIO_DFEMODE_DFEOPMODE_AoD (2UL)
- #define RADIO_DFEMODE_DFEOPMODE_AoA (3UL)
- #define RADIO_CTEINLINECONF_S0MASK_Pos (24UL)
- #define RADIO_CTEINLINECONF_S0MASK_Msk (0xFFUL << RADIO_CTEINLINECONF_S0MASK_Pos)
- #define RADIO_CTEINLINECONF_S0CONF_Pos (16UL)
- #define RADIO_CTEINLINECONF_S0CONF_Msk (0xFFUL << RADIO_CTEINLINECONF_S0CONF_Pos)
- #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos (13UL)
- #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos)
- #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (1UL)
- #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (2UL)
- #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (3UL)
- #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (4UL)
- #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (5UL)
- #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (6UL)
- #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos (10UL)
- #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos)
- #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (1UL)
- #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (2UL)
- #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (3UL)
- #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (4UL)
- #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (5UL)
- #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (6UL)
- #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos (6UL)
- #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Msk (0x3UL << RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos)
- #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0UL)
- #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (1UL)
- #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (2UL)
- #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos (4UL)
- #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Msk (0x1UL << RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos)
- #define RADIO_CTEINLINECONF_CTEERRORHANDLING_No (0UL)
- #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Yes (1UL)
- #define RADIO_CTEINLINECONF_CTEINFOINS1_Pos (3UL)
- #define RADIO_CTEINLINECONF_CTEINFOINS1_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINFOINS1_Pos)
- #define RADIO_CTEINLINECONF_CTEINFOINS1_NotInS1 (0UL)
- #define RADIO_CTEINLINECONF_CTEINFOINS1_InS1 (1UL)
- #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos (0UL)
- #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos)
- #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Disabled (0UL)
- #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Enabled (1UL)
- #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos (24UL)
- #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Msk (0xFUL << RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos)
- #define RADIO_DFECTRL1_REPEATPATTERN_Pos (20UL)
- #define RADIO_DFECTRL1_REPEATPATTERN_Msk (0xFUL << RADIO_DFECTRL1_REPEATPATTERN_Pos)
- #define RADIO_DFECTRL1_REPEATPATTERN_NoRepeat (0UL)
- #define RADIO_DFECTRL1_TSAMPLESPACING_Pos (16UL)
- #define RADIO_DFECTRL1_TSAMPLESPACING_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACING_Pos)
- #define RADIO_DFECTRL1_TSAMPLESPACING_4us (1UL)
- #define RADIO_DFECTRL1_TSAMPLESPACING_2us (2UL)
- #define RADIO_DFECTRL1_TSAMPLESPACING_1us (3UL)
- #define RADIO_DFECTRL1_TSAMPLESPACING_500ns (4UL)
- #define RADIO_DFECTRL1_TSAMPLESPACING_250ns (5UL)
- #define RADIO_DFECTRL1_TSAMPLESPACING_125ns (6UL)
- #define RADIO_DFECTRL1_SAMPLETYPE_Pos (15UL)
- #define RADIO_DFECTRL1_SAMPLETYPE_Msk (0x1UL << RADIO_DFECTRL1_SAMPLETYPE_Pos)
- #define RADIO_DFECTRL1_SAMPLETYPE_IQ (0UL)
- #define RADIO_DFECTRL1_SAMPLETYPE_MagPhase (1UL)
- #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos (12UL)
- #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos)
- #define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (1UL)
- #define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (2UL)
- #define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (3UL)
- #define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (4UL)
- #define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (5UL)
- #define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (6UL)
- #define RADIO_DFECTRL1_TSWITCHSPACING_Pos (8UL)
- #define RADIO_DFECTRL1_TSWITCHSPACING_Msk (0x7UL << RADIO_DFECTRL1_TSWITCHSPACING_Pos)
- #define RADIO_DFECTRL1_TSWITCHSPACING_4us (1UL)
- #define RADIO_DFECTRL1_TSWITCHSPACING_2us (2UL)
- #define RADIO_DFECTRL1_TSWITCHSPACING_1us (3UL)
- #define RADIO_DFECTRL1_DFEINEXTENSION_Pos (7UL)
- #define RADIO_DFECTRL1_DFEINEXTENSION_Msk (0x1UL << RADIO_DFECTRL1_DFEINEXTENSION_Pos)
- #define RADIO_DFECTRL1_DFEINEXTENSION_Payload (0UL)
- #define RADIO_DFECTRL1_DFEINEXTENSION_CRC (1UL)
- #define RADIO_DFECTRL1_NUMBEROF8US_Pos (0UL)
- #define RADIO_DFECTRL1_NUMBEROF8US_Msk (0x3FUL << RADIO_DFECTRL1_NUMBEROF8US_Pos)
- #define RADIO_DFECTRL2_TSAMPLEOFFSET_Pos (16UL)
- #define RADIO_DFECTRL2_TSAMPLEOFFSET_Msk (0xFFFUL << RADIO_DFECTRL2_TSAMPLEOFFSET_Pos)
- #define RADIO_DFECTRL2_TSWITCHOFFSET_Pos (0UL)
- #define RADIO_DFECTRL2_TSWITCHOFFSET_Msk (0x1FFFUL << RADIO_DFECTRL2_TSWITCHOFFSET_Pos)
- #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos (0UL)
- #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Msk (0xFFUL << RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos)
- #define RADIO_CLEARPATTERN_CLEARPATTERN_Pos (0UL)
- #define RADIO_CLEARPATTERN_CLEARPATTERN_Msk (0x1UL << RADIO_CLEARPATTERN_CLEARPATTERN_Pos)
- #define RADIO_CLEARPATTERN_CLEARPATTERN_Clear (1UL)
- #define RADIO_PSEL_DFEGPIO_CONNECT_Pos (31UL)
- #define RADIO_PSEL_DFEGPIO_CONNECT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_CONNECT_Pos)
- #define RADIO_PSEL_DFEGPIO_CONNECT_Connected (0UL)
- #define RADIO_PSEL_DFEGPIO_CONNECT_Disconnected (1UL)
- #define RADIO_PSEL_DFEGPIO_PORT_Pos (5UL)
- #define RADIO_PSEL_DFEGPIO_PORT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_PORT_Pos)
- #define RADIO_PSEL_DFEGPIO_PIN_Pos (0UL)
- #define RADIO_PSEL_DFEGPIO_PIN_Msk (0x1FUL << RADIO_PSEL_DFEGPIO_PIN_Pos)
- #define RADIO_DFEPACKET_PTR_PTR_Pos (0UL)
- #define RADIO_DFEPACKET_PTR_PTR_Msk (0xFFFFFFFFUL << RADIO_DFEPACKET_PTR_PTR_Pos)
- #define RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos (0UL)
- #define RADIO_DFEPACKET_MAXCNT_MAXCNT_Msk (0x3FFFUL << RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos)
- #define RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos (0UL)
- #define RADIO_DFEPACKET_AMOUNT_AMOUNT_Msk (0xFFFFUL << RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos)
- #define RADIO_POWER_POWER_Pos (0UL)
- #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos)
- #define RADIO_POWER_POWER_Disabled (0UL)
- #define RADIO_POWER_POWER_Enabled (1UL)
- #define RESET_RESETREAS_LCTRLAP_Pos (27UL)
- #define RESET_RESETREAS_LCTRLAP_Msk (0x1UL << RESET_RESETREAS_LCTRLAP_Pos)
- #define RESET_RESETREAS_LCTRLAP_NotDetected (0UL)
- #define RESET_RESETREAS_LCTRLAP_Detected (1UL)
- #define RESET_RESETREAS_VBUS_Pos (26UL)
- #define RESET_RESETREAS_VBUS_Msk (0x1UL << RESET_RESETREAS_VBUS_Pos)
- #define RESET_RESETREAS_VBUS_NotDetected (0UL)
- #define RESET_RESETREAS_VBUS_Detected (1UL)
- #define RESET_RESETREAS_DOG1_Pos (25UL)
- #define RESET_RESETREAS_DOG1_Msk (0x1UL << RESET_RESETREAS_DOG1_Pos)
- #define RESET_RESETREAS_DOG1_NotDetected (0UL)
- #define RESET_RESETREAS_DOG1_Detected (1UL)
- #define RESET_RESETREAS_NFC_Pos (24UL)
- #define RESET_RESETREAS_NFC_Msk (0x1UL << RESET_RESETREAS_NFC_Pos)
- #define RESET_RESETREAS_NFC_NotDetected (0UL)
- #define RESET_RESETREAS_NFC_Detected (1UL)
- #define RESET_RESETREAS_MFORCEOFF_Pos (23UL)
- #define RESET_RESETREAS_MFORCEOFF_Msk (0x1UL << RESET_RESETREAS_MFORCEOFF_Pos)
- #define RESET_RESETREAS_MFORCEOFF_NotDetected (0UL)
- #define RESET_RESETREAS_MFORCEOFF_Detected (1UL)
- #define RESET_RESETREAS_LDOG_Pos (18UL)
- #define RESET_RESETREAS_LDOG_Msk (0x1UL << RESET_RESETREAS_LDOG_Pos)
- #define RESET_RESETREAS_LDOG_NotDetected (0UL)
- #define RESET_RESETREAS_LDOG_Detected (1UL)
- #define RESET_RESETREAS_LLOCKUP_Pos (17UL)
- #define RESET_RESETREAS_LLOCKUP_Msk (0x1UL << RESET_RESETREAS_LLOCKUP_Pos)
- #define RESET_RESETREAS_LLOCKUP_NotDetected (0UL)
- #define RESET_RESETREAS_LLOCKUP_Detected (1UL)
- #define RESET_RESETREAS_LSREQ_Pos (16UL)
- #define RESET_RESETREAS_LSREQ_Msk (0x1UL << RESET_RESETREAS_LSREQ_Pos)
- #define RESET_RESETREAS_LSREQ_NotDetected (0UL)
- #define RESET_RESETREAS_LSREQ_Detected (1UL)
- #define RESET_RESETREAS_DIF_Pos (7UL)
- #define RESET_RESETREAS_DIF_Msk (0x1UL << RESET_RESETREAS_DIF_Pos)
- #define RESET_RESETREAS_DIF_NotDetected (0UL)
- #define RESET_RESETREAS_DIF_Detected (1UL)
- #define RESET_RESETREAS_LPCOMP_Pos (6UL)
- #define RESET_RESETREAS_LPCOMP_Msk (0x1UL << RESET_RESETREAS_LPCOMP_Pos)
- #define RESET_RESETREAS_LPCOMP_NotDetected (0UL)
- #define RESET_RESETREAS_LPCOMP_Detected (1UL)
- #define RESET_RESETREAS_OFF_Pos (5UL)
- #define RESET_RESETREAS_OFF_Msk (0x1UL << RESET_RESETREAS_OFF_Pos)
- #define RESET_RESETREAS_OFF_NotDetected (0UL)
- #define RESET_RESETREAS_OFF_Detected (1UL)
- #define RESET_RESETREAS_LOCKUP_Pos (4UL)
- #define RESET_RESETREAS_LOCKUP_Msk (0x1UL << RESET_RESETREAS_LOCKUP_Pos)
- #define RESET_RESETREAS_LOCKUP_NotDetected (0UL)
- #define RESET_RESETREAS_LOCKUP_Detected (1UL)
- #define RESET_RESETREAS_SREQ_Pos (3UL)
- #define RESET_RESETREAS_SREQ_Msk (0x1UL << RESET_RESETREAS_SREQ_Pos)
- #define RESET_RESETREAS_SREQ_NotDetected (0UL)
- #define RESET_RESETREAS_SREQ_Detected (1UL)
- #define RESET_RESETREAS_CTRLAP_Pos (2UL)
- #define RESET_RESETREAS_CTRLAP_Msk (0x1UL << RESET_RESETREAS_CTRLAP_Pos)
- #define RESET_RESETREAS_CTRLAP_NotDetected (0UL)
- #define RESET_RESETREAS_CTRLAP_Detected (1UL)
- #define RESET_RESETREAS_DOG0_Pos (1UL)
- #define RESET_RESETREAS_DOG0_Msk (0x1UL << RESET_RESETREAS_DOG0_Pos)
- #define RESET_RESETREAS_DOG0_NotDetected (0UL)
- #define RESET_RESETREAS_DOG0_Detected (1UL)
- #define RESET_RESETREAS_RESETPIN_Pos (0UL)
- #define RESET_RESETREAS_RESETPIN_Msk (0x1UL << RESET_RESETREAS_RESETPIN_Pos)
- #define RESET_RESETREAS_RESETPIN_NotDetected (0UL)
- #define RESET_RESETREAS_RESETPIN_Detected (1UL)
- #define RNG_TASKS_START_TASKS_START_Pos (0UL)
- #define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos)
- #define RNG_TASKS_START_TASKS_START_Trigger (1UL)
- #define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos)
- #define RNG_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define RNG_SUBSCRIBE_START_EN_Pos (31UL)
- #define RNG_SUBSCRIBE_START_EN_Msk (0x1UL << RNG_SUBSCRIBE_START_EN_Pos)
- #define RNG_SUBSCRIBE_START_EN_Disabled (0UL)
- #define RNG_SUBSCRIBE_START_EN_Enabled (1UL)
- #define RNG_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define RNG_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RNG_SUBSCRIBE_START_CHIDX_Pos)
- #define RNG_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define RNG_SUBSCRIBE_STOP_EN_Msk (0x1UL << RNG_SUBSCRIBE_STOP_EN_Pos)
- #define RNG_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define RNG_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define RNG_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define RNG_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RNG_SUBSCRIBE_STOP_CHIDX_Pos)
- #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL)
- #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos)
- #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_NotGenerated (0UL)
- #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Generated (1UL)
- #define RNG_PUBLISH_VALRDY_EN_Pos (31UL)
- #define RNG_PUBLISH_VALRDY_EN_Msk (0x1UL << RNG_PUBLISH_VALRDY_EN_Pos)
- #define RNG_PUBLISH_VALRDY_EN_Disabled (0UL)
- #define RNG_PUBLISH_VALRDY_EN_Enabled (1UL)
- #define RNG_PUBLISH_VALRDY_CHIDX_Pos (0UL)
- #define RNG_PUBLISH_VALRDY_CHIDX_Msk (0xFFUL << RNG_PUBLISH_VALRDY_CHIDX_Pos)
- #define RNG_SHORTS_VALRDY_STOP_Pos (0UL)
- #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos)
- #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL)
- #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL)
- #define RNG_INTENSET_VALRDY_Pos (0UL)
- #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos)
- #define RNG_INTENSET_VALRDY_Disabled (0UL)
- #define RNG_INTENSET_VALRDY_Enabled (1UL)
- #define RNG_INTENSET_VALRDY_Set (1UL)
- #define RNG_INTENCLR_VALRDY_Pos (0UL)
- #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos)
- #define RNG_INTENCLR_VALRDY_Disabled (0UL)
- #define RNG_INTENCLR_VALRDY_Enabled (1UL)
- #define RNG_INTENCLR_VALRDY_Clear (1UL)
- #define RNG_CONFIG_DERCEN_Pos (0UL)
- #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos)
- #define RNG_CONFIG_DERCEN_Disabled (0UL)
- #define RNG_CONFIG_DERCEN_Enabled (1UL)
- #define RNG_VALUE_VALUE_Pos (0UL)
- #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos)
- #define RTC_TASKS_START_TASKS_START_Pos (0UL)
- #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos)
- #define RTC_TASKS_START_TASKS_START_Trigger (1UL)
- #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos)
- #define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL)
- #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos)
- #define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL)
- #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL)
- #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos)
- #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL)
- #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL)
- #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << RTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos)
- #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL)
- #define RTC_SUBSCRIBE_START_EN_Pos (31UL)
- #define RTC_SUBSCRIBE_START_EN_Msk (0x1UL << RTC_SUBSCRIBE_START_EN_Pos)
- #define RTC_SUBSCRIBE_START_EN_Disabled (0UL)
- #define RTC_SUBSCRIBE_START_EN_Enabled (1UL)
- #define RTC_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define RTC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_START_CHIDX_Pos)
- #define RTC_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define RTC_SUBSCRIBE_STOP_EN_Msk (0x1UL << RTC_SUBSCRIBE_STOP_EN_Pos)
- #define RTC_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define RTC_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define RTC_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define RTC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_STOP_CHIDX_Pos)
- #define RTC_SUBSCRIBE_CLEAR_EN_Pos (31UL)
- #define RTC_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << RTC_SUBSCRIBE_CLEAR_EN_Pos)
- #define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0UL)
- #define RTC_SUBSCRIBE_CLEAR_EN_Enabled (1UL)
- #define RTC_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL)
- #define RTC_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CLEAR_CHIDX_Pos)
- #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos (31UL)
- #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Msk (0x1UL << RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos)
- #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0UL)
- #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (1UL)
- #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos (0UL)
- #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos)
- #define RTC_SUBSCRIBE_CAPTURE_EN_Pos (31UL)
- #define RTC_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << RTC_SUBSCRIBE_CAPTURE_EN_Pos)
- #define RTC_SUBSCRIBE_CAPTURE_EN_Disabled (0UL)
- #define RTC_SUBSCRIBE_CAPTURE_EN_Enabled (1UL)
- #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL)
- #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CAPTURE_CHIDX_Pos)
- #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL)
- #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos)
- #define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL)
- #define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL)
- #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL)
- #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos)
- #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL)
- #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL)
- #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL)
- #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos)
- #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL)
- #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL)
- #define RTC_PUBLISH_TICK_EN_Pos (31UL)
- #define RTC_PUBLISH_TICK_EN_Msk (0x1UL << RTC_PUBLISH_TICK_EN_Pos)
- #define RTC_PUBLISH_TICK_EN_Disabled (0UL)
- #define RTC_PUBLISH_TICK_EN_Enabled (1UL)
- #define RTC_PUBLISH_TICK_CHIDX_Pos (0UL)
- #define RTC_PUBLISH_TICK_CHIDX_Msk (0xFFUL << RTC_PUBLISH_TICK_CHIDX_Pos)
- #define RTC_PUBLISH_OVRFLW_EN_Pos (31UL)
- #define RTC_PUBLISH_OVRFLW_EN_Msk (0x1UL << RTC_PUBLISH_OVRFLW_EN_Pos)
- #define RTC_PUBLISH_OVRFLW_EN_Disabled (0UL)
- #define RTC_PUBLISH_OVRFLW_EN_Enabled (1UL)
- #define RTC_PUBLISH_OVRFLW_CHIDX_Pos (0UL)
- #define RTC_PUBLISH_OVRFLW_CHIDX_Msk (0xFFUL << RTC_PUBLISH_OVRFLW_CHIDX_Pos)
- #define RTC_PUBLISH_COMPARE_EN_Pos (31UL)
- #define RTC_PUBLISH_COMPARE_EN_Msk (0x1UL << RTC_PUBLISH_COMPARE_EN_Pos)
- #define RTC_PUBLISH_COMPARE_EN_Disabled (0UL)
- #define RTC_PUBLISH_COMPARE_EN_Enabled (1UL)
- #define RTC_PUBLISH_COMPARE_CHIDX_Pos (0UL)
- #define RTC_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << RTC_PUBLISH_COMPARE_CHIDX_Pos)
- #define RTC_SHORTS_COMPARE3_CLEAR_Pos (3UL)
- #define RTC_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE3_CLEAR_Pos)
- #define RTC_SHORTS_COMPARE3_CLEAR_Disabled (0UL)
- #define RTC_SHORTS_COMPARE3_CLEAR_Enabled (1UL)
- #define RTC_SHORTS_COMPARE2_CLEAR_Pos (2UL)
- #define RTC_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE2_CLEAR_Pos)
- #define RTC_SHORTS_COMPARE2_CLEAR_Disabled (0UL)
- #define RTC_SHORTS_COMPARE2_CLEAR_Enabled (1UL)
- #define RTC_SHORTS_COMPARE1_CLEAR_Pos (1UL)
- #define RTC_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE1_CLEAR_Pos)
- #define RTC_SHORTS_COMPARE1_CLEAR_Disabled (0UL)
- #define RTC_SHORTS_COMPARE1_CLEAR_Enabled (1UL)
- #define RTC_SHORTS_COMPARE0_CLEAR_Pos (0UL)
- #define RTC_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE0_CLEAR_Pos)
- #define RTC_SHORTS_COMPARE0_CLEAR_Disabled (0UL)
- #define RTC_SHORTS_COMPARE0_CLEAR_Enabled (1UL)
- #define RTC_INTENSET_COMPARE3_Pos (19UL)
- #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos)
- #define RTC_INTENSET_COMPARE3_Disabled (0UL)
- #define RTC_INTENSET_COMPARE3_Enabled (1UL)
- #define RTC_INTENSET_COMPARE3_Set (1UL)
- #define RTC_INTENSET_COMPARE2_Pos (18UL)
- #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos)
- #define RTC_INTENSET_COMPARE2_Disabled (0UL)
- #define RTC_INTENSET_COMPARE2_Enabled (1UL)
- #define RTC_INTENSET_COMPARE2_Set (1UL)
- #define RTC_INTENSET_COMPARE1_Pos (17UL)
- #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos)
- #define RTC_INTENSET_COMPARE1_Disabled (0UL)
- #define RTC_INTENSET_COMPARE1_Enabled (1UL)
- #define RTC_INTENSET_COMPARE1_Set (1UL)
- #define RTC_INTENSET_COMPARE0_Pos (16UL)
- #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos)
- #define RTC_INTENSET_COMPARE0_Disabled (0UL)
- #define RTC_INTENSET_COMPARE0_Enabled (1UL)
- #define RTC_INTENSET_COMPARE0_Set (1UL)
- #define RTC_INTENSET_OVRFLW_Pos (1UL)
- #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos)
- #define RTC_INTENSET_OVRFLW_Disabled (0UL)
- #define RTC_INTENSET_OVRFLW_Enabled (1UL)
- #define RTC_INTENSET_OVRFLW_Set (1UL)
- #define RTC_INTENSET_TICK_Pos (0UL)
- #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos)
- #define RTC_INTENSET_TICK_Disabled (0UL)
- #define RTC_INTENSET_TICK_Enabled (1UL)
- #define RTC_INTENSET_TICK_Set (1UL)
- #define RTC_INTENCLR_COMPARE3_Pos (19UL)
- #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos)
- #define RTC_INTENCLR_COMPARE3_Disabled (0UL)
- #define RTC_INTENCLR_COMPARE3_Enabled (1UL)
- #define RTC_INTENCLR_COMPARE3_Clear (1UL)
- #define RTC_INTENCLR_COMPARE2_Pos (18UL)
- #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos)
- #define RTC_INTENCLR_COMPARE2_Disabled (0UL)
- #define RTC_INTENCLR_COMPARE2_Enabled (1UL)
- #define RTC_INTENCLR_COMPARE2_Clear (1UL)
- #define RTC_INTENCLR_COMPARE1_Pos (17UL)
- #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos)
- #define RTC_INTENCLR_COMPARE1_Disabled (0UL)
- #define RTC_INTENCLR_COMPARE1_Enabled (1UL)
- #define RTC_INTENCLR_COMPARE1_Clear (1UL)
- #define RTC_INTENCLR_COMPARE0_Pos (16UL)
- #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos)
- #define RTC_INTENCLR_COMPARE0_Disabled (0UL)
- #define RTC_INTENCLR_COMPARE0_Enabled (1UL)
- #define RTC_INTENCLR_COMPARE0_Clear (1UL)
- #define RTC_INTENCLR_OVRFLW_Pos (1UL)
- #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos)
- #define RTC_INTENCLR_OVRFLW_Disabled (0UL)
- #define RTC_INTENCLR_OVRFLW_Enabled (1UL)
- #define RTC_INTENCLR_OVRFLW_Clear (1UL)
- #define RTC_INTENCLR_TICK_Pos (0UL)
- #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos)
- #define RTC_INTENCLR_TICK_Disabled (0UL)
- #define RTC_INTENCLR_TICK_Enabled (1UL)
- #define RTC_INTENCLR_TICK_Clear (1UL)
- #define RTC_EVTEN_COMPARE3_Pos (19UL)
- #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos)
- #define RTC_EVTEN_COMPARE3_Disabled (0UL)
- #define RTC_EVTEN_COMPARE3_Enabled (1UL)
- #define RTC_EVTEN_COMPARE2_Pos (18UL)
- #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos)
- #define RTC_EVTEN_COMPARE2_Disabled (0UL)
- #define RTC_EVTEN_COMPARE2_Enabled (1UL)
- #define RTC_EVTEN_COMPARE1_Pos (17UL)
- #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos)
- #define RTC_EVTEN_COMPARE1_Disabled (0UL)
- #define RTC_EVTEN_COMPARE1_Enabled (1UL)
- #define RTC_EVTEN_COMPARE0_Pos (16UL)
- #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos)
- #define RTC_EVTEN_COMPARE0_Disabled (0UL)
- #define RTC_EVTEN_COMPARE0_Enabled (1UL)
- #define RTC_EVTEN_OVRFLW_Pos (1UL)
- #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos)
- #define RTC_EVTEN_OVRFLW_Disabled (0UL)
- #define RTC_EVTEN_OVRFLW_Enabled (1UL)
- #define RTC_EVTEN_TICK_Pos (0UL)
- #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos)
- #define RTC_EVTEN_TICK_Disabled (0UL)
- #define RTC_EVTEN_TICK_Enabled (1UL)
- #define RTC_EVTENSET_COMPARE3_Pos (19UL)
- #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos)
- #define RTC_EVTENSET_COMPARE3_Disabled (0UL)
- #define RTC_EVTENSET_COMPARE3_Enabled (1UL)
- #define RTC_EVTENSET_COMPARE3_Set (1UL)
- #define RTC_EVTENSET_COMPARE2_Pos (18UL)
- #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos)
- #define RTC_EVTENSET_COMPARE2_Disabled (0UL)
- #define RTC_EVTENSET_COMPARE2_Enabled (1UL)
- #define RTC_EVTENSET_COMPARE2_Set (1UL)
- #define RTC_EVTENSET_COMPARE1_Pos (17UL)
- #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos)
- #define RTC_EVTENSET_COMPARE1_Disabled (0UL)
- #define RTC_EVTENSET_COMPARE1_Enabled (1UL)
- #define RTC_EVTENSET_COMPARE1_Set (1UL)
- #define RTC_EVTENSET_COMPARE0_Pos (16UL)
- #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos)
- #define RTC_EVTENSET_COMPARE0_Disabled (0UL)
- #define RTC_EVTENSET_COMPARE0_Enabled (1UL)
- #define RTC_EVTENSET_COMPARE0_Set (1UL)
- #define RTC_EVTENSET_OVRFLW_Pos (1UL)
- #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos)
- #define RTC_EVTENSET_OVRFLW_Disabled (0UL)
- #define RTC_EVTENSET_OVRFLW_Enabled (1UL)
- #define RTC_EVTENSET_OVRFLW_Set (1UL)
- #define RTC_EVTENSET_TICK_Pos (0UL)
- #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos)
- #define RTC_EVTENSET_TICK_Disabled (0UL)
- #define RTC_EVTENSET_TICK_Enabled (1UL)
- #define RTC_EVTENSET_TICK_Set (1UL)
- #define RTC_EVTENCLR_COMPARE3_Pos (19UL)
- #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos)
- #define RTC_EVTENCLR_COMPARE3_Disabled (0UL)
- #define RTC_EVTENCLR_COMPARE3_Enabled (1UL)
- #define RTC_EVTENCLR_COMPARE3_Clear (1UL)
- #define RTC_EVTENCLR_COMPARE2_Pos (18UL)
- #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos)
- #define RTC_EVTENCLR_COMPARE2_Disabled (0UL)
- #define RTC_EVTENCLR_COMPARE2_Enabled (1UL)
- #define RTC_EVTENCLR_COMPARE2_Clear (1UL)
- #define RTC_EVTENCLR_COMPARE1_Pos (17UL)
- #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos)
- #define RTC_EVTENCLR_COMPARE1_Disabled (0UL)
- #define RTC_EVTENCLR_COMPARE1_Enabled (1UL)
- #define RTC_EVTENCLR_COMPARE1_Clear (1UL)
- #define RTC_EVTENCLR_COMPARE0_Pos (16UL)
- #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos)
- #define RTC_EVTENCLR_COMPARE0_Disabled (0UL)
- #define RTC_EVTENCLR_COMPARE0_Enabled (1UL)
- #define RTC_EVTENCLR_COMPARE0_Clear (1UL)
- #define RTC_EVTENCLR_OVRFLW_Pos (1UL)
- #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos)
- #define RTC_EVTENCLR_OVRFLW_Disabled (0UL)
- #define RTC_EVTENCLR_OVRFLW_Enabled (1UL)
- #define RTC_EVTENCLR_OVRFLW_Clear (1UL)
- #define RTC_EVTENCLR_TICK_Pos (0UL)
- #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos)
- #define RTC_EVTENCLR_TICK_Disabled (0UL)
- #define RTC_EVTENCLR_TICK_Enabled (1UL)
- #define RTC_EVTENCLR_TICK_Clear (1UL)
- #define RTC_COUNTER_COUNTER_Pos (0UL)
- #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos)
- #define RTC_PRESCALER_PRESCALER_Pos (0UL)
- #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos)
- #define RTC_CC_COMPARE_Pos (0UL)
- #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos)
- #define SPIM_TASKS_START_TASKS_START_Pos (0UL)
- #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos)
- #define SPIM_TASKS_START_TASKS_START_Trigger (1UL)
- #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos)
- #define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL)
- #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos)
- #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL)
- #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL)
- #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos)
- #define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL)
- #define SPIM_SUBSCRIBE_START_EN_Pos (31UL)
- #define SPIM_SUBSCRIBE_START_EN_Msk (0x1UL << SPIM_SUBSCRIBE_START_EN_Pos)
- #define SPIM_SUBSCRIBE_START_EN_Disabled (0UL)
- #define SPIM_SUBSCRIBE_START_EN_Enabled (1UL)
- #define SPIM_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define SPIM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_START_CHIDX_Pos)
- #define SPIM_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define SPIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << SPIM_SUBSCRIBE_STOP_EN_Pos)
- #define SPIM_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define SPIM_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define SPIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define SPIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_STOP_CHIDX_Pos)
- #define SPIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL)
- #define SPIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << SPIM_SUBSCRIBE_SUSPEND_EN_Pos)
- #define SPIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL)
- #define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL)
- #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL)
- #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos)
- #define SPIM_SUBSCRIBE_RESUME_EN_Pos (31UL)
- #define SPIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << SPIM_SUBSCRIBE_RESUME_EN_Pos)
- #define SPIM_SUBSCRIBE_RESUME_EN_Disabled (0UL)
- #define SPIM_SUBSCRIBE_RESUME_EN_Enabled (1UL)
- #define SPIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL)
- #define SPIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_RESUME_CHIDX_Pos)
- #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL)
- #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos)
- #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL)
- #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL)
- #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL)
- #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos)
- #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL)
- #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL)
- #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL)
- #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos)
- #define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL)
- #define SPIM_EVENTS_END_EVENTS_END_Generated (1UL)
- #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL)
- #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos)
- #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL)
- #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL)
- #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL)
- #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos)
- #define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL)
- #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL)
- #define SPIM_PUBLISH_STOPPED_EN_Pos (31UL)
- #define SPIM_PUBLISH_STOPPED_EN_Msk (0x1UL << SPIM_PUBLISH_STOPPED_EN_Pos)
- #define SPIM_PUBLISH_STOPPED_EN_Disabled (0UL)
- #define SPIM_PUBLISH_STOPPED_EN_Enabled (1UL)
- #define SPIM_PUBLISH_STOPPED_CHIDX_Pos (0UL)
- #define SPIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STOPPED_CHIDX_Pos)
- #define SPIM_PUBLISH_ENDRX_EN_Pos (31UL)
- #define SPIM_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDRX_EN_Pos)
- #define SPIM_PUBLISH_ENDRX_EN_Disabled (0UL)
- #define SPIM_PUBLISH_ENDRX_EN_Enabled (1UL)
- #define SPIM_PUBLISH_ENDRX_CHIDX_Pos (0UL)
- #define SPIM_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDRX_CHIDX_Pos)
- #define SPIM_PUBLISH_END_EN_Pos (31UL)
- #define SPIM_PUBLISH_END_EN_Msk (0x1UL << SPIM_PUBLISH_END_EN_Pos)
- #define SPIM_PUBLISH_END_EN_Disabled (0UL)
- #define SPIM_PUBLISH_END_EN_Enabled (1UL)
- #define SPIM_PUBLISH_END_CHIDX_Pos (0UL)
- #define SPIM_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_END_CHIDX_Pos)
- #define SPIM_PUBLISH_ENDTX_EN_Pos (31UL)
- #define SPIM_PUBLISH_ENDTX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDTX_EN_Pos)
- #define SPIM_PUBLISH_ENDTX_EN_Disabled (0UL)
- #define SPIM_PUBLISH_ENDTX_EN_Enabled (1UL)
- #define SPIM_PUBLISH_ENDTX_CHIDX_Pos (0UL)
- #define SPIM_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDTX_CHIDX_Pos)
- #define SPIM_PUBLISH_STARTED_EN_Pos (31UL)
- #define SPIM_PUBLISH_STARTED_EN_Msk (0x1UL << SPIM_PUBLISH_STARTED_EN_Pos)
- #define SPIM_PUBLISH_STARTED_EN_Disabled (0UL)
- #define SPIM_PUBLISH_STARTED_EN_Enabled (1UL)
- #define SPIM_PUBLISH_STARTED_CHIDX_Pos (0UL)
- #define SPIM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STARTED_CHIDX_Pos)
- #define SPIM_SHORTS_END_START_Pos (17UL)
- #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos)
- #define SPIM_SHORTS_END_START_Disabled (0UL)
- #define SPIM_SHORTS_END_START_Enabled (1UL)
- #define SPIM_INTENSET_STARTED_Pos (19UL)
- #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos)
- #define SPIM_INTENSET_STARTED_Disabled (0UL)
- #define SPIM_INTENSET_STARTED_Enabled (1UL)
- #define SPIM_INTENSET_STARTED_Set (1UL)
- #define SPIM_INTENSET_ENDTX_Pos (8UL)
- #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos)
- #define SPIM_INTENSET_ENDTX_Disabled (0UL)
- #define SPIM_INTENSET_ENDTX_Enabled (1UL)
- #define SPIM_INTENSET_ENDTX_Set (1UL)
- #define SPIM_INTENSET_END_Pos (6UL)
- #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos)
- #define SPIM_INTENSET_END_Disabled (0UL)
- #define SPIM_INTENSET_END_Enabled (1UL)
- #define SPIM_INTENSET_END_Set (1UL)
- #define SPIM_INTENSET_ENDRX_Pos (4UL)
- #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos)
- #define SPIM_INTENSET_ENDRX_Disabled (0UL)
- #define SPIM_INTENSET_ENDRX_Enabled (1UL)
- #define SPIM_INTENSET_ENDRX_Set (1UL)
- #define SPIM_INTENSET_STOPPED_Pos (1UL)
- #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos)
- #define SPIM_INTENSET_STOPPED_Disabled (0UL)
- #define SPIM_INTENSET_STOPPED_Enabled (1UL)
- #define SPIM_INTENSET_STOPPED_Set (1UL)
- #define SPIM_INTENCLR_STARTED_Pos (19UL)
- #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos)
- #define SPIM_INTENCLR_STARTED_Disabled (0UL)
- #define SPIM_INTENCLR_STARTED_Enabled (1UL)
- #define SPIM_INTENCLR_STARTED_Clear (1UL)
- #define SPIM_INTENCLR_ENDTX_Pos (8UL)
- #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos)
- #define SPIM_INTENCLR_ENDTX_Disabled (0UL)
- #define SPIM_INTENCLR_ENDTX_Enabled (1UL)
- #define SPIM_INTENCLR_ENDTX_Clear (1UL)
- #define SPIM_INTENCLR_END_Pos (6UL)
- #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos)
- #define SPIM_INTENCLR_END_Disabled (0UL)
- #define SPIM_INTENCLR_END_Enabled (1UL)
- #define SPIM_INTENCLR_END_Clear (1UL)
- #define SPIM_INTENCLR_ENDRX_Pos (4UL)
- #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos)
- #define SPIM_INTENCLR_ENDRX_Disabled (0UL)
- #define SPIM_INTENCLR_ENDRX_Enabled (1UL)
- #define SPIM_INTENCLR_ENDRX_Clear (1UL)
- #define SPIM_INTENCLR_STOPPED_Pos (1UL)
- #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos)
- #define SPIM_INTENCLR_STOPPED_Disabled (0UL)
- #define SPIM_INTENCLR_STOPPED_Enabled (1UL)
- #define SPIM_INTENCLR_STOPPED_Clear (1UL)
- #define SPIM_STALLSTAT_RX_Pos (1UL)
- #define SPIM_STALLSTAT_RX_Msk (0x1UL << SPIM_STALLSTAT_RX_Pos)
- #define SPIM_STALLSTAT_RX_NOSTALL (0UL)
- #define SPIM_STALLSTAT_RX_STALL (1UL)
- #define SPIM_STALLSTAT_TX_Pos (0UL)
- #define SPIM_STALLSTAT_TX_Msk (0x1UL << SPIM_STALLSTAT_TX_Pos)
- #define SPIM_STALLSTAT_TX_NOSTALL (0UL)
- #define SPIM_STALLSTAT_TX_STALL (1UL)
- #define SPIM_ENABLE_ENABLE_Pos (0UL)
- #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos)
- #define SPIM_ENABLE_ENABLE_Disabled (0UL)
- #define SPIM_ENABLE_ENABLE_Enabled (7UL)
- #define SPIM_PSEL_SCK_CONNECT_Pos (31UL)
- #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos)
- #define SPIM_PSEL_SCK_CONNECT_Connected (0UL)
- #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL)
- #define SPIM_PSEL_SCK_PORT_Pos (5UL)
- #define SPIM_PSEL_SCK_PORT_Msk (0x1UL << SPIM_PSEL_SCK_PORT_Pos)
- #define SPIM_PSEL_SCK_PIN_Pos (0UL)
- #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos)
- #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL)
- #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos)
- #define SPIM_PSEL_MOSI_CONNECT_Connected (0UL)
- #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL)
- #define SPIM_PSEL_MOSI_PORT_Pos (5UL)
- #define SPIM_PSEL_MOSI_PORT_Msk (0x1UL << SPIM_PSEL_MOSI_PORT_Pos)
- #define SPIM_PSEL_MOSI_PIN_Pos (0UL)
- #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos)
- #define SPIM_PSEL_MISO_CONNECT_Pos (31UL)
- #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos)
- #define SPIM_PSEL_MISO_CONNECT_Connected (0UL)
- #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL)
- #define SPIM_PSEL_MISO_PORT_Pos (5UL)
- #define SPIM_PSEL_MISO_PORT_Msk (0x1UL << SPIM_PSEL_MISO_PORT_Pos)
- #define SPIM_PSEL_MISO_PIN_Pos (0UL)
- #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos)
- #define SPIM_PSEL_CSN_CONNECT_Pos (31UL)
- #define SPIM_PSEL_CSN_CONNECT_Msk (0x1UL << SPIM_PSEL_CSN_CONNECT_Pos)
- #define SPIM_PSEL_CSN_CONNECT_Connected (0UL)
- #define SPIM_PSEL_CSN_CONNECT_Disconnected (1UL)
- #define SPIM_PSEL_CSN_PORT_Pos (5UL)
- #define SPIM_PSEL_CSN_PORT_Msk (0x1UL << SPIM_PSEL_CSN_PORT_Pos)
- #define SPIM_PSEL_CSN_PIN_Pos (0UL)
- #define SPIM_PSEL_CSN_PIN_Msk (0x1FUL << SPIM_PSEL_CSN_PIN_Pos)
- #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL)
- #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos)
- #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL)
- #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL)
- #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL)
- #define SPIM_FREQUENCY_FREQUENCY_M16 (0x0A000000UL)
- #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL)
- #define SPIM_FREQUENCY_FREQUENCY_M32 (0x14000000UL)
- #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL)
- #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL)
- #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL)
- #define SPIM_RXD_PTR_PTR_Pos (0UL)
- #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos)
- #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL)
- #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos)
- #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL)
- #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos)
- #define SPIM_RXD_LIST_LIST_Pos (0UL)
- #define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos)
- #define SPIM_RXD_LIST_LIST_Disabled (0UL)
- #define SPIM_RXD_LIST_LIST_ArrayList (1UL)
- #define SPIM_TXD_PTR_PTR_Pos (0UL)
- #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos)
- #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL)
- #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos)
- #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL)
- #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos)
- #define SPIM_TXD_LIST_LIST_Pos (0UL)
- #define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos)
- #define SPIM_TXD_LIST_LIST_Disabled (0UL)
- #define SPIM_TXD_LIST_LIST_ArrayList (1UL)
- #define SPIM_CONFIG_CPOL_Pos (2UL)
- #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos)
- #define SPIM_CONFIG_CPOL_ActiveHigh (0UL)
- #define SPIM_CONFIG_CPOL_ActiveLow (1UL)
- #define SPIM_CONFIG_CPHA_Pos (1UL)
- #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos)
- #define SPIM_CONFIG_CPHA_Leading (0UL)
- #define SPIM_CONFIG_CPHA_Trailing (1UL)
- #define SPIM_CONFIG_ORDER_Pos (0UL)
- #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos)
- #define SPIM_CONFIG_ORDER_MsbFirst (0UL)
- #define SPIM_CONFIG_ORDER_LsbFirst (1UL)
- #define SPIM_IFTIMING_RXDELAY_RXDELAY_Pos (0UL)
- #define SPIM_IFTIMING_RXDELAY_RXDELAY_Msk (0x7UL << SPIM_IFTIMING_RXDELAY_RXDELAY_Pos)
- #define SPIM_IFTIMING_CSNDUR_CSNDUR_Pos (0UL)
- #define SPIM_IFTIMING_CSNDUR_CSNDUR_Msk (0xFFUL << SPIM_IFTIMING_CSNDUR_CSNDUR_Pos)
- #define SPIM_CSNPOL_CSNPOL_Pos (0UL)
- #define SPIM_CSNPOL_CSNPOL_Msk (0x1UL << SPIM_CSNPOL_CSNPOL_Pos)
- #define SPIM_CSNPOL_CSNPOL_LOW (0UL)
- #define SPIM_CSNPOL_CSNPOL_HIGH (1UL)
- #define SPIM_PSELDCX_CONNECT_Pos (31UL)
- #define SPIM_PSELDCX_CONNECT_Msk (0x1UL << SPIM_PSELDCX_CONNECT_Pos)
- #define SPIM_PSELDCX_CONNECT_Connected (0UL)
- #define SPIM_PSELDCX_CONNECT_Disconnected (1UL)
- #define SPIM_PSELDCX_PORT_Pos (5UL)
- #define SPIM_PSELDCX_PORT_Msk (0x1UL << SPIM_PSELDCX_PORT_Pos)
- #define SPIM_PSELDCX_PIN_Pos (0UL)
- #define SPIM_PSELDCX_PIN_Msk (0x1FUL << SPIM_PSELDCX_PIN_Pos)
- #define SPIM_DCXCNT_DCXCNT_Pos (0UL)
- #define SPIM_DCXCNT_DCXCNT_Msk (0xFUL << SPIM_DCXCNT_DCXCNT_Pos)
- #define SPIM_ORC_ORC_Pos (0UL)
- #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos)
- #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL)
- #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos)
- #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL)
- #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL)
- #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos)
- #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL)
- #define SPIS_SUBSCRIBE_ACQUIRE_EN_Pos (31UL)
- #define SPIS_SUBSCRIBE_ACQUIRE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_ACQUIRE_EN_Pos)
- #define SPIS_SUBSCRIBE_ACQUIRE_EN_Disabled (0UL)
- #define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (1UL)
- #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos (0UL)
- #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos)
- #define SPIS_SUBSCRIBE_RELEASE_EN_Pos (31UL)
- #define SPIS_SUBSCRIBE_RELEASE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_RELEASE_EN_Pos)
- #define SPIS_SUBSCRIBE_RELEASE_EN_Disabled (0UL)
- #define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (1UL)
- #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos (0UL)
- #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos)
- #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL)
- #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos)
- #define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL)
- #define SPIS_EVENTS_END_EVENTS_END_Generated (1UL)
- #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL)
- #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos)
- #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL)
- #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL)
- #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL)
- #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos)
- #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL)
- #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL)
- #define SPIS_PUBLISH_END_EN_Pos (31UL)
- #define SPIS_PUBLISH_END_EN_Msk (0x1UL << SPIS_PUBLISH_END_EN_Pos)
- #define SPIS_PUBLISH_END_EN_Disabled (0UL)
- #define SPIS_PUBLISH_END_EN_Enabled (1UL)
- #define SPIS_PUBLISH_END_CHIDX_Pos (0UL)
- #define SPIS_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_END_CHIDX_Pos)
- #define SPIS_PUBLISH_ENDRX_EN_Pos (31UL)
- #define SPIS_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIS_PUBLISH_ENDRX_EN_Pos)
- #define SPIS_PUBLISH_ENDRX_EN_Disabled (0UL)
- #define SPIS_PUBLISH_ENDRX_EN_Enabled (1UL)
- #define SPIS_PUBLISH_ENDRX_CHIDX_Pos (0UL)
- #define SPIS_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ENDRX_CHIDX_Pos)
- #define SPIS_PUBLISH_ACQUIRED_EN_Pos (31UL)
- #define SPIS_PUBLISH_ACQUIRED_EN_Msk (0x1UL << SPIS_PUBLISH_ACQUIRED_EN_Pos)
- #define SPIS_PUBLISH_ACQUIRED_EN_Disabled (0UL)
- #define SPIS_PUBLISH_ACQUIRED_EN_Enabled (1UL)
- #define SPIS_PUBLISH_ACQUIRED_CHIDX_Pos (0UL)
- #define SPIS_PUBLISH_ACQUIRED_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ACQUIRED_CHIDX_Pos)
- #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL)
- #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos)
- #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL)
- #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL)
- #define SPIS_INTENSET_ACQUIRED_Pos (10UL)
- #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos)
- #define SPIS_INTENSET_ACQUIRED_Disabled (0UL)
- #define SPIS_INTENSET_ACQUIRED_Enabled (1UL)
- #define SPIS_INTENSET_ACQUIRED_Set (1UL)
- #define SPIS_INTENSET_ENDRX_Pos (4UL)
- #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos)
- #define SPIS_INTENSET_ENDRX_Disabled (0UL)
- #define SPIS_INTENSET_ENDRX_Enabled (1UL)
- #define SPIS_INTENSET_ENDRX_Set (1UL)
- #define SPIS_INTENSET_END_Pos (1UL)
- #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos)
- #define SPIS_INTENSET_END_Disabled (0UL)
- #define SPIS_INTENSET_END_Enabled (1UL)
- #define SPIS_INTENSET_END_Set (1UL)
- #define SPIS_INTENCLR_ACQUIRED_Pos (10UL)
- #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos)
- #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL)
- #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL)
- #define SPIS_INTENCLR_ACQUIRED_Clear (1UL)
- #define SPIS_INTENCLR_ENDRX_Pos (4UL)
- #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos)
- #define SPIS_INTENCLR_ENDRX_Disabled (0UL)
- #define SPIS_INTENCLR_ENDRX_Enabled (1UL)
- #define SPIS_INTENCLR_ENDRX_Clear (1UL)
- #define SPIS_INTENCLR_END_Pos (1UL)
- #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos)
- #define SPIS_INTENCLR_END_Disabled (0UL)
- #define SPIS_INTENCLR_END_Enabled (1UL)
- #define SPIS_INTENCLR_END_Clear (1UL)
- #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL)
- #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos)
- #define SPIS_SEMSTAT_SEMSTAT_Free (0UL)
- #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL)
- #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL)
- #define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL)
- #define SPIS_STATUS_OVERFLOW_Pos (1UL)
- #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos)
- #define SPIS_STATUS_OVERFLOW_NotPresent (0UL)
- #define SPIS_STATUS_OVERFLOW_Present (1UL)
- #define SPIS_STATUS_OVERFLOW_Clear (1UL)
- #define SPIS_STATUS_OVERREAD_Pos (0UL)
- #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos)
- #define SPIS_STATUS_OVERREAD_NotPresent (0UL)
- #define SPIS_STATUS_OVERREAD_Present (1UL)
- #define SPIS_STATUS_OVERREAD_Clear (1UL)
- #define SPIS_ENABLE_ENABLE_Pos (0UL)
- #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos)
- #define SPIS_ENABLE_ENABLE_Disabled (0UL)
- #define SPIS_ENABLE_ENABLE_Enabled (2UL)
- #define SPIS_PSEL_SCK_CONNECT_Pos (31UL)
- #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos)
- #define SPIS_PSEL_SCK_CONNECT_Connected (0UL)
- #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL)
- #define SPIS_PSEL_SCK_PORT_Pos (5UL)
- #define SPIS_PSEL_SCK_PORT_Msk (0x1UL << SPIS_PSEL_SCK_PORT_Pos)
- #define SPIS_PSEL_SCK_PIN_Pos (0UL)
- #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos)
- #define SPIS_PSEL_MISO_CONNECT_Pos (31UL)
- #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos)
- #define SPIS_PSEL_MISO_CONNECT_Connected (0UL)
- #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL)
- #define SPIS_PSEL_MISO_PORT_Pos (5UL)
- #define SPIS_PSEL_MISO_PORT_Msk (0x1UL << SPIS_PSEL_MISO_PORT_Pos)
- #define SPIS_PSEL_MISO_PIN_Pos (0UL)
- #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos)
- #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL)
- #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos)
- #define SPIS_PSEL_MOSI_CONNECT_Connected (0UL)
- #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL)
- #define SPIS_PSEL_MOSI_PORT_Pos (5UL)
- #define SPIS_PSEL_MOSI_PORT_Msk (0x1UL << SPIS_PSEL_MOSI_PORT_Pos)
- #define SPIS_PSEL_MOSI_PIN_Pos (0UL)
- #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos)
- #define SPIS_PSEL_CSN_CONNECT_Pos (31UL)
- #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos)
- #define SPIS_PSEL_CSN_CONNECT_Connected (0UL)
- #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL)
- #define SPIS_PSEL_CSN_PORT_Pos (5UL)
- #define SPIS_PSEL_CSN_PORT_Msk (0x1UL << SPIS_PSEL_CSN_PORT_Pos)
- #define SPIS_PSEL_CSN_PIN_Pos (0UL)
- #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos)
- #define SPIS_RXD_PTR_PTR_Pos (0UL)
- #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos)
- #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL)
- #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos)
- #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL)
- #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos)
- #define SPIS_RXD_LIST_LIST_Pos (0UL)
- #define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos)
- #define SPIS_RXD_LIST_LIST_Disabled (0UL)
- #define SPIS_RXD_LIST_LIST_ArrayList (1UL)
- #define SPIS_TXD_PTR_PTR_Pos (0UL)
- #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos)
- #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL)
- #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos)
- #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL)
- #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos)
- #define SPIS_TXD_LIST_LIST_Pos (0UL)
- #define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos)
- #define SPIS_TXD_LIST_LIST_Disabled (0UL)
- #define SPIS_TXD_LIST_LIST_ArrayList (1UL)
- #define SPIS_CONFIG_CPOL_Pos (2UL)
- #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos)
- #define SPIS_CONFIG_CPOL_ActiveHigh (0UL)
- #define SPIS_CONFIG_CPOL_ActiveLow (1UL)
- #define SPIS_CONFIG_CPHA_Pos (1UL)
- #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos)
- #define SPIS_CONFIG_CPHA_Leading (0UL)
- #define SPIS_CONFIG_CPHA_Trailing (1UL)
- #define SPIS_CONFIG_ORDER_Pos (0UL)
- #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos)
- #define SPIS_CONFIG_ORDER_MsbFirst (0UL)
- #define SPIS_CONFIG_ORDER_LsbFirst (1UL)
- #define SPIS_DEF_DEF_Pos (0UL)
- #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos)
- #define SPIS_ORC_ORC_Pos (0UL)
- #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos)
- #define TEMP_TASKS_START_TASKS_START_Pos (0UL)
- #define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos)
- #define TEMP_TASKS_START_TASKS_START_Trigger (1UL)
- #define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos)
- #define TEMP_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define TEMP_SUBSCRIBE_START_EN_Pos (31UL)
- #define TEMP_SUBSCRIBE_START_EN_Msk (0x1UL << TEMP_SUBSCRIBE_START_EN_Pos)
- #define TEMP_SUBSCRIBE_START_EN_Disabled (0UL)
- #define TEMP_SUBSCRIBE_START_EN_Enabled (1UL)
- #define TEMP_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define TEMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TEMP_SUBSCRIBE_START_CHIDX_Pos)
- #define TEMP_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define TEMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << TEMP_SUBSCRIBE_STOP_EN_Pos)
- #define TEMP_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define TEMP_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define TEMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define TEMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TEMP_SUBSCRIBE_STOP_CHIDX_Pos)
- #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL)
- #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos)
- #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0UL)
- #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (1UL)
- #define TEMP_PUBLISH_DATARDY_EN_Pos (31UL)
- #define TEMP_PUBLISH_DATARDY_EN_Msk (0x1UL << TEMP_PUBLISH_DATARDY_EN_Pos)
- #define TEMP_PUBLISH_DATARDY_EN_Disabled (0UL)
- #define TEMP_PUBLISH_DATARDY_EN_Enabled (1UL)
- #define TEMP_PUBLISH_DATARDY_CHIDX_Pos (0UL)
- #define TEMP_PUBLISH_DATARDY_CHIDX_Msk (0xFFUL << TEMP_PUBLISH_DATARDY_CHIDX_Pos)
- #define TEMP_INTENSET_DATARDY_Pos (0UL)
- #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos)
- #define TEMP_INTENSET_DATARDY_Disabled (0UL)
- #define TEMP_INTENSET_DATARDY_Enabled (1UL)
- #define TEMP_INTENSET_DATARDY_Set (1UL)
- #define TEMP_INTENCLR_DATARDY_Pos (0UL)
- #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos)
- #define TEMP_INTENCLR_DATARDY_Disabled (0UL)
- #define TEMP_INTENCLR_DATARDY_Enabled (1UL)
- #define TEMP_INTENCLR_DATARDY_Clear (1UL)
- #define TEMP_TEMP_TEMP_Pos (0UL)
- #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos)
- #define TEMP_A0_A0_Pos (0UL)
- #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos)
- #define TEMP_A1_A1_Pos (0UL)
- #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos)
- #define TEMP_A2_A2_Pos (0UL)
- #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos)
- #define TEMP_A3_A3_Pos (0UL)
- #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos)
- #define TEMP_A4_A4_Pos (0UL)
- #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos)
- #define TEMP_A5_A5_Pos (0UL)
- #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos)
- #define TEMP_B0_B0_Pos (0UL)
- #define TEMP_B0_B0_Msk (0xFFFUL << TEMP_B0_B0_Pos)
- #define TEMP_B1_B1_Pos (0UL)
- #define TEMP_B1_B1_Msk (0xFFFUL << TEMP_B1_B1_Pos)
- #define TEMP_B2_B2_Pos (0UL)
- #define TEMP_B2_B2_Msk (0xFFFUL << TEMP_B2_B2_Pos)
- #define TEMP_B3_B3_Pos (0UL)
- #define TEMP_B3_B3_Msk (0xFFFUL << TEMP_B3_B3_Pos)
- #define TEMP_B4_B4_Pos (0UL)
- #define TEMP_B4_B4_Msk (0xFFFUL << TEMP_B4_B4_Pos)
- #define TEMP_B5_B5_Pos (0UL)
- #define TEMP_B5_B5_Msk (0xFFFUL << TEMP_B5_B5_Pos)
- #define TEMP_T0_T0_Pos (0UL)
- #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos)
- #define TEMP_T1_T1_Pos (0UL)
- #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos)
- #define TEMP_T2_T2_Pos (0UL)
- #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos)
- #define TEMP_T3_T3_Pos (0UL)
- #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos)
- #define TEMP_T4_T4_Pos (0UL)
- #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos)
- #define TIMER_TASKS_START_TASKS_START_Pos (0UL)
- #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos)
- #define TIMER_TASKS_START_TASKS_START_Trigger (1UL)
- #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos)
- #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL)
- #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos)
- #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL)
- #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL)
- #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos)
- #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL)
- #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL)
- #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos)
- #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL)
- #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL)
- #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos)
- #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL)
- #define TIMER_SUBSCRIBE_START_EN_Pos (31UL)
- #define TIMER_SUBSCRIBE_START_EN_Msk (0x1UL << TIMER_SUBSCRIBE_START_EN_Pos)
- #define TIMER_SUBSCRIBE_START_EN_Disabled (0UL)
- #define TIMER_SUBSCRIBE_START_EN_Enabled (1UL)
- #define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos)
- #define TIMER_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define TIMER_SUBSCRIBE_STOP_EN_Msk (0x1UL << TIMER_SUBSCRIBE_STOP_EN_Pos)
- #define TIMER_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define TIMER_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos)
- #define TIMER_SUBSCRIBE_COUNT_EN_Pos (31UL)
- #define TIMER_SUBSCRIBE_COUNT_EN_Msk (0x1UL << TIMER_SUBSCRIBE_COUNT_EN_Pos)
- #define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0UL)
- #define TIMER_SUBSCRIBE_COUNT_EN_Enabled (1UL)
- #define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL)
- #define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos)
- #define TIMER_SUBSCRIBE_CLEAR_EN_Pos (31UL)
- #define TIMER_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CLEAR_EN_Pos)
- #define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0UL)
- #define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (1UL)
- #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL)
- #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos)
- #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos (31UL)
- #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Msk (0x1UL << TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos)
- #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0UL)
- #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (1UL)
- #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos (0UL)
- #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos)
- #define TIMER_SUBSCRIBE_CAPTURE_EN_Pos (31UL)
- #define TIMER_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CAPTURE_EN_Pos)
- #define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0UL)
- #define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (1UL)
- #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL)
- #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos)
- #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL)
- #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos)
- #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL)
- #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL)
- #define TIMER_PUBLISH_COMPARE_EN_Pos (31UL)
- #define TIMER_PUBLISH_COMPARE_EN_Msk (0x1UL << TIMER_PUBLISH_COMPARE_EN_Pos)
- #define TIMER_PUBLISH_COMPARE_EN_Disabled (0UL)
- #define TIMER_PUBLISH_COMPARE_EN_Enabled (1UL)
- #define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL)
- #define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos)
- #define TIMER_SHORTS_COMPARE7_STOP_Pos (23UL)
- #define TIMER_SHORTS_COMPARE7_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE7_STOP_Pos)
- #define TIMER_SHORTS_COMPARE7_STOP_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE7_STOP_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE6_STOP_Pos (22UL)
- #define TIMER_SHORTS_COMPARE6_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE6_STOP_Pos)
- #define TIMER_SHORTS_COMPARE6_STOP_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE6_STOP_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE5_STOP_Pos (21UL)
- #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos)
- #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE4_STOP_Pos (20UL)
- #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos)
- #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE3_STOP_Pos (19UL)
- #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos)
- #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE2_STOP_Pos (18UL)
- #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos)
- #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE1_STOP_Pos (17UL)
- #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos)
- #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE0_STOP_Pos (16UL)
- #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos)
- #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE7_CLEAR_Pos (7UL)
- #define TIMER_SHORTS_COMPARE7_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE7_CLEAR_Pos)
- #define TIMER_SHORTS_COMPARE7_CLEAR_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE7_CLEAR_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE6_CLEAR_Pos (6UL)
- #define TIMER_SHORTS_COMPARE6_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE6_CLEAR_Pos)
- #define TIMER_SHORTS_COMPARE6_CLEAR_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE6_CLEAR_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL)
- #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos)
- #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL)
- #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos)
- #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL)
- #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos)
- #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL)
- #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos)
- #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL)
- #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos)
- #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL)
- #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos)
- #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL)
- #define TIMER_INTEN_COMPARE7_Pos (23UL)
- #define TIMER_INTEN_COMPARE7_Msk (0x1UL << TIMER_INTEN_COMPARE7_Pos)
- #define TIMER_INTEN_COMPARE7_Disabled (0UL)
- #define TIMER_INTEN_COMPARE7_Enabled (1UL)
- #define TIMER_INTEN_COMPARE6_Pos (22UL)
- #define TIMER_INTEN_COMPARE6_Msk (0x1UL << TIMER_INTEN_COMPARE6_Pos)
- #define TIMER_INTEN_COMPARE6_Disabled (0UL)
- #define TIMER_INTEN_COMPARE6_Enabled (1UL)
- #define TIMER_INTEN_COMPARE5_Pos (21UL)
- #define TIMER_INTEN_COMPARE5_Msk (0x1UL << TIMER_INTEN_COMPARE5_Pos)
- #define TIMER_INTEN_COMPARE5_Disabled (0UL)
- #define TIMER_INTEN_COMPARE5_Enabled (1UL)
- #define TIMER_INTEN_COMPARE4_Pos (20UL)
- #define TIMER_INTEN_COMPARE4_Msk (0x1UL << TIMER_INTEN_COMPARE4_Pos)
- #define TIMER_INTEN_COMPARE4_Disabled (0UL)
- #define TIMER_INTEN_COMPARE4_Enabled (1UL)
- #define TIMER_INTEN_COMPARE3_Pos (19UL)
- #define TIMER_INTEN_COMPARE3_Msk (0x1UL << TIMER_INTEN_COMPARE3_Pos)
- #define TIMER_INTEN_COMPARE3_Disabled (0UL)
- #define TIMER_INTEN_COMPARE3_Enabled (1UL)
- #define TIMER_INTEN_COMPARE2_Pos (18UL)
- #define TIMER_INTEN_COMPARE2_Msk (0x1UL << TIMER_INTEN_COMPARE2_Pos)
- #define TIMER_INTEN_COMPARE2_Disabled (0UL)
- #define TIMER_INTEN_COMPARE2_Enabled (1UL)
- #define TIMER_INTEN_COMPARE1_Pos (17UL)
- #define TIMER_INTEN_COMPARE1_Msk (0x1UL << TIMER_INTEN_COMPARE1_Pos)
- #define TIMER_INTEN_COMPARE1_Disabled (0UL)
- #define TIMER_INTEN_COMPARE1_Enabled (1UL)
- #define TIMER_INTEN_COMPARE0_Pos (16UL)
- #define TIMER_INTEN_COMPARE0_Msk (0x1UL << TIMER_INTEN_COMPARE0_Pos)
- #define TIMER_INTEN_COMPARE0_Disabled (0UL)
- #define TIMER_INTEN_COMPARE0_Enabled (1UL)
- #define TIMER_INTENSET_COMPARE7_Pos (23UL)
- #define TIMER_INTENSET_COMPARE7_Msk (0x1UL << TIMER_INTENSET_COMPARE7_Pos)
- #define TIMER_INTENSET_COMPARE7_Disabled (0UL)
- #define TIMER_INTENSET_COMPARE7_Enabled (1UL)
- #define TIMER_INTENSET_COMPARE7_Set (1UL)
- #define TIMER_INTENSET_COMPARE6_Pos (22UL)
- #define TIMER_INTENSET_COMPARE6_Msk (0x1UL << TIMER_INTENSET_COMPARE6_Pos)
- #define TIMER_INTENSET_COMPARE6_Disabled (0UL)
- #define TIMER_INTENSET_COMPARE6_Enabled (1UL)
- #define TIMER_INTENSET_COMPARE6_Set (1UL)
- #define TIMER_INTENSET_COMPARE5_Pos (21UL)
- #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos)
- #define TIMER_INTENSET_COMPARE5_Disabled (0UL)
- #define TIMER_INTENSET_COMPARE5_Enabled (1UL)
- #define TIMER_INTENSET_COMPARE5_Set (1UL)
- #define TIMER_INTENSET_COMPARE4_Pos (20UL)
- #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos)
- #define TIMER_INTENSET_COMPARE4_Disabled (0UL)
- #define TIMER_INTENSET_COMPARE4_Enabled (1UL)
- #define TIMER_INTENSET_COMPARE4_Set (1UL)
- #define TIMER_INTENSET_COMPARE3_Pos (19UL)
- #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos)
- #define TIMER_INTENSET_COMPARE3_Disabled (0UL)
- #define TIMER_INTENSET_COMPARE3_Enabled (1UL)
- #define TIMER_INTENSET_COMPARE3_Set (1UL)
- #define TIMER_INTENSET_COMPARE2_Pos (18UL)
- #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos)
- #define TIMER_INTENSET_COMPARE2_Disabled (0UL)
- #define TIMER_INTENSET_COMPARE2_Enabled (1UL)
- #define TIMER_INTENSET_COMPARE2_Set (1UL)
- #define TIMER_INTENSET_COMPARE1_Pos (17UL)
- #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos)
- #define TIMER_INTENSET_COMPARE1_Disabled (0UL)
- #define TIMER_INTENSET_COMPARE1_Enabled (1UL)
- #define TIMER_INTENSET_COMPARE1_Set (1UL)
- #define TIMER_INTENSET_COMPARE0_Pos (16UL)
- #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos)
- #define TIMER_INTENSET_COMPARE0_Disabled (0UL)
- #define TIMER_INTENSET_COMPARE0_Enabled (1UL)
- #define TIMER_INTENSET_COMPARE0_Set (1UL)
- #define TIMER_INTENCLR_COMPARE7_Pos (23UL)
- #define TIMER_INTENCLR_COMPARE7_Msk (0x1UL << TIMER_INTENCLR_COMPARE7_Pos)
- #define TIMER_INTENCLR_COMPARE7_Disabled (0UL)
- #define TIMER_INTENCLR_COMPARE7_Enabled (1UL)
- #define TIMER_INTENCLR_COMPARE7_Clear (1UL)
- #define TIMER_INTENCLR_COMPARE6_Pos (22UL)
- #define TIMER_INTENCLR_COMPARE6_Msk (0x1UL << TIMER_INTENCLR_COMPARE6_Pos)
- #define TIMER_INTENCLR_COMPARE6_Disabled (0UL)
- #define TIMER_INTENCLR_COMPARE6_Enabled (1UL)
- #define TIMER_INTENCLR_COMPARE6_Clear (1UL)
- #define TIMER_INTENCLR_COMPARE5_Pos (21UL)
- #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos)
- #define TIMER_INTENCLR_COMPARE5_Disabled (0UL)
- #define TIMER_INTENCLR_COMPARE5_Enabled (1UL)
- #define TIMER_INTENCLR_COMPARE5_Clear (1UL)
- #define TIMER_INTENCLR_COMPARE4_Pos (20UL)
- #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos)
- #define TIMER_INTENCLR_COMPARE4_Disabled (0UL)
- #define TIMER_INTENCLR_COMPARE4_Enabled (1UL)
- #define TIMER_INTENCLR_COMPARE4_Clear (1UL)
- #define TIMER_INTENCLR_COMPARE3_Pos (19UL)
- #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos)
- #define TIMER_INTENCLR_COMPARE3_Disabled (0UL)
- #define TIMER_INTENCLR_COMPARE3_Enabled (1UL)
- #define TIMER_INTENCLR_COMPARE3_Clear (1UL)
- #define TIMER_INTENCLR_COMPARE2_Pos (18UL)
- #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos)
- #define TIMER_INTENCLR_COMPARE2_Disabled (0UL)
- #define TIMER_INTENCLR_COMPARE2_Enabled (1UL)
- #define TIMER_INTENCLR_COMPARE2_Clear (1UL)
- #define TIMER_INTENCLR_COMPARE1_Pos (17UL)
- #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos)
- #define TIMER_INTENCLR_COMPARE1_Disabled (0UL)
- #define TIMER_INTENCLR_COMPARE1_Enabled (1UL)
- #define TIMER_INTENCLR_COMPARE1_Clear (1UL)
- #define TIMER_INTENCLR_COMPARE0_Pos (16UL)
- #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos)
- #define TIMER_INTENCLR_COMPARE0_Disabled (0UL)
- #define TIMER_INTENCLR_COMPARE0_Enabled (1UL)
- #define TIMER_INTENCLR_COMPARE0_Clear (1UL)
- #define TIMER_MODE_MODE_Pos (0UL)
- #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos)
- #define TIMER_MODE_MODE_Timer (0UL)
- #define TIMER_MODE_MODE_Counter (1UL)
- #define TIMER_MODE_MODE_LowPowerCounter (2UL)
- #define TIMER_BITMODE_BITMODE_Pos (0UL)
- #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos)
- #define TIMER_BITMODE_BITMODE_16Bit (0UL)
- #define TIMER_BITMODE_BITMODE_08Bit (1UL)
- #define TIMER_BITMODE_BITMODE_24Bit (2UL)
- #define TIMER_BITMODE_BITMODE_32Bit (3UL)
- #define TIMER_PRESCALER_PRESCALER_Pos (0UL)
- #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos)
- #define TIMER_CC_CC_Pos (0UL)
- #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos)
- #define TIMER_ONESHOTEN_ONESHOTEN_Pos (0UL)
- #define TIMER_ONESHOTEN_ONESHOTEN_Msk (0x1UL << TIMER_ONESHOTEN_ONESHOTEN_Pos)
- #define TIMER_ONESHOTEN_ONESHOTEN_Disable (0UL)
- #define TIMER_ONESHOTEN_ONESHOTEN_Enable (1UL)
- #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL)
- #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos)
- #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL)
- #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL)
- #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos)
- #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL)
- #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos)
- #define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL)
- #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos)
- #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL)
- #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL)
- #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos)
- #define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL)
- #define TWIM_SUBSCRIBE_STARTRX_EN_Pos (31UL)
- #define TWIM_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTRX_EN_Pos)
- #define TWIM_SUBSCRIBE_STARTRX_EN_Disabled (0UL)
- #define TWIM_SUBSCRIBE_STARTRX_EN_Enabled (1UL)
- #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL)
- #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos)
- #define TWIM_SUBSCRIBE_STARTTX_EN_Pos (31UL)
- #define TWIM_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTTX_EN_Pos)
- #define TWIM_SUBSCRIBE_STARTTX_EN_Disabled (0UL)
- #define TWIM_SUBSCRIBE_STARTTX_EN_Enabled (1UL)
- #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL)
- #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos)
- #define TWIM_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define TWIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STOP_EN_Pos)
- #define TWIM_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define TWIM_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define TWIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define TWIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STOP_CHIDX_Pos)
- #define TWIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL)
- #define TWIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIM_SUBSCRIBE_SUSPEND_EN_Pos)
- #define TWIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL)
- #define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL)
- #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL)
- #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos)
- #define TWIM_SUBSCRIBE_RESUME_EN_Pos (31UL)
- #define TWIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIM_SUBSCRIBE_RESUME_EN_Pos)
- #define TWIM_SUBSCRIBE_RESUME_EN_Disabled (0UL)
- #define TWIM_SUBSCRIBE_RESUME_EN_Enabled (1UL)
- #define TWIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL)
- #define TWIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_RESUME_CHIDX_Pos)
- #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL)
- #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos)
- #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL)
- #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL)
- #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)
- #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos)
- #define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL)
- #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL)
- #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL)
- #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos)
- #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL)
- #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL)
- #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL)
- #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos)
- #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL)
- #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL)
- #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL)
- #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos)
- #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL)
- #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL)
- #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL)
- #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos)
- #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL)
- #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL)
- #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL)
- #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos)
- #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL)
- #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL)
- #define TWIM_PUBLISH_STOPPED_EN_Pos (31UL)
- #define TWIM_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIM_PUBLISH_STOPPED_EN_Pos)
- #define TWIM_PUBLISH_STOPPED_EN_Disabled (0UL)
- #define TWIM_PUBLISH_STOPPED_EN_Enabled (1UL)
- #define TWIM_PUBLISH_STOPPED_CHIDX_Pos (0UL)
- #define TWIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_STOPPED_CHIDX_Pos)
- #define TWIM_PUBLISH_ERROR_EN_Pos (31UL)
- #define TWIM_PUBLISH_ERROR_EN_Msk (0x1UL << TWIM_PUBLISH_ERROR_EN_Pos)
- #define TWIM_PUBLISH_ERROR_EN_Disabled (0UL)
- #define TWIM_PUBLISH_ERROR_EN_Enabled (1UL)
- #define TWIM_PUBLISH_ERROR_CHIDX_Pos (0UL)
- #define TWIM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_ERROR_CHIDX_Pos)
- #define TWIM_PUBLISH_SUSPENDED_EN_Pos (31UL)
- #define TWIM_PUBLISH_SUSPENDED_EN_Msk (0x1UL << TWIM_PUBLISH_SUSPENDED_EN_Pos)
- #define TWIM_PUBLISH_SUSPENDED_EN_Disabled (0UL)
- #define TWIM_PUBLISH_SUSPENDED_EN_Enabled (1UL)
- #define TWIM_PUBLISH_SUSPENDED_CHIDX_Pos (0UL)
- #define TWIM_PUBLISH_SUSPENDED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_SUSPENDED_CHIDX_Pos)
- #define TWIM_PUBLISH_RXSTARTED_EN_Pos (31UL)
- #define TWIM_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_RXSTARTED_EN_Pos)
- #define TWIM_PUBLISH_RXSTARTED_EN_Disabled (0UL)
- #define TWIM_PUBLISH_RXSTARTED_EN_Enabled (1UL)
- #define TWIM_PUBLISH_RXSTARTED_CHIDX_Pos (0UL)
- #define TWIM_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_RXSTARTED_CHIDX_Pos)
- #define TWIM_PUBLISH_TXSTARTED_EN_Pos (31UL)
- #define TWIM_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_TXSTARTED_EN_Pos)
- #define TWIM_PUBLISH_TXSTARTED_EN_Disabled (0UL)
- #define TWIM_PUBLISH_TXSTARTED_EN_Enabled (1UL)
- #define TWIM_PUBLISH_TXSTARTED_CHIDX_Pos (0UL)
- #define TWIM_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_TXSTARTED_CHIDX_Pos)
- #define TWIM_PUBLISH_LASTRX_EN_Pos (31UL)
- #define TWIM_PUBLISH_LASTRX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTRX_EN_Pos)
- #define TWIM_PUBLISH_LASTRX_EN_Disabled (0UL)
- #define TWIM_PUBLISH_LASTRX_EN_Enabled (1UL)
- #define TWIM_PUBLISH_LASTRX_CHIDX_Pos (0UL)
- #define TWIM_PUBLISH_LASTRX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTRX_CHIDX_Pos)
- #define TWIM_PUBLISH_LASTTX_EN_Pos (31UL)
- #define TWIM_PUBLISH_LASTTX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTTX_EN_Pos)
- #define TWIM_PUBLISH_LASTTX_EN_Disabled (0UL)
- #define TWIM_PUBLISH_LASTTX_EN_Enabled (1UL)
- #define TWIM_PUBLISH_LASTTX_CHIDX_Pos (0UL)
- #define TWIM_PUBLISH_LASTTX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTTX_CHIDX_Pos)
- #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL)
- #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos)
- #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL)
- #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL)
- #define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL)
- #define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos)
- #define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL)
- #define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL)
- #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL)
- #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos)
- #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL)
- #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL)
- #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL)
- #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos)
- #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL)
- #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL)
- #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL)
- #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos)
- #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL)
- #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL)
- #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL)
- #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos)
- #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL)
- #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL)
- #define TWIM_INTEN_LASTTX_Pos (24UL)
- #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos)
- #define TWIM_INTEN_LASTTX_Disabled (0UL)
- #define TWIM_INTEN_LASTTX_Enabled (1UL)
- #define TWIM_INTEN_LASTRX_Pos (23UL)
- #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos)
- #define TWIM_INTEN_LASTRX_Disabled (0UL)
- #define TWIM_INTEN_LASTRX_Enabled (1UL)
- #define TWIM_INTEN_TXSTARTED_Pos (20UL)
- #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos)
- #define TWIM_INTEN_TXSTARTED_Disabled (0UL)
- #define TWIM_INTEN_TXSTARTED_Enabled (1UL)
- #define TWIM_INTEN_RXSTARTED_Pos (19UL)
- #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos)
- #define TWIM_INTEN_RXSTARTED_Disabled (0UL)
- #define TWIM_INTEN_RXSTARTED_Enabled (1UL)
- #define TWIM_INTEN_SUSPENDED_Pos (18UL)
- #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos)
- #define TWIM_INTEN_SUSPENDED_Disabled (0UL)
- #define TWIM_INTEN_SUSPENDED_Enabled (1UL)
- #define TWIM_INTEN_ERROR_Pos (9UL)
- #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos)
- #define TWIM_INTEN_ERROR_Disabled (0UL)
- #define TWIM_INTEN_ERROR_Enabled (1UL)
- #define TWIM_INTEN_STOPPED_Pos (1UL)
- #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos)
- #define TWIM_INTEN_STOPPED_Disabled (0UL)
- #define TWIM_INTEN_STOPPED_Enabled (1UL)
- #define TWIM_INTENSET_LASTTX_Pos (24UL)
- #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos)
- #define TWIM_INTENSET_LASTTX_Disabled (0UL)
- #define TWIM_INTENSET_LASTTX_Enabled (1UL)
- #define TWIM_INTENSET_LASTTX_Set (1UL)
- #define TWIM_INTENSET_LASTRX_Pos (23UL)
- #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos)
- #define TWIM_INTENSET_LASTRX_Disabled (0UL)
- #define TWIM_INTENSET_LASTRX_Enabled (1UL)
- #define TWIM_INTENSET_LASTRX_Set (1UL)
- #define TWIM_INTENSET_TXSTARTED_Pos (20UL)
- #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos)
- #define TWIM_INTENSET_TXSTARTED_Disabled (0UL)
- #define TWIM_INTENSET_TXSTARTED_Enabled (1UL)
- #define TWIM_INTENSET_TXSTARTED_Set (1UL)
- #define TWIM_INTENSET_RXSTARTED_Pos (19UL)
- #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos)
- #define TWIM_INTENSET_RXSTARTED_Disabled (0UL)
- #define TWIM_INTENSET_RXSTARTED_Enabled (1UL)
- #define TWIM_INTENSET_RXSTARTED_Set (1UL)
- #define TWIM_INTENSET_SUSPENDED_Pos (18UL)
- #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos)
- #define TWIM_INTENSET_SUSPENDED_Disabled (0UL)
- #define TWIM_INTENSET_SUSPENDED_Enabled (1UL)
- #define TWIM_INTENSET_SUSPENDED_Set (1UL)
- #define TWIM_INTENSET_ERROR_Pos (9UL)
- #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos)
- #define TWIM_INTENSET_ERROR_Disabled (0UL)
- #define TWIM_INTENSET_ERROR_Enabled (1UL)
- #define TWIM_INTENSET_ERROR_Set (1UL)
- #define TWIM_INTENSET_STOPPED_Pos (1UL)
- #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos)
- #define TWIM_INTENSET_STOPPED_Disabled (0UL)
- #define TWIM_INTENSET_STOPPED_Enabled (1UL)
- #define TWIM_INTENSET_STOPPED_Set (1UL)
- #define TWIM_INTENCLR_LASTTX_Pos (24UL)
- #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos)
- #define TWIM_INTENCLR_LASTTX_Disabled (0UL)
- #define TWIM_INTENCLR_LASTTX_Enabled (1UL)
- #define TWIM_INTENCLR_LASTTX_Clear (1UL)
- #define TWIM_INTENCLR_LASTRX_Pos (23UL)
- #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos)
- #define TWIM_INTENCLR_LASTRX_Disabled (0UL)
- #define TWIM_INTENCLR_LASTRX_Enabled (1UL)
- #define TWIM_INTENCLR_LASTRX_Clear (1UL)
- #define TWIM_INTENCLR_TXSTARTED_Pos (20UL)
- #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos)
- #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL)
- #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL)
- #define TWIM_INTENCLR_TXSTARTED_Clear (1UL)
- #define TWIM_INTENCLR_RXSTARTED_Pos (19UL)
- #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos)
- #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL)
- #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL)
- #define TWIM_INTENCLR_RXSTARTED_Clear (1UL)
- #define TWIM_INTENCLR_SUSPENDED_Pos (18UL)
- #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos)
- #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL)
- #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL)
- #define TWIM_INTENCLR_SUSPENDED_Clear (1UL)
- #define TWIM_INTENCLR_ERROR_Pos (9UL)
- #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos)
- #define TWIM_INTENCLR_ERROR_Disabled (0UL)
- #define TWIM_INTENCLR_ERROR_Enabled (1UL)
- #define TWIM_INTENCLR_ERROR_Clear (1UL)
- #define TWIM_INTENCLR_STOPPED_Pos (1UL)
- #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos)
- #define TWIM_INTENCLR_STOPPED_Disabled (0UL)
- #define TWIM_INTENCLR_STOPPED_Enabled (1UL)
- #define TWIM_INTENCLR_STOPPED_Clear (1UL)
- #define TWIM_ERRORSRC_DNACK_Pos (2UL)
- #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos)
- #define TWIM_ERRORSRC_DNACK_NotReceived (0UL)
- #define TWIM_ERRORSRC_DNACK_Received (1UL)
- #define TWIM_ERRORSRC_ANACK_Pos (1UL)
- #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos)
- #define TWIM_ERRORSRC_ANACK_NotReceived (0UL)
- #define TWIM_ERRORSRC_ANACK_Received (1UL)
- #define TWIM_ERRORSRC_OVERRUN_Pos (0UL)
- #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos)
- #define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL)
- #define TWIM_ERRORSRC_OVERRUN_Received (1UL)
- #define TWIM_ENABLE_ENABLE_Pos (0UL)
- #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos)
- #define TWIM_ENABLE_ENABLE_Disabled (0UL)
- #define TWIM_ENABLE_ENABLE_Enabled (6UL)
- #define TWIM_PSEL_SCL_CONNECT_Pos (31UL)
- #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos)
- #define TWIM_PSEL_SCL_CONNECT_Connected (0UL)
- #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL)
- #define TWIM_PSEL_SCL_PORT_Pos (5UL)
- #define TWIM_PSEL_SCL_PORT_Msk (0x1UL << TWIM_PSEL_SCL_PORT_Pos)
- #define TWIM_PSEL_SCL_PIN_Pos (0UL)
- #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos)
- #define TWIM_PSEL_SDA_CONNECT_Pos (31UL)
- #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos)
- #define TWIM_PSEL_SDA_CONNECT_Connected (0UL)
- #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL)
- #define TWIM_PSEL_SDA_PORT_Pos (5UL)
- #define TWIM_PSEL_SDA_PORT_Msk (0x1UL << TWIM_PSEL_SDA_PORT_Pos)
- #define TWIM_PSEL_SDA_PIN_Pos (0UL)
- #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos)
- #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL)
- #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos)
- #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL)
- #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL)
- #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL)
- #define TWIM_FREQUENCY_FREQUENCY_K1000 (0x0FF00000UL)
- #define TWIM_RXD_PTR_PTR_Pos (0UL)
- #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos)
- #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL)
- #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos)
- #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL)
- #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos)
- #define TWIM_RXD_LIST_LIST_Pos (0UL)
- #define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos)
- #define TWIM_RXD_LIST_LIST_Disabled (0UL)
- #define TWIM_RXD_LIST_LIST_ArrayList (1UL)
- #define TWIM_TXD_PTR_PTR_Pos (0UL)
- #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos)
- #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL)
- #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos)
- #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL)
- #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos)
- #define TWIM_TXD_LIST_LIST_Pos (0UL)
- #define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos)
- #define TWIM_TXD_LIST_LIST_Disabled (0UL)
- #define TWIM_TXD_LIST_LIST_ArrayList (1UL)
- #define TWIM_ADDRESS_ADDRESS_Pos (0UL)
- #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos)
- #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos)
- #define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL)
- #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos)
- #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL)
- #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL)
- #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos)
- #define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL)
- #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL)
- #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos)
- #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL)
- #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL)
- #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos)
- #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL)
- #define TWIS_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define TWIS_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIS_SUBSCRIBE_STOP_EN_Pos)
- #define TWIS_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define TWIS_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define TWIS_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define TWIS_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_STOP_CHIDX_Pos)
- #define TWIS_SUBSCRIBE_SUSPEND_EN_Pos (31UL)
- #define TWIS_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIS_SUBSCRIBE_SUSPEND_EN_Pos)
- #define TWIS_SUBSCRIBE_SUSPEND_EN_Disabled (0UL)
- #define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (1UL)
- #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL)
- #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos)
- #define TWIS_SUBSCRIBE_RESUME_EN_Pos (31UL)
- #define TWIS_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIS_SUBSCRIBE_RESUME_EN_Pos)
- #define TWIS_SUBSCRIBE_RESUME_EN_Disabled (0UL)
- #define TWIS_SUBSCRIBE_RESUME_EN_Enabled (1UL)
- #define TWIS_SUBSCRIBE_RESUME_CHIDX_Pos (0UL)
- #define TWIS_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_RESUME_CHIDX_Pos)
- #define TWIS_SUBSCRIBE_PREPARERX_EN_Pos (31UL)
- #define TWIS_SUBSCRIBE_PREPARERX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARERX_EN_Pos)
- #define TWIS_SUBSCRIBE_PREPARERX_EN_Disabled (0UL)
- #define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (1UL)
- #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos (0UL)
- #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos)
- #define TWIS_SUBSCRIBE_PREPARETX_EN_Pos (31UL)
- #define TWIS_SUBSCRIBE_PREPARETX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARETX_EN_Pos)
- #define TWIS_SUBSCRIBE_PREPARETX_EN_Disabled (0UL)
- #define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (1UL)
- #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos (0UL)
- #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos)
- #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL)
- #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos)
- #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL)
- #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL)
- #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)
- #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos)
- #define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL)
- #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL)
- #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL)
- #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos)
- #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL)
- #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL)
- #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL)
- #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos)
- #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL)
- #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL)
- #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL)
- #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos)
- #define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL)
- #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL)
- #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL)
- #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos)
- #define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL)
- #define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL)
- #define TWIS_PUBLISH_STOPPED_EN_Pos (31UL)
- #define TWIS_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIS_PUBLISH_STOPPED_EN_Pos)
- #define TWIS_PUBLISH_STOPPED_EN_Disabled (0UL)
- #define TWIS_PUBLISH_STOPPED_EN_Enabled (1UL)
- #define TWIS_PUBLISH_STOPPED_CHIDX_Pos (0UL)
- #define TWIS_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_STOPPED_CHIDX_Pos)
- #define TWIS_PUBLISH_ERROR_EN_Pos (31UL)
- #define TWIS_PUBLISH_ERROR_EN_Msk (0x1UL << TWIS_PUBLISH_ERROR_EN_Pos)
- #define TWIS_PUBLISH_ERROR_EN_Disabled (0UL)
- #define TWIS_PUBLISH_ERROR_EN_Enabled (1UL)
- #define TWIS_PUBLISH_ERROR_CHIDX_Pos (0UL)
- #define TWIS_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_ERROR_CHIDX_Pos)
- #define TWIS_PUBLISH_RXSTARTED_EN_Pos (31UL)
- #define TWIS_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_RXSTARTED_EN_Pos)
- #define TWIS_PUBLISH_RXSTARTED_EN_Disabled (0UL)
- #define TWIS_PUBLISH_RXSTARTED_EN_Enabled (1UL)
- #define TWIS_PUBLISH_RXSTARTED_CHIDX_Pos (0UL)
- #define TWIS_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_RXSTARTED_CHIDX_Pos)
- #define TWIS_PUBLISH_TXSTARTED_EN_Pos (31UL)
- #define TWIS_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_TXSTARTED_EN_Pos)
- #define TWIS_PUBLISH_TXSTARTED_EN_Disabled (0UL)
- #define TWIS_PUBLISH_TXSTARTED_EN_Enabled (1UL)
- #define TWIS_PUBLISH_TXSTARTED_CHIDX_Pos (0UL)
- #define TWIS_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_TXSTARTED_CHIDX_Pos)
- #define TWIS_PUBLISH_WRITE_EN_Pos (31UL)
- #define TWIS_PUBLISH_WRITE_EN_Msk (0x1UL << TWIS_PUBLISH_WRITE_EN_Pos)
- #define TWIS_PUBLISH_WRITE_EN_Disabled (0UL)
- #define TWIS_PUBLISH_WRITE_EN_Enabled (1UL)
- #define TWIS_PUBLISH_WRITE_CHIDX_Pos (0UL)
- #define TWIS_PUBLISH_WRITE_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_WRITE_CHIDX_Pos)
- #define TWIS_PUBLISH_READ_EN_Pos (31UL)
- #define TWIS_PUBLISH_READ_EN_Msk (0x1UL << TWIS_PUBLISH_READ_EN_Pos)
- #define TWIS_PUBLISH_READ_EN_Disabled (0UL)
- #define TWIS_PUBLISH_READ_EN_Enabled (1UL)
- #define TWIS_PUBLISH_READ_CHIDX_Pos (0UL)
- #define TWIS_PUBLISH_READ_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_READ_CHIDX_Pos)
- #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL)
- #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos)
- #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL)
- #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL)
- #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL)
- #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos)
- #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL)
- #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL)
- #define TWIS_INTEN_READ_Pos (26UL)
- #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos)
- #define TWIS_INTEN_READ_Disabled (0UL)
- #define TWIS_INTEN_READ_Enabled (1UL)
- #define TWIS_INTEN_WRITE_Pos (25UL)
- #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos)
- #define TWIS_INTEN_WRITE_Disabled (0UL)
- #define TWIS_INTEN_WRITE_Enabled (1UL)
- #define TWIS_INTEN_TXSTARTED_Pos (20UL)
- #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos)
- #define TWIS_INTEN_TXSTARTED_Disabled (0UL)
- #define TWIS_INTEN_TXSTARTED_Enabled (1UL)
- #define TWIS_INTEN_RXSTARTED_Pos (19UL)
- #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos)
- #define TWIS_INTEN_RXSTARTED_Disabled (0UL)
- #define TWIS_INTEN_RXSTARTED_Enabled (1UL)
- #define TWIS_INTEN_ERROR_Pos (9UL)
- #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos)
- #define TWIS_INTEN_ERROR_Disabled (0UL)
- #define TWIS_INTEN_ERROR_Enabled (1UL)
- #define TWIS_INTEN_STOPPED_Pos (1UL)
- #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos)
- #define TWIS_INTEN_STOPPED_Disabled (0UL)
- #define TWIS_INTEN_STOPPED_Enabled (1UL)
- #define TWIS_INTENSET_READ_Pos (26UL)
- #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos)
- #define TWIS_INTENSET_READ_Disabled (0UL)
- #define TWIS_INTENSET_READ_Enabled (1UL)
- #define TWIS_INTENSET_READ_Set (1UL)
- #define TWIS_INTENSET_WRITE_Pos (25UL)
- #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos)
- #define TWIS_INTENSET_WRITE_Disabled (0UL)
- #define TWIS_INTENSET_WRITE_Enabled (1UL)
- #define TWIS_INTENSET_WRITE_Set (1UL)
- #define TWIS_INTENSET_TXSTARTED_Pos (20UL)
- #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos)
- #define TWIS_INTENSET_TXSTARTED_Disabled (0UL)
- #define TWIS_INTENSET_TXSTARTED_Enabled (1UL)
- #define TWIS_INTENSET_TXSTARTED_Set (1UL)
- #define TWIS_INTENSET_RXSTARTED_Pos (19UL)
- #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos)
- #define TWIS_INTENSET_RXSTARTED_Disabled (0UL)
- #define TWIS_INTENSET_RXSTARTED_Enabled (1UL)
- #define TWIS_INTENSET_RXSTARTED_Set (1UL)
- #define TWIS_INTENSET_ERROR_Pos (9UL)
- #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos)
- #define TWIS_INTENSET_ERROR_Disabled (0UL)
- #define TWIS_INTENSET_ERROR_Enabled (1UL)
- #define TWIS_INTENSET_ERROR_Set (1UL)
- #define TWIS_INTENSET_STOPPED_Pos (1UL)
- #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos)
- #define TWIS_INTENSET_STOPPED_Disabled (0UL)
- #define TWIS_INTENSET_STOPPED_Enabled (1UL)
- #define TWIS_INTENSET_STOPPED_Set (1UL)
- #define TWIS_INTENCLR_READ_Pos (26UL)
- #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos)
- #define TWIS_INTENCLR_READ_Disabled (0UL)
- #define TWIS_INTENCLR_READ_Enabled (1UL)
- #define TWIS_INTENCLR_READ_Clear (1UL)
- #define TWIS_INTENCLR_WRITE_Pos (25UL)
- #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos)
- #define TWIS_INTENCLR_WRITE_Disabled (0UL)
- #define TWIS_INTENCLR_WRITE_Enabled (1UL)
- #define TWIS_INTENCLR_WRITE_Clear (1UL)
- #define TWIS_INTENCLR_TXSTARTED_Pos (20UL)
- #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos)
- #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL)
- #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL)
- #define TWIS_INTENCLR_TXSTARTED_Clear (1UL)
- #define TWIS_INTENCLR_RXSTARTED_Pos (19UL)
- #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos)
- #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL)
- #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL)
- #define TWIS_INTENCLR_RXSTARTED_Clear (1UL)
- #define TWIS_INTENCLR_ERROR_Pos (9UL)
- #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos)
- #define TWIS_INTENCLR_ERROR_Disabled (0UL)
- #define TWIS_INTENCLR_ERROR_Enabled (1UL)
- #define TWIS_INTENCLR_ERROR_Clear (1UL)
- #define TWIS_INTENCLR_STOPPED_Pos (1UL)
- #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos)
- #define TWIS_INTENCLR_STOPPED_Disabled (0UL)
- #define TWIS_INTENCLR_STOPPED_Enabled (1UL)
- #define TWIS_INTENCLR_STOPPED_Clear (1UL)
- #define TWIS_ERRORSRC_OVERREAD_Pos (3UL)
- #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos)
- #define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL)
- #define TWIS_ERRORSRC_OVERREAD_Detected (1UL)
- #define TWIS_ERRORSRC_DNACK_Pos (2UL)
- #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos)
- #define TWIS_ERRORSRC_DNACK_NotReceived (0UL)
- #define TWIS_ERRORSRC_DNACK_Received (1UL)
- #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL)
- #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos)
- #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL)
- #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL)
- #define TWIS_MATCH_MATCH_Pos (0UL)
- #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos)
- #define TWIS_ENABLE_ENABLE_Pos (0UL)
- #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos)
- #define TWIS_ENABLE_ENABLE_Disabled (0UL)
- #define TWIS_ENABLE_ENABLE_Enabled (9UL)
- #define TWIS_PSEL_SCL_CONNECT_Pos (31UL)
- #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos)
- #define TWIS_PSEL_SCL_CONNECT_Connected (0UL)
- #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL)
- #define TWIS_PSEL_SCL_PORT_Pos (5UL)
- #define TWIS_PSEL_SCL_PORT_Msk (0x1UL << TWIS_PSEL_SCL_PORT_Pos)
- #define TWIS_PSEL_SCL_PIN_Pos (0UL)
- #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos)
- #define TWIS_PSEL_SDA_CONNECT_Pos (31UL)
- #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos)
- #define TWIS_PSEL_SDA_CONNECT_Connected (0UL)
- #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL)
- #define TWIS_PSEL_SDA_PORT_Pos (5UL)
- #define TWIS_PSEL_SDA_PORT_Msk (0x1UL << TWIS_PSEL_SDA_PORT_Pos)
- #define TWIS_PSEL_SDA_PIN_Pos (0UL)
- #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos)
- #define TWIS_RXD_PTR_PTR_Pos (0UL)
- #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos)
- #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL)
- #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos)
- #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL)
- #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos)
- #define TWIS_RXD_LIST_LIST_Pos (0UL)
- #define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos)
- #define TWIS_RXD_LIST_LIST_Disabled (0UL)
- #define TWIS_RXD_LIST_LIST_ArrayList (1UL)
- #define TWIS_TXD_PTR_PTR_Pos (0UL)
- #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos)
- #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL)
- #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos)
- #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL)
- #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos)
- #define TWIS_TXD_LIST_LIST_Pos (0UL)
- #define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos)
- #define TWIS_TXD_LIST_LIST_Disabled (0UL)
- #define TWIS_TXD_LIST_LIST_ArrayList (1UL)
- #define TWIS_ADDRESS_ADDRESS_Pos (0UL)
- #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos)
- #define TWIS_CONFIG_ADDRESS1_Pos (1UL)
- #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos)
- #define TWIS_CONFIG_ADDRESS1_Disabled (0UL)
- #define TWIS_CONFIG_ADDRESS1_Enabled (1UL)
- #define TWIS_CONFIG_ADDRESS0_Pos (0UL)
- #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos)
- #define TWIS_CONFIG_ADDRESS0_Disabled (0UL)
- #define TWIS_CONFIG_ADDRESS0_Enabled (1UL)
- #define TWIS_ORC_ORC_Pos (0UL)
- #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos)
- #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL)
- #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos)
- #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL)
- #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL)
- #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos)
- #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL)
- #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL)
- #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos)
- #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL)
- #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL)
- #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos)
- #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL)
- #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL)
- #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos)
- #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL)
- #define UARTE_SUBSCRIBE_STARTRX_EN_Pos (31UL)
- #define UARTE_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTRX_EN_Pos)
- #define UARTE_SUBSCRIBE_STARTRX_EN_Disabled (0UL)
- #define UARTE_SUBSCRIBE_STARTRX_EN_Enabled (1UL)
- #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL)
- #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos)
- #define UARTE_SUBSCRIBE_STOPRX_EN_Pos (31UL)
- #define UARTE_SUBSCRIBE_STOPRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPRX_EN_Pos)
- #define UARTE_SUBSCRIBE_STOPRX_EN_Disabled (0UL)
- #define UARTE_SUBSCRIBE_STOPRX_EN_Enabled (1UL)
- #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos (0UL)
- #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos)
- #define UARTE_SUBSCRIBE_STARTTX_EN_Pos (31UL)
- #define UARTE_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTTX_EN_Pos)
- #define UARTE_SUBSCRIBE_STARTTX_EN_Disabled (0UL)
- #define UARTE_SUBSCRIBE_STARTTX_EN_Enabled (1UL)
- #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL)
- #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos)
- #define UARTE_SUBSCRIBE_STOPTX_EN_Pos (31UL)
- #define UARTE_SUBSCRIBE_STOPTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPTX_EN_Pos)
- #define UARTE_SUBSCRIBE_STOPTX_EN_Disabled (0UL)
- #define UARTE_SUBSCRIBE_STOPTX_EN_Enabled (1UL)
- #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos (0UL)
- #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos)
- #define UARTE_SUBSCRIBE_FLUSHRX_EN_Pos (31UL)
- #define UARTE_SUBSCRIBE_FLUSHRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_FLUSHRX_EN_Pos)
- #define UARTE_SUBSCRIBE_FLUSHRX_EN_Disabled (0UL)
- #define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (1UL)
- #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos (0UL)
- #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos)
- #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL)
- #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos)
- #define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL)
- #define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL)
- #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL)
- #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos)
- #define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL)
- #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL)
- #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL)
- #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos)
- #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL)
- #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL)
- #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL)
- #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos)
- #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL)
- #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL)
- #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL)
- #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos)
- #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL)
- #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL)
- #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL)
- #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos)
- #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL)
- #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL)
- #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)
- #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos)
- #define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL)
- #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL)
- #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL)
- #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos)
- #define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL)
- #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL)
- #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL)
- #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos)
- #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL)
- #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL)
- #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL)
- #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos)
- #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL)
- #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL)
- #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL)
- #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos)
- #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL)
- #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL)
- #define UARTE_PUBLISH_CTS_EN_Pos (31UL)
- #define UARTE_PUBLISH_CTS_EN_Msk (0x1UL << UARTE_PUBLISH_CTS_EN_Pos)
- #define UARTE_PUBLISH_CTS_EN_Disabled (0UL)
- #define UARTE_PUBLISH_CTS_EN_Enabled (1UL)
- #define UARTE_PUBLISH_CTS_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_CTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_CTS_CHIDX_Pos)
- #define UARTE_PUBLISH_NCTS_EN_Pos (31UL)
- #define UARTE_PUBLISH_NCTS_EN_Msk (0x1UL << UARTE_PUBLISH_NCTS_EN_Pos)
- #define UARTE_PUBLISH_NCTS_EN_Disabled (0UL)
- #define UARTE_PUBLISH_NCTS_EN_Enabled (1UL)
- #define UARTE_PUBLISH_NCTS_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_NCTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_NCTS_CHIDX_Pos)
- #define UARTE_PUBLISH_RXDRDY_EN_Pos (31UL)
- #define UARTE_PUBLISH_RXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_RXDRDY_EN_Pos)
- #define UARTE_PUBLISH_RXDRDY_EN_Disabled (0UL)
- #define UARTE_PUBLISH_RXDRDY_EN_Enabled (1UL)
- #define UARTE_PUBLISH_RXDRDY_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_RXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXDRDY_CHIDX_Pos)
- #define UARTE_PUBLISH_ENDRX_EN_Pos (31UL)
- #define UARTE_PUBLISH_ENDRX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDRX_EN_Pos)
- #define UARTE_PUBLISH_ENDRX_EN_Disabled (0UL)
- #define UARTE_PUBLISH_ENDRX_EN_Enabled (1UL)
- #define UARTE_PUBLISH_ENDRX_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDRX_CHIDX_Pos)
- #define UARTE_PUBLISH_TXDRDY_EN_Pos (31UL)
- #define UARTE_PUBLISH_TXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_TXDRDY_EN_Pos)
- #define UARTE_PUBLISH_TXDRDY_EN_Disabled (0UL)
- #define UARTE_PUBLISH_TXDRDY_EN_Enabled (1UL)
- #define UARTE_PUBLISH_TXDRDY_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_TXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXDRDY_CHIDX_Pos)
- #define UARTE_PUBLISH_ENDTX_EN_Pos (31UL)
- #define UARTE_PUBLISH_ENDTX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDTX_EN_Pos)
- #define UARTE_PUBLISH_ENDTX_EN_Disabled (0UL)
- #define UARTE_PUBLISH_ENDTX_EN_Enabled (1UL)
- #define UARTE_PUBLISH_ENDTX_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDTX_CHIDX_Pos)
- #define UARTE_PUBLISH_ERROR_EN_Pos (31UL)
- #define UARTE_PUBLISH_ERROR_EN_Msk (0x1UL << UARTE_PUBLISH_ERROR_EN_Pos)
- #define UARTE_PUBLISH_ERROR_EN_Disabled (0UL)
- #define UARTE_PUBLISH_ERROR_EN_Enabled (1UL)
- #define UARTE_PUBLISH_ERROR_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ERROR_CHIDX_Pos)
- #define UARTE_PUBLISH_RXTO_EN_Pos (31UL)
- #define UARTE_PUBLISH_RXTO_EN_Msk (0x1UL << UARTE_PUBLISH_RXTO_EN_Pos)
- #define UARTE_PUBLISH_RXTO_EN_Disabled (0UL)
- #define UARTE_PUBLISH_RXTO_EN_Enabled (1UL)
- #define UARTE_PUBLISH_RXTO_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_RXTO_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXTO_CHIDX_Pos)
- #define UARTE_PUBLISH_RXSTARTED_EN_Pos (31UL)
- #define UARTE_PUBLISH_RXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_RXSTARTED_EN_Pos)
- #define UARTE_PUBLISH_RXSTARTED_EN_Disabled (0UL)
- #define UARTE_PUBLISH_RXSTARTED_EN_Enabled (1UL)
- #define UARTE_PUBLISH_RXSTARTED_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXSTARTED_CHIDX_Pos)
- #define UARTE_PUBLISH_TXSTARTED_EN_Pos (31UL)
- #define UARTE_PUBLISH_TXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTARTED_EN_Pos)
- #define UARTE_PUBLISH_TXSTARTED_EN_Disabled (0UL)
- #define UARTE_PUBLISH_TXSTARTED_EN_Enabled (1UL)
- #define UARTE_PUBLISH_TXSTARTED_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTARTED_CHIDX_Pos)
- #define UARTE_PUBLISH_TXSTOPPED_EN_Pos (31UL)
- #define UARTE_PUBLISH_TXSTOPPED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTOPPED_EN_Pos)
- #define UARTE_PUBLISH_TXSTOPPED_EN_Disabled (0UL)
- #define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (1UL)
- #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos)
- #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL)
- #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos)
- #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL)
- #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL)
- #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL)
- #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos)
- #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL)
- #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL)
- #define UARTE_INTEN_TXSTOPPED_Pos (22UL)
- #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos)
- #define UARTE_INTEN_TXSTOPPED_Disabled (0UL)
- #define UARTE_INTEN_TXSTOPPED_Enabled (1UL)
- #define UARTE_INTEN_TXSTARTED_Pos (20UL)
- #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos)
- #define UARTE_INTEN_TXSTARTED_Disabled (0UL)
- #define UARTE_INTEN_TXSTARTED_Enabled (1UL)
- #define UARTE_INTEN_RXSTARTED_Pos (19UL)
- #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos)
- #define UARTE_INTEN_RXSTARTED_Disabled (0UL)
- #define UARTE_INTEN_RXSTARTED_Enabled (1UL)
- #define UARTE_INTEN_RXTO_Pos (17UL)
- #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos)
- #define UARTE_INTEN_RXTO_Disabled (0UL)
- #define UARTE_INTEN_RXTO_Enabled (1UL)
- #define UARTE_INTEN_ERROR_Pos (9UL)
- #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos)
- #define UARTE_INTEN_ERROR_Disabled (0UL)
- #define UARTE_INTEN_ERROR_Enabled (1UL)
- #define UARTE_INTEN_ENDTX_Pos (8UL)
- #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos)
- #define UARTE_INTEN_ENDTX_Disabled (0UL)
- #define UARTE_INTEN_ENDTX_Enabled (1UL)
- #define UARTE_INTEN_TXDRDY_Pos (7UL)
- #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos)
- #define UARTE_INTEN_TXDRDY_Disabled (0UL)
- #define UARTE_INTEN_TXDRDY_Enabled (1UL)
- #define UARTE_INTEN_ENDRX_Pos (4UL)
- #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos)
- #define UARTE_INTEN_ENDRX_Disabled (0UL)
- #define UARTE_INTEN_ENDRX_Enabled (1UL)
- #define UARTE_INTEN_RXDRDY_Pos (2UL)
- #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos)
- #define UARTE_INTEN_RXDRDY_Disabled (0UL)
- #define UARTE_INTEN_RXDRDY_Enabled (1UL)
- #define UARTE_INTEN_NCTS_Pos (1UL)
- #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos)
- #define UARTE_INTEN_NCTS_Disabled (0UL)
- #define UARTE_INTEN_NCTS_Enabled (1UL)
- #define UARTE_INTEN_CTS_Pos (0UL)
- #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos)
- #define UARTE_INTEN_CTS_Disabled (0UL)
- #define UARTE_INTEN_CTS_Enabled (1UL)
- #define UARTE_INTENSET_TXSTOPPED_Pos (22UL)
- #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos)
- #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL)
- #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL)
- #define UARTE_INTENSET_TXSTOPPED_Set (1UL)
- #define UARTE_INTENSET_TXSTARTED_Pos (20UL)
- #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos)
- #define UARTE_INTENSET_TXSTARTED_Disabled (0UL)
- #define UARTE_INTENSET_TXSTARTED_Enabled (1UL)
- #define UARTE_INTENSET_TXSTARTED_Set (1UL)
- #define UARTE_INTENSET_RXSTARTED_Pos (19UL)
- #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos)
- #define UARTE_INTENSET_RXSTARTED_Disabled (0UL)
- #define UARTE_INTENSET_RXSTARTED_Enabled (1UL)
- #define UARTE_INTENSET_RXSTARTED_Set (1UL)
- #define UARTE_INTENSET_RXTO_Pos (17UL)
- #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos)
- #define UARTE_INTENSET_RXTO_Disabled (0UL)
- #define UARTE_INTENSET_RXTO_Enabled (1UL)
- #define UARTE_INTENSET_RXTO_Set (1UL)
- #define UARTE_INTENSET_ERROR_Pos (9UL)
- #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos)
- #define UARTE_INTENSET_ERROR_Disabled (0UL)
- #define UARTE_INTENSET_ERROR_Enabled (1UL)
- #define UARTE_INTENSET_ERROR_Set (1UL)
- #define UARTE_INTENSET_ENDTX_Pos (8UL)
- #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos)
- #define UARTE_INTENSET_ENDTX_Disabled (0UL)
- #define UARTE_INTENSET_ENDTX_Enabled (1UL)
- #define UARTE_INTENSET_ENDTX_Set (1UL)
- #define UARTE_INTENSET_TXDRDY_Pos (7UL)
- #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos)
- #define UARTE_INTENSET_TXDRDY_Disabled (0UL)
- #define UARTE_INTENSET_TXDRDY_Enabled (1UL)
- #define UARTE_INTENSET_TXDRDY_Set (1UL)
- #define UARTE_INTENSET_ENDRX_Pos (4UL)
- #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos)
- #define UARTE_INTENSET_ENDRX_Disabled (0UL)
- #define UARTE_INTENSET_ENDRX_Enabled (1UL)
- #define UARTE_INTENSET_ENDRX_Set (1UL)
- #define UARTE_INTENSET_RXDRDY_Pos (2UL)
- #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos)
- #define UARTE_INTENSET_RXDRDY_Disabled (0UL)
- #define UARTE_INTENSET_RXDRDY_Enabled (1UL)
- #define UARTE_INTENSET_RXDRDY_Set (1UL)
- #define UARTE_INTENSET_NCTS_Pos (1UL)
- #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos)
- #define UARTE_INTENSET_NCTS_Disabled (0UL)
- #define UARTE_INTENSET_NCTS_Enabled (1UL)
- #define UARTE_INTENSET_NCTS_Set (1UL)
- #define UARTE_INTENSET_CTS_Pos (0UL)
- #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos)
- #define UARTE_INTENSET_CTS_Disabled (0UL)
- #define UARTE_INTENSET_CTS_Enabled (1UL)
- #define UARTE_INTENSET_CTS_Set (1UL)
- #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL)
- #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos)
- #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL)
- #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL)
- #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL)
- #define UARTE_INTENCLR_TXSTARTED_Pos (20UL)
- #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos)
- #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL)
- #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL)
- #define UARTE_INTENCLR_TXSTARTED_Clear (1UL)
- #define UARTE_INTENCLR_RXSTARTED_Pos (19UL)
- #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos)
- #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL)
- #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL)
- #define UARTE_INTENCLR_RXSTARTED_Clear (1UL)
- #define UARTE_INTENCLR_RXTO_Pos (17UL)
- #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos)
- #define UARTE_INTENCLR_RXTO_Disabled (0UL)
- #define UARTE_INTENCLR_RXTO_Enabled (1UL)
- #define UARTE_INTENCLR_RXTO_Clear (1UL)
- #define UARTE_INTENCLR_ERROR_Pos (9UL)
- #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos)
- #define UARTE_INTENCLR_ERROR_Disabled (0UL)
- #define UARTE_INTENCLR_ERROR_Enabled (1UL)
- #define UARTE_INTENCLR_ERROR_Clear (1UL)
- #define UARTE_INTENCLR_ENDTX_Pos (8UL)
- #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos)
- #define UARTE_INTENCLR_ENDTX_Disabled (0UL)
- #define UARTE_INTENCLR_ENDTX_Enabled (1UL)
- #define UARTE_INTENCLR_ENDTX_Clear (1UL)
- #define UARTE_INTENCLR_TXDRDY_Pos (7UL)
- #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos)
- #define UARTE_INTENCLR_TXDRDY_Disabled (0UL)
- #define UARTE_INTENCLR_TXDRDY_Enabled (1UL)
- #define UARTE_INTENCLR_TXDRDY_Clear (1UL)
- #define UARTE_INTENCLR_ENDRX_Pos (4UL)
- #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos)
- #define UARTE_INTENCLR_ENDRX_Disabled (0UL)
- #define UARTE_INTENCLR_ENDRX_Enabled (1UL)
- #define UARTE_INTENCLR_ENDRX_Clear (1UL)
- #define UARTE_INTENCLR_RXDRDY_Pos (2UL)
- #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos)
- #define UARTE_INTENCLR_RXDRDY_Disabled (0UL)
- #define UARTE_INTENCLR_RXDRDY_Enabled (1UL)
- #define UARTE_INTENCLR_RXDRDY_Clear (1UL)
- #define UARTE_INTENCLR_NCTS_Pos (1UL)
- #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos)
- #define UARTE_INTENCLR_NCTS_Disabled (0UL)
- #define UARTE_INTENCLR_NCTS_Enabled (1UL)
- #define UARTE_INTENCLR_NCTS_Clear (1UL)
- #define UARTE_INTENCLR_CTS_Pos (0UL)
- #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos)
- #define UARTE_INTENCLR_CTS_Disabled (0UL)
- #define UARTE_INTENCLR_CTS_Enabled (1UL)
- #define UARTE_INTENCLR_CTS_Clear (1UL)
- #define UARTE_ERRORSRC_BREAK_Pos (3UL)
- #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos)
- #define UARTE_ERRORSRC_BREAK_NotPresent (0UL)
- #define UARTE_ERRORSRC_BREAK_Present (1UL)
- #define UARTE_ERRORSRC_FRAMING_Pos (2UL)
- #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos)
- #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL)
- #define UARTE_ERRORSRC_FRAMING_Present (1UL)
- #define UARTE_ERRORSRC_PARITY_Pos (1UL)
- #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos)
- #define UARTE_ERRORSRC_PARITY_NotPresent (0UL)
- #define UARTE_ERRORSRC_PARITY_Present (1UL)
- #define UARTE_ERRORSRC_OVERRUN_Pos (0UL)
- #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos)
- #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL)
- #define UARTE_ERRORSRC_OVERRUN_Present (1UL)
- #define UARTE_ENABLE_ENABLE_Pos (0UL)
- #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos)
- #define UARTE_ENABLE_ENABLE_Disabled (0UL)
- #define UARTE_ENABLE_ENABLE_Enabled (8UL)
- #define UARTE_PSEL_RTS_CONNECT_Pos (31UL)
- #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos)
- #define UARTE_PSEL_RTS_CONNECT_Connected (0UL)
- #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL)
- #define UARTE_PSEL_RTS_PORT_Pos (5UL)
- #define UARTE_PSEL_RTS_PORT_Msk (0x1UL << UARTE_PSEL_RTS_PORT_Pos)
- #define UARTE_PSEL_RTS_PIN_Pos (0UL)
- #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos)
- #define UARTE_PSEL_TXD_CONNECT_Pos (31UL)
- #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos)
- #define UARTE_PSEL_TXD_CONNECT_Connected (0UL)
- #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL)
- #define UARTE_PSEL_TXD_PORT_Pos (5UL)
- #define UARTE_PSEL_TXD_PORT_Msk (0x1UL << UARTE_PSEL_TXD_PORT_Pos)
- #define UARTE_PSEL_TXD_PIN_Pos (0UL)
- #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos)
- #define UARTE_PSEL_CTS_CONNECT_Pos (31UL)
- #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos)
- #define UARTE_PSEL_CTS_CONNECT_Connected (0UL)
- #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL)
- #define UARTE_PSEL_CTS_PORT_Pos (5UL)
- #define UARTE_PSEL_CTS_PORT_Msk (0x1UL << UARTE_PSEL_CTS_PORT_Pos)
- #define UARTE_PSEL_CTS_PIN_Pos (0UL)
- #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos)
- #define UARTE_PSEL_RXD_CONNECT_Pos (31UL)
- #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos)
- #define UARTE_PSEL_RXD_CONNECT_Connected (0UL)
- #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL)
- #define UARTE_PSEL_RXD_PORT_Pos (5UL)
- #define UARTE_PSEL_RXD_PORT_Msk (0x1UL << UARTE_PSEL_RXD_PORT_Pos)
- #define UARTE_PSEL_RXD_PIN_Pos (0UL)
- #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos)
- #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL)
- #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos)
- #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL)
- #define UARTE_RXD_PTR_PTR_Pos (0UL)
- #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos)
- #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL)
- #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos)
- #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL)
- #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos)
- #define UARTE_TXD_PTR_PTR_Pos (0UL)
- #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos)
- #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL)
- #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos)
- #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL)
- #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos)
- #define UARTE_CONFIG_PARITYTYPE_Pos (8UL)
- #define UARTE_CONFIG_PARITYTYPE_Msk (0x1UL << UARTE_CONFIG_PARITYTYPE_Pos)
- #define UARTE_CONFIG_PARITYTYPE_Even (0UL)
- #define UARTE_CONFIG_PARITYTYPE_Odd (1UL)
- #define UARTE_CONFIG_STOP_Pos (4UL)
- #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos)
- #define UARTE_CONFIG_STOP_One (0UL)
- #define UARTE_CONFIG_STOP_Two (1UL)
- #define UARTE_CONFIG_PARITY_Pos (1UL)
- #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos)
- #define UARTE_CONFIG_PARITY_Excluded (0x0UL)
- #define UARTE_CONFIG_PARITY_Included (0x7UL)
- #define UARTE_CONFIG_HWFC_Pos (0UL)
- #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos)
- #define UARTE_CONFIG_HWFC_Disabled (0UL)
- #define UARTE_CONFIG_HWFC_Enabled (1UL)
- #define UICR_APPROTECT_PALL_Pos (0UL)
- #define UICR_APPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_APPROTECT_PALL_Pos)
- #define UICR_APPROTECT_PALL_Protected (0x00000000UL)
- #define UICR_APPROTECT_PALL_Unprotected (0xFFFFFFFFUL)
- #define UICR_ERASEPROTECT_PALL_Pos (0UL)
- #define UICR_ERASEPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_ERASEPROTECT_PALL_Pos)
- #define UICR_ERASEPROTECT_PALL_Protected (0x00000000UL)
- #define UICR_ERASEPROTECT_PALL_Unprotected (0xFFFFFFFFUL)
- #define UICR_NRFFW_NRFFW_Pos (0UL)
- #define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos)
- #define UICR_CUSTOMER_CUSTOMER_Pos (0UL)
- #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos)
- #define VMC_RAM_POWER_S3RETENTION_Pos (19UL)
- #define VMC_RAM_POWER_S3RETENTION_Msk (0x1UL << VMC_RAM_POWER_S3RETENTION_Pos)
- #define VMC_RAM_POWER_S3RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S3RETENTION_On (1UL)
- #define VMC_RAM_POWER_S2RETENTION_Pos (18UL)
- #define VMC_RAM_POWER_S2RETENTION_Msk (0x1UL << VMC_RAM_POWER_S2RETENTION_Pos)
- #define VMC_RAM_POWER_S2RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S2RETENTION_On (1UL)
- #define VMC_RAM_POWER_S1RETENTION_Pos (17UL)
- #define VMC_RAM_POWER_S1RETENTION_Msk (0x1UL << VMC_RAM_POWER_S1RETENTION_Pos)
- #define VMC_RAM_POWER_S1RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S1RETENTION_On (1UL)
- #define VMC_RAM_POWER_S0RETENTION_Pos (16UL)
- #define VMC_RAM_POWER_S0RETENTION_Msk (0x1UL << VMC_RAM_POWER_S0RETENTION_Pos)
- #define VMC_RAM_POWER_S0RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S0RETENTION_On (1UL)
- #define VMC_RAM_POWER_S3POWER_Pos (3UL)
- #define VMC_RAM_POWER_S3POWER_Msk (0x1UL << VMC_RAM_POWER_S3POWER_Pos)
- #define VMC_RAM_POWER_S3POWER_Off (0UL)
- #define VMC_RAM_POWER_S3POWER_On (1UL)
- #define VMC_RAM_POWER_S2POWER_Pos (2UL)
- #define VMC_RAM_POWER_S2POWER_Msk (0x1UL << VMC_RAM_POWER_S2POWER_Pos)
- #define VMC_RAM_POWER_S2POWER_Off (0UL)
- #define VMC_RAM_POWER_S2POWER_On (1UL)
- #define VMC_RAM_POWER_S1POWER_Pos (1UL)
- #define VMC_RAM_POWER_S1POWER_Msk (0x1UL << VMC_RAM_POWER_S1POWER_Pos)
- #define VMC_RAM_POWER_S1POWER_Off (0UL)
- #define VMC_RAM_POWER_S1POWER_On (1UL)
- #define VMC_RAM_POWER_S0POWER_Pos (0UL)
- #define VMC_RAM_POWER_S0POWER_Msk (0x1UL << VMC_RAM_POWER_S0POWER_Pos)
- #define VMC_RAM_POWER_S0POWER_Off (0UL)
- #define VMC_RAM_POWER_S0POWER_On (1UL)
- #define VMC_RAM_POWERSET_S3RETENTION_Pos (19UL)
- #define VMC_RAM_POWERSET_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S3RETENTION_Pos)
- #define VMC_RAM_POWERSET_S3RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S2RETENTION_Pos (18UL)
- #define VMC_RAM_POWERSET_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S2RETENTION_Pos)
- #define VMC_RAM_POWERSET_S2RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S1RETENTION_Pos (17UL)
- #define VMC_RAM_POWERSET_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S1RETENTION_Pos)
- #define VMC_RAM_POWERSET_S1RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S0RETENTION_Pos (16UL)
- #define VMC_RAM_POWERSET_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S0RETENTION_Pos)
- #define VMC_RAM_POWERSET_S0RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S3POWER_Pos (3UL)
- #define VMC_RAM_POWERSET_S3POWER_Msk (0x1UL << VMC_RAM_POWERSET_S3POWER_Pos)
- #define VMC_RAM_POWERSET_S3POWER_On (1UL)
- #define VMC_RAM_POWERSET_S2POWER_Pos (2UL)
- #define VMC_RAM_POWERSET_S2POWER_Msk (0x1UL << VMC_RAM_POWERSET_S2POWER_Pos)
- #define VMC_RAM_POWERSET_S2POWER_On (1UL)
- #define VMC_RAM_POWERSET_S1POWER_Pos (1UL)
- #define VMC_RAM_POWERSET_S1POWER_Msk (0x1UL << VMC_RAM_POWERSET_S1POWER_Pos)
- #define VMC_RAM_POWERSET_S1POWER_On (1UL)
- #define VMC_RAM_POWERSET_S0POWER_Pos (0UL)
- #define VMC_RAM_POWERSET_S0POWER_Msk (0x1UL << VMC_RAM_POWERSET_S0POWER_Pos)
- #define VMC_RAM_POWERSET_S0POWER_On (1UL)
- #define VMC_RAM_POWERCLR_S3RETENTION_Pos (19UL)
- #define VMC_RAM_POWERCLR_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S3RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S3RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S2RETENTION_Pos (18UL)
- #define VMC_RAM_POWERCLR_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S2RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S2RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S1RETENTION_Pos (17UL)
- #define VMC_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S1RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S1RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S0RETENTION_Pos (16UL)
- #define VMC_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S0RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S0RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S3POWER_Pos (3UL)
- #define VMC_RAM_POWERCLR_S3POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S3POWER_Pos)
- #define VMC_RAM_POWERCLR_S3POWER_Off (1UL)
- #define VMC_RAM_POWERCLR_S2POWER_Pos (2UL)
- #define VMC_RAM_POWERCLR_S2POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S2POWER_Pos)
- #define VMC_RAM_POWERCLR_S2POWER_Off (1UL)
- #define VMC_RAM_POWERCLR_S1POWER_Pos (1UL)
- #define VMC_RAM_POWERCLR_S1POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S1POWER_Pos)
- #define VMC_RAM_POWERCLR_S1POWER_Off (1UL)
- #define VMC_RAM_POWERCLR_S0POWER_Pos (0UL)
- #define VMC_RAM_POWERCLR_S0POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S0POWER_Pos)
- #define VMC_RAM_POWERCLR_S0POWER_Off (1UL)
- #define VREQCTRL_VREGRADIO_VREQH_VREQH_Pos (0UL)
- #define VREQCTRL_VREGRADIO_VREQH_VREQH_Msk (0x1UL << VREQCTRL_VREGRADIO_VREQH_VREQH_Pos)
- #define VREQCTRL_VREGRADIO_VREQH_VREQH_Disabled (0UL)
- #define VREQCTRL_VREGRADIO_VREQH_VREQH_Enabled (1UL)
- #define VREQCTRL_VREGRADIO_VREQHREADY_READY_Pos (0UL)
- #define VREQCTRL_VREGRADIO_VREQHREADY_READY_Msk (0x1UL << VREQCTRL_VREGRADIO_VREQHREADY_READY_Pos)
- #define VREQCTRL_VREGRADIO_VREQHREADY_READY_NotReady (0UL)
- #define VREQCTRL_VREGRADIO_VREQHREADY_READY_Ready (1UL)
- #define WDT_TASKS_START_TASKS_START_Pos (0UL)
- #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos)
- #define WDT_TASKS_START_TASKS_START_Trigger (1UL)
- #define WDT_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define WDT_TASKS_STOP_TASKS_STOP_Msk (0x1UL << WDT_TASKS_STOP_TASKS_STOP_Pos)
- #define WDT_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define WDT_SUBSCRIBE_START_EN_Pos (31UL)
- #define WDT_SUBSCRIBE_START_EN_Msk (0x1UL << WDT_SUBSCRIBE_START_EN_Pos)
- #define WDT_SUBSCRIBE_START_EN_Disabled (0UL)
- #define WDT_SUBSCRIBE_START_EN_Enabled (1UL)
- #define WDT_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define WDT_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_START_CHIDX_Pos)
- #define WDT_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define WDT_SUBSCRIBE_STOP_EN_Msk (0x1UL << WDT_SUBSCRIBE_STOP_EN_Pos)
- #define WDT_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define WDT_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define WDT_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define WDT_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_STOP_CHIDX_Pos)
- #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL)
- #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos)
- #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL)
- #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL)
- #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL)
- #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << WDT_EVENTS_STOPPED_EVENTS_STOPPED_Pos)
- #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL)
- #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL)
- #define WDT_PUBLISH_TIMEOUT_EN_Pos (31UL)
- #define WDT_PUBLISH_TIMEOUT_EN_Msk (0x1UL << WDT_PUBLISH_TIMEOUT_EN_Pos)
- #define WDT_PUBLISH_TIMEOUT_EN_Disabled (0UL)
- #define WDT_PUBLISH_TIMEOUT_EN_Enabled (1UL)
- #define WDT_PUBLISH_TIMEOUT_CHIDX_Pos (0UL)
- #define WDT_PUBLISH_TIMEOUT_CHIDX_Msk (0xFFUL << WDT_PUBLISH_TIMEOUT_CHIDX_Pos)
- #define WDT_PUBLISH_STOPPED_EN_Pos (31UL)
- #define WDT_PUBLISH_STOPPED_EN_Msk (0x1UL << WDT_PUBLISH_STOPPED_EN_Pos)
- #define WDT_PUBLISH_STOPPED_EN_Disabled (0UL)
- #define WDT_PUBLISH_STOPPED_EN_Enabled (1UL)
- #define WDT_PUBLISH_STOPPED_CHIDX_Pos (0UL)
- #define WDT_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << WDT_PUBLISH_STOPPED_CHIDX_Pos)
- #define WDT_INTENSET_STOPPED_Pos (1UL)
- #define WDT_INTENSET_STOPPED_Msk (0x1UL << WDT_INTENSET_STOPPED_Pos)
- #define WDT_INTENSET_STOPPED_Disabled (0UL)
- #define WDT_INTENSET_STOPPED_Enabled (1UL)
- #define WDT_INTENSET_STOPPED_Set (1UL)
- #define WDT_INTENSET_TIMEOUT_Pos (0UL)
- #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos)
- #define WDT_INTENSET_TIMEOUT_Disabled (0UL)
- #define WDT_INTENSET_TIMEOUT_Enabled (1UL)
- #define WDT_INTENSET_TIMEOUT_Set (1UL)
- #define WDT_INTENCLR_STOPPED_Pos (1UL)
- #define WDT_INTENCLR_STOPPED_Msk (0x1UL << WDT_INTENCLR_STOPPED_Pos)
- #define WDT_INTENCLR_STOPPED_Disabled (0UL)
- #define WDT_INTENCLR_STOPPED_Enabled (1UL)
- #define WDT_INTENCLR_STOPPED_Clear (1UL)
- #define WDT_INTENCLR_TIMEOUT_Pos (0UL)
- #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos)
- #define WDT_INTENCLR_TIMEOUT_Disabled (0UL)
- #define WDT_INTENCLR_TIMEOUT_Enabled (1UL)
- #define WDT_INTENCLR_TIMEOUT_Clear (1UL)
- #define WDT_NMIENSET_STOPPED_Pos (1UL)
- #define WDT_NMIENSET_STOPPED_Msk (0x1UL << WDT_NMIENSET_STOPPED_Pos)
- #define WDT_NMIENSET_STOPPED_Disabled (0UL)
- #define WDT_NMIENSET_STOPPED_Enabled (1UL)
- #define WDT_NMIENSET_STOPPED_Set (1UL)
- #define WDT_NMIENSET_TIMEOUT_Pos (0UL)
- #define WDT_NMIENSET_TIMEOUT_Msk (0x1UL << WDT_NMIENSET_TIMEOUT_Pos)
- #define WDT_NMIENSET_TIMEOUT_Disabled (0UL)
- #define WDT_NMIENSET_TIMEOUT_Enabled (1UL)
- #define WDT_NMIENSET_TIMEOUT_Set (1UL)
- #define WDT_NMIENCLR_STOPPED_Pos (1UL)
- #define WDT_NMIENCLR_STOPPED_Msk (0x1UL << WDT_NMIENCLR_STOPPED_Pos)
- #define WDT_NMIENCLR_STOPPED_Disabled (0UL)
- #define WDT_NMIENCLR_STOPPED_Enabled (1UL)
- #define WDT_NMIENCLR_STOPPED_Clear (1UL)
- #define WDT_NMIENCLR_TIMEOUT_Pos (0UL)
- #define WDT_NMIENCLR_TIMEOUT_Msk (0x1UL << WDT_NMIENCLR_TIMEOUT_Pos)
- #define WDT_NMIENCLR_TIMEOUT_Disabled (0UL)
- #define WDT_NMIENCLR_TIMEOUT_Enabled (1UL)
- #define WDT_NMIENCLR_TIMEOUT_Clear (1UL)
- #define WDT_RUNSTATUS_RUNSTATUSWDT_Pos (0UL)
- #define WDT_RUNSTATUS_RUNSTATUSWDT_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUSWDT_Pos)
- #define WDT_RUNSTATUS_RUNSTATUSWDT_NotRunning (0UL)
- #define WDT_RUNSTATUS_RUNSTATUSWDT_Running (1UL)
- #define WDT_REQSTATUS_RR7_Pos (7UL)
- #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos)
- #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL)
- #define WDT_REQSTATUS_RR6_Pos (6UL)
- #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos)
- #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL)
- #define WDT_REQSTATUS_RR5_Pos (5UL)
- #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos)
- #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL)
- #define WDT_REQSTATUS_RR4_Pos (4UL)
- #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos)
- #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL)
- #define WDT_REQSTATUS_RR3_Pos (3UL)
- #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos)
- #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL)
- #define WDT_REQSTATUS_RR2_Pos (2UL)
- #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos)
- #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL)
- #define WDT_REQSTATUS_RR1_Pos (1UL)
- #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos)
- #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL)
- #define WDT_REQSTATUS_RR0_Pos (0UL)
- #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos)
- #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL)
- #define WDT_CRV_CRV_Pos (0UL)
- #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos)
- #define WDT_RREN_RR7_Pos (7UL)
- #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos)
- #define WDT_RREN_RR7_Disabled (0UL)
- #define WDT_RREN_RR7_Enabled (1UL)
- #define WDT_RREN_RR6_Pos (6UL)
- #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos)
- #define WDT_RREN_RR6_Disabled (0UL)
- #define WDT_RREN_RR6_Enabled (1UL)
- #define WDT_RREN_RR5_Pos (5UL)
- #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos)
- #define WDT_RREN_RR5_Disabled (0UL)
- #define WDT_RREN_RR5_Enabled (1UL)
- #define WDT_RREN_RR4_Pos (4UL)
- #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos)
- #define WDT_RREN_RR4_Disabled (0UL)
- #define WDT_RREN_RR4_Enabled (1UL)
- #define WDT_RREN_RR3_Pos (3UL)
- #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos)
- #define WDT_RREN_RR3_Disabled (0UL)
- #define WDT_RREN_RR3_Enabled (1UL)
- #define WDT_RREN_RR2_Pos (2UL)
- #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos)
- #define WDT_RREN_RR2_Disabled (0UL)
- #define WDT_RREN_RR2_Enabled (1UL)
- #define WDT_RREN_RR1_Pos (1UL)
- #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos)
- #define WDT_RREN_RR1_Disabled (0UL)
- #define WDT_RREN_RR1_Enabled (1UL)
- #define WDT_RREN_RR0_Pos (0UL)
- #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos)
- #define WDT_RREN_RR0_Disabled (0UL)
- #define WDT_RREN_RR0_Enabled (1UL)
- #define WDT_CONFIG_STOPEN_Pos (6UL)
- #define WDT_CONFIG_STOPEN_Msk (0x1UL << WDT_CONFIG_STOPEN_Pos)
- #define WDT_CONFIG_STOPEN_Disable (0UL)
- #define WDT_CONFIG_STOPEN_Enable (1UL)
- #define WDT_CONFIG_HALT_Pos (3UL)
- #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos)
- #define WDT_CONFIG_HALT_Pause (0UL)
- #define WDT_CONFIG_HALT_Run (1UL)
- #define WDT_CONFIG_SLEEP_Pos (0UL)
- #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos)
- #define WDT_CONFIG_SLEEP_Pause (0UL)
- #define WDT_CONFIG_SLEEP_Run (1UL)
- #define WDT_TSEN_TSEN_Pos (0UL)
- #define WDT_TSEN_TSEN_Msk (0xFFFFFFFFUL << WDT_TSEN_TSEN_Pos)
- #define WDT_TSEN_TSEN_Enable (0x6E524635UL)
- #define WDT_RR_RR_Pos (0UL)
- #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos)
- #define WDT_RR_RR_Reload (0x6E524635UL)
- #endif
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