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- #ifndef __NRF5340_APPLICATION_BITS_H
- #define __NRF5340_APPLICATION_BITS_H
- #define CACHEDATA_SET_WAY_DATA0_Data_Pos (0UL)
- #define CACHEDATA_SET_WAY_DATA0_Data_Msk (0xFFFFFFFFUL << CACHEDATA_SET_WAY_DATA0_Data_Pos)
- #define CACHEDATA_SET_WAY_DATA1_Data_Pos (0UL)
- #define CACHEDATA_SET_WAY_DATA1_Data_Msk (0xFFFFFFFFUL << CACHEDATA_SET_WAY_DATA1_Data_Pos)
- #define CACHEDATA_SET_WAY_DATA2_Data_Pos (0UL)
- #define CACHEDATA_SET_WAY_DATA2_Data_Msk (0xFFFFFFFFUL << CACHEDATA_SET_WAY_DATA2_Data_Pos)
- #define CACHEDATA_SET_WAY_DATA3_Data_Pos (0UL)
- #define CACHEDATA_SET_WAY_DATA3_Data_Msk (0xFFFFFFFFUL << CACHEDATA_SET_WAY_DATA3_Data_Pos)
- #define CACHEINFO_SET_WAY_MRU_Pos (31UL)
- #define CACHEINFO_SET_WAY_MRU_Msk (0x1UL << CACHEINFO_SET_WAY_MRU_Pos)
- #define CACHEINFO_SET_WAY_MRU_Way0 (0UL)
- #define CACHEINFO_SET_WAY_MRU_Way1 (1UL)
- #define CACHEINFO_SET_WAY_V_Pos (30UL)
- #define CACHEINFO_SET_WAY_V_Msk (0x1UL << CACHEINFO_SET_WAY_V_Pos)
- #define CACHEINFO_SET_WAY_V_Invalid (0UL)
- #define CACHEINFO_SET_WAY_V_Valid (1UL)
- #define CACHEINFO_SET_WAY_TAG_Pos (0UL)
- #define CACHEINFO_SET_WAY_TAG_Msk (0x1FFFFUL << CACHEINFO_SET_WAY_TAG_Pos)
- #define CACHE_PROFILING_IHIT_HITS_Pos (0UL)
- #define CACHE_PROFILING_IHIT_HITS_Msk (0xFFFFFFFFUL << CACHE_PROFILING_IHIT_HITS_Pos)
- #define CACHE_PROFILING_IMISS_MISSES_Pos (0UL)
- #define CACHE_PROFILING_IMISS_MISSES_Msk (0xFFFFFFFFUL << CACHE_PROFILING_IMISS_MISSES_Pos)
- #define CACHE_PROFILING_DHIT_HITS_Pos (0UL)
- #define CACHE_PROFILING_DHIT_HITS_Msk (0xFFFFFFFFUL << CACHE_PROFILING_DHIT_HITS_Pos)
- #define CACHE_PROFILING_DMISS_MISSES_Pos (0UL)
- #define CACHE_PROFILING_DMISS_MISSES_Msk (0xFFFFFFFFUL << CACHE_PROFILING_DMISS_MISSES_Pos)
- #define CACHE_ENABLE_ENABLE_Pos (0UL)
- #define CACHE_ENABLE_ENABLE_Msk (0x1UL << CACHE_ENABLE_ENABLE_Pos)
- #define CACHE_ENABLE_ENABLE_Disabled (0UL)
- #define CACHE_ENABLE_ENABLE_Enabled (1UL)
- #define CACHE_INVALIDATE_INVALIDATE_Pos (0UL)
- #define CACHE_INVALIDATE_INVALIDATE_Msk (0x1UL << CACHE_INVALIDATE_INVALIDATE_Pos)
- #define CACHE_INVALIDATE_INVALIDATE_Invalidate (1UL)
- #define CACHE_ERASE_ERASE_Pos (0UL)
- #define CACHE_ERASE_ERASE_Msk (0x1UL << CACHE_ERASE_ERASE_Pos)
- #define CACHE_ERASE_ERASE_Erase (1UL)
- #define CACHE_PROFILINGENABLE_ENABLE_Pos (0UL)
- #define CACHE_PROFILINGENABLE_ENABLE_Msk (0x1UL << CACHE_PROFILINGENABLE_ENABLE_Pos)
- #define CACHE_PROFILINGENABLE_ENABLE_Disable (0UL)
- #define CACHE_PROFILINGENABLE_ENABLE_Enable (1UL)
- #define CACHE_PROFILINGCLEAR_CLEAR_Pos (0UL)
- #define CACHE_PROFILINGCLEAR_CLEAR_Msk (0x1UL << CACHE_PROFILINGCLEAR_CLEAR_Pos)
- #define CACHE_PROFILINGCLEAR_CLEAR_Clear (1UL)
- #define CACHE_MODE_MODE_Pos (0UL)
- #define CACHE_MODE_MODE_Msk (0x1UL << CACHE_MODE_MODE_Pos)
- #define CACHE_MODE_MODE_Cache (0UL)
- #define CACHE_MODE_MODE_Ram (1UL)
- #define CACHE_DEBUGLOCK_DEBUGLOCK_Pos (0UL)
- #define CACHE_DEBUGLOCK_DEBUGLOCK_Msk (0x1UL << CACHE_DEBUGLOCK_DEBUGLOCK_Pos)
- #define CACHE_DEBUGLOCK_DEBUGLOCK_Unlocked (0UL)
- #define CACHE_DEBUGLOCK_DEBUGLOCK_Locked (1UL)
- #define CACHE_ERASESTATUS_ERASESTATUS_Pos (0UL)
- #define CACHE_ERASESTATUS_ERASESTATUS_Msk (0x1UL << CACHE_ERASESTATUS_ERASESTATUS_Pos)
- #define CACHE_ERASESTATUS_ERASESTATUS_Idle (0UL)
- #define CACHE_ERASESTATUS_ERASESTATUS_Finished (1UL)
- #define CACHE_WRITELOCK_WRITELOCK_Pos (0UL)
- #define CACHE_WRITELOCK_WRITELOCK_Msk (0x1UL << CACHE_WRITELOCK_WRITELOCK_Pos)
- #define CACHE_WRITELOCK_WRITELOCK_Unlocked (0UL)
- #define CACHE_WRITELOCK_WRITELOCK_Locked (1UL)
- #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL)
- #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos)
- #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL)
- #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL)
- #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos)
- #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL)
- #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL)
- #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos)
- #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL)
- #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL)
- #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos)
- #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL)
- #define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL)
- #define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos)
- #define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL)
- #define CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Pos (0UL)
- #define CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Pos)
- #define CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Trigger (1UL)
- #define CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Pos (0UL)
- #define CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Pos)
- #define CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Trigger (1UL)
- #define CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Pos (0UL)
- #define CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Msk (0x1UL << CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Pos)
- #define CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Trigger (1UL)
- #define CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Pos (0UL)
- #define CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Pos)
- #define CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Trigger (1UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos (31UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos)
- #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Disabled (0UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Enabled (1UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos (0UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos)
- #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos (31UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos)
- #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Disabled (0UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Enabled (1UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos (0UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos)
- #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos (31UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos)
- #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (1UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos (0UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos)
- #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos (31UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos)
- #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (1UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos (0UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos)
- #define CLOCK_SUBSCRIBE_CAL_EN_Pos (31UL)
- #define CLOCK_SUBSCRIBE_CAL_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_CAL_EN_Pos)
- #define CLOCK_SUBSCRIBE_CAL_EN_Disabled (0UL)
- #define CLOCK_SUBSCRIBE_CAL_EN_Enabled (1UL)
- #define CLOCK_SUBSCRIBE_CAL_CHIDX_Pos (0UL)
- #define CLOCK_SUBSCRIBE_CAL_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_CAL_CHIDX_Pos)
- #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Pos (31UL)
- #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Pos)
- #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Disabled (0UL)
- #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Enabled (1UL)
- #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_CHIDX_Pos (0UL)
- #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_CHIDX_Pos)
- #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Pos (31UL)
- #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Pos)
- #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Disabled (0UL)
- #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Enabled (1UL)
- #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_CHIDX_Pos (0UL)
- #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_CHIDX_Pos)
- #define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Pos (31UL)
- #define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Pos)
- #define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Disabled (0UL)
- #define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Enabled (1UL)
- #define CLOCK_SUBSCRIBE_HFCLK192MSTART_CHIDX_Pos (0UL)
- #define CLOCK_SUBSCRIBE_HFCLK192MSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLK192MSTART_CHIDX_Pos)
- #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Pos (31UL)
- #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Pos)
- #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Disabled (0UL)
- #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Enabled (1UL)
- #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_CHIDX_Pos (0UL)
- #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLK192MSTOP_CHIDX_Pos)
- #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL)
- #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos)
- #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL)
- #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL)
- #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL)
- #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos)
- #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL)
- #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL)
- #define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL)
- #define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos)
- #define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL)
- #define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL)
- #define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Pos (0UL)
- #define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Pos)
- #define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_NotGenerated (0UL)
- #define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Generated (1UL)
- #define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Pos (0UL)
- #define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Pos)
- #define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_NotGenerated (0UL)
- #define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Generated (1UL)
- #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos (31UL)
- #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos)
- #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Disabled (0UL)
- #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Enabled (1UL)
- #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos (0UL)
- #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos)
- #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos (31UL)
- #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos)
- #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Disabled (0UL)
- #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (1UL)
- #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos (0UL)
- #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos)
- #define CLOCK_PUBLISH_DONE_EN_Pos (31UL)
- #define CLOCK_PUBLISH_DONE_EN_Msk (0x1UL << CLOCK_PUBLISH_DONE_EN_Pos)
- #define CLOCK_PUBLISH_DONE_EN_Disabled (0UL)
- #define CLOCK_PUBLISH_DONE_EN_Enabled (1UL)
- #define CLOCK_PUBLISH_DONE_CHIDX_Pos (0UL)
- #define CLOCK_PUBLISH_DONE_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_DONE_CHIDX_Pos)
- #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Pos (31UL)
- #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Pos)
- #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Disabled (0UL)
- #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Enabled (1UL)
- #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_CHIDX_Pos (0UL)
- #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKAUDIOSTARTED_CHIDX_Pos)
- #define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Pos (31UL)
- #define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Pos)
- #define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Disabled (0UL)
- #define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Enabled (1UL)
- #define CLOCK_PUBLISH_HFCLK192MSTARTED_CHIDX_Pos (0UL)
- #define CLOCK_PUBLISH_HFCLK192MSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLK192MSTARTED_CHIDX_Pos)
- #define CLOCK_INTEN_HFCLK192MSTARTED_Pos (9UL)
- #define CLOCK_INTEN_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLK192MSTARTED_Pos)
- #define CLOCK_INTEN_HFCLK192MSTARTED_Disabled (0UL)
- #define CLOCK_INTEN_HFCLK192MSTARTED_Enabled (1UL)
- #define CLOCK_INTEN_HFCLKAUDIOSTARTED_Pos (8UL)
- #define CLOCK_INTEN_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKAUDIOSTARTED_Pos)
- #define CLOCK_INTEN_HFCLKAUDIOSTARTED_Disabled (0UL)
- #define CLOCK_INTEN_HFCLKAUDIOSTARTED_Enabled (1UL)
- #define CLOCK_INTEN_DONE_Pos (7UL)
- #define CLOCK_INTEN_DONE_Msk (0x1UL << CLOCK_INTEN_DONE_Pos)
- #define CLOCK_INTEN_DONE_Disabled (0UL)
- #define CLOCK_INTEN_DONE_Enabled (1UL)
- #define CLOCK_INTEN_LFCLKSTARTED_Pos (1UL)
- #define CLOCK_INTEN_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_LFCLKSTARTED_Pos)
- #define CLOCK_INTEN_LFCLKSTARTED_Disabled (0UL)
- #define CLOCK_INTEN_LFCLKSTARTED_Enabled (1UL)
- #define CLOCK_INTEN_HFCLKSTARTED_Pos (0UL)
- #define CLOCK_INTEN_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKSTARTED_Pos)
- #define CLOCK_INTEN_HFCLKSTARTED_Disabled (0UL)
- #define CLOCK_INTEN_HFCLKSTARTED_Enabled (1UL)
- #define CLOCK_INTENSET_HFCLK192MSTARTED_Pos (9UL)
- #define CLOCK_INTENSET_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLK192MSTARTED_Pos)
- #define CLOCK_INTENSET_HFCLK192MSTARTED_Disabled (0UL)
- #define CLOCK_INTENSET_HFCLK192MSTARTED_Enabled (1UL)
- #define CLOCK_INTENSET_HFCLK192MSTARTED_Set (1UL)
- #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Pos (8UL)
- #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKAUDIOSTARTED_Pos)
- #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Disabled (0UL)
- #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Enabled (1UL)
- #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Set (1UL)
- #define CLOCK_INTENSET_DONE_Pos (7UL)
- #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos)
- #define CLOCK_INTENSET_DONE_Disabled (0UL)
- #define CLOCK_INTENSET_DONE_Enabled (1UL)
- #define CLOCK_INTENSET_DONE_Set (1UL)
- #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL)
- #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos)
- #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL)
- #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL)
- #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL)
- #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL)
- #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos)
- #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL)
- #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL)
- #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL)
- #define CLOCK_INTENCLR_HFCLK192MSTARTED_Pos (9UL)
- #define CLOCK_INTENCLR_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLK192MSTARTED_Pos)
- #define CLOCK_INTENCLR_HFCLK192MSTARTED_Disabled (0UL)
- #define CLOCK_INTENCLR_HFCLK192MSTARTED_Enabled (1UL)
- #define CLOCK_INTENCLR_HFCLK192MSTARTED_Clear (1UL)
- #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Pos (8UL)
- #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Pos)
- #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Disabled (0UL)
- #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Enabled (1UL)
- #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Clear (1UL)
- #define CLOCK_INTENCLR_DONE_Pos (7UL)
- #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos)
- #define CLOCK_INTENCLR_DONE_Disabled (0UL)
- #define CLOCK_INTENCLR_DONE_Enabled (1UL)
- #define CLOCK_INTENCLR_DONE_Clear (1UL)
- #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL)
- #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos)
- #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL)
- #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL)
- #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL)
- #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL)
- #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos)
- #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL)
- #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL)
- #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL)
- #define CLOCK_INTPEND_HFCLK192MSTARTED_Pos (9UL)
- #define CLOCK_INTPEND_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLK192MSTARTED_Pos)
- #define CLOCK_INTPEND_HFCLK192MSTARTED_NotPending (0UL)
- #define CLOCK_INTPEND_HFCLK192MSTARTED_Pending (1UL)
- #define CLOCK_INTPEND_HFCLKAUDIOSTARTED_Pos (8UL)
- #define CLOCK_INTPEND_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKAUDIOSTARTED_Pos)
- #define CLOCK_INTPEND_HFCLKAUDIOSTARTED_NotPending (0UL)
- #define CLOCK_INTPEND_HFCLKAUDIOSTARTED_Pending (1UL)
- #define CLOCK_INTPEND_DONE_Pos (7UL)
- #define CLOCK_INTPEND_DONE_Msk (0x1UL << CLOCK_INTPEND_DONE_Pos)
- #define CLOCK_INTPEND_DONE_NotPending (0UL)
- #define CLOCK_INTPEND_DONE_Pending (1UL)
- #define CLOCK_INTPEND_LFCLKSTARTED_Pos (1UL)
- #define CLOCK_INTPEND_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_LFCLKSTARTED_Pos)
- #define CLOCK_INTPEND_LFCLKSTARTED_NotPending (0UL)
- #define CLOCK_INTPEND_LFCLKSTARTED_Pending (1UL)
- #define CLOCK_INTPEND_HFCLKSTARTED_Pos (0UL)
- #define CLOCK_INTPEND_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKSTARTED_Pos)
- #define CLOCK_INTPEND_HFCLKSTARTED_NotPending (0UL)
- #define CLOCK_INTPEND_HFCLKSTARTED_Pending (1UL)
- #define CLOCK_HFCLKRUN_STATUS_Pos (0UL)
- #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos)
- #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL)
- #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL)
- #define CLOCK_HFCLKSTAT_STATE_Pos (16UL)
- #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos)
- #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL)
- #define CLOCK_HFCLKSTAT_STATE_Running (1UL)
- #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Pos (4UL)
- #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_HFCLKSTAT_ALWAYSRUNNING_Pos)
- #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_NotRunning (0UL)
- #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Running (1UL)
- #define CLOCK_HFCLKSTAT_SRC_Pos (0UL)
- #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos)
- #define CLOCK_HFCLKSTAT_SRC_HFINT (0UL)
- #define CLOCK_HFCLKSTAT_SRC_HFXO (1UL)
- #define CLOCK_LFCLKRUN_STATUS_Pos (0UL)
- #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos)
- #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL)
- #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL)
- #define CLOCK_LFCLKSTAT_STATE_Pos (16UL)
- #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos)
- #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL)
- #define CLOCK_LFCLKSTAT_STATE_Running (1UL)
- #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos (4UL)
- #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos)
- #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_NotRunning (0UL)
- #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Running (1UL)
- #define CLOCK_LFCLKSTAT_SRC_Pos (0UL)
- #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos)
- #define CLOCK_LFCLKSTAT_SRC_LFULP (0UL)
- #define CLOCK_LFCLKSTAT_SRC_LFRC (1UL)
- #define CLOCK_LFCLKSTAT_SRC_LFXO (2UL)
- #define CLOCK_LFCLKSTAT_SRC_LFSYNT (3UL)
- #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL)
- #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos)
- #define CLOCK_LFCLKSRCCOPY_SRC_LFULP (0UL)
- #define CLOCK_LFCLKSRCCOPY_SRC_LFRC (1UL)
- #define CLOCK_LFCLKSRCCOPY_SRC_LFXO (2UL)
- #define CLOCK_LFCLKSRCCOPY_SRC_LFSYNT (3UL)
- #define CLOCK_HFCLKAUDIORUN_STATUS_Pos (0UL)
- #define CLOCK_HFCLKAUDIORUN_STATUS_Msk (0x1UL << CLOCK_HFCLKAUDIORUN_STATUS_Pos)
- #define CLOCK_HFCLKAUDIORUN_STATUS_NotTriggered (0UL)
- #define CLOCK_HFCLKAUDIORUN_STATUS_Triggered (1UL)
- #define CLOCK_HFCLKAUDIOSTAT_STATE_Pos (16UL)
- #define CLOCK_HFCLKAUDIOSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKAUDIOSTAT_STATE_Pos)
- #define CLOCK_HFCLKAUDIOSTAT_STATE_NotRunning (0UL)
- #define CLOCK_HFCLKAUDIOSTAT_STATE_Running (1UL)
- #define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Pos (4UL)
- #define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Pos)
- #define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_NotRunning (0UL)
- #define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Running (1UL)
- #define CLOCK_HFCLK192MRUN_STATUS_Pos (0UL)
- #define CLOCK_HFCLK192MRUN_STATUS_Msk (0x1UL << CLOCK_HFCLK192MRUN_STATUS_Pos)
- #define CLOCK_HFCLK192MRUN_STATUS_NotTriggered (0UL)
- #define CLOCK_HFCLK192MRUN_STATUS_Triggered (1UL)
- #define CLOCK_HFCLK192MSTAT_STATE_Pos (16UL)
- #define CLOCK_HFCLK192MSTAT_STATE_Msk (0x1UL << CLOCK_HFCLK192MSTAT_STATE_Pos)
- #define CLOCK_HFCLK192MSTAT_STATE_NotRunning (0UL)
- #define CLOCK_HFCLK192MSTAT_STATE_Running (1UL)
- #define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Pos (4UL)
- #define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Pos)
- #define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_NotRunning (0UL)
- #define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Running (1UL)
- #define CLOCK_HFCLK192MSTAT_SRC_Pos (0UL)
- #define CLOCK_HFCLK192MSTAT_SRC_Msk (0x1UL << CLOCK_HFCLK192MSTAT_SRC_Pos)
- #define CLOCK_HFCLK192MSTAT_SRC_HFINT (0UL)
- #define CLOCK_HFCLK192MSTAT_SRC_HFXO (1UL)
- #define CLOCK_HFCLKSRC_SRC_Pos (0UL)
- #define CLOCK_HFCLKSRC_SRC_Msk (0x1UL << CLOCK_HFCLKSRC_SRC_Pos)
- #define CLOCK_HFCLKSRC_SRC_HFINT (0UL)
- #define CLOCK_HFCLKSRC_SRC_HFXO (1UL)
- #define CLOCK_LFCLKSRC_SRC_Pos (0UL)
- #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos)
- #define CLOCK_LFCLKSRC_SRC_LFULP (0UL)
- #define CLOCK_LFCLKSRC_SRC_LFRC (1UL)
- #define CLOCK_LFCLKSRC_SRC_LFXO (2UL)
- #define CLOCK_LFCLKSRC_SRC_LFSYNT (3UL)
- #define CLOCK_HFCLKCTRL_HCLK_Pos (0UL)
- #define CLOCK_HFCLKCTRL_HCLK_Msk (0x3UL << CLOCK_HFCLKCTRL_HCLK_Pos)
- #define CLOCK_HFCLKCTRL_HCLK_Div1 (0UL)
- #define CLOCK_HFCLKCTRL_HCLK_Div2 (1UL)
- #define CLOCK_HFCLKAUDIO_FREQUENCY_FREQUENCY_Pos (0UL)
- #define CLOCK_HFCLKAUDIO_FREQUENCY_FREQUENCY_Msk (0xFFFFUL << CLOCK_HFCLKAUDIO_FREQUENCY_FREQUENCY_Pos)
- #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos (0UL)
- #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos)
- #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Automatic (0UL)
- #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL)
- #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos (0UL)
- #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos)
- #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Automatic (0UL)
- #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL)
- #define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Pos (0UL)
- #define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Pos)
- #define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Automatic (0UL)
- #define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL)
- #define CLOCK_HFCLK192MSRC_SRC_Pos (0UL)
- #define CLOCK_HFCLK192MSRC_SRC_Msk (0x1UL << CLOCK_HFCLK192MSRC_SRC_Pos)
- #define CLOCK_HFCLK192MSRC_SRC_HFINT (0UL)
- #define CLOCK_HFCLK192MSRC_SRC_HFXO (1UL)
- #define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Pos (0UL)
- #define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Pos)
- #define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Automatic (0UL)
- #define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL)
- #define CLOCK_HFCLK192MCTRL_HCLK192M_Pos (0UL)
- #define CLOCK_HFCLK192MCTRL_HCLK192M_Msk (0x3UL << CLOCK_HFCLK192MCTRL_HCLK192M_Pos)
- #define CLOCK_HFCLK192MCTRL_HCLK192M_Div1 (0UL)
- #define CLOCK_HFCLK192MCTRL_HCLK192M_Div2 (1UL)
- #define CLOCK_HFCLK192MCTRL_HCLK192M_Div4 (2UL)
- #define COMP_TASKS_START_TASKS_START_Pos (0UL)
- #define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos)
- #define COMP_TASKS_START_TASKS_START_Trigger (1UL)
- #define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos)
- #define COMP_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL)
- #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos)
- #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL)
- #define COMP_SUBSCRIBE_START_EN_Pos (31UL)
- #define COMP_SUBSCRIBE_START_EN_Msk (0x1UL << COMP_SUBSCRIBE_START_EN_Pos)
- #define COMP_SUBSCRIBE_START_EN_Disabled (0UL)
- #define COMP_SUBSCRIBE_START_EN_Enabled (1UL)
- #define COMP_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define COMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << COMP_SUBSCRIBE_START_CHIDX_Pos)
- #define COMP_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define COMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << COMP_SUBSCRIBE_STOP_EN_Pos)
- #define COMP_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define COMP_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define COMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define COMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << COMP_SUBSCRIBE_STOP_CHIDX_Pos)
- #define COMP_SUBSCRIBE_SAMPLE_EN_Pos (31UL)
- #define COMP_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << COMP_SUBSCRIBE_SAMPLE_EN_Pos)
- #define COMP_SUBSCRIBE_SAMPLE_EN_Disabled (0UL)
- #define COMP_SUBSCRIBE_SAMPLE_EN_Enabled (1UL)
- #define COMP_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL)
- #define COMP_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << COMP_SUBSCRIBE_SAMPLE_CHIDX_Pos)
- #define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL)
- #define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos)
- #define COMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL)
- #define COMP_EVENTS_READY_EVENTS_READY_Generated (1UL)
- #define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL)
- #define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos)
- #define COMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL)
- #define COMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL)
- #define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL)
- #define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos)
- #define COMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL)
- #define COMP_EVENTS_UP_EVENTS_UP_Generated (1UL)
- #define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL)
- #define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos)
- #define COMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL)
- #define COMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL)
- #define COMP_PUBLISH_READY_EN_Pos (31UL)
- #define COMP_PUBLISH_READY_EN_Msk (0x1UL << COMP_PUBLISH_READY_EN_Pos)
- #define COMP_PUBLISH_READY_EN_Disabled (0UL)
- #define COMP_PUBLISH_READY_EN_Enabled (1UL)
- #define COMP_PUBLISH_READY_CHIDX_Pos (0UL)
- #define COMP_PUBLISH_READY_CHIDX_Msk (0xFFUL << COMP_PUBLISH_READY_CHIDX_Pos)
- #define COMP_PUBLISH_DOWN_EN_Pos (31UL)
- #define COMP_PUBLISH_DOWN_EN_Msk (0x1UL << COMP_PUBLISH_DOWN_EN_Pos)
- #define COMP_PUBLISH_DOWN_EN_Disabled (0UL)
- #define COMP_PUBLISH_DOWN_EN_Enabled (1UL)
- #define COMP_PUBLISH_DOWN_CHIDX_Pos (0UL)
- #define COMP_PUBLISH_DOWN_CHIDX_Msk (0xFFUL << COMP_PUBLISH_DOWN_CHIDX_Pos)
- #define COMP_PUBLISH_UP_EN_Pos (31UL)
- #define COMP_PUBLISH_UP_EN_Msk (0x1UL << COMP_PUBLISH_UP_EN_Pos)
- #define COMP_PUBLISH_UP_EN_Disabled (0UL)
- #define COMP_PUBLISH_UP_EN_Enabled (1UL)
- #define COMP_PUBLISH_UP_CHIDX_Pos (0UL)
- #define COMP_PUBLISH_UP_CHIDX_Msk (0xFFUL << COMP_PUBLISH_UP_CHIDX_Pos)
- #define COMP_PUBLISH_CROSS_EN_Pos (31UL)
- #define COMP_PUBLISH_CROSS_EN_Msk (0x1UL << COMP_PUBLISH_CROSS_EN_Pos)
- #define COMP_PUBLISH_CROSS_EN_Disabled (0UL)
- #define COMP_PUBLISH_CROSS_EN_Enabled (1UL)
- #define COMP_PUBLISH_CROSS_CHIDX_Pos (0UL)
- #define COMP_PUBLISH_CROSS_CHIDX_Msk (0xFFUL << COMP_PUBLISH_CROSS_CHIDX_Pos)
- #define COMP_SHORTS_CROSS_STOP_Pos (4UL)
- #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos)
- #define COMP_SHORTS_CROSS_STOP_Disabled (0UL)
- #define COMP_SHORTS_CROSS_STOP_Enabled (1UL)
- #define COMP_SHORTS_UP_STOP_Pos (3UL)
- #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos)
- #define COMP_SHORTS_UP_STOP_Disabled (0UL)
- #define COMP_SHORTS_UP_STOP_Enabled (1UL)
- #define COMP_SHORTS_DOWN_STOP_Pos (2UL)
- #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos)
- #define COMP_SHORTS_DOWN_STOP_Disabled (0UL)
- #define COMP_SHORTS_DOWN_STOP_Enabled (1UL)
- #define COMP_SHORTS_READY_STOP_Pos (1UL)
- #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos)
- #define COMP_SHORTS_READY_STOP_Disabled (0UL)
- #define COMP_SHORTS_READY_STOP_Enabled (1UL)
- #define COMP_SHORTS_READY_SAMPLE_Pos (0UL)
- #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos)
- #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL)
- #define COMP_SHORTS_READY_SAMPLE_Enabled (1UL)
- #define COMP_INTEN_CROSS_Pos (3UL)
- #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos)
- #define COMP_INTEN_CROSS_Disabled (0UL)
- #define COMP_INTEN_CROSS_Enabled (1UL)
- #define COMP_INTEN_UP_Pos (2UL)
- #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos)
- #define COMP_INTEN_UP_Disabled (0UL)
- #define COMP_INTEN_UP_Enabled (1UL)
- #define COMP_INTEN_DOWN_Pos (1UL)
- #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos)
- #define COMP_INTEN_DOWN_Disabled (0UL)
- #define COMP_INTEN_DOWN_Enabled (1UL)
- #define COMP_INTEN_READY_Pos (0UL)
- #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos)
- #define COMP_INTEN_READY_Disabled (0UL)
- #define COMP_INTEN_READY_Enabled (1UL)
- #define COMP_INTENSET_CROSS_Pos (3UL)
- #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos)
- #define COMP_INTENSET_CROSS_Disabled (0UL)
- #define COMP_INTENSET_CROSS_Enabled (1UL)
- #define COMP_INTENSET_CROSS_Set (1UL)
- #define COMP_INTENSET_UP_Pos (2UL)
- #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos)
- #define COMP_INTENSET_UP_Disabled (0UL)
- #define COMP_INTENSET_UP_Enabled (1UL)
- #define COMP_INTENSET_UP_Set (1UL)
- #define COMP_INTENSET_DOWN_Pos (1UL)
- #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos)
- #define COMP_INTENSET_DOWN_Disabled (0UL)
- #define COMP_INTENSET_DOWN_Enabled (1UL)
- #define COMP_INTENSET_DOWN_Set (1UL)
- #define COMP_INTENSET_READY_Pos (0UL)
- #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos)
- #define COMP_INTENSET_READY_Disabled (0UL)
- #define COMP_INTENSET_READY_Enabled (1UL)
- #define COMP_INTENSET_READY_Set (1UL)
- #define COMP_INTENCLR_CROSS_Pos (3UL)
- #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos)
- #define COMP_INTENCLR_CROSS_Disabled (0UL)
- #define COMP_INTENCLR_CROSS_Enabled (1UL)
- #define COMP_INTENCLR_CROSS_Clear (1UL)
- #define COMP_INTENCLR_UP_Pos (2UL)
- #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos)
- #define COMP_INTENCLR_UP_Disabled (0UL)
- #define COMP_INTENCLR_UP_Enabled (1UL)
- #define COMP_INTENCLR_UP_Clear (1UL)
- #define COMP_INTENCLR_DOWN_Pos (1UL)
- #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos)
- #define COMP_INTENCLR_DOWN_Disabled (0UL)
- #define COMP_INTENCLR_DOWN_Enabled (1UL)
- #define COMP_INTENCLR_DOWN_Clear (1UL)
- #define COMP_INTENCLR_READY_Pos (0UL)
- #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos)
- #define COMP_INTENCLR_READY_Disabled (0UL)
- #define COMP_INTENCLR_READY_Enabled (1UL)
- #define COMP_INTENCLR_READY_Clear (1UL)
- #define COMP_RESULT_RESULT_Pos (0UL)
- #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos)
- #define COMP_RESULT_RESULT_Below (0UL)
- #define COMP_RESULT_RESULT_Above (1UL)
- #define COMP_ENABLE_ENABLE_Pos (0UL)
- #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos)
- #define COMP_ENABLE_ENABLE_Disabled (0UL)
- #define COMP_ENABLE_ENABLE_Enabled (2UL)
- #define COMP_PSEL_PSEL_Pos (0UL)
- #define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos)
- #define COMP_PSEL_PSEL_AnalogInput0 (0UL)
- #define COMP_PSEL_PSEL_AnalogInput1 (1UL)
- #define COMP_PSEL_PSEL_AnalogInput2 (2UL)
- #define COMP_PSEL_PSEL_AnalogInput3 (3UL)
- #define COMP_PSEL_PSEL_AnalogInput4 (4UL)
- #define COMP_PSEL_PSEL_AnalogInput5 (5UL)
- #define COMP_PSEL_PSEL_AnalogInput6 (6UL)
- #define COMP_PSEL_PSEL_AnalogInput7 (7UL)
- #define COMP_REFSEL_REFSEL_Pos (0UL)
- #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos)
- #define COMP_REFSEL_REFSEL_Int1V2 (0UL)
- #define COMP_REFSEL_REFSEL_Int1V8 (1UL)
- #define COMP_REFSEL_REFSEL_Int2V4 (2UL)
- #define COMP_REFSEL_REFSEL_VDD (4UL)
- #define COMP_REFSEL_REFSEL_ARef (5UL)
- #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL)
- #define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos)
- #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL)
- #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL)
- #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL)
- #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (3UL)
- #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (4UL)
- #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (5UL)
- #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (6UL)
- #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (7UL)
- #define COMP_TH_THUP_Pos (8UL)
- #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos)
- #define COMP_TH_THDOWN_Pos (0UL)
- #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos)
- #define COMP_MODE_MAIN_Pos (8UL)
- #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos)
- #define COMP_MODE_MAIN_SE (0UL)
- #define COMP_MODE_MAIN_Diff (1UL)
- #define COMP_MODE_SP_Pos (0UL)
- #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos)
- #define COMP_MODE_SP_Low (0UL)
- #define COMP_MODE_SP_Normal (1UL)
- #define COMP_MODE_SP_High (2UL)
- #define COMP_HYST_HYST_Pos (0UL)
- #define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos)
- #define COMP_HYST_HYST_NoHyst (0UL)
- #define COMP_HYST_HYST_Hyst50mV (1UL)
- #define COMP_ISOURCE_ISOURCE_Pos (0UL)
- #define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos)
- #define COMP_ISOURCE_ISOURCE_Off (0UL)
- #define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL)
- #define COMP_ISOURCE_ISOURCE_Ien5mA (2UL)
- #define COMP_ISOURCE_ISOURCE_Ien10mA (3UL)
- #define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL)
- #define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos)
- #define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL)
- #define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL)
- #define CTI_CTICONTROL_GLBEN_Pos (0UL)
- #define CTI_CTICONTROL_GLBEN_Msk (0x1UL << CTI_CTICONTROL_GLBEN_Pos)
- #define CTI_CTICONTROL_GLBEN_Disabled (0UL)
- #define CTI_CTICONTROL_GLBEN_Enabled (1UL)
- #define CTI_CTIINTACK_ETMEVTIN3_Pos (7UL)
- #define CTI_CTIINTACK_ETMEVTIN3_Msk (0x1UL << CTI_CTIINTACK_ETMEVTIN3_Pos)
- #define CTI_CTIINTACK_ETMEVTIN3_Acknowledge (1UL)
- #define CTI_CTIINTACK_ETMEVTIN2_Pos (6UL)
- #define CTI_CTIINTACK_ETMEVTIN2_Msk (0x1UL << CTI_CTIINTACK_ETMEVTIN2_Pos)
- #define CTI_CTIINTACK_ETMEVTIN2_Acknowledge (1UL)
- #define CTI_CTIINTACK_ETMEVTIN1_Pos (5UL)
- #define CTI_CTIINTACK_ETMEVTIN1_Msk (0x1UL << CTI_CTIINTACK_ETMEVTIN1_Pos)
- #define CTI_CTIINTACK_ETMEVTIN1_Acknowledge (1UL)
- #define CTI_CTIINTACK_ETMEVTIN0_Pos (4UL)
- #define CTI_CTIINTACK_ETMEVTIN0_Msk (0x1UL << CTI_CTIINTACK_ETMEVTIN0_Pos)
- #define CTI_CTIINTACK_ETMEVTIN0_Acknowledge (1UL)
- #define CTI_CTIINTACK_UNUSED1_Pos (3UL)
- #define CTI_CTIINTACK_UNUSED1_Msk (0x1UL << CTI_CTIINTACK_UNUSED1_Pos)
- #define CTI_CTIINTACK_UNUSED1_Acknowledge (1UL)
- #define CTI_CTIINTACK_UNUSED0_Pos (2UL)
- #define CTI_CTIINTACK_UNUSED0_Msk (0x1UL << CTI_CTIINTACK_UNUSED0_Pos)
- #define CTI_CTIINTACK_UNUSED0_Acknowledge (1UL)
- #define CTI_CTIINTACK_CPURESTART_Pos (1UL)
- #define CTI_CTIINTACK_CPURESTART_Msk (0x1UL << CTI_CTIINTACK_CPURESTART_Pos)
- #define CTI_CTIINTACK_CPURESTART_Acknowledge (1UL)
- #define CTI_CTIINTACK_DEBUGREQ_Pos (0UL)
- #define CTI_CTIINTACK_DEBUGREQ_Msk (0x1UL << CTI_CTIINTACK_DEBUGREQ_Pos)
- #define CTI_CTIINTACK_DEBUGREQ_Acknowledge (1UL)
- #define CTI_CTIAPPSET_APPSET_3_Pos (3UL)
- #define CTI_CTIAPPSET_APPSET_3_Msk (0x1UL << CTI_CTIAPPSET_APPSET_3_Pos)
- #define CTI_CTIAPPSET_APPSET_3_Inactive (0UL)
- #define CTI_CTIAPPSET_APPSET_3_Active (1UL)
- #define CTI_CTIAPPSET_APPSET_3_Activate (1UL)
- #define CTI_CTIAPPSET_APPSET_2_Pos (2UL)
- #define CTI_CTIAPPSET_APPSET_2_Msk (0x1UL << CTI_CTIAPPSET_APPSET_2_Pos)
- #define CTI_CTIAPPSET_APPSET_2_Inactive (0UL)
- #define CTI_CTIAPPSET_APPSET_2_Active (1UL)
- #define CTI_CTIAPPSET_APPSET_2_Activate (1UL)
- #define CTI_CTIAPPSET_APPSET_1_Pos (1UL)
- #define CTI_CTIAPPSET_APPSET_1_Msk (0x1UL << CTI_CTIAPPSET_APPSET_1_Pos)
- #define CTI_CTIAPPSET_APPSET_1_Inactive (0UL)
- #define CTI_CTIAPPSET_APPSET_1_Active (1UL)
- #define CTI_CTIAPPSET_APPSET_1_Activate (1UL)
- #define CTI_CTIAPPSET_APPSET_0_Pos (0UL)
- #define CTI_CTIAPPSET_APPSET_0_Msk (0x1UL << CTI_CTIAPPSET_APPSET_0_Pos)
- #define CTI_CTIAPPSET_APPSET_0_Inactive (0UL)
- #define CTI_CTIAPPSET_APPSET_0_Active (1UL)
- #define CTI_CTIAPPSET_APPSET_0_Activate (1UL)
- #define CTI_CTIAPPCLEAR_APPCLEAR_3_Pos (3UL)
- #define CTI_CTIAPPCLEAR_APPCLEAR_3_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_3_Pos)
- #define CTI_CTIAPPCLEAR_APPCLEAR_3_Clear (1UL)
- #define CTI_CTIAPPCLEAR_APPCLEAR_2_Pos (2UL)
- #define CTI_CTIAPPCLEAR_APPCLEAR_2_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_2_Pos)
- #define CTI_CTIAPPCLEAR_APPCLEAR_2_Clear (1UL)
- #define CTI_CTIAPPCLEAR_APPCLEAR_1_Pos (1UL)
- #define CTI_CTIAPPCLEAR_APPCLEAR_1_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_1_Pos)
- #define CTI_CTIAPPCLEAR_APPCLEAR_1_Clear (1UL)
- #define CTI_CTIAPPCLEAR_APPCLEAR_0_Pos (0UL)
- #define CTI_CTIAPPCLEAR_APPCLEAR_0_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_0_Pos)
- #define CTI_CTIAPPCLEAR_APPCLEAR_0_Clear (1UL)
- #define CTI_CTIAPPPULSE_APPULSE_3_Pos (3UL)
- #define CTI_CTIAPPPULSE_APPULSE_3_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_3_Pos)
- #define CTI_CTIAPPPULSE_APPULSE_3_Generate (1UL)
- #define CTI_CTIAPPPULSE_APPULSE_2_Pos (2UL)
- #define CTI_CTIAPPPULSE_APPULSE_2_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_2_Pos)
- #define CTI_CTIAPPPULSE_APPULSE_2_Generate (1UL)
- #define CTI_CTIAPPPULSE_APPULSE_1_Pos (1UL)
- #define CTI_CTIAPPPULSE_APPULSE_1_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_1_Pos)
- #define CTI_CTIAPPPULSE_APPULSE_1_Generate (1UL)
- #define CTI_CTIAPPPULSE_APPULSE_0_Pos (0UL)
- #define CTI_CTIAPPPULSE_APPULSE_0_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_0_Pos)
- #define CTI_CTIAPPPULSE_APPULSE_0_Generate (1UL)
- #define CTI_CTIINEN_TRIGINEN_3_Pos (3UL)
- #define CTI_CTIINEN_TRIGINEN_3_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_3_Pos)
- #define CTI_CTIINEN_TRIGINEN_3_Disabled (0UL)
- #define CTI_CTIINEN_TRIGINEN_3_Enabled (1UL)
- #define CTI_CTIINEN_TRIGINEN_2_Pos (2UL)
- #define CTI_CTIINEN_TRIGINEN_2_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_2_Pos)
- #define CTI_CTIINEN_TRIGINEN_2_Disabled (0UL)
- #define CTI_CTIINEN_TRIGINEN_2_Enabled (1UL)
- #define CTI_CTIINEN_TRIGINEN_1_Pos (1UL)
- #define CTI_CTIINEN_TRIGINEN_1_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_1_Pos)
- #define CTI_CTIINEN_TRIGINEN_1_Disabled (0UL)
- #define CTI_CTIINEN_TRIGINEN_1_Enabled (1UL)
- #define CTI_CTIINEN_TRIGINEN_0_Pos (0UL)
- #define CTI_CTIINEN_TRIGINEN_0_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_0_Pos)
- #define CTI_CTIINEN_TRIGINEN_0_Disabled (0UL)
- #define CTI_CTIINEN_TRIGINEN_0_Enabled (1UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_3_Pos (3UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_3_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_3_Pos)
- #define CTI_CTIOUTEN_TRIGOUTEN_3_Disabled (0UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_3_Enabled (1UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_2_Pos (2UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_2_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_2_Pos)
- #define CTI_CTIOUTEN_TRIGOUTEN_2_Disabled (0UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_2_Enabled (1UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_1_Pos (1UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_1_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_1_Pos)
- #define CTI_CTIOUTEN_TRIGOUTEN_1_Disabled (0UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_1_Enabled (1UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_0_Pos (0UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_0_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_0_Pos)
- #define CTI_CTIOUTEN_TRIGOUTEN_0_Disabled (0UL)
- #define CTI_CTIOUTEN_TRIGOUTEN_0_Enabled (1UL)
- #define CTI_CTITRIGINSTATUS_UNUSED1_Pos (7UL)
- #define CTI_CTITRIGINSTATUS_UNUSED1_Msk (0x1UL << CTI_CTITRIGINSTATUS_UNUSED1_Pos)
- #define CTI_CTITRIGINSTATUS_UNUSED1_Inactive (0UL)
- #define CTI_CTITRIGINSTATUS_UNUSED1_Active (1UL)
- #define CTI_CTITRIGINSTATUS_UNUSED0_Pos (6UL)
- #define CTI_CTITRIGINSTATUS_UNUSED0_Msk (0x1UL << CTI_CTITRIGINSTATUS_UNUSED0_Pos)
- #define CTI_CTITRIGINSTATUS_UNUSED0_Inactive (0UL)
- #define CTI_CTITRIGINSTATUS_UNUSED0_Active (1UL)
- #define CTI_CTITRIGINSTATUS_ETMEVTOUT1_Pos (5UL)
- #define CTI_CTITRIGINSTATUS_ETMEVTOUT1_Msk (0x1UL << CTI_CTITRIGINSTATUS_ETMEVTOUT1_Pos)
- #define CTI_CTITRIGINSTATUS_ETMEVTOUT1_Inactive (0UL)
- #define CTI_CTITRIGINSTATUS_ETMEVTOUT1_Active (1UL)
- #define CTI_CTITRIGINSTATUS_ETMEVTOUT0_Pos (4UL)
- #define CTI_CTITRIGINSTATUS_ETMEVTOUT0_Msk (0x1UL << CTI_CTITRIGINSTATUS_ETMEVTOUT0_Pos)
- #define CTI_CTITRIGINSTATUS_ETMEVTOUT0_Inactive (0UL)
- #define CTI_CTITRIGINSTATUS_ETMEVTOUT0_Active (1UL)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Pos (3UL)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Msk (0x1UL << CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Pos)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Inactive (0UL)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Active (1UL)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Pos (2UL)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Msk (0x1UL << CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Pos)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Inactive (0UL)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Active (1UL)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Pos (1UL)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Msk (0x1UL << CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Pos)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Inactive (0UL)
- #define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Active (1UL)
- #define CTI_CTITRIGINSTATUS_CPUHALTED_Pos (0UL)
- #define CTI_CTITRIGINSTATUS_CPUHALTED_Msk (0x1UL << CTI_CTITRIGINSTATUS_CPUHALTED_Pos)
- #define CTI_CTITRIGINSTATUS_CPUHALTED_Inactive (0UL)
- #define CTI_CTITRIGINSTATUS_CPUHALTED_Active (1UL)
- #define CTI_CTITRIGOUTSTATUS_ETMEVTIN3_Pos (7UL)
- #define CTI_CTITRIGOUTSTATUS_ETMEVTIN3_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_ETMEVTIN3_Pos)
- #define CTI_CTITRIGOUTSTATUS_ETMEVTIN3_Inactive (0UL)
- #define CTI_CTITRIGOUTSTATUS_ETMEVTIN3_Active (1UL)
- #define CTI_CTITRIGOUTSTATUS_ETMEVTIN2_Pos (6UL)
- #define CTI_CTITRIGOUTSTATUS_ETMEVTIN2_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_ETMEVTIN2_Pos)
- #define CTI_CTITRIGOUTSTATUS_ETMEVTIN2_Inactive (0UL)
- #define CTI_CTITRIGOUTSTATUS_ETMEVTIN2_Active (1UL)
- #define CTI_CTITRIGOUTSTATUS_ETMEVTIN1_Pos (5UL)
- #define CTI_CTITRIGOUTSTATUS_ETMEVTIN1_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_ETMEVTIN1_Pos)
- #define CTI_CTITRIGOUTSTATUS_ETMEVTIN1_Inactive (0UL)
- #define CTI_CTITRIGOUTSTATUS_ETMEVTIN1_Active (1UL)
- #define CTI_CTITRIGOUTSTATUS_ETMEVTIN0_Pos (4UL)
- #define CTI_CTITRIGOUTSTATUS_ETMEVTIN0_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_ETMEVTIN0_Pos)
- #define CTI_CTITRIGOUTSTATUS_ETMEVTIN0_Inactive (0UL)
- #define CTI_CTITRIGOUTSTATUS_ETMEVTIN0_Active (1UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED1_Pos (3UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED1_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED1_Pos)
- #define CTI_CTITRIGOUTSTATUS_UNUSED1_Inactive (0UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED1_Active (1UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED0_Pos (2UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED0_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED0_Pos)
- #define CTI_CTITRIGOUTSTATUS_UNUSED0_Inactive (0UL)
- #define CTI_CTITRIGOUTSTATUS_UNUSED0_Active (1UL)
- #define CTI_CTITRIGOUTSTATUS_CPURESTART_Pos (1UL)
- #define CTI_CTITRIGOUTSTATUS_CPURESTART_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_CPURESTART_Pos)
- #define CTI_CTITRIGOUTSTATUS_CPURESTART_Inactive (0UL)
- #define CTI_CTITRIGOUTSTATUS_CPURESTART_Active (1UL)
- #define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Pos (0UL)
- #define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_DEBUGREQ_Pos)
- #define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Inactive (0UL)
- #define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Active (1UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Pos (3UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_3_Pos)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Inactive (0UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Active (1UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Pos (2UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_2_Pos)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Inactive (0UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Active (1UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Pos (1UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_1_Pos)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Inactive (0UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Active (1UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Pos (0UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_0_Pos)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Inactive (0UL)
- #define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Active (1UL)
- #define CTI_CTIGATE_CTIGATEEN_3_Pos (3UL)
- #define CTI_CTIGATE_CTIGATEEN_3_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_3_Pos)
- #define CTI_CTIGATE_CTIGATEEN_3_Disabled (0UL)
- #define CTI_CTIGATE_CTIGATEEN_3_Enabled (1UL)
- #define CTI_CTIGATE_CTIGATEEN_2_Pos (2UL)
- #define CTI_CTIGATE_CTIGATEEN_2_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_2_Pos)
- #define CTI_CTIGATE_CTIGATEEN_2_Disabled (0UL)
- #define CTI_CTIGATE_CTIGATEEN_2_Enabled (1UL)
- #define CTI_CTIGATE_CTIGATEEN_1_Pos (1UL)
- #define CTI_CTIGATE_CTIGATEEN_1_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_1_Pos)
- #define CTI_CTIGATE_CTIGATEEN_1_Disabled (0UL)
- #define CTI_CTIGATE_CTIGATEEN_1_Enabled (1UL)
- #define CTI_CTIGATE_CTIGATEEN_0_Pos (0UL)
- #define CTI_CTIGATE_CTIGATEEN_0_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_0_Pos)
- #define CTI_CTIGATE_CTIGATEEN_0_Disabled (0UL)
- #define CTI_CTIGATE_CTIGATEEN_0_Enabled (1UL)
- #define CTI_DEVARCH_Architecture_Pos (0UL)
- #define CTI_DEVARCH_Architecture_Msk (0x1UL << CTI_DEVARCH_Architecture_Pos)
- #define CTI_DEVID_NUMCH_Pos (16UL)
- #define CTI_DEVID_NUMCH_Msk (0xFUL << CTI_DEVID_NUMCH_Pos)
- #define CTI_DEVID_NUMTRIG_Pos (8UL)
- #define CTI_DEVID_NUMTRIG_Msk (0xFFUL << CTI_DEVID_NUMTRIG_Pos)
- #define CTI_DEVID_EXTMUXNUM_Pos (0UL)
- #define CTI_DEVID_EXTMUXNUM_Msk (0x1FUL << CTI_DEVID_EXTMUXNUM_Pos)
- #define CTI_DEVTYPE_SUB_Pos (4UL)
- #define CTI_DEVTYPE_SUB_Msk (0xFUL << CTI_DEVTYPE_SUB_Pos)
- #define CTI_DEVTYPE_SUB_Crosstrigger (0b0001UL)
- #define CTI_DEVTYPE_MAJOR_Pos (0UL)
- #define CTI_DEVTYPE_MAJOR_Msk (0xFUL << CTI_DEVTYPE_MAJOR_Pos)
- #define CTI_DEVTYPE_MAJOR_Controller (0b0100UL)
- #define CTI_PIDR4_SIZE_Pos (4UL)
- #define CTI_PIDR4_SIZE_Msk (0xFUL << CTI_PIDR4_SIZE_Pos)
- #define CTI_PIDR4_DES_2_Pos (0UL)
- #define CTI_PIDR4_DES_2_Msk (0xFUL << CTI_PIDR4_DES_2_Pos)
- #define CTI_PIDR4_DES_2_Code (0b0100UL)
- #define CTI_PIDR0_PART_0_Pos (0UL)
- #define CTI_PIDR0_PART_0_Msk (0xFFUL << CTI_PIDR0_PART_0_Pos)
- #define CTI_PIDR0_PART_0_PartnumberL (0x21UL)
- #define CTI_PIDR1_DES_0_Pos (4UL)
- #define CTI_PIDR1_DES_0_Msk (0xFUL << CTI_PIDR1_DES_0_Pos)
- #define CTI_PIDR1_DES_0_Arm (0b1011UL)
- #define CTI_PIDR1_PART_1_Pos (0UL)
- #define CTI_PIDR1_PART_1_Msk (0xFUL << CTI_PIDR1_PART_1_Pos)
- #define CTI_PIDR1_PART_1_PartnumberH (0b1101UL)
- #define CTI_PIDR2_REVISION_Pos (4UL)
- #define CTI_PIDR2_REVISION_Msk (0xFUL << CTI_PIDR2_REVISION_Pos)
- #define CTI_PIDR2_REVISION_Rev0p0 (0b0000UL)
- #define CTI_PIDR2_JEDEC_Pos (3UL)
- #define CTI_PIDR2_JEDEC_Msk (0x1UL << CTI_PIDR2_JEDEC_Pos)
- #define CTI_PIDR2_DES_1_Pos (0UL)
- #define CTI_PIDR2_DES_1_Msk (0x7UL << CTI_PIDR2_DES_1_Pos)
- #define CTI_PIDR2_DES_1_Arm (0b011UL)
- #define CTI_PIDR3_REVAND_Pos (4UL)
- #define CTI_PIDR3_REVAND_Msk (0xFUL << CTI_PIDR3_REVAND_Pos)
- #define CTI_PIDR3_REVAND_NoErrata (0b000UL)
- #define CTI_PIDR3_CMOD_Pos (0UL)
- #define CTI_PIDR3_CMOD_Msk (0xFUL << CTI_PIDR3_CMOD_Pos)
- #define CTI_PIDR3_CMOD_Unmodified (0b000UL)
- #define CTI_CIDR0_PRMBL_0_Pos (0UL)
- #define CTI_CIDR0_PRMBL_0_Msk (0xFFUL << CTI_CIDR0_PRMBL_0_Pos)
- #define CTI_CIDR0_PRMBL_0_Value (0x0DUL)
- #define CTI_CIDR1_CLASS_Pos (4UL)
- #define CTI_CIDR1_CLASS_Msk (0xFUL << CTI_CIDR1_CLASS_Pos)
- #define CTI_CIDR1_CLASS_Coresight (0b1001UL)
- #define CTI_CIDR1_PRMBL_1_Pos (0UL)
- #define CTI_CIDR1_PRMBL_1_Msk (0xFUL << CTI_CIDR1_PRMBL_1_Pos)
- #define CTI_CIDR1_PRMBL_1_Value (0b0000UL)
- #define CTI_CIDR2_PRMBL_2_Pos (0UL)
- #define CTI_CIDR2_PRMBL_2_Msk (0xFFUL << CTI_CIDR2_PRMBL_2_Pos)
- #define CTI_CIDR2_PRMBL_2_Value (0x05UL)
- #define CTI_CIDR3_PRMBL_3_Pos (0UL)
- #define CTI_CIDR3_PRMBL_3_Msk (0xFFUL << CTI_CIDR3_PRMBL_3_Pos)
- #define CTI_CIDR3_PRMBL_3_Value (0xB1UL)
- #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos (0UL)
- #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos)
- #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos (0UL)
- #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos)
- #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_NoDataPending (0UL)
- #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (1UL)
- #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos (0UL)
- #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos)
- #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos (0UL)
- #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos)
- #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_NoDataPending (0UL)
- #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (1UL)
- #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos (0UL)
- #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos)
- #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked (0UL)
- #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked (1UL)
- #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos (0UL)
- #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos)
- #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Pos (0UL)
- #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_APPROTECT_LOCK_LOCK_Pos)
- #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Unlocked (0UL)
- #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Locked (1UL)
- #define CTRLAPPERI_APPROTECT_DISABLE_KEY_Pos (0UL)
- #define CTRLAPPERI_APPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_APPROTECT_DISABLE_KEY_Pos)
- #define CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Pos (0UL)
- #define CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Pos)
- #define CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Unlocked (0UL)
- #define CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Locked (1UL)
- #define CTRLAPPERI_SECUREAPPROTECT_DISABLE_KEY_Pos (0UL)
- #define CTRLAPPERI_SECUREAPPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_SECUREAPPROTECT_DISABLE_KEY_Pos)
- #define CTRLAPPERI_STATUS_DBGIFACEMODE_Pos (2UL)
- #define CTRLAPPERI_STATUS_DBGIFACEMODE_Msk (0x1UL << CTRLAPPERI_STATUS_DBGIFACEMODE_Pos)
- #define CTRLAPPERI_STATUS_DBGIFACEMODE_Disabled (0UL)
- #define CTRLAPPERI_STATUS_DBGIFACEMODE_Enabled (1UL)
- #define CTRLAPPERI_STATUS_SECUREAPPROTECT_Pos (1UL)
- #define CTRLAPPERI_STATUS_SECUREAPPROTECT_Msk (0x1UL << CTRLAPPERI_STATUS_SECUREAPPROTECT_Pos)
- #define CTRLAPPERI_STATUS_SECUREAPPROTECT_Disabled (0UL)
- #define CTRLAPPERI_STATUS_SECUREAPPROTECT_Enabled (1UL)
- #define CTRLAPPERI_STATUS_APPROTECT_Pos (0UL)
- #define CTRLAPPERI_STATUS_APPROTECT_Msk (0x1UL << CTRLAPPERI_STATUS_APPROTECT_Pos)
- #define CTRLAPPERI_STATUS_APPROTECT_Disabled (0UL)
- #define CTRLAPPERI_STATUS_APPROTECT_Enabled (1UL)
- #define DCNF_CPUID_CPUID_Pos (0UL)
- #define DCNF_CPUID_CPUID_Msk (0xFFUL << DCNF_CPUID_CPUID_Pos)
- #define DCNF_EXTPERI_PROTECT_SLAVE0_Pos (0UL)
- #define DCNF_EXTPERI_PROTECT_SLAVE0_Msk (0x1UL << DCNF_EXTPERI_PROTECT_SLAVE0_Pos)
- #define DCNF_EXTPERI_PROTECT_SLAVE0_Allowed (0UL)
- #define DCNF_EXTPERI_PROTECT_SLAVE0_Blocked (1UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE7_Pos (7UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE7_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE7_Pos)
- #define DCNF_EXTRAM_PROTECT_SLAVE7_Allowed (0UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE7_Blocked (1UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE6_Pos (6UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE6_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE6_Pos)
- #define DCNF_EXTRAM_PROTECT_SLAVE6_Allowed (0UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE6_Blocked (1UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE5_Pos (5UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE5_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE5_Pos)
- #define DCNF_EXTRAM_PROTECT_SLAVE5_Allowed (0UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE5_Blocked (1UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE4_Pos (4UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE4_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE4_Pos)
- #define DCNF_EXTRAM_PROTECT_SLAVE4_Allowed (0UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE4_Blocked (1UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE3_Pos (3UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE3_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE3_Pos)
- #define DCNF_EXTRAM_PROTECT_SLAVE3_Allowed (0UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE3_Blocked (1UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE2_Pos (2UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE2_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE2_Pos)
- #define DCNF_EXTRAM_PROTECT_SLAVE2_Allowed (0UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE2_Blocked (1UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE1_Pos (1UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE1_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE1_Pos)
- #define DCNF_EXTRAM_PROTECT_SLAVE1_Allowed (0UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE1_Blocked (1UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE0_Pos (0UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE0_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE0_Pos)
- #define DCNF_EXTRAM_PROTECT_SLAVE0_Allowed (0UL)
- #define DCNF_EXTRAM_PROTECT_SLAVE0_Blocked (1UL)
- #define DCNF_EXTCODE_PROTECT_SLAVE0_Pos (0UL)
- #define DCNF_EXTCODE_PROTECT_SLAVE0_Msk (0x1UL << DCNF_EXTCODE_PROTECT_SLAVE0_Pos)
- #define DCNF_EXTCODE_PROTECT_SLAVE0_Allowed (0UL)
- #define DCNF_EXTCODE_PROTECT_SLAVE0_Blocked (1UL)
- #define DPPIC_TASKS_CHG_EN_EN_Pos (0UL)
- #define DPPIC_TASKS_CHG_EN_EN_Msk (0x1UL << DPPIC_TASKS_CHG_EN_EN_Pos)
- #define DPPIC_TASKS_CHG_EN_EN_Trigger (1UL)
- #define DPPIC_TASKS_CHG_DIS_DIS_Pos (0UL)
- #define DPPIC_TASKS_CHG_DIS_DIS_Msk (0x1UL << DPPIC_TASKS_CHG_DIS_DIS_Pos)
- #define DPPIC_TASKS_CHG_DIS_DIS_Trigger (1UL)
- #define DPPIC_SUBSCRIBE_CHG_EN_EN_Pos (31UL)
- #define DPPIC_SUBSCRIBE_CHG_EN_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_EN_EN_Pos)
- #define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0UL)
- #define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (1UL)
- #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL)
- #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos)
- #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos (31UL)
- #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos)
- #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0UL)
- #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (1UL)
- #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL)
- #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos)
- #define DPPIC_CHEN_CH31_Pos (31UL)
- #define DPPIC_CHEN_CH31_Msk (0x1UL << DPPIC_CHEN_CH31_Pos)
- #define DPPIC_CHEN_CH31_Disabled (0UL)
- #define DPPIC_CHEN_CH31_Enabled (1UL)
- #define DPPIC_CHEN_CH30_Pos (30UL)
- #define DPPIC_CHEN_CH30_Msk (0x1UL << DPPIC_CHEN_CH30_Pos)
- #define DPPIC_CHEN_CH30_Disabled (0UL)
- #define DPPIC_CHEN_CH30_Enabled (1UL)
- #define DPPIC_CHEN_CH29_Pos (29UL)
- #define DPPIC_CHEN_CH29_Msk (0x1UL << DPPIC_CHEN_CH29_Pos)
- #define DPPIC_CHEN_CH29_Disabled (0UL)
- #define DPPIC_CHEN_CH29_Enabled (1UL)
- #define DPPIC_CHEN_CH28_Pos (28UL)
- #define DPPIC_CHEN_CH28_Msk (0x1UL << DPPIC_CHEN_CH28_Pos)
- #define DPPIC_CHEN_CH28_Disabled (0UL)
- #define DPPIC_CHEN_CH28_Enabled (1UL)
- #define DPPIC_CHEN_CH27_Pos (27UL)
- #define DPPIC_CHEN_CH27_Msk (0x1UL << DPPIC_CHEN_CH27_Pos)
- #define DPPIC_CHEN_CH27_Disabled (0UL)
- #define DPPIC_CHEN_CH27_Enabled (1UL)
- #define DPPIC_CHEN_CH26_Pos (26UL)
- #define DPPIC_CHEN_CH26_Msk (0x1UL << DPPIC_CHEN_CH26_Pos)
- #define DPPIC_CHEN_CH26_Disabled (0UL)
- #define DPPIC_CHEN_CH26_Enabled (1UL)
- #define DPPIC_CHEN_CH25_Pos (25UL)
- #define DPPIC_CHEN_CH25_Msk (0x1UL << DPPIC_CHEN_CH25_Pos)
- #define DPPIC_CHEN_CH25_Disabled (0UL)
- #define DPPIC_CHEN_CH25_Enabled (1UL)
- #define DPPIC_CHEN_CH24_Pos (24UL)
- #define DPPIC_CHEN_CH24_Msk (0x1UL << DPPIC_CHEN_CH24_Pos)
- #define DPPIC_CHEN_CH24_Disabled (0UL)
- #define DPPIC_CHEN_CH24_Enabled (1UL)
- #define DPPIC_CHEN_CH23_Pos (23UL)
- #define DPPIC_CHEN_CH23_Msk (0x1UL << DPPIC_CHEN_CH23_Pos)
- #define DPPIC_CHEN_CH23_Disabled (0UL)
- #define DPPIC_CHEN_CH23_Enabled (1UL)
- #define DPPIC_CHEN_CH22_Pos (22UL)
- #define DPPIC_CHEN_CH22_Msk (0x1UL << DPPIC_CHEN_CH22_Pos)
- #define DPPIC_CHEN_CH22_Disabled (0UL)
- #define DPPIC_CHEN_CH22_Enabled (1UL)
- #define DPPIC_CHEN_CH21_Pos (21UL)
- #define DPPIC_CHEN_CH21_Msk (0x1UL << DPPIC_CHEN_CH21_Pos)
- #define DPPIC_CHEN_CH21_Disabled (0UL)
- #define DPPIC_CHEN_CH21_Enabled (1UL)
- #define DPPIC_CHEN_CH20_Pos (20UL)
- #define DPPIC_CHEN_CH20_Msk (0x1UL << DPPIC_CHEN_CH20_Pos)
- #define DPPIC_CHEN_CH20_Disabled (0UL)
- #define DPPIC_CHEN_CH20_Enabled (1UL)
- #define DPPIC_CHEN_CH19_Pos (19UL)
- #define DPPIC_CHEN_CH19_Msk (0x1UL << DPPIC_CHEN_CH19_Pos)
- #define DPPIC_CHEN_CH19_Disabled (0UL)
- #define DPPIC_CHEN_CH19_Enabled (1UL)
- #define DPPIC_CHEN_CH18_Pos (18UL)
- #define DPPIC_CHEN_CH18_Msk (0x1UL << DPPIC_CHEN_CH18_Pos)
- #define DPPIC_CHEN_CH18_Disabled (0UL)
- #define DPPIC_CHEN_CH18_Enabled (1UL)
- #define DPPIC_CHEN_CH17_Pos (17UL)
- #define DPPIC_CHEN_CH17_Msk (0x1UL << DPPIC_CHEN_CH17_Pos)
- #define DPPIC_CHEN_CH17_Disabled (0UL)
- #define DPPIC_CHEN_CH17_Enabled (1UL)
- #define DPPIC_CHEN_CH16_Pos (16UL)
- #define DPPIC_CHEN_CH16_Msk (0x1UL << DPPIC_CHEN_CH16_Pos)
- #define DPPIC_CHEN_CH16_Disabled (0UL)
- #define DPPIC_CHEN_CH16_Enabled (1UL)
- #define DPPIC_CHEN_CH15_Pos (15UL)
- #define DPPIC_CHEN_CH15_Msk (0x1UL << DPPIC_CHEN_CH15_Pos)
- #define DPPIC_CHEN_CH15_Disabled (0UL)
- #define DPPIC_CHEN_CH15_Enabled (1UL)
- #define DPPIC_CHEN_CH14_Pos (14UL)
- #define DPPIC_CHEN_CH14_Msk (0x1UL << DPPIC_CHEN_CH14_Pos)
- #define DPPIC_CHEN_CH14_Disabled (0UL)
- #define DPPIC_CHEN_CH14_Enabled (1UL)
- #define DPPIC_CHEN_CH13_Pos (13UL)
- #define DPPIC_CHEN_CH13_Msk (0x1UL << DPPIC_CHEN_CH13_Pos)
- #define DPPIC_CHEN_CH13_Disabled (0UL)
- #define DPPIC_CHEN_CH13_Enabled (1UL)
- #define DPPIC_CHEN_CH12_Pos (12UL)
- #define DPPIC_CHEN_CH12_Msk (0x1UL << DPPIC_CHEN_CH12_Pos)
- #define DPPIC_CHEN_CH12_Disabled (0UL)
- #define DPPIC_CHEN_CH12_Enabled (1UL)
- #define DPPIC_CHEN_CH11_Pos (11UL)
- #define DPPIC_CHEN_CH11_Msk (0x1UL << DPPIC_CHEN_CH11_Pos)
- #define DPPIC_CHEN_CH11_Disabled (0UL)
- #define DPPIC_CHEN_CH11_Enabled (1UL)
- #define DPPIC_CHEN_CH10_Pos (10UL)
- #define DPPIC_CHEN_CH10_Msk (0x1UL << DPPIC_CHEN_CH10_Pos)
- #define DPPIC_CHEN_CH10_Disabled (0UL)
- #define DPPIC_CHEN_CH10_Enabled (1UL)
- #define DPPIC_CHEN_CH9_Pos (9UL)
- #define DPPIC_CHEN_CH9_Msk (0x1UL << DPPIC_CHEN_CH9_Pos)
- #define DPPIC_CHEN_CH9_Disabled (0UL)
- #define DPPIC_CHEN_CH9_Enabled (1UL)
- #define DPPIC_CHEN_CH8_Pos (8UL)
- #define DPPIC_CHEN_CH8_Msk (0x1UL << DPPIC_CHEN_CH8_Pos)
- #define DPPIC_CHEN_CH8_Disabled (0UL)
- #define DPPIC_CHEN_CH8_Enabled (1UL)
- #define DPPIC_CHEN_CH7_Pos (7UL)
- #define DPPIC_CHEN_CH7_Msk (0x1UL << DPPIC_CHEN_CH7_Pos)
- #define DPPIC_CHEN_CH7_Disabled (0UL)
- #define DPPIC_CHEN_CH7_Enabled (1UL)
- #define DPPIC_CHEN_CH6_Pos (6UL)
- #define DPPIC_CHEN_CH6_Msk (0x1UL << DPPIC_CHEN_CH6_Pos)
- #define DPPIC_CHEN_CH6_Disabled (0UL)
- #define DPPIC_CHEN_CH6_Enabled (1UL)
- #define DPPIC_CHEN_CH5_Pos (5UL)
- #define DPPIC_CHEN_CH5_Msk (0x1UL << DPPIC_CHEN_CH5_Pos)
- #define DPPIC_CHEN_CH5_Disabled (0UL)
- #define DPPIC_CHEN_CH5_Enabled (1UL)
- #define DPPIC_CHEN_CH4_Pos (4UL)
- #define DPPIC_CHEN_CH4_Msk (0x1UL << DPPIC_CHEN_CH4_Pos)
- #define DPPIC_CHEN_CH4_Disabled (0UL)
- #define DPPIC_CHEN_CH4_Enabled (1UL)
- #define DPPIC_CHEN_CH3_Pos (3UL)
- #define DPPIC_CHEN_CH3_Msk (0x1UL << DPPIC_CHEN_CH3_Pos)
- #define DPPIC_CHEN_CH3_Disabled (0UL)
- #define DPPIC_CHEN_CH3_Enabled (1UL)
- #define DPPIC_CHEN_CH2_Pos (2UL)
- #define DPPIC_CHEN_CH2_Msk (0x1UL << DPPIC_CHEN_CH2_Pos)
- #define DPPIC_CHEN_CH2_Disabled (0UL)
- #define DPPIC_CHEN_CH2_Enabled (1UL)
- #define DPPIC_CHEN_CH1_Pos (1UL)
- #define DPPIC_CHEN_CH1_Msk (0x1UL << DPPIC_CHEN_CH1_Pos)
- #define DPPIC_CHEN_CH1_Disabled (0UL)
- #define DPPIC_CHEN_CH1_Enabled (1UL)
- #define DPPIC_CHEN_CH0_Pos (0UL)
- #define DPPIC_CHEN_CH0_Msk (0x1UL << DPPIC_CHEN_CH0_Pos)
- #define DPPIC_CHEN_CH0_Disabled (0UL)
- #define DPPIC_CHEN_CH0_Enabled (1UL)
- #define DPPIC_CHENSET_CH31_Pos (31UL)
- #define DPPIC_CHENSET_CH31_Msk (0x1UL << DPPIC_CHENSET_CH31_Pos)
- #define DPPIC_CHENSET_CH31_Disabled (0UL)
- #define DPPIC_CHENSET_CH31_Enabled (1UL)
- #define DPPIC_CHENSET_CH31_Set (1UL)
- #define DPPIC_CHENSET_CH30_Pos (30UL)
- #define DPPIC_CHENSET_CH30_Msk (0x1UL << DPPIC_CHENSET_CH30_Pos)
- #define DPPIC_CHENSET_CH30_Disabled (0UL)
- #define DPPIC_CHENSET_CH30_Enabled (1UL)
- #define DPPIC_CHENSET_CH30_Set (1UL)
- #define DPPIC_CHENSET_CH29_Pos (29UL)
- #define DPPIC_CHENSET_CH29_Msk (0x1UL << DPPIC_CHENSET_CH29_Pos)
- #define DPPIC_CHENSET_CH29_Disabled (0UL)
- #define DPPIC_CHENSET_CH29_Enabled (1UL)
- #define DPPIC_CHENSET_CH29_Set (1UL)
- #define DPPIC_CHENSET_CH28_Pos (28UL)
- #define DPPIC_CHENSET_CH28_Msk (0x1UL << DPPIC_CHENSET_CH28_Pos)
- #define DPPIC_CHENSET_CH28_Disabled (0UL)
- #define DPPIC_CHENSET_CH28_Enabled (1UL)
- #define DPPIC_CHENSET_CH28_Set (1UL)
- #define DPPIC_CHENSET_CH27_Pos (27UL)
- #define DPPIC_CHENSET_CH27_Msk (0x1UL << DPPIC_CHENSET_CH27_Pos)
- #define DPPIC_CHENSET_CH27_Disabled (0UL)
- #define DPPIC_CHENSET_CH27_Enabled (1UL)
- #define DPPIC_CHENSET_CH27_Set (1UL)
- #define DPPIC_CHENSET_CH26_Pos (26UL)
- #define DPPIC_CHENSET_CH26_Msk (0x1UL << DPPIC_CHENSET_CH26_Pos)
- #define DPPIC_CHENSET_CH26_Disabled (0UL)
- #define DPPIC_CHENSET_CH26_Enabled (1UL)
- #define DPPIC_CHENSET_CH26_Set (1UL)
- #define DPPIC_CHENSET_CH25_Pos (25UL)
- #define DPPIC_CHENSET_CH25_Msk (0x1UL << DPPIC_CHENSET_CH25_Pos)
- #define DPPIC_CHENSET_CH25_Disabled (0UL)
- #define DPPIC_CHENSET_CH25_Enabled (1UL)
- #define DPPIC_CHENSET_CH25_Set (1UL)
- #define DPPIC_CHENSET_CH24_Pos (24UL)
- #define DPPIC_CHENSET_CH24_Msk (0x1UL << DPPIC_CHENSET_CH24_Pos)
- #define DPPIC_CHENSET_CH24_Disabled (0UL)
- #define DPPIC_CHENSET_CH24_Enabled (1UL)
- #define DPPIC_CHENSET_CH24_Set (1UL)
- #define DPPIC_CHENSET_CH23_Pos (23UL)
- #define DPPIC_CHENSET_CH23_Msk (0x1UL << DPPIC_CHENSET_CH23_Pos)
- #define DPPIC_CHENSET_CH23_Disabled (0UL)
- #define DPPIC_CHENSET_CH23_Enabled (1UL)
- #define DPPIC_CHENSET_CH23_Set (1UL)
- #define DPPIC_CHENSET_CH22_Pos (22UL)
- #define DPPIC_CHENSET_CH22_Msk (0x1UL << DPPIC_CHENSET_CH22_Pos)
- #define DPPIC_CHENSET_CH22_Disabled (0UL)
- #define DPPIC_CHENSET_CH22_Enabled (1UL)
- #define DPPIC_CHENSET_CH22_Set (1UL)
- #define DPPIC_CHENSET_CH21_Pos (21UL)
- #define DPPIC_CHENSET_CH21_Msk (0x1UL << DPPIC_CHENSET_CH21_Pos)
- #define DPPIC_CHENSET_CH21_Disabled (0UL)
- #define DPPIC_CHENSET_CH21_Enabled (1UL)
- #define DPPIC_CHENSET_CH21_Set (1UL)
- #define DPPIC_CHENSET_CH20_Pos (20UL)
- #define DPPIC_CHENSET_CH20_Msk (0x1UL << DPPIC_CHENSET_CH20_Pos)
- #define DPPIC_CHENSET_CH20_Disabled (0UL)
- #define DPPIC_CHENSET_CH20_Enabled (1UL)
- #define DPPIC_CHENSET_CH20_Set (1UL)
- #define DPPIC_CHENSET_CH19_Pos (19UL)
- #define DPPIC_CHENSET_CH19_Msk (0x1UL << DPPIC_CHENSET_CH19_Pos)
- #define DPPIC_CHENSET_CH19_Disabled (0UL)
- #define DPPIC_CHENSET_CH19_Enabled (1UL)
- #define DPPIC_CHENSET_CH19_Set (1UL)
- #define DPPIC_CHENSET_CH18_Pos (18UL)
- #define DPPIC_CHENSET_CH18_Msk (0x1UL << DPPIC_CHENSET_CH18_Pos)
- #define DPPIC_CHENSET_CH18_Disabled (0UL)
- #define DPPIC_CHENSET_CH18_Enabled (1UL)
- #define DPPIC_CHENSET_CH18_Set (1UL)
- #define DPPIC_CHENSET_CH17_Pos (17UL)
- #define DPPIC_CHENSET_CH17_Msk (0x1UL << DPPIC_CHENSET_CH17_Pos)
- #define DPPIC_CHENSET_CH17_Disabled (0UL)
- #define DPPIC_CHENSET_CH17_Enabled (1UL)
- #define DPPIC_CHENSET_CH17_Set (1UL)
- #define DPPIC_CHENSET_CH16_Pos (16UL)
- #define DPPIC_CHENSET_CH16_Msk (0x1UL << DPPIC_CHENSET_CH16_Pos)
- #define DPPIC_CHENSET_CH16_Disabled (0UL)
- #define DPPIC_CHENSET_CH16_Enabled (1UL)
- #define DPPIC_CHENSET_CH16_Set (1UL)
- #define DPPIC_CHENSET_CH15_Pos (15UL)
- #define DPPIC_CHENSET_CH15_Msk (0x1UL << DPPIC_CHENSET_CH15_Pos)
- #define DPPIC_CHENSET_CH15_Disabled (0UL)
- #define DPPIC_CHENSET_CH15_Enabled (1UL)
- #define DPPIC_CHENSET_CH15_Set (1UL)
- #define DPPIC_CHENSET_CH14_Pos (14UL)
- #define DPPIC_CHENSET_CH14_Msk (0x1UL << DPPIC_CHENSET_CH14_Pos)
- #define DPPIC_CHENSET_CH14_Disabled (0UL)
- #define DPPIC_CHENSET_CH14_Enabled (1UL)
- #define DPPIC_CHENSET_CH14_Set (1UL)
- #define DPPIC_CHENSET_CH13_Pos (13UL)
- #define DPPIC_CHENSET_CH13_Msk (0x1UL << DPPIC_CHENSET_CH13_Pos)
- #define DPPIC_CHENSET_CH13_Disabled (0UL)
- #define DPPIC_CHENSET_CH13_Enabled (1UL)
- #define DPPIC_CHENSET_CH13_Set (1UL)
- #define DPPIC_CHENSET_CH12_Pos (12UL)
- #define DPPIC_CHENSET_CH12_Msk (0x1UL << DPPIC_CHENSET_CH12_Pos)
- #define DPPIC_CHENSET_CH12_Disabled (0UL)
- #define DPPIC_CHENSET_CH12_Enabled (1UL)
- #define DPPIC_CHENSET_CH12_Set (1UL)
- #define DPPIC_CHENSET_CH11_Pos (11UL)
- #define DPPIC_CHENSET_CH11_Msk (0x1UL << DPPIC_CHENSET_CH11_Pos)
- #define DPPIC_CHENSET_CH11_Disabled (0UL)
- #define DPPIC_CHENSET_CH11_Enabled (1UL)
- #define DPPIC_CHENSET_CH11_Set (1UL)
- #define DPPIC_CHENSET_CH10_Pos (10UL)
- #define DPPIC_CHENSET_CH10_Msk (0x1UL << DPPIC_CHENSET_CH10_Pos)
- #define DPPIC_CHENSET_CH10_Disabled (0UL)
- #define DPPIC_CHENSET_CH10_Enabled (1UL)
- #define DPPIC_CHENSET_CH10_Set (1UL)
- #define DPPIC_CHENSET_CH9_Pos (9UL)
- #define DPPIC_CHENSET_CH9_Msk (0x1UL << DPPIC_CHENSET_CH9_Pos)
- #define DPPIC_CHENSET_CH9_Disabled (0UL)
- #define DPPIC_CHENSET_CH9_Enabled (1UL)
- #define DPPIC_CHENSET_CH9_Set (1UL)
- #define DPPIC_CHENSET_CH8_Pos (8UL)
- #define DPPIC_CHENSET_CH8_Msk (0x1UL << DPPIC_CHENSET_CH8_Pos)
- #define DPPIC_CHENSET_CH8_Disabled (0UL)
- #define DPPIC_CHENSET_CH8_Enabled (1UL)
- #define DPPIC_CHENSET_CH8_Set (1UL)
- #define DPPIC_CHENSET_CH7_Pos (7UL)
- #define DPPIC_CHENSET_CH7_Msk (0x1UL << DPPIC_CHENSET_CH7_Pos)
- #define DPPIC_CHENSET_CH7_Disabled (0UL)
- #define DPPIC_CHENSET_CH7_Enabled (1UL)
- #define DPPIC_CHENSET_CH7_Set (1UL)
- #define DPPIC_CHENSET_CH6_Pos (6UL)
- #define DPPIC_CHENSET_CH6_Msk (0x1UL << DPPIC_CHENSET_CH6_Pos)
- #define DPPIC_CHENSET_CH6_Disabled (0UL)
- #define DPPIC_CHENSET_CH6_Enabled (1UL)
- #define DPPIC_CHENSET_CH6_Set (1UL)
- #define DPPIC_CHENSET_CH5_Pos (5UL)
- #define DPPIC_CHENSET_CH5_Msk (0x1UL << DPPIC_CHENSET_CH5_Pos)
- #define DPPIC_CHENSET_CH5_Disabled (0UL)
- #define DPPIC_CHENSET_CH5_Enabled (1UL)
- #define DPPIC_CHENSET_CH5_Set (1UL)
- #define DPPIC_CHENSET_CH4_Pos (4UL)
- #define DPPIC_CHENSET_CH4_Msk (0x1UL << DPPIC_CHENSET_CH4_Pos)
- #define DPPIC_CHENSET_CH4_Disabled (0UL)
- #define DPPIC_CHENSET_CH4_Enabled (1UL)
- #define DPPIC_CHENSET_CH4_Set (1UL)
- #define DPPIC_CHENSET_CH3_Pos (3UL)
- #define DPPIC_CHENSET_CH3_Msk (0x1UL << DPPIC_CHENSET_CH3_Pos)
- #define DPPIC_CHENSET_CH3_Disabled (0UL)
- #define DPPIC_CHENSET_CH3_Enabled (1UL)
- #define DPPIC_CHENSET_CH3_Set (1UL)
- #define DPPIC_CHENSET_CH2_Pos (2UL)
- #define DPPIC_CHENSET_CH2_Msk (0x1UL << DPPIC_CHENSET_CH2_Pos)
- #define DPPIC_CHENSET_CH2_Disabled (0UL)
- #define DPPIC_CHENSET_CH2_Enabled (1UL)
- #define DPPIC_CHENSET_CH2_Set (1UL)
- #define DPPIC_CHENSET_CH1_Pos (1UL)
- #define DPPIC_CHENSET_CH1_Msk (0x1UL << DPPIC_CHENSET_CH1_Pos)
- #define DPPIC_CHENSET_CH1_Disabled (0UL)
- #define DPPIC_CHENSET_CH1_Enabled (1UL)
- #define DPPIC_CHENSET_CH1_Set (1UL)
- #define DPPIC_CHENSET_CH0_Pos (0UL)
- #define DPPIC_CHENSET_CH0_Msk (0x1UL << DPPIC_CHENSET_CH0_Pos)
- #define DPPIC_CHENSET_CH0_Disabled (0UL)
- #define DPPIC_CHENSET_CH0_Enabled (1UL)
- #define DPPIC_CHENSET_CH0_Set (1UL)
- #define DPPIC_CHENCLR_CH31_Pos (31UL)
- #define DPPIC_CHENCLR_CH31_Msk (0x1UL << DPPIC_CHENCLR_CH31_Pos)
- #define DPPIC_CHENCLR_CH31_Disabled (0UL)
- #define DPPIC_CHENCLR_CH31_Enabled (1UL)
- #define DPPIC_CHENCLR_CH31_Clear (1UL)
- #define DPPIC_CHENCLR_CH30_Pos (30UL)
- #define DPPIC_CHENCLR_CH30_Msk (0x1UL << DPPIC_CHENCLR_CH30_Pos)
- #define DPPIC_CHENCLR_CH30_Disabled (0UL)
- #define DPPIC_CHENCLR_CH30_Enabled (1UL)
- #define DPPIC_CHENCLR_CH30_Clear (1UL)
- #define DPPIC_CHENCLR_CH29_Pos (29UL)
- #define DPPIC_CHENCLR_CH29_Msk (0x1UL << DPPIC_CHENCLR_CH29_Pos)
- #define DPPIC_CHENCLR_CH29_Disabled (0UL)
- #define DPPIC_CHENCLR_CH29_Enabled (1UL)
- #define DPPIC_CHENCLR_CH29_Clear (1UL)
- #define DPPIC_CHENCLR_CH28_Pos (28UL)
- #define DPPIC_CHENCLR_CH28_Msk (0x1UL << DPPIC_CHENCLR_CH28_Pos)
- #define DPPIC_CHENCLR_CH28_Disabled (0UL)
- #define DPPIC_CHENCLR_CH28_Enabled (1UL)
- #define DPPIC_CHENCLR_CH28_Clear (1UL)
- #define DPPIC_CHENCLR_CH27_Pos (27UL)
- #define DPPIC_CHENCLR_CH27_Msk (0x1UL << DPPIC_CHENCLR_CH27_Pos)
- #define DPPIC_CHENCLR_CH27_Disabled (0UL)
- #define DPPIC_CHENCLR_CH27_Enabled (1UL)
- #define DPPIC_CHENCLR_CH27_Clear (1UL)
- #define DPPIC_CHENCLR_CH26_Pos (26UL)
- #define DPPIC_CHENCLR_CH26_Msk (0x1UL << DPPIC_CHENCLR_CH26_Pos)
- #define DPPIC_CHENCLR_CH26_Disabled (0UL)
- #define DPPIC_CHENCLR_CH26_Enabled (1UL)
- #define DPPIC_CHENCLR_CH26_Clear (1UL)
- #define DPPIC_CHENCLR_CH25_Pos (25UL)
- #define DPPIC_CHENCLR_CH25_Msk (0x1UL << DPPIC_CHENCLR_CH25_Pos)
- #define DPPIC_CHENCLR_CH25_Disabled (0UL)
- #define DPPIC_CHENCLR_CH25_Enabled (1UL)
- #define DPPIC_CHENCLR_CH25_Clear (1UL)
- #define DPPIC_CHENCLR_CH24_Pos (24UL)
- #define DPPIC_CHENCLR_CH24_Msk (0x1UL << DPPIC_CHENCLR_CH24_Pos)
- #define DPPIC_CHENCLR_CH24_Disabled (0UL)
- #define DPPIC_CHENCLR_CH24_Enabled (1UL)
- #define DPPIC_CHENCLR_CH24_Clear (1UL)
- #define DPPIC_CHENCLR_CH23_Pos (23UL)
- #define DPPIC_CHENCLR_CH23_Msk (0x1UL << DPPIC_CHENCLR_CH23_Pos)
- #define DPPIC_CHENCLR_CH23_Disabled (0UL)
- #define DPPIC_CHENCLR_CH23_Enabled (1UL)
- #define DPPIC_CHENCLR_CH23_Clear (1UL)
- #define DPPIC_CHENCLR_CH22_Pos (22UL)
- #define DPPIC_CHENCLR_CH22_Msk (0x1UL << DPPIC_CHENCLR_CH22_Pos)
- #define DPPIC_CHENCLR_CH22_Disabled (0UL)
- #define DPPIC_CHENCLR_CH22_Enabled (1UL)
- #define DPPIC_CHENCLR_CH22_Clear (1UL)
- #define DPPIC_CHENCLR_CH21_Pos (21UL)
- #define DPPIC_CHENCLR_CH21_Msk (0x1UL << DPPIC_CHENCLR_CH21_Pos)
- #define DPPIC_CHENCLR_CH21_Disabled (0UL)
- #define DPPIC_CHENCLR_CH21_Enabled (1UL)
- #define DPPIC_CHENCLR_CH21_Clear (1UL)
- #define DPPIC_CHENCLR_CH20_Pos (20UL)
- #define DPPIC_CHENCLR_CH20_Msk (0x1UL << DPPIC_CHENCLR_CH20_Pos)
- #define DPPIC_CHENCLR_CH20_Disabled (0UL)
- #define DPPIC_CHENCLR_CH20_Enabled (1UL)
- #define DPPIC_CHENCLR_CH20_Clear (1UL)
- #define DPPIC_CHENCLR_CH19_Pos (19UL)
- #define DPPIC_CHENCLR_CH19_Msk (0x1UL << DPPIC_CHENCLR_CH19_Pos)
- #define DPPIC_CHENCLR_CH19_Disabled (0UL)
- #define DPPIC_CHENCLR_CH19_Enabled (1UL)
- #define DPPIC_CHENCLR_CH19_Clear (1UL)
- #define DPPIC_CHENCLR_CH18_Pos (18UL)
- #define DPPIC_CHENCLR_CH18_Msk (0x1UL << DPPIC_CHENCLR_CH18_Pos)
- #define DPPIC_CHENCLR_CH18_Disabled (0UL)
- #define DPPIC_CHENCLR_CH18_Enabled (1UL)
- #define DPPIC_CHENCLR_CH18_Clear (1UL)
- #define DPPIC_CHENCLR_CH17_Pos (17UL)
- #define DPPIC_CHENCLR_CH17_Msk (0x1UL << DPPIC_CHENCLR_CH17_Pos)
- #define DPPIC_CHENCLR_CH17_Disabled (0UL)
- #define DPPIC_CHENCLR_CH17_Enabled (1UL)
- #define DPPIC_CHENCLR_CH17_Clear (1UL)
- #define DPPIC_CHENCLR_CH16_Pos (16UL)
- #define DPPIC_CHENCLR_CH16_Msk (0x1UL << DPPIC_CHENCLR_CH16_Pos)
- #define DPPIC_CHENCLR_CH16_Disabled (0UL)
- #define DPPIC_CHENCLR_CH16_Enabled (1UL)
- #define DPPIC_CHENCLR_CH16_Clear (1UL)
- #define DPPIC_CHENCLR_CH15_Pos (15UL)
- #define DPPIC_CHENCLR_CH15_Msk (0x1UL << DPPIC_CHENCLR_CH15_Pos)
- #define DPPIC_CHENCLR_CH15_Disabled (0UL)
- #define DPPIC_CHENCLR_CH15_Enabled (1UL)
- #define DPPIC_CHENCLR_CH15_Clear (1UL)
- #define DPPIC_CHENCLR_CH14_Pos (14UL)
- #define DPPIC_CHENCLR_CH14_Msk (0x1UL << DPPIC_CHENCLR_CH14_Pos)
- #define DPPIC_CHENCLR_CH14_Disabled (0UL)
- #define DPPIC_CHENCLR_CH14_Enabled (1UL)
- #define DPPIC_CHENCLR_CH14_Clear (1UL)
- #define DPPIC_CHENCLR_CH13_Pos (13UL)
- #define DPPIC_CHENCLR_CH13_Msk (0x1UL << DPPIC_CHENCLR_CH13_Pos)
- #define DPPIC_CHENCLR_CH13_Disabled (0UL)
- #define DPPIC_CHENCLR_CH13_Enabled (1UL)
- #define DPPIC_CHENCLR_CH13_Clear (1UL)
- #define DPPIC_CHENCLR_CH12_Pos (12UL)
- #define DPPIC_CHENCLR_CH12_Msk (0x1UL << DPPIC_CHENCLR_CH12_Pos)
- #define DPPIC_CHENCLR_CH12_Disabled (0UL)
- #define DPPIC_CHENCLR_CH12_Enabled (1UL)
- #define DPPIC_CHENCLR_CH12_Clear (1UL)
- #define DPPIC_CHENCLR_CH11_Pos (11UL)
- #define DPPIC_CHENCLR_CH11_Msk (0x1UL << DPPIC_CHENCLR_CH11_Pos)
- #define DPPIC_CHENCLR_CH11_Disabled (0UL)
- #define DPPIC_CHENCLR_CH11_Enabled (1UL)
- #define DPPIC_CHENCLR_CH11_Clear (1UL)
- #define DPPIC_CHENCLR_CH10_Pos (10UL)
- #define DPPIC_CHENCLR_CH10_Msk (0x1UL << DPPIC_CHENCLR_CH10_Pos)
- #define DPPIC_CHENCLR_CH10_Disabled (0UL)
- #define DPPIC_CHENCLR_CH10_Enabled (1UL)
- #define DPPIC_CHENCLR_CH10_Clear (1UL)
- #define DPPIC_CHENCLR_CH9_Pos (9UL)
- #define DPPIC_CHENCLR_CH9_Msk (0x1UL << DPPIC_CHENCLR_CH9_Pos)
- #define DPPIC_CHENCLR_CH9_Disabled (0UL)
- #define DPPIC_CHENCLR_CH9_Enabled (1UL)
- #define DPPIC_CHENCLR_CH9_Clear (1UL)
- #define DPPIC_CHENCLR_CH8_Pos (8UL)
- #define DPPIC_CHENCLR_CH8_Msk (0x1UL << DPPIC_CHENCLR_CH8_Pos)
- #define DPPIC_CHENCLR_CH8_Disabled (0UL)
- #define DPPIC_CHENCLR_CH8_Enabled (1UL)
- #define DPPIC_CHENCLR_CH8_Clear (1UL)
- #define DPPIC_CHENCLR_CH7_Pos (7UL)
- #define DPPIC_CHENCLR_CH7_Msk (0x1UL << DPPIC_CHENCLR_CH7_Pos)
- #define DPPIC_CHENCLR_CH7_Disabled (0UL)
- #define DPPIC_CHENCLR_CH7_Enabled (1UL)
- #define DPPIC_CHENCLR_CH7_Clear (1UL)
- #define DPPIC_CHENCLR_CH6_Pos (6UL)
- #define DPPIC_CHENCLR_CH6_Msk (0x1UL << DPPIC_CHENCLR_CH6_Pos)
- #define DPPIC_CHENCLR_CH6_Disabled (0UL)
- #define DPPIC_CHENCLR_CH6_Enabled (1UL)
- #define DPPIC_CHENCLR_CH6_Clear (1UL)
- #define DPPIC_CHENCLR_CH5_Pos (5UL)
- #define DPPIC_CHENCLR_CH5_Msk (0x1UL << DPPIC_CHENCLR_CH5_Pos)
- #define DPPIC_CHENCLR_CH5_Disabled (0UL)
- #define DPPIC_CHENCLR_CH5_Enabled (1UL)
- #define DPPIC_CHENCLR_CH5_Clear (1UL)
- #define DPPIC_CHENCLR_CH4_Pos (4UL)
- #define DPPIC_CHENCLR_CH4_Msk (0x1UL << DPPIC_CHENCLR_CH4_Pos)
- #define DPPIC_CHENCLR_CH4_Disabled (0UL)
- #define DPPIC_CHENCLR_CH4_Enabled (1UL)
- #define DPPIC_CHENCLR_CH4_Clear (1UL)
- #define DPPIC_CHENCLR_CH3_Pos (3UL)
- #define DPPIC_CHENCLR_CH3_Msk (0x1UL << DPPIC_CHENCLR_CH3_Pos)
- #define DPPIC_CHENCLR_CH3_Disabled (0UL)
- #define DPPIC_CHENCLR_CH3_Enabled (1UL)
- #define DPPIC_CHENCLR_CH3_Clear (1UL)
- #define DPPIC_CHENCLR_CH2_Pos (2UL)
- #define DPPIC_CHENCLR_CH2_Msk (0x1UL << DPPIC_CHENCLR_CH2_Pos)
- #define DPPIC_CHENCLR_CH2_Disabled (0UL)
- #define DPPIC_CHENCLR_CH2_Enabled (1UL)
- #define DPPIC_CHENCLR_CH2_Clear (1UL)
- #define DPPIC_CHENCLR_CH1_Pos (1UL)
- #define DPPIC_CHENCLR_CH1_Msk (0x1UL << DPPIC_CHENCLR_CH1_Pos)
- #define DPPIC_CHENCLR_CH1_Disabled (0UL)
- #define DPPIC_CHENCLR_CH1_Enabled (1UL)
- #define DPPIC_CHENCLR_CH1_Clear (1UL)
- #define DPPIC_CHENCLR_CH0_Pos (0UL)
- #define DPPIC_CHENCLR_CH0_Msk (0x1UL << DPPIC_CHENCLR_CH0_Pos)
- #define DPPIC_CHENCLR_CH0_Disabled (0UL)
- #define DPPIC_CHENCLR_CH0_Enabled (1UL)
- #define DPPIC_CHENCLR_CH0_Clear (1UL)
- #define DPPIC_CHG_CH31_Pos (31UL)
- #define DPPIC_CHG_CH31_Msk (0x1UL << DPPIC_CHG_CH31_Pos)
- #define DPPIC_CHG_CH31_Excluded (0UL)
- #define DPPIC_CHG_CH31_Included (1UL)
- #define DPPIC_CHG_CH30_Pos (30UL)
- #define DPPIC_CHG_CH30_Msk (0x1UL << DPPIC_CHG_CH30_Pos)
- #define DPPIC_CHG_CH30_Excluded (0UL)
- #define DPPIC_CHG_CH30_Included (1UL)
- #define DPPIC_CHG_CH29_Pos (29UL)
- #define DPPIC_CHG_CH29_Msk (0x1UL << DPPIC_CHG_CH29_Pos)
- #define DPPIC_CHG_CH29_Excluded (0UL)
- #define DPPIC_CHG_CH29_Included (1UL)
- #define DPPIC_CHG_CH28_Pos (28UL)
- #define DPPIC_CHG_CH28_Msk (0x1UL << DPPIC_CHG_CH28_Pos)
- #define DPPIC_CHG_CH28_Excluded (0UL)
- #define DPPIC_CHG_CH28_Included (1UL)
- #define DPPIC_CHG_CH27_Pos (27UL)
- #define DPPIC_CHG_CH27_Msk (0x1UL << DPPIC_CHG_CH27_Pos)
- #define DPPIC_CHG_CH27_Excluded (0UL)
- #define DPPIC_CHG_CH27_Included (1UL)
- #define DPPIC_CHG_CH26_Pos (26UL)
- #define DPPIC_CHG_CH26_Msk (0x1UL << DPPIC_CHG_CH26_Pos)
- #define DPPIC_CHG_CH26_Excluded (0UL)
- #define DPPIC_CHG_CH26_Included (1UL)
- #define DPPIC_CHG_CH25_Pos (25UL)
- #define DPPIC_CHG_CH25_Msk (0x1UL << DPPIC_CHG_CH25_Pos)
- #define DPPIC_CHG_CH25_Excluded (0UL)
- #define DPPIC_CHG_CH25_Included (1UL)
- #define DPPIC_CHG_CH24_Pos (24UL)
- #define DPPIC_CHG_CH24_Msk (0x1UL << DPPIC_CHG_CH24_Pos)
- #define DPPIC_CHG_CH24_Excluded (0UL)
- #define DPPIC_CHG_CH24_Included (1UL)
- #define DPPIC_CHG_CH23_Pos (23UL)
- #define DPPIC_CHG_CH23_Msk (0x1UL << DPPIC_CHG_CH23_Pos)
- #define DPPIC_CHG_CH23_Excluded (0UL)
- #define DPPIC_CHG_CH23_Included (1UL)
- #define DPPIC_CHG_CH22_Pos (22UL)
- #define DPPIC_CHG_CH22_Msk (0x1UL << DPPIC_CHG_CH22_Pos)
- #define DPPIC_CHG_CH22_Excluded (0UL)
- #define DPPIC_CHG_CH22_Included (1UL)
- #define DPPIC_CHG_CH21_Pos (21UL)
- #define DPPIC_CHG_CH21_Msk (0x1UL << DPPIC_CHG_CH21_Pos)
- #define DPPIC_CHG_CH21_Excluded (0UL)
- #define DPPIC_CHG_CH21_Included (1UL)
- #define DPPIC_CHG_CH20_Pos (20UL)
- #define DPPIC_CHG_CH20_Msk (0x1UL << DPPIC_CHG_CH20_Pos)
- #define DPPIC_CHG_CH20_Excluded (0UL)
- #define DPPIC_CHG_CH20_Included (1UL)
- #define DPPIC_CHG_CH19_Pos (19UL)
- #define DPPIC_CHG_CH19_Msk (0x1UL << DPPIC_CHG_CH19_Pos)
- #define DPPIC_CHG_CH19_Excluded (0UL)
- #define DPPIC_CHG_CH19_Included (1UL)
- #define DPPIC_CHG_CH18_Pos (18UL)
- #define DPPIC_CHG_CH18_Msk (0x1UL << DPPIC_CHG_CH18_Pos)
- #define DPPIC_CHG_CH18_Excluded (0UL)
- #define DPPIC_CHG_CH18_Included (1UL)
- #define DPPIC_CHG_CH17_Pos (17UL)
- #define DPPIC_CHG_CH17_Msk (0x1UL << DPPIC_CHG_CH17_Pos)
- #define DPPIC_CHG_CH17_Excluded (0UL)
- #define DPPIC_CHG_CH17_Included (1UL)
- #define DPPIC_CHG_CH16_Pos (16UL)
- #define DPPIC_CHG_CH16_Msk (0x1UL << DPPIC_CHG_CH16_Pos)
- #define DPPIC_CHG_CH16_Excluded (0UL)
- #define DPPIC_CHG_CH16_Included (1UL)
- #define DPPIC_CHG_CH15_Pos (15UL)
- #define DPPIC_CHG_CH15_Msk (0x1UL << DPPIC_CHG_CH15_Pos)
- #define DPPIC_CHG_CH15_Excluded (0UL)
- #define DPPIC_CHG_CH15_Included (1UL)
- #define DPPIC_CHG_CH14_Pos (14UL)
- #define DPPIC_CHG_CH14_Msk (0x1UL << DPPIC_CHG_CH14_Pos)
- #define DPPIC_CHG_CH14_Excluded (0UL)
- #define DPPIC_CHG_CH14_Included (1UL)
- #define DPPIC_CHG_CH13_Pos (13UL)
- #define DPPIC_CHG_CH13_Msk (0x1UL << DPPIC_CHG_CH13_Pos)
- #define DPPIC_CHG_CH13_Excluded (0UL)
- #define DPPIC_CHG_CH13_Included (1UL)
- #define DPPIC_CHG_CH12_Pos (12UL)
- #define DPPIC_CHG_CH12_Msk (0x1UL << DPPIC_CHG_CH12_Pos)
- #define DPPIC_CHG_CH12_Excluded (0UL)
- #define DPPIC_CHG_CH12_Included (1UL)
- #define DPPIC_CHG_CH11_Pos (11UL)
- #define DPPIC_CHG_CH11_Msk (0x1UL << DPPIC_CHG_CH11_Pos)
- #define DPPIC_CHG_CH11_Excluded (0UL)
- #define DPPIC_CHG_CH11_Included (1UL)
- #define DPPIC_CHG_CH10_Pos (10UL)
- #define DPPIC_CHG_CH10_Msk (0x1UL << DPPIC_CHG_CH10_Pos)
- #define DPPIC_CHG_CH10_Excluded (0UL)
- #define DPPIC_CHG_CH10_Included (1UL)
- #define DPPIC_CHG_CH9_Pos (9UL)
- #define DPPIC_CHG_CH9_Msk (0x1UL << DPPIC_CHG_CH9_Pos)
- #define DPPIC_CHG_CH9_Excluded (0UL)
- #define DPPIC_CHG_CH9_Included (1UL)
- #define DPPIC_CHG_CH8_Pos (8UL)
- #define DPPIC_CHG_CH8_Msk (0x1UL << DPPIC_CHG_CH8_Pos)
- #define DPPIC_CHG_CH8_Excluded (0UL)
- #define DPPIC_CHG_CH8_Included (1UL)
- #define DPPIC_CHG_CH7_Pos (7UL)
- #define DPPIC_CHG_CH7_Msk (0x1UL << DPPIC_CHG_CH7_Pos)
- #define DPPIC_CHG_CH7_Excluded (0UL)
- #define DPPIC_CHG_CH7_Included (1UL)
- #define DPPIC_CHG_CH6_Pos (6UL)
- #define DPPIC_CHG_CH6_Msk (0x1UL << DPPIC_CHG_CH6_Pos)
- #define DPPIC_CHG_CH6_Excluded (0UL)
- #define DPPIC_CHG_CH6_Included (1UL)
- #define DPPIC_CHG_CH5_Pos (5UL)
- #define DPPIC_CHG_CH5_Msk (0x1UL << DPPIC_CHG_CH5_Pos)
- #define DPPIC_CHG_CH5_Excluded (0UL)
- #define DPPIC_CHG_CH5_Included (1UL)
- #define DPPIC_CHG_CH4_Pos (4UL)
- #define DPPIC_CHG_CH4_Msk (0x1UL << DPPIC_CHG_CH4_Pos)
- #define DPPIC_CHG_CH4_Excluded (0UL)
- #define DPPIC_CHG_CH4_Included (1UL)
- #define DPPIC_CHG_CH3_Pos (3UL)
- #define DPPIC_CHG_CH3_Msk (0x1UL << DPPIC_CHG_CH3_Pos)
- #define DPPIC_CHG_CH3_Excluded (0UL)
- #define DPPIC_CHG_CH3_Included (1UL)
- #define DPPIC_CHG_CH2_Pos (2UL)
- #define DPPIC_CHG_CH2_Msk (0x1UL << DPPIC_CHG_CH2_Pos)
- #define DPPIC_CHG_CH2_Excluded (0UL)
- #define DPPIC_CHG_CH2_Included (1UL)
- #define DPPIC_CHG_CH1_Pos (1UL)
- #define DPPIC_CHG_CH1_Msk (0x1UL << DPPIC_CHG_CH1_Pos)
- #define DPPIC_CHG_CH1_Excluded (0UL)
- #define DPPIC_CHG_CH1_Included (1UL)
- #define DPPIC_CHG_CH0_Pos (0UL)
- #define DPPIC_CHG_CH0_Msk (0x1UL << DPPIC_CHG_CH0_Pos)
- #define DPPIC_CHG_CH0_Excluded (0UL)
- #define DPPIC_CHG_CH0_Included (1UL)
- #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL)
- #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos)
- #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL)
- #define EGU_SUBSCRIBE_TRIGGER_EN_Pos (31UL)
- #define EGU_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << EGU_SUBSCRIBE_TRIGGER_EN_Pos)
- #define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0UL)
- #define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (1UL)
- #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL)
- #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos)
- #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL)
- #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos)
- #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL)
- #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL)
- #define EGU_PUBLISH_TRIGGERED_EN_Pos (31UL)
- #define EGU_PUBLISH_TRIGGERED_EN_Msk (0x1UL << EGU_PUBLISH_TRIGGERED_EN_Pos)
- #define EGU_PUBLISH_TRIGGERED_EN_Disabled (0UL)
- #define EGU_PUBLISH_TRIGGERED_EN_Enabled (1UL)
- #define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL)
- #define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos)
- #define EGU_INTEN_TRIGGERED15_Pos (15UL)
- #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos)
- #define EGU_INTEN_TRIGGERED15_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED15_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED14_Pos (14UL)
- #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos)
- #define EGU_INTEN_TRIGGERED14_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED14_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED13_Pos (13UL)
- #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos)
- #define EGU_INTEN_TRIGGERED13_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED13_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED12_Pos (12UL)
- #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos)
- #define EGU_INTEN_TRIGGERED12_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED12_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED11_Pos (11UL)
- #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos)
- #define EGU_INTEN_TRIGGERED11_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED11_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED10_Pos (10UL)
- #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos)
- #define EGU_INTEN_TRIGGERED10_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED10_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED9_Pos (9UL)
- #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos)
- #define EGU_INTEN_TRIGGERED9_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED9_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED8_Pos (8UL)
- #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos)
- #define EGU_INTEN_TRIGGERED8_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED8_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED7_Pos (7UL)
- #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos)
- #define EGU_INTEN_TRIGGERED7_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED7_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED6_Pos (6UL)
- #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos)
- #define EGU_INTEN_TRIGGERED6_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED6_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED5_Pos (5UL)
- #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos)
- #define EGU_INTEN_TRIGGERED5_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED5_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED4_Pos (4UL)
- #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos)
- #define EGU_INTEN_TRIGGERED4_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED4_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED3_Pos (3UL)
- #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos)
- #define EGU_INTEN_TRIGGERED3_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED3_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED2_Pos (2UL)
- #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos)
- #define EGU_INTEN_TRIGGERED2_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED2_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED1_Pos (1UL)
- #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos)
- #define EGU_INTEN_TRIGGERED1_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED1_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED0_Pos (0UL)
- #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos)
- #define EGU_INTEN_TRIGGERED0_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED0_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED15_Pos (15UL)
- #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos)
- #define EGU_INTENSET_TRIGGERED15_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED15_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED15_Set (1UL)
- #define EGU_INTENSET_TRIGGERED14_Pos (14UL)
- #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos)
- #define EGU_INTENSET_TRIGGERED14_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED14_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED14_Set (1UL)
- #define EGU_INTENSET_TRIGGERED13_Pos (13UL)
- #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos)
- #define EGU_INTENSET_TRIGGERED13_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED13_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED13_Set (1UL)
- #define EGU_INTENSET_TRIGGERED12_Pos (12UL)
- #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos)
- #define EGU_INTENSET_TRIGGERED12_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED12_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED12_Set (1UL)
- #define EGU_INTENSET_TRIGGERED11_Pos (11UL)
- #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos)
- #define EGU_INTENSET_TRIGGERED11_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED11_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED11_Set (1UL)
- #define EGU_INTENSET_TRIGGERED10_Pos (10UL)
- #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos)
- #define EGU_INTENSET_TRIGGERED10_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED10_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED10_Set (1UL)
- #define EGU_INTENSET_TRIGGERED9_Pos (9UL)
- #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos)
- #define EGU_INTENSET_TRIGGERED9_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED9_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED9_Set (1UL)
- #define EGU_INTENSET_TRIGGERED8_Pos (8UL)
- #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos)
- #define EGU_INTENSET_TRIGGERED8_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED8_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED8_Set (1UL)
- #define EGU_INTENSET_TRIGGERED7_Pos (7UL)
- #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos)
- #define EGU_INTENSET_TRIGGERED7_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED7_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED7_Set (1UL)
- #define EGU_INTENSET_TRIGGERED6_Pos (6UL)
- #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos)
- #define EGU_INTENSET_TRIGGERED6_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED6_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED6_Set (1UL)
- #define EGU_INTENSET_TRIGGERED5_Pos (5UL)
- #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos)
- #define EGU_INTENSET_TRIGGERED5_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED5_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED5_Set (1UL)
- #define EGU_INTENSET_TRIGGERED4_Pos (4UL)
- #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos)
- #define EGU_INTENSET_TRIGGERED4_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED4_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED4_Set (1UL)
- #define EGU_INTENSET_TRIGGERED3_Pos (3UL)
- #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos)
- #define EGU_INTENSET_TRIGGERED3_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED3_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED3_Set (1UL)
- #define EGU_INTENSET_TRIGGERED2_Pos (2UL)
- #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos)
- #define EGU_INTENSET_TRIGGERED2_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED2_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED2_Set (1UL)
- #define EGU_INTENSET_TRIGGERED1_Pos (1UL)
- #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos)
- #define EGU_INTENSET_TRIGGERED1_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED1_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED1_Set (1UL)
- #define EGU_INTENSET_TRIGGERED0_Pos (0UL)
- #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos)
- #define EGU_INTENSET_TRIGGERED0_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED0_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED0_Set (1UL)
- #define EGU_INTENCLR_TRIGGERED15_Pos (15UL)
- #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos)
- #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED15_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED14_Pos (14UL)
- #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos)
- #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED14_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED13_Pos (13UL)
- #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos)
- #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED13_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED12_Pos (12UL)
- #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos)
- #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED12_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED11_Pos (11UL)
- #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos)
- #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED11_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED10_Pos (10UL)
- #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos)
- #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED10_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED9_Pos (9UL)
- #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos)
- #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED9_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED8_Pos (8UL)
- #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos)
- #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED8_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED7_Pos (7UL)
- #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos)
- #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED7_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED6_Pos (6UL)
- #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos)
- #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED6_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED5_Pos (5UL)
- #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos)
- #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED5_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED4_Pos (4UL)
- #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos)
- #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED4_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED3_Pos (3UL)
- #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos)
- #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED3_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED2_Pos (2UL)
- #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos)
- #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED2_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED1_Pos (1UL)
- #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos)
- #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED1_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED0_Pos (0UL)
- #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos)
- #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED0_Clear (1UL)
- #define FICR_INFO_CONFIGID_HWID_Pos (0UL)
- #define FICR_INFO_CONFIGID_HWID_Msk (0xFFFFUL << FICR_INFO_CONFIGID_HWID_Pos)
- #define FICR_INFO_DEVICEID_DEVICEID_Pos (0UL)
- #define FICR_INFO_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICEID_DEVICEID_Pos)
- #define FICR_INFO_PART_PART_Pos (0UL)
- #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos)
- #define FICR_INFO_PART_PART_N5340 (0x5340UL)
- #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL)
- #define FICR_INFO_VARIANT_VARIANT_Pos (0UL)
- #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos)
- #define FICR_INFO_VARIANT_VARIANT_QKAA (0x514B4141UL)
- #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL)
- #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL)
- #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos)
- #define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL)
- #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL)
- #define FICR_INFO_RAM_RAM_Pos (0UL)
- #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos)
- #define FICR_INFO_RAM_RAM_K16 (0x10UL)
- #define FICR_INFO_RAM_RAM_K32 (0x20UL)
- #define FICR_INFO_RAM_RAM_K64 (0x40UL)
- #define FICR_INFO_RAM_RAM_K128 (0x80UL)
- #define FICR_INFO_RAM_RAM_K256 (0x100UL)
- #define FICR_INFO_RAM_RAM_K512 (0x200UL)
- #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL)
- #define FICR_INFO_FLASH_FLASH_Pos (0UL)
- #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos)
- #define FICR_INFO_FLASH_FLASH_K128 (0x80UL)
- #define FICR_INFO_FLASH_FLASH_K256 (0x100UL)
- #define FICR_INFO_FLASH_FLASH_K512 (0x200UL)
- #define FICR_INFO_FLASH_FLASH_K1024 (0x400UL)
- #define FICR_INFO_FLASH_FLASH_K2048 (0x800UL)
- #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL)
- #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL)
- #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos)
- #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_K4096 (0x1000UL)
- #define FICR_INFO_CODESIZE_CODESIZE_Pos (0UL)
- #define FICR_INFO_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODESIZE_CODESIZE_Pos)
- #define FICR_INFO_CODESIZE_CODESIZE_P256 (256UL)
- #define FICR_INFO_DEVICETYPE_DEVICETYPE_Pos (0UL)
- #define FICR_INFO_DEVICETYPE_DEVICETYPE_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICETYPE_DEVICETYPE_Pos)
- #define FICR_INFO_DEVICETYPE_DEVICETYPE_Die (0x0000000UL)
- #define FICR_INFO_DEVICETYPE_DEVICETYPE_FPGA (0xFFFFFFFFUL)
- #define FICR_TRIMCNF_ADDR_Address_Pos (0UL)
- #define FICR_TRIMCNF_ADDR_Address_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_ADDR_Address_Pos)
- #define FICR_TRIMCNF_DATA_Data_Pos (0UL)
- #define FICR_TRIMCNF_DATA_Data_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_DATA_Data_Pos)
- #define FICR_NFC_TAGHEADER0_UD3_Pos (24UL)
- #define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos)
- #define FICR_NFC_TAGHEADER0_UD2_Pos (16UL)
- #define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos)
- #define FICR_NFC_TAGHEADER0_UD1_Pos (8UL)
- #define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos)
- #define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL)
- #define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos)
- #define FICR_NFC_TAGHEADER1_UD7_Pos (24UL)
- #define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos)
- #define FICR_NFC_TAGHEADER1_UD6_Pos (16UL)
- #define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos)
- #define FICR_NFC_TAGHEADER1_UD5_Pos (8UL)
- #define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos)
- #define FICR_NFC_TAGHEADER1_UD4_Pos (0UL)
- #define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos)
- #define FICR_NFC_TAGHEADER2_UD11_Pos (24UL)
- #define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos)
- #define FICR_NFC_TAGHEADER2_UD10_Pos (16UL)
- #define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos)
- #define FICR_NFC_TAGHEADER2_UD9_Pos (8UL)
- #define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos)
- #define FICR_NFC_TAGHEADER2_UD8_Pos (0UL)
- #define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos)
- #define FICR_NFC_TAGHEADER3_UD15_Pos (24UL)
- #define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos)
- #define FICR_NFC_TAGHEADER3_UD14_Pos (16UL)
- #define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos)
- #define FICR_NFC_TAGHEADER3_UD13_Pos (8UL)
- #define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos)
- #define FICR_NFC_TAGHEADER3_UD12_Pos (0UL)
- #define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos)
- #define FICR_TRNG90B_BYTES_BYTES_Pos (0UL)
- #define FICR_TRNG90B_BYTES_BYTES_Msk (0xFFFFFFFFUL << FICR_TRNG90B_BYTES_BYTES_Pos)
- #define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos (0UL)
- #define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos)
- #define FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos (0UL)
- #define FICR_TRNG90B_APCUTOFF_APCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos)
- #define FICR_TRNG90B_STARTUP_STARTUP_Pos (0UL)
- #define FICR_TRNG90B_STARTUP_STARTUP_Msk (0xFFFFFFFFUL << FICR_TRNG90B_STARTUP_STARTUP_Pos)
- #define FICR_TRNG90B_ROSC1_ROSC1_Pos (0UL)
- #define FICR_TRNG90B_ROSC1_ROSC1_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC1_ROSC1_Pos)
- #define FICR_TRNG90B_ROSC2_ROSC2_Pos (0UL)
- #define FICR_TRNG90B_ROSC2_ROSC2_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC2_ROSC2_Pos)
- #define FICR_TRNG90B_ROSC3_ROSC3_Pos (0UL)
- #define FICR_TRNG90B_ROSC3_ROSC3_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC3_ROSC3_Pos)
- #define FICR_TRNG90B_ROSC4_ROSC4_Pos (0UL)
- #define FICR_TRNG90B_ROSC4_ROSC4_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC4_ROSC4_Pos)
- #define FICR_XOSC32MTRIM_OFFSET_Pos (5UL)
- #define FICR_XOSC32MTRIM_OFFSET_Msk (0x1FUL << FICR_XOSC32MTRIM_OFFSET_Pos)
- #define FICR_XOSC32MTRIM_SLOPE_Pos (0UL)
- #define FICR_XOSC32MTRIM_SLOPE_Msk (0x1FUL << FICR_XOSC32MTRIM_SLOPE_Pos)
- #define FPU_EVENTS_INVALIDOPERATION_EVENTS_INVALIDOPERATION_Pos (0UL)
- #define FPU_EVENTS_INVALIDOPERATION_EVENTS_INVALIDOPERATION_Msk (0x1UL << FPU_EVENTS_INVALIDOPERATION_EVENTS_INVALIDOPERATION_Pos)
- #define FPU_EVENTS_INVALIDOPERATION_EVENTS_INVALIDOPERATION_NotGenerated (0UL)
- #define FPU_EVENTS_INVALIDOPERATION_EVENTS_INVALIDOPERATION_Generated (1UL)
- #define FPU_EVENTS_DIVIDEBYZERO_EVENTS_DIVIDEBYZERO_Pos (0UL)
- #define FPU_EVENTS_DIVIDEBYZERO_EVENTS_DIVIDEBYZERO_Msk (0x1UL << FPU_EVENTS_DIVIDEBYZERO_EVENTS_DIVIDEBYZERO_Pos)
- #define FPU_EVENTS_DIVIDEBYZERO_EVENTS_DIVIDEBYZERO_NotGenerated (0UL)
- #define FPU_EVENTS_DIVIDEBYZERO_EVENTS_DIVIDEBYZERO_Generated (1UL)
- #define FPU_EVENTS_OVERFLOW_EVENTS_OVERFLOW_Pos (0UL)
- #define FPU_EVENTS_OVERFLOW_EVENTS_OVERFLOW_Msk (0x1UL << FPU_EVENTS_OVERFLOW_EVENTS_OVERFLOW_Pos)
- #define FPU_EVENTS_OVERFLOW_EVENTS_OVERFLOW_NotGenerated (0UL)
- #define FPU_EVENTS_OVERFLOW_EVENTS_OVERFLOW_Generated (1UL)
- #define FPU_EVENTS_UNDERFLOW_EVENTS_UNDERFLOW_Pos (0UL)
- #define FPU_EVENTS_UNDERFLOW_EVENTS_UNDERFLOW_Msk (0x1UL << FPU_EVENTS_UNDERFLOW_EVENTS_UNDERFLOW_Pos)
- #define FPU_EVENTS_UNDERFLOW_EVENTS_UNDERFLOW_NotGenerated (0UL)
- #define FPU_EVENTS_UNDERFLOW_EVENTS_UNDERFLOW_Generated (1UL)
- #define FPU_EVENTS_INEXACT_EVENTS_INEXACT_Pos (0UL)
- #define FPU_EVENTS_INEXACT_EVENTS_INEXACT_Msk (0x1UL << FPU_EVENTS_INEXACT_EVENTS_INEXACT_Pos)
- #define FPU_EVENTS_INEXACT_EVENTS_INEXACT_NotGenerated (0UL)
- #define FPU_EVENTS_INEXACT_EVENTS_INEXACT_Generated (1UL)
- #define FPU_EVENTS_DENORMALINPUT_EVENTS_DENORMALINPUT_Pos (0UL)
- #define FPU_EVENTS_DENORMALINPUT_EVENTS_DENORMALINPUT_Msk (0x1UL << FPU_EVENTS_DENORMALINPUT_EVENTS_DENORMALINPUT_Pos)
- #define FPU_EVENTS_DENORMALINPUT_EVENTS_DENORMALINPUT_NotGenerated (0UL)
- #define FPU_EVENTS_DENORMALINPUT_EVENTS_DENORMALINPUT_Generated (1UL)
- #define FPU_INTEN_DENORMALINPUT_Pos (5UL)
- #define FPU_INTEN_DENORMALINPUT_Msk (0x1UL << FPU_INTEN_DENORMALINPUT_Pos)
- #define FPU_INTEN_DENORMALINPUT_Disabled (0UL)
- #define FPU_INTEN_DENORMALINPUT_Enabled (1UL)
- #define FPU_INTEN_INEXACT_Pos (4UL)
- #define FPU_INTEN_INEXACT_Msk (0x1UL << FPU_INTEN_INEXACT_Pos)
- #define FPU_INTEN_INEXACT_Disabled (0UL)
- #define FPU_INTEN_INEXACT_Enabled (1UL)
- #define FPU_INTEN_UNDERFLOW_Pos (3UL)
- #define FPU_INTEN_UNDERFLOW_Msk (0x1UL << FPU_INTEN_UNDERFLOW_Pos)
- #define FPU_INTEN_UNDERFLOW_Disabled (0UL)
- #define FPU_INTEN_UNDERFLOW_Enabled (1UL)
- #define FPU_INTEN_OVERFLOW_Pos (2UL)
- #define FPU_INTEN_OVERFLOW_Msk (0x1UL << FPU_INTEN_OVERFLOW_Pos)
- #define FPU_INTEN_OVERFLOW_Disabled (0UL)
- #define FPU_INTEN_OVERFLOW_Enabled (1UL)
- #define FPU_INTEN_DIVIDEBYZERO_Pos (1UL)
- #define FPU_INTEN_DIVIDEBYZERO_Msk (0x1UL << FPU_INTEN_DIVIDEBYZERO_Pos)
- #define FPU_INTEN_DIVIDEBYZERO_Disabled (0UL)
- #define FPU_INTEN_DIVIDEBYZERO_Enabled (1UL)
- #define FPU_INTEN_INVALIDOPERATION_Pos (0UL)
- #define FPU_INTEN_INVALIDOPERATION_Msk (0x1UL << FPU_INTEN_INVALIDOPERATION_Pos)
- #define FPU_INTEN_INVALIDOPERATION_Disabled (0UL)
- #define FPU_INTEN_INVALIDOPERATION_Enabled (1UL)
- #define FPU_INTENSET_DENORMALINPUT_Pos (5UL)
- #define FPU_INTENSET_DENORMALINPUT_Msk (0x1UL << FPU_INTENSET_DENORMALINPUT_Pos)
- #define FPU_INTENSET_DENORMALINPUT_Disabled (0UL)
- #define FPU_INTENSET_DENORMALINPUT_Enabled (1UL)
- #define FPU_INTENSET_DENORMALINPUT_Set (1UL)
- #define FPU_INTENSET_INEXACT_Pos (4UL)
- #define FPU_INTENSET_INEXACT_Msk (0x1UL << FPU_INTENSET_INEXACT_Pos)
- #define FPU_INTENSET_INEXACT_Disabled (0UL)
- #define FPU_INTENSET_INEXACT_Enabled (1UL)
- #define FPU_INTENSET_INEXACT_Set (1UL)
- #define FPU_INTENSET_UNDERFLOW_Pos (3UL)
- #define FPU_INTENSET_UNDERFLOW_Msk (0x1UL << FPU_INTENSET_UNDERFLOW_Pos)
- #define FPU_INTENSET_UNDERFLOW_Disabled (0UL)
- #define FPU_INTENSET_UNDERFLOW_Enabled (1UL)
- #define FPU_INTENSET_UNDERFLOW_Set (1UL)
- #define FPU_INTENSET_OVERFLOW_Pos (2UL)
- #define FPU_INTENSET_OVERFLOW_Msk (0x1UL << FPU_INTENSET_OVERFLOW_Pos)
- #define FPU_INTENSET_OVERFLOW_Disabled (0UL)
- #define FPU_INTENSET_OVERFLOW_Enabled (1UL)
- #define FPU_INTENSET_OVERFLOW_Set (1UL)
- #define FPU_INTENSET_DIVIDEBYZERO_Pos (1UL)
- #define FPU_INTENSET_DIVIDEBYZERO_Msk (0x1UL << FPU_INTENSET_DIVIDEBYZERO_Pos)
- #define FPU_INTENSET_DIVIDEBYZERO_Disabled (0UL)
- #define FPU_INTENSET_DIVIDEBYZERO_Enabled (1UL)
- #define FPU_INTENSET_DIVIDEBYZERO_Set (1UL)
- #define FPU_INTENSET_INVALIDOPERATION_Pos (0UL)
- #define FPU_INTENSET_INVALIDOPERATION_Msk (0x1UL << FPU_INTENSET_INVALIDOPERATION_Pos)
- #define FPU_INTENSET_INVALIDOPERATION_Disabled (0UL)
- #define FPU_INTENSET_INVALIDOPERATION_Enabled (1UL)
- #define FPU_INTENSET_INVALIDOPERATION_Set (1UL)
- #define FPU_INTENCLR_DENORMALINPUT_Pos (5UL)
- #define FPU_INTENCLR_DENORMALINPUT_Msk (0x1UL << FPU_INTENCLR_DENORMALINPUT_Pos)
- #define FPU_INTENCLR_DENORMALINPUT_Disabled (0UL)
- #define FPU_INTENCLR_DENORMALINPUT_Enabled (1UL)
- #define FPU_INTENCLR_DENORMALINPUT_Clear (1UL)
- #define FPU_INTENCLR_INEXACT_Pos (4UL)
- #define FPU_INTENCLR_INEXACT_Msk (0x1UL << FPU_INTENCLR_INEXACT_Pos)
- #define FPU_INTENCLR_INEXACT_Disabled (0UL)
- #define FPU_INTENCLR_INEXACT_Enabled (1UL)
- #define FPU_INTENCLR_INEXACT_Clear (1UL)
- #define FPU_INTENCLR_UNDERFLOW_Pos (3UL)
- #define FPU_INTENCLR_UNDERFLOW_Msk (0x1UL << FPU_INTENCLR_UNDERFLOW_Pos)
- #define FPU_INTENCLR_UNDERFLOW_Disabled (0UL)
- #define FPU_INTENCLR_UNDERFLOW_Enabled (1UL)
- #define FPU_INTENCLR_UNDERFLOW_Clear (1UL)
- #define FPU_INTENCLR_OVERFLOW_Pos (2UL)
- #define FPU_INTENCLR_OVERFLOW_Msk (0x1UL << FPU_INTENCLR_OVERFLOW_Pos)
- #define FPU_INTENCLR_OVERFLOW_Disabled (0UL)
- #define FPU_INTENCLR_OVERFLOW_Enabled (1UL)
- #define FPU_INTENCLR_OVERFLOW_Clear (1UL)
- #define FPU_INTENCLR_DIVIDEBYZERO_Pos (1UL)
- #define FPU_INTENCLR_DIVIDEBYZERO_Msk (0x1UL << FPU_INTENCLR_DIVIDEBYZERO_Pos)
- #define FPU_INTENCLR_DIVIDEBYZERO_Disabled (0UL)
- #define FPU_INTENCLR_DIVIDEBYZERO_Enabled (1UL)
- #define FPU_INTENCLR_DIVIDEBYZERO_Clear (1UL)
- #define FPU_INTENCLR_INVALIDOPERATION_Pos (0UL)
- #define FPU_INTENCLR_INVALIDOPERATION_Msk (0x1UL << FPU_INTENCLR_INVALIDOPERATION_Pos)
- #define FPU_INTENCLR_INVALIDOPERATION_Disabled (0UL)
- #define FPU_INTENCLR_INVALIDOPERATION_Enabled (1UL)
- #define FPU_INTENCLR_INVALIDOPERATION_Clear (1UL)
- #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL)
- #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos)
- #define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL)
- #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL)
- #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos)
- #define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL)
- #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL)
- #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos)
- #define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL)
- #define GPIOTE_SUBSCRIBE_OUT_EN_Pos (31UL)
- #define GPIOTE_SUBSCRIBE_OUT_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_OUT_EN_Pos)
- #define GPIOTE_SUBSCRIBE_OUT_EN_Disabled (0UL)
- #define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (1UL)
- #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos (0UL)
- #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos)
- #define GPIOTE_SUBSCRIBE_SET_EN_Pos (31UL)
- #define GPIOTE_SUBSCRIBE_SET_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_SET_EN_Pos)
- #define GPIOTE_SUBSCRIBE_SET_EN_Disabled (0UL)
- #define GPIOTE_SUBSCRIBE_SET_EN_Enabled (1UL)
- #define GPIOTE_SUBSCRIBE_SET_CHIDX_Pos (0UL)
- #define GPIOTE_SUBSCRIBE_SET_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_SET_CHIDX_Pos)
- #define GPIOTE_SUBSCRIBE_CLR_EN_Pos (31UL)
- #define GPIOTE_SUBSCRIBE_CLR_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_CLR_EN_Pos)
- #define GPIOTE_SUBSCRIBE_CLR_EN_Disabled (0UL)
- #define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (1UL)
- #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos (0UL)
- #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos)
- #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL)
- #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos)
- #define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL)
- #define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL)
- #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL)
- #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos)
- #define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL)
- #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL)
- #define GPIOTE_PUBLISH_IN_EN_Pos (31UL)
- #define GPIOTE_PUBLISH_IN_EN_Msk (0x1UL << GPIOTE_PUBLISH_IN_EN_Pos)
- #define GPIOTE_PUBLISH_IN_EN_Disabled (0UL)
- #define GPIOTE_PUBLISH_IN_EN_Enabled (1UL)
- #define GPIOTE_PUBLISH_IN_CHIDX_Pos (0UL)
- #define GPIOTE_PUBLISH_IN_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_IN_CHIDX_Pos)
- #define GPIOTE_PUBLISH_PORT_EN_Pos (31UL)
- #define GPIOTE_PUBLISH_PORT_EN_Msk (0x1UL << GPIOTE_PUBLISH_PORT_EN_Pos)
- #define GPIOTE_PUBLISH_PORT_EN_Disabled (0UL)
- #define GPIOTE_PUBLISH_PORT_EN_Enabled (1UL)
- #define GPIOTE_PUBLISH_PORT_CHIDX_Pos (0UL)
- #define GPIOTE_PUBLISH_PORT_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_PORT_CHIDX_Pos)
- #define GPIOTE_INTENSET_PORT_Pos (31UL)
- #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos)
- #define GPIOTE_INTENSET_PORT_Disabled (0UL)
- #define GPIOTE_INTENSET_PORT_Enabled (1UL)
- #define GPIOTE_INTENSET_PORT_Set (1UL)
- #define GPIOTE_INTENSET_IN7_Pos (7UL)
- #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos)
- #define GPIOTE_INTENSET_IN7_Disabled (0UL)
- #define GPIOTE_INTENSET_IN7_Enabled (1UL)
- #define GPIOTE_INTENSET_IN7_Set (1UL)
- #define GPIOTE_INTENSET_IN6_Pos (6UL)
- #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos)
- #define GPIOTE_INTENSET_IN6_Disabled (0UL)
- #define GPIOTE_INTENSET_IN6_Enabled (1UL)
- #define GPIOTE_INTENSET_IN6_Set (1UL)
- #define GPIOTE_INTENSET_IN5_Pos (5UL)
- #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos)
- #define GPIOTE_INTENSET_IN5_Disabled (0UL)
- #define GPIOTE_INTENSET_IN5_Enabled (1UL)
- #define GPIOTE_INTENSET_IN5_Set (1UL)
- #define GPIOTE_INTENSET_IN4_Pos (4UL)
- #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos)
- #define GPIOTE_INTENSET_IN4_Disabled (0UL)
- #define GPIOTE_INTENSET_IN4_Enabled (1UL)
- #define GPIOTE_INTENSET_IN4_Set (1UL)
- #define GPIOTE_INTENSET_IN3_Pos (3UL)
- #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos)
- #define GPIOTE_INTENSET_IN3_Disabled (0UL)
- #define GPIOTE_INTENSET_IN3_Enabled (1UL)
- #define GPIOTE_INTENSET_IN3_Set (1UL)
- #define GPIOTE_INTENSET_IN2_Pos (2UL)
- #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos)
- #define GPIOTE_INTENSET_IN2_Disabled (0UL)
- #define GPIOTE_INTENSET_IN2_Enabled (1UL)
- #define GPIOTE_INTENSET_IN2_Set (1UL)
- #define GPIOTE_INTENSET_IN1_Pos (1UL)
- #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos)
- #define GPIOTE_INTENSET_IN1_Disabled (0UL)
- #define GPIOTE_INTENSET_IN1_Enabled (1UL)
- #define GPIOTE_INTENSET_IN1_Set (1UL)
- #define GPIOTE_INTENSET_IN0_Pos (0UL)
- #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos)
- #define GPIOTE_INTENSET_IN0_Disabled (0UL)
- #define GPIOTE_INTENSET_IN0_Enabled (1UL)
- #define GPIOTE_INTENSET_IN0_Set (1UL)
- #define GPIOTE_INTENCLR_PORT_Pos (31UL)
- #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos)
- #define GPIOTE_INTENCLR_PORT_Disabled (0UL)
- #define GPIOTE_INTENCLR_PORT_Enabled (1UL)
- #define GPIOTE_INTENCLR_PORT_Clear (1UL)
- #define GPIOTE_INTENCLR_IN7_Pos (7UL)
- #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos)
- #define GPIOTE_INTENCLR_IN7_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN7_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN7_Clear (1UL)
- #define GPIOTE_INTENCLR_IN6_Pos (6UL)
- #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos)
- #define GPIOTE_INTENCLR_IN6_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN6_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN6_Clear (1UL)
- #define GPIOTE_INTENCLR_IN5_Pos (5UL)
- #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos)
- #define GPIOTE_INTENCLR_IN5_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN5_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN5_Clear (1UL)
- #define GPIOTE_INTENCLR_IN4_Pos (4UL)
- #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos)
- #define GPIOTE_INTENCLR_IN4_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN4_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN4_Clear (1UL)
- #define GPIOTE_INTENCLR_IN3_Pos (3UL)
- #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos)
- #define GPIOTE_INTENCLR_IN3_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN3_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN3_Clear (1UL)
- #define GPIOTE_INTENCLR_IN2_Pos (2UL)
- #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos)
- #define GPIOTE_INTENCLR_IN2_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN2_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN2_Clear (1UL)
- #define GPIOTE_INTENCLR_IN1_Pos (1UL)
- #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos)
- #define GPIOTE_INTENCLR_IN1_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN1_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN1_Clear (1UL)
- #define GPIOTE_INTENCLR_IN0_Pos (0UL)
- #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos)
- #define GPIOTE_INTENCLR_IN0_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN0_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN0_Clear (1UL)
- #define GPIOTE_LATENCY_LATENCY_Pos (0UL)
- #define GPIOTE_LATENCY_LATENCY_Msk (0x1UL << GPIOTE_LATENCY_LATENCY_Pos)
- #define GPIOTE_LATENCY_LATENCY_LowPower (0UL)
- #define GPIOTE_LATENCY_LATENCY_LowLatency (1UL)
- #define GPIOTE_CONFIG_OUTINIT_Pos (20UL)
- #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos)
- #define GPIOTE_CONFIG_OUTINIT_Low (0UL)
- #define GPIOTE_CONFIG_OUTINIT_High (1UL)
- #define GPIOTE_CONFIG_POLARITY_Pos (16UL)
- #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos)
- #define GPIOTE_CONFIG_POLARITY_None (0UL)
- #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL)
- #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL)
- #define GPIOTE_CONFIG_POLARITY_Toggle (3UL)
- #define GPIOTE_CONFIG_PORT_Pos (13UL)
- #define GPIOTE_CONFIG_PORT_Msk (0x1UL << GPIOTE_CONFIG_PORT_Pos)
- #define GPIOTE_CONFIG_PSEL_Pos (8UL)
- #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos)
- #define GPIOTE_CONFIG_MODE_Pos (0UL)
- #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos)
- #define GPIOTE_CONFIG_MODE_Disabled (0UL)
- #define GPIOTE_CONFIG_MODE_Event (1UL)
- #define GPIOTE_CONFIG_MODE_Task (3UL)
- #define I2S_TASKS_START_TASKS_START_Pos (0UL)
- #define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos)
- #define I2S_TASKS_START_TASKS_START_Trigger (1UL)
- #define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos)
- #define I2S_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define I2S_SUBSCRIBE_START_EN_Pos (31UL)
- #define I2S_SUBSCRIBE_START_EN_Msk (0x1UL << I2S_SUBSCRIBE_START_EN_Pos)
- #define I2S_SUBSCRIBE_START_EN_Disabled (0UL)
- #define I2S_SUBSCRIBE_START_EN_Enabled (1UL)
- #define I2S_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define I2S_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_START_CHIDX_Pos)
- #define I2S_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define I2S_SUBSCRIBE_STOP_EN_Msk (0x1UL << I2S_SUBSCRIBE_STOP_EN_Pos)
- #define I2S_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define I2S_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define I2S_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define I2S_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_STOP_CHIDX_Pos)
- #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL)
- #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos)
- #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0UL)
- #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (1UL)
- #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL)
- #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos)
- #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL)
- #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL)
- #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL)
- #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos)
- #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0UL)
- #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (1UL)
- #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL)
- #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos)
- #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0UL)
- #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL)
- #define I2S_PUBLISH_RXPTRUPD_EN_Pos (31UL)
- #define I2S_PUBLISH_RXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_RXPTRUPD_EN_Pos)
- #define I2S_PUBLISH_RXPTRUPD_EN_Disabled (0UL)
- #define I2S_PUBLISH_RXPTRUPD_EN_Enabled (1UL)
- #define I2S_PUBLISH_RXPTRUPD_CHIDX_Pos (0UL)
- #define I2S_PUBLISH_RXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_RXPTRUPD_CHIDX_Pos)
- #define I2S_PUBLISH_STOPPED_EN_Pos (31UL)
- #define I2S_PUBLISH_STOPPED_EN_Msk (0x1UL << I2S_PUBLISH_STOPPED_EN_Pos)
- #define I2S_PUBLISH_STOPPED_EN_Disabled (0UL)
- #define I2S_PUBLISH_STOPPED_EN_Enabled (1UL)
- #define I2S_PUBLISH_STOPPED_CHIDX_Pos (0UL)
- #define I2S_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << I2S_PUBLISH_STOPPED_CHIDX_Pos)
- #define I2S_PUBLISH_TXPTRUPD_EN_Pos (31UL)
- #define I2S_PUBLISH_TXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_TXPTRUPD_EN_Pos)
- #define I2S_PUBLISH_TXPTRUPD_EN_Disabled (0UL)
- #define I2S_PUBLISH_TXPTRUPD_EN_Enabled (1UL)
- #define I2S_PUBLISH_TXPTRUPD_CHIDX_Pos (0UL)
- #define I2S_PUBLISH_TXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_TXPTRUPD_CHIDX_Pos)
- #define I2S_PUBLISH_FRAMESTART_EN_Pos (31UL)
- #define I2S_PUBLISH_FRAMESTART_EN_Msk (0x1UL << I2S_PUBLISH_FRAMESTART_EN_Pos)
- #define I2S_PUBLISH_FRAMESTART_EN_Disabled (0UL)
- #define I2S_PUBLISH_FRAMESTART_EN_Enabled (1UL)
- #define I2S_PUBLISH_FRAMESTART_CHIDX_Pos (0UL)
- #define I2S_PUBLISH_FRAMESTART_CHIDX_Msk (0xFFUL << I2S_PUBLISH_FRAMESTART_CHIDX_Pos)
- #define I2S_INTEN_FRAMESTART_Pos (7UL)
- #define I2S_INTEN_FRAMESTART_Msk (0x1UL << I2S_INTEN_FRAMESTART_Pos)
- #define I2S_INTEN_FRAMESTART_Disabled (0UL)
- #define I2S_INTEN_FRAMESTART_Enabled (1UL)
- #define I2S_INTEN_TXPTRUPD_Pos (5UL)
- #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos)
- #define I2S_INTEN_TXPTRUPD_Disabled (0UL)
- #define I2S_INTEN_TXPTRUPD_Enabled (1UL)
- #define I2S_INTEN_STOPPED_Pos (2UL)
- #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos)
- #define I2S_INTEN_STOPPED_Disabled (0UL)
- #define I2S_INTEN_STOPPED_Enabled (1UL)
- #define I2S_INTEN_RXPTRUPD_Pos (1UL)
- #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos)
- #define I2S_INTEN_RXPTRUPD_Disabled (0UL)
- #define I2S_INTEN_RXPTRUPD_Enabled (1UL)
- #define I2S_INTENSET_FRAMESTART_Pos (7UL)
- #define I2S_INTENSET_FRAMESTART_Msk (0x1UL << I2S_INTENSET_FRAMESTART_Pos)
- #define I2S_INTENSET_FRAMESTART_Disabled (0UL)
- #define I2S_INTENSET_FRAMESTART_Enabled (1UL)
- #define I2S_INTENSET_FRAMESTART_Set (1UL)
- #define I2S_INTENSET_TXPTRUPD_Pos (5UL)
- #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos)
- #define I2S_INTENSET_TXPTRUPD_Disabled (0UL)
- #define I2S_INTENSET_TXPTRUPD_Enabled (1UL)
- #define I2S_INTENSET_TXPTRUPD_Set (1UL)
- #define I2S_INTENSET_STOPPED_Pos (2UL)
- #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos)
- #define I2S_INTENSET_STOPPED_Disabled (0UL)
- #define I2S_INTENSET_STOPPED_Enabled (1UL)
- #define I2S_INTENSET_STOPPED_Set (1UL)
- #define I2S_INTENSET_RXPTRUPD_Pos (1UL)
- #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos)
- #define I2S_INTENSET_RXPTRUPD_Disabled (0UL)
- #define I2S_INTENSET_RXPTRUPD_Enabled (1UL)
- #define I2S_INTENSET_RXPTRUPD_Set (1UL)
- #define I2S_INTENCLR_FRAMESTART_Pos (7UL)
- #define I2S_INTENCLR_FRAMESTART_Msk (0x1UL << I2S_INTENCLR_FRAMESTART_Pos)
- #define I2S_INTENCLR_FRAMESTART_Disabled (0UL)
- #define I2S_INTENCLR_FRAMESTART_Enabled (1UL)
- #define I2S_INTENCLR_FRAMESTART_Clear (1UL)
- #define I2S_INTENCLR_TXPTRUPD_Pos (5UL)
- #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos)
- #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL)
- #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL)
- #define I2S_INTENCLR_TXPTRUPD_Clear (1UL)
- #define I2S_INTENCLR_STOPPED_Pos (2UL)
- #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos)
- #define I2S_INTENCLR_STOPPED_Disabled (0UL)
- #define I2S_INTENCLR_STOPPED_Enabled (1UL)
- #define I2S_INTENCLR_STOPPED_Clear (1UL)
- #define I2S_INTENCLR_RXPTRUPD_Pos (1UL)
- #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos)
- #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL)
- #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL)
- #define I2S_INTENCLR_RXPTRUPD_Clear (1UL)
- #define I2S_ENABLE_ENABLE_Pos (0UL)
- #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos)
- #define I2S_ENABLE_ENABLE_Disabled (0UL)
- #define I2S_ENABLE_ENABLE_Enabled (1UL)
- #define I2S_CONFIG_MODE_MODE_Pos (0UL)
- #define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos)
- #define I2S_CONFIG_MODE_MODE_Master (0UL)
- #define I2S_CONFIG_MODE_MODE_Slave (1UL)
- #define I2S_CONFIG_RXEN_RXEN_Pos (0UL)
- #define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos)
- #define I2S_CONFIG_RXEN_RXEN_Disabled (0UL)
- #define I2S_CONFIG_RXEN_RXEN_Enabled (1UL)
- #define I2S_CONFIG_TXEN_TXEN_Pos (0UL)
- #define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos)
- #define I2S_CONFIG_TXEN_TXEN_Disabled (0UL)
- #define I2S_CONFIG_TXEN_TXEN_Enabled (1UL)
- #define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL)
- #define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos)
- #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL)
- #define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL)
- #define I2S_CONFIG_RATIO_RATIO_Pos (0UL)
- #define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos)
- #define I2S_CONFIG_RATIO_RATIO_32X (0UL)
- #define I2S_CONFIG_RATIO_RATIO_48X (1UL)
- #define I2S_CONFIG_RATIO_RATIO_64X (2UL)
- #define I2S_CONFIG_RATIO_RATIO_96X (3UL)
- #define I2S_CONFIG_RATIO_RATIO_128X (4UL)
- #define I2S_CONFIG_RATIO_RATIO_192X (5UL)
- #define I2S_CONFIG_RATIO_RATIO_256X (6UL)
- #define I2S_CONFIG_RATIO_RATIO_384X (7UL)
- #define I2S_CONFIG_RATIO_RATIO_512X (8UL)
- #define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL)
- #define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x7UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos)
- #define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL)
- #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL)
- #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL)
- #define I2S_CONFIG_SWIDTH_SWIDTH_32Bit (3UL)
- #define I2S_CONFIG_SWIDTH_SWIDTH_8BitIn16 (4UL)
- #define I2S_CONFIG_SWIDTH_SWIDTH_8BitIn32 (5UL)
- #define I2S_CONFIG_SWIDTH_SWIDTH_16BitIn32 (6UL)
- #define I2S_CONFIG_SWIDTH_SWIDTH_24BitIn32 (7UL)
- #define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL)
- #define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos)
- #define I2S_CONFIG_ALIGN_ALIGN_Left (0UL)
- #define I2S_CONFIG_ALIGN_ALIGN_Right (1UL)
- #define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL)
- #define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos)
- #define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL)
- #define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL)
- #define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL)
- #define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos)
- #define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL)
- #define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL)
- #define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL)
- #define I2S_CONFIG_CLKCONFIG_BYPASS_Pos (8UL)
- #define I2S_CONFIG_CLKCONFIG_BYPASS_Msk (0x1UL << I2S_CONFIG_CLKCONFIG_BYPASS_Pos)
- #define I2S_CONFIG_CLKCONFIG_BYPASS_Disable (0UL)
- #define I2S_CONFIG_CLKCONFIG_BYPASS_Enable (1UL)
- #define I2S_CONFIG_CLKCONFIG_CLKSRC_Pos (0UL)
- #define I2S_CONFIG_CLKCONFIG_CLKSRC_Msk (0x1UL << I2S_CONFIG_CLKCONFIG_CLKSRC_Pos)
- #define I2S_CONFIG_CLKCONFIG_CLKSRC_PCLK32M (0UL)
- #define I2S_CONFIG_CLKCONFIG_CLKSRC_ACLK (1UL)
- #define I2S_RXD_PTR_PTR_Pos (0UL)
- #define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos)
- #define I2S_TXD_PTR_PTR_Pos (0UL)
- #define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos)
- #define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL)
- #define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos)
- #define I2S_PSEL_MCK_CONNECT_Pos (31UL)
- #define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos)
- #define I2S_PSEL_MCK_CONNECT_Connected (0UL)
- #define I2S_PSEL_MCK_CONNECT_Disconnected (1UL)
- #define I2S_PSEL_MCK_PORT_Pos (5UL)
- #define I2S_PSEL_MCK_PORT_Msk (0x1UL << I2S_PSEL_MCK_PORT_Pos)
- #define I2S_PSEL_MCK_PIN_Pos (0UL)
- #define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos)
- #define I2S_PSEL_SCK_CONNECT_Pos (31UL)
- #define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos)
- #define I2S_PSEL_SCK_CONNECT_Connected (0UL)
- #define I2S_PSEL_SCK_CONNECT_Disconnected (1UL)
- #define I2S_PSEL_SCK_PORT_Pos (5UL)
- #define I2S_PSEL_SCK_PORT_Msk (0x1UL << I2S_PSEL_SCK_PORT_Pos)
- #define I2S_PSEL_SCK_PIN_Pos (0UL)
- #define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos)
- #define I2S_PSEL_LRCK_CONNECT_Pos (31UL)
- #define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos)
- #define I2S_PSEL_LRCK_CONNECT_Connected (0UL)
- #define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL)
- #define I2S_PSEL_LRCK_PORT_Pos (5UL)
- #define I2S_PSEL_LRCK_PORT_Msk (0x1UL << I2S_PSEL_LRCK_PORT_Pos)
- #define I2S_PSEL_LRCK_PIN_Pos (0UL)
- #define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos)
- #define I2S_PSEL_SDIN_CONNECT_Pos (31UL)
- #define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos)
- #define I2S_PSEL_SDIN_CONNECT_Connected (0UL)
- #define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL)
- #define I2S_PSEL_SDIN_PORT_Pos (5UL)
- #define I2S_PSEL_SDIN_PORT_Msk (0x1UL << I2S_PSEL_SDIN_PORT_Pos)
- #define I2S_PSEL_SDIN_PIN_Pos (0UL)
- #define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos)
- #define I2S_PSEL_SDOUT_CONNECT_Pos (31UL)
- #define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos)
- #define I2S_PSEL_SDOUT_CONNECT_Connected (0UL)
- #define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL)
- #define I2S_PSEL_SDOUT_PORT_Pos (5UL)
- #define I2S_PSEL_SDOUT_PORT_Msk (0x1UL << I2S_PSEL_SDOUT_PORT_Pos)
- #define I2S_PSEL_SDOUT_PIN_Pos (0UL)
- #define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos)
- #define IPC_TASKS_SEND_TASKS_SEND_Pos (0UL)
- #define IPC_TASKS_SEND_TASKS_SEND_Msk (0x1UL << IPC_TASKS_SEND_TASKS_SEND_Pos)
- #define IPC_TASKS_SEND_TASKS_SEND_Trigger (1UL)
- #define IPC_SUBSCRIBE_SEND_EN_Pos (31UL)
- #define IPC_SUBSCRIBE_SEND_EN_Msk (0x1UL << IPC_SUBSCRIBE_SEND_EN_Pos)
- #define IPC_SUBSCRIBE_SEND_EN_Disabled (0UL)
- #define IPC_SUBSCRIBE_SEND_EN_Enabled (1UL)
- #define IPC_SUBSCRIBE_SEND_CHIDX_Pos (0UL)
- #define IPC_SUBSCRIBE_SEND_CHIDX_Msk (0xFFUL << IPC_SUBSCRIBE_SEND_CHIDX_Pos)
- #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos (0UL)
- #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Msk (0x1UL << IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos)
- #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_NotGenerated (0UL)
- #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Generated (1UL)
- #define IPC_PUBLISH_RECEIVE_EN_Pos (31UL)
- #define IPC_PUBLISH_RECEIVE_EN_Msk (0x1UL << IPC_PUBLISH_RECEIVE_EN_Pos)
- #define IPC_PUBLISH_RECEIVE_EN_Disabled (0UL)
- #define IPC_PUBLISH_RECEIVE_EN_Enabled (1UL)
- #define IPC_PUBLISH_RECEIVE_CHIDX_Pos (0UL)
- #define IPC_PUBLISH_RECEIVE_CHIDX_Msk (0xFFUL << IPC_PUBLISH_RECEIVE_CHIDX_Pos)
- #define IPC_INTEN_RECEIVE15_Pos (15UL)
- #define IPC_INTEN_RECEIVE15_Msk (0x1UL << IPC_INTEN_RECEIVE15_Pos)
- #define IPC_INTEN_RECEIVE15_Disabled (0UL)
- #define IPC_INTEN_RECEIVE15_Enabled (1UL)
- #define IPC_INTEN_RECEIVE14_Pos (14UL)
- #define IPC_INTEN_RECEIVE14_Msk (0x1UL << IPC_INTEN_RECEIVE14_Pos)
- #define IPC_INTEN_RECEIVE14_Disabled (0UL)
- #define IPC_INTEN_RECEIVE14_Enabled (1UL)
- #define IPC_INTEN_RECEIVE13_Pos (13UL)
- #define IPC_INTEN_RECEIVE13_Msk (0x1UL << IPC_INTEN_RECEIVE13_Pos)
- #define IPC_INTEN_RECEIVE13_Disabled (0UL)
- #define IPC_INTEN_RECEIVE13_Enabled (1UL)
- #define IPC_INTEN_RECEIVE12_Pos (12UL)
- #define IPC_INTEN_RECEIVE12_Msk (0x1UL << IPC_INTEN_RECEIVE12_Pos)
- #define IPC_INTEN_RECEIVE12_Disabled (0UL)
- #define IPC_INTEN_RECEIVE12_Enabled (1UL)
- #define IPC_INTEN_RECEIVE11_Pos (11UL)
- #define IPC_INTEN_RECEIVE11_Msk (0x1UL << IPC_INTEN_RECEIVE11_Pos)
- #define IPC_INTEN_RECEIVE11_Disabled (0UL)
- #define IPC_INTEN_RECEIVE11_Enabled (1UL)
- #define IPC_INTEN_RECEIVE10_Pos (10UL)
- #define IPC_INTEN_RECEIVE10_Msk (0x1UL << IPC_INTEN_RECEIVE10_Pos)
- #define IPC_INTEN_RECEIVE10_Disabled (0UL)
- #define IPC_INTEN_RECEIVE10_Enabled (1UL)
- #define IPC_INTEN_RECEIVE9_Pos (9UL)
- #define IPC_INTEN_RECEIVE9_Msk (0x1UL << IPC_INTEN_RECEIVE9_Pos)
- #define IPC_INTEN_RECEIVE9_Disabled (0UL)
- #define IPC_INTEN_RECEIVE9_Enabled (1UL)
- #define IPC_INTEN_RECEIVE8_Pos (8UL)
- #define IPC_INTEN_RECEIVE8_Msk (0x1UL << IPC_INTEN_RECEIVE8_Pos)
- #define IPC_INTEN_RECEIVE8_Disabled (0UL)
- #define IPC_INTEN_RECEIVE8_Enabled (1UL)
- #define IPC_INTEN_RECEIVE7_Pos (7UL)
- #define IPC_INTEN_RECEIVE7_Msk (0x1UL << IPC_INTEN_RECEIVE7_Pos)
- #define IPC_INTEN_RECEIVE7_Disabled (0UL)
- #define IPC_INTEN_RECEIVE7_Enabled (1UL)
- #define IPC_INTEN_RECEIVE6_Pos (6UL)
- #define IPC_INTEN_RECEIVE6_Msk (0x1UL << IPC_INTEN_RECEIVE6_Pos)
- #define IPC_INTEN_RECEIVE6_Disabled (0UL)
- #define IPC_INTEN_RECEIVE6_Enabled (1UL)
- #define IPC_INTEN_RECEIVE5_Pos (5UL)
- #define IPC_INTEN_RECEIVE5_Msk (0x1UL << IPC_INTEN_RECEIVE5_Pos)
- #define IPC_INTEN_RECEIVE5_Disabled (0UL)
- #define IPC_INTEN_RECEIVE5_Enabled (1UL)
- #define IPC_INTEN_RECEIVE4_Pos (4UL)
- #define IPC_INTEN_RECEIVE4_Msk (0x1UL << IPC_INTEN_RECEIVE4_Pos)
- #define IPC_INTEN_RECEIVE4_Disabled (0UL)
- #define IPC_INTEN_RECEIVE4_Enabled (1UL)
- #define IPC_INTEN_RECEIVE3_Pos (3UL)
- #define IPC_INTEN_RECEIVE3_Msk (0x1UL << IPC_INTEN_RECEIVE3_Pos)
- #define IPC_INTEN_RECEIVE3_Disabled (0UL)
- #define IPC_INTEN_RECEIVE3_Enabled (1UL)
- #define IPC_INTEN_RECEIVE2_Pos (2UL)
- #define IPC_INTEN_RECEIVE2_Msk (0x1UL << IPC_INTEN_RECEIVE2_Pos)
- #define IPC_INTEN_RECEIVE2_Disabled (0UL)
- #define IPC_INTEN_RECEIVE2_Enabled (1UL)
- #define IPC_INTEN_RECEIVE1_Pos (1UL)
- #define IPC_INTEN_RECEIVE1_Msk (0x1UL << IPC_INTEN_RECEIVE1_Pos)
- #define IPC_INTEN_RECEIVE1_Disabled (0UL)
- #define IPC_INTEN_RECEIVE1_Enabled (1UL)
- #define IPC_INTEN_RECEIVE0_Pos (0UL)
- #define IPC_INTEN_RECEIVE0_Msk (0x1UL << IPC_INTEN_RECEIVE0_Pos)
- #define IPC_INTEN_RECEIVE0_Disabled (0UL)
- #define IPC_INTEN_RECEIVE0_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE15_Pos (15UL)
- #define IPC_INTENSET_RECEIVE15_Msk (0x1UL << IPC_INTENSET_RECEIVE15_Pos)
- #define IPC_INTENSET_RECEIVE15_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE15_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE15_Set (1UL)
- #define IPC_INTENSET_RECEIVE14_Pos (14UL)
- #define IPC_INTENSET_RECEIVE14_Msk (0x1UL << IPC_INTENSET_RECEIVE14_Pos)
- #define IPC_INTENSET_RECEIVE14_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE14_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE14_Set (1UL)
- #define IPC_INTENSET_RECEIVE13_Pos (13UL)
- #define IPC_INTENSET_RECEIVE13_Msk (0x1UL << IPC_INTENSET_RECEIVE13_Pos)
- #define IPC_INTENSET_RECEIVE13_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE13_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE13_Set (1UL)
- #define IPC_INTENSET_RECEIVE12_Pos (12UL)
- #define IPC_INTENSET_RECEIVE12_Msk (0x1UL << IPC_INTENSET_RECEIVE12_Pos)
- #define IPC_INTENSET_RECEIVE12_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE12_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE12_Set (1UL)
- #define IPC_INTENSET_RECEIVE11_Pos (11UL)
- #define IPC_INTENSET_RECEIVE11_Msk (0x1UL << IPC_INTENSET_RECEIVE11_Pos)
- #define IPC_INTENSET_RECEIVE11_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE11_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE11_Set (1UL)
- #define IPC_INTENSET_RECEIVE10_Pos (10UL)
- #define IPC_INTENSET_RECEIVE10_Msk (0x1UL << IPC_INTENSET_RECEIVE10_Pos)
- #define IPC_INTENSET_RECEIVE10_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE10_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE10_Set (1UL)
- #define IPC_INTENSET_RECEIVE9_Pos (9UL)
- #define IPC_INTENSET_RECEIVE9_Msk (0x1UL << IPC_INTENSET_RECEIVE9_Pos)
- #define IPC_INTENSET_RECEIVE9_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE9_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE9_Set (1UL)
- #define IPC_INTENSET_RECEIVE8_Pos (8UL)
- #define IPC_INTENSET_RECEIVE8_Msk (0x1UL << IPC_INTENSET_RECEIVE8_Pos)
- #define IPC_INTENSET_RECEIVE8_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE8_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE8_Set (1UL)
- #define IPC_INTENSET_RECEIVE7_Pos (7UL)
- #define IPC_INTENSET_RECEIVE7_Msk (0x1UL << IPC_INTENSET_RECEIVE7_Pos)
- #define IPC_INTENSET_RECEIVE7_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE7_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE7_Set (1UL)
- #define IPC_INTENSET_RECEIVE6_Pos (6UL)
- #define IPC_INTENSET_RECEIVE6_Msk (0x1UL << IPC_INTENSET_RECEIVE6_Pos)
- #define IPC_INTENSET_RECEIVE6_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE6_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE6_Set (1UL)
- #define IPC_INTENSET_RECEIVE5_Pos (5UL)
- #define IPC_INTENSET_RECEIVE5_Msk (0x1UL << IPC_INTENSET_RECEIVE5_Pos)
- #define IPC_INTENSET_RECEIVE5_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE5_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE5_Set (1UL)
- #define IPC_INTENSET_RECEIVE4_Pos (4UL)
- #define IPC_INTENSET_RECEIVE4_Msk (0x1UL << IPC_INTENSET_RECEIVE4_Pos)
- #define IPC_INTENSET_RECEIVE4_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE4_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE4_Set (1UL)
- #define IPC_INTENSET_RECEIVE3_Pos (3UL)
- #define IPC_INTENSET_RECEIVE3_Msk (0x1UL << IPC_INTENSET_RECEIVE3_Pos)
- #define IPC_INTENSET_RECEIVE3_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE3_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE3_Set (1UL)
- #define IPC_INTENSET_RECEIVE2_Pos (2UL)
- #define IPC_INTENSET_RECEIVE2_Msk (0x1UL << IPC_INTENSET_RECEIVE2_Pos)
- #define IPC_INTENSET_RECEIVE2_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE2_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE2_Set (1UL)
- #define IPC_INTENSET_RECEIVE1_Pos (1UL)
- #define IPC_INTENSET_RECEIVE1_Msk (0x1UL << IPC_INTENSET_RECEIVE1_Pos)
- #define IPC_INTENSET_RECEIVE1_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE1_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE1_Set (1UL)
- #define IPC_INTENSET_RECEIVE0_Pos (0UL)
- #define IPC_INTENSET_RECEIVE0_Msk (0x1UL << IPC_INTENSET_RECEIVE0_Pos)
- #define IPC_INTENSET_RECEIVE0_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE0_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE0_Set (1UL)
- #define IPC_INTENCLR_RECEIVE15_Pos (15UL)
- #define IPC_INTENCLR_RECEIVE15_Msk (0x1UL << IPC_INTENCLR_RECEIVE15_Pos)
- #define IPC_INTENCLR_RECEIVE15_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE15_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE15_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE14_Pos (14UL)
- #define IPC_INTENCLR_RECEIVE14_Msk (0x1UL << IPC_INTENCLR_RECEIVE14_Pos)
- #define IPC_INTENCLR_RECEIVE14_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE14_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE14_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE13_Pos (13UL)
- #define IPC_INTENCLR_RECEIVE13_Msk (0x1UL << IPC_INTENCLR_RECEIVE13_Pos)
- #define IPC_INTENCLR_RECEIVE13_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE13_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE13_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE12_Pos (12UL)
- #define IPC_INTENCLR_RECEIVE12_Msk (0x1UL << IPC_INTENCLR_RECEIVE12_Pos)
- #define IPC_INTENCLR_RECEIVE12_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE12_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE12_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE11_Pos (11UL)
- #define IPC_INTENCLR_RECEIVE11_Msk (0x1UL << IPC_INTENCLR_RECEIVE11_Pos)
- #define IPC_INTENCLR_RECEIVE11_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE11_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE11_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE10_Pos (10UL)
- #define IPC_INTENCLR_RECEIVE10_Msk (0x1UL << IPC_INTENCLR_RECEIVE10_Pos)
- #define IPC_INTENCLR_RECEIVE10_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE10_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE10_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE9_Pos (9UL)
- #define IPC_INTENCLR_RECEIVE9_Msk (0x1UL << IPC_INTENCLR_RECEIVE9_Pos)
- #define IPC_INTENCLR_RECEIVE9_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE9_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE9_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE8_Pos (8UL)
- #define IPC_INTENCLR_RECEIVE8_Msk (0x1UL << IPC_INTENCLR_RECEIVE8_Pos)
- #define IPC_INTENCLR_RECEIVE8_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE8_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE8_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE7_Pos (7UL)
- #define IPC_INTENCLR_RECEIVE7_Msk (0x1UL << IPC_INTENCLR_RECEIVE7_Pos)
- #define IPC_INTENCLR_RECEIVE7_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE7_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE7_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE6_Pos (6UL)
- #define IPC_INTENCLR_RECEIVE6_Msk (0x1UL << IPC_INTENCLR_RECEIVE6_Pos)
- #define IPC_INTENCLR_RECEIVE6_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE6_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE6_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE5_Pos (5UL)
- #define IPC_INTENCLR_RECEIVE5_Msk (0x1UL << IPC_INTENCLR_RECEIVE5_Pos)
- #define IPC_INTENCLR_RECEIVE5_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE5_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE5_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE4_Pos (4UL)
- #define IPC_INTENCLR_RECEIVE4_Msk (0x1UL << IPC_INTENCLR_RECEIVE4_Pos)
- #define IPC_INTENCLR_RECEIVE4_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE4_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE4_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE3_Pos (3UL)
- #define IPC_INTENCLR_RECEIVE3_Msk (0x1UL << IPC_INTENCLR_RECEIVE3_Pos)
- #define IPC_INTENCLR_RECEIVE3_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE3_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE3_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE2_Pos (2UL)
- #define IPC_INTENCLR_RECEIVE2_Msk (0x1UL << IPC_INTENCLR_RECEIVE2_Pos)
- #define IPC_INTENCLR_RECEIVE2_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE2_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE2_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE1_Pos (1UL)
- #define IPC_INTENCLR_RECEIVE1_Msk (0x1UL << IPC_INTENCLR_RECEIVE1_Pos)
- #define IPC_INTENCLR_RECEIVE1_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE1_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE1_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE0_Pos (0UL)
- #define IPC_INTENCLR_RECEIVE0_Msk (0x1UL << IPC_INTENCLR_RECEIVE0_Pos)
- #define IPC_INTENCLR_RECEIVE0_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE0_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE0_Clear (1UL)
- #define IPC_INTPEND_RECEIVE15_Pos (15UL)
- #define IPC_INTPEND_RECEIVE15_Msk (0x1UL << IPC_INTPEND_RECEIVE15_Pos)
- #define IPC_INTPEND_RECEIVE15_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE15_Pending (1UL)
- #define IPC_INTPEND_RECEIVE14_Pos (14UL)
- #define IPC_INTPEND_RECEIVE14_Msk (0x1UL << IPC_INTPEND_RECEIVE14_Pos)
- #define IPC_INTPEND_RECEIVE14_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE14_Pending (1UL)
- #define IPC_INTPEND_RECEIVE13_Pos (13UL)
- #define IPC_INTPEND_RECEIVE13_Msk (0x1UL << IPC_INTPEND_RECEIVE13_Pos)
- #define IPC_INTPEND_RECEIVE13_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE13_Pending (1UL)
- #define IPC_INTPEND_RECEIVE12_Pos (12UL)
- #define IPC_INTPEND_RECEIVE12_Msk (0x1UL << IPC_INTPEND_RECEIVE12_Pos)
- #define IPC_INTPEND_RECEIVE12_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE12_Pending (1UL)
- #define IPC_INTPEND_RECEIVE11_Pos (11UL)
- #define IPC_INTPEND_RECEIVE11_Msk (0x1UL << IPC_INTPEND_RECEIVE11_Pos)
- #define IPC_INTPEND_RECEIVE11_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE11_Pending (1UL)
- #define IPC_INTPEND_RECEIVE10_Pos (10UL)
- #define IPC_INTPEND_RECEIVE10_Msk (0x1UL << IPC_INTPEND_RECEIVE10_Pos)
- #define IPC_INTPEND_RECEIVE10_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE10_Pending (1UL)
- #define IPC_INTPEND_RECEIVE9_Pos (9UL)
- #define IPC_INTPEND_RECEIVE9_Msk (0x1UL << IPC_INTPEND_RECEIVE9_Pos)
- #define IPC_INTPEND_RECEIVE9_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE9_Pending (1UL)
- #define IPC_INTPEND_RECEIVE8_Pos (8UL)
- #define IPC_INTPEND_RECEIVE8_Msk (0x1UL << IPC_INTPEND_RECEIVE8_Pos)
- #define IPC_INTPEND_RECEIVE8_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE8_Pending (1UL)
- #define IPC_INTPEND_RECEIVE7_Pos (7UL)
- #define IPC_INTPEND_RECEIVE7_Msk (0x1UL << IPC_INTPEND_RECEIVE7_Pos)
- #define IPC_INTPEND_RECEIVE7_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE7_Pending (1UL)
- #define IPC_INTPEND_RECEIVE6_Pos (6UL)
- #define IPC_INTPEND_RECEIVE6_Msk (0x1UL << IPC_INTPEND_RECEIVE6_Pos)
- #define IPC_INTPEND_RECEIVE6_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE6_Pending (1UL)
- #define IPC_INTPEND_RECEIVE5_Pos (5UL)
- #define IPC_INTPEND_RECEIVE5_Msk (0x1UL << IPC_INTPEND_RECEIVE5_Pos)
- #define IPC_INTPEND_RECEIVE5_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE5_Pending (1UL)
- #define IPC_INTPEND_RECEIVE4_Pos (4UL)
- #define IPC_INTPEND_RECEIVE4_Msk (0x1UL << IPC_INTPEND_RECEIVE4_Pos)
- #define IPC_INTPEND_RECEIVE4_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE4_Pending (1UL)
- #define IPC_INTPEND_RECEIVE3_Pos (3UL)
- #define IPC_INTPEND_RECEIVE3_Msk (0x1UL << IPC_INTPEND_RECEIVE3_Pos)
- #define IPC_INTPEND_RECEIVE3_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE3_Pending (1UL)
- #define IPC_INTPEND_RECEIVE2_Pos (2UL)
- #define IPC_INTPEND_RECEIVE2_Msk (0x1UL << IPC_INTPEND_RECEIVE2_Pos)
- #define IPC_INTPEND_RECEIVE2_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE2_Pending (1UL)
- #define IPC_INTPEND_RECEIVE1_Pos (1UL)
- #define IPC_INTPEND_RECEIVE1_Msk (0x1UL << IPC_INTPEND_RECEIVE1_Pos)
- #define IPC_INTPEND_RECEIVE1_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE1_Pending (1UL)
- #define IPC_INTPEND_RECEIVE0_Pos (0UL)
- #define IPC_INTPEND_RECEIVE0_Msk (0x1UL << IPC_INTPEND_RECEIVE0_Pos)
- #define IPC_INTPEND_RECEIVE0_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE0_Pending (1UL)
- #define IPC_SEND_CNF_CHEN15_Pos (15UL)
- #define IPC_SEND_CNF_CHEN15_Msk (0x1UL << IPC_SEND_CNF_CHEN15_Pos)
- #define IPC_SEND_CNF_CHEN15_Disable (0UL)
- #define IPC_SEND_CNF_CHEN15_Enable (1UL)
- #define IPC_SEND_CNF_CHEN14_Pos (14UL)
- #define IPC_SEND_CNF_CHEN14_Msk (0x1UL << IPC_SEND_CNF_CHEN14_Pos)
- #define IPC_SEND_CNF_CHEN14_Disable (0UL)
- #define IPC_SEND_CNF_CHEN14_Enable (1UL)
- #define IPC_SEND_CNF_CHEN13_Pos (13UL)
- #define IPC_SEND_CNF_CHEN13_Msk (0x1UL << IPC_SEND_CNF_CHEN13_Pos)
- #define IPC_SEND_CNF_CHEN13_Disable (0UL)
- #define IPC_SEND_CNF_CHEN13_Enable (1UL)
- #define IPC_SEND_CNF_CHEN12_Pos (12UL)
- #define IPC_SEND_CNF_CHEN12_Msk (0x1UL << IPC_SEND_CNF_CHEN12_Pos)
- #define IPC_SEND_CNF_CHEN12_Disable (0UL)
- #define IPC_SEND_CNF_CHEN12_Enable (1UL)
- #define IPC_SEND_CNF_CHEN11_Pos (11UL)
- #define IPC_SEND_CNF_CHEN11_Msk (0x1UL << IPC_SEND_CNF_CHEN11_Pos)
- #define IPC_SEND_CNF_CHEN11_Disable (0UL)
- #define IPC_SEND_CNF_CHEN11_Enable (1UL)
- #define IPC_SEND_CNF_CHEN10_Pos (10UL)
- #define IPC_SEND_CNF_CHEN10_Msk (0x1UL << IPC_SEND_CNF_CHEN10_Pos)
- #define IPC_SEND_CNF_CHEN10_Disable (0UL)
- #define IPC_SEND_CNF_CHEN10_Enable (1UL)
- #define IPC_SEND_CNF_CHEN9_Pos (9UL)
- #define IPC_SEND_CNF_CHEN9_Msk (0x1UL << IPC_SEND_CNF_CHEN9_Pos)
- #define IPC_SEND_CNF_CHEN9_Disable (0UL)
- #define IPC_SEND_CNF_CHEN9_Enable (1UL)
- #define IPC_SEND_CNF_CHEN8_Pos (8UL)
- #define IPC_SEND_CNF_CHEN8_Msk (0x1UL << IPC_SEND_CNF_CHEN8_Pos)
- #define IPC_SEND_CNF_CHEN8_Disable (0UL)
- #define IPC_SEND_CNF_CHEN8_Enable (1UL)
- #define IPC_SEND_CNF_CHEN7_Pos (7UL)
- #define IPC_SEND_CNF_CHEN7_Msk (0x1UL << IPC_SEND_CNF_CHEN7_Pos)
- #define IPC_SEND_CNF_CHEN7_Disable (0UL)
- #define IPC_SEND_CNF_CHEN7_Enable (1UL)
- #define IPC_SEND_CNF_CHEN6_Pos (6UL)
- #define IPC_SEND_CNF_CHEN6_Msk (0x1UL << IPC_SEND_CNF_CHEN6_Pos)
- #define IPC_SEND_CNF_CHEN6_Disable (0UL)
- #define IPC_SEND_CNF_CHEN6_Enable (1UL)
- #define IPC_SEND_CNF_CHEN5_Pos (5UL)
- #define IPC_SEND_CNF_CHEN5_Msk (0x1UL << IPC_SEND_CNF_CHEN5_Pos)
- #define IPC_SEND_CNF_CHEN5_Disable (0UL)
- #define IPC_SEND_CNF_CHEN5_Enable (1UL)
- #define IPC_SEND_CNF_CHEN4_Pos (4UL)
- #define IPC_SEND_CNF_CHEN4_Msk (0x1UL << IPC_SEND_CNF_CHEN4_Pos)
- #define IPC_SEND_CNF_CHEN4_Disable (0UL)
- #define IPC_SEND_CNF_CHEN4_Enable (1UL)
- #define IPC_SEND_CNF_CHEN3_Pos (3UL)
- #define IPC_SEND_CNF_CHEN3_Msk (0x1UL << IPC_SEND_CNF_CHEN3_Pos)
- #define IPC_SEND_CNF_CHEN3_Disable (0UL)
- #define IPC_SEND_CNF_CHEN3_Enable (1UL)
- #define IPC_SEND_CNF_CHEN2_Pos (2UL)
- #define IPC_SEND_CNF_CHEN2_Msk (0x1UL << IPC_SEND_CNF_CHEN2_Pos)
- #define IPC_SEND_CNF_CHEN2_Disable (0UL)
- #define IPC_SEND_CNF_CHEN2_Enable (1UL)
- #define IPC_SEND_CNF_CHEN1_Pos (1UL)
- #define IPC_SEND_CNF_CHEN1_Msk (0x1UL << IPC_SEND_CNF_CHEN1_Pos)
- #define IPC_SEND_CNF_CHEN1_Disable (0UL)
- #define IPC_SEND_CNF_CHEN1_Enable (1UL)
- #define IPC_SEND_CNF_CHEN0_Pos (0UL)
- #define IPC_SEND_CNF_CHEN0_Msk (0x1UL << IPC_SEND_CNF_CHEN0_Pos)
- #define IPC_SEND_CNF_CHEN0_Disable (0UL)
- #define IPC_SEND_CNF_CHEN0_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN15_Pos (15UL)
- #define IPC_RECEIVE_CNF_CHEN15_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN15_Pos)
- #define IPC_RECEIVE_CNF_CHEN15_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN15_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN14_Pos (14UL)
- #define IPC_RECEIVE_CNF_CHEN14_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN14_Pos)
- #define IPC_RECEIVE_CNF_CHEN14_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN14_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN13_Pos (13UL)
- #define IPC_RECEIVE_CNF_CHEN13_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN13_Pos)
- #define IPC_RECEIVE_CNF_CHEN13_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN13_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN12_Pos (12UL)
- #define IPC_RECEIVE_CNF_CHEN12_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN12_Pos)
- #define IPC_RECEIVE_CNF_CHEN12_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN12_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN11_Pos (11UL)
- #define IPC_RECEIVE_CNF_CHEN11_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN11_Pos)
- #define IPC_RECEIVE_CNF_CHEN11_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN11_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN10_Pos (10UL)
- #define IPC_RECEIVE_CNF_CHEN10_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN10_Pos)
- #define IPC_RECEIVE_CNF_CHEN10_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN10_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN9_Pos (9UL)
- #define IPC_RECEIVE_CNF_CHEN9_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN9_Pos)
- #define IPC_RECEIVE_CNF_CHEN9_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN9_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN8_Pos (8UL)
- #define IPC_RECEIVE_CNF_CHEN8_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN8_Pos)
- #define IPC_RECEIVE_CNF_CHEN8_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN8_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN7_Pos (7UL)
- #define IPC_RECEIVE_CNF_CHEN7_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN7_Pos)
- #define IPC_RECEIVE_CNF_CHEN7_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN7_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN6_Pos (6UL)
- #define IPC_RECEIVE_CNF_CHEN6_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN6_Pos)
- #define IPC_RECEIVE_CNF_CHEN6_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN6_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN5_Pos (5UL)
- #define IPC_RECEIVE_CNF_CHEN5_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN5_Pos)
- #define IPC_RECEIVE_CNF_CHEN5_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN5_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN4_Pos (4UL)
- #define IPC_RECEIVE_CNF_CHEN4_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN4_Pos)
- #define IPC_RECEIVE_CNF_CHEN4_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN4_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN3_Pos (3UL)
- #define IPC_RECEIVE_CNF_CHEN3_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN3_Pos)
- #define IPC_RECEIVE_CNF_CHEN3_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN3_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN2_Pos (2UL)
- #define IPC_RECEIVE_CNF_CHEN2_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN2_Pos)
- #define IPC_RECEIVE_CNF_CHEN2_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN2_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN1_Pos (1UL)
- #define IPC_RECEIVE_CNF_CHEN1_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN1_Pos)
- #define IPC_RECEIVE_CNF_CHEN1_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN1_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN0_Pos (0UL)
- #define IPC_RECEIVE_CNF_CHEN0_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN0_Pos)
- #define IPC_RECEIVE_CNF_CHEN0_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN0_Enable (1UL)
- #define IPC_GPMEM_GPMEM_Pos (0UL)
- #define IPC_GPMEM_GPMEM_Msk (0xFFFFFFFFUL << IPC_GPMEM_GPMEM_Pos)
- #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos (0UL)
- #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Msk (0x1UL << KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos)
- #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Trigger (1UL)
- #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos (0UL)
- #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos)
- #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_NotGenerated (0UL)
- #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Generated (1UL)
- #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos (0UL)
- #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos)
- #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_NotGenerated (0UL)
- #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Generated (1UL)
- #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos (0UL)
- #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Msk (0x1UL << KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos)
- #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_NotGenerated (0UL)
- #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Generated (1UL)
- #define KMU_INTEN_KEYSLOT_ERROR_Pos (2UL)
- #define KMU_INTEN_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTEN_KEYSLOT_ERROR_Pos)
- #define KMU_INTEN_KEYSLOT_ERROR_Disabled (0UL)
- #define KMU_INTEN_KEYSLOT_ERROR_Enabled (1UL)
- #define KMU_INTEN_KEYSLOT_REVOKED_Pos (1UL)
- #define KMU_INTEN_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTEN_KEYSLOT_REVOKED_Pos)
- #define KMU_INTEN_KEYSLOT_REVOKED_Disabled (0UL)
- #define KMU_INTEN_KEYSLOT_REVOKED_Enabled (1UL)
- #define KMU_INTEN_KEYSLOT_PUSHED_Pos (0UL)
- #define KMU_INTEN_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTEN_KEYSLOT_PUSHED_Pos)
- #define KMU_INTEN_KEYSLOT_PUSHED_Disabled (0UL)
- #define KMU_INTEN_KEYSLOT_PUSHED_Enabled (1UL)
- #define KMU_INTENSET_KEYSLOT_ERROR_Pos (2UL)
- #define KMU_INTENSET_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENSET_KEYSLOT_ERROR_Pos)
- #define KMU_INTENSET_KEYSLOT_ERROR_Disabled (0UL)
- #define KMU_INTENSET_KEYSLOT_ERROR_Enabled (1UL)
- #define KMU_INTENSET_KEYSLOT_ERROR_Set (1UL)
- #define KMU_INTENSET_KEYSLOT_REVOKED_Pos (1UL)
- #define KMU_INTENSET_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_REVOKED_Pos)
- #define KMU_INTENSET_KEYSLOT_REVOKED_Disabled (0UL)
- #define KMU_INTENSET_KEYSLOT_REVOKED_Enabled (1UL)
- #define KMU_INTENSET_KEYSLOT_REVOKED_Set (1UL)
- #define KMU_INTENSET_KEYSLOT_PUSHED_Pos (0UL)
- #define KMU_INTENSET_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_PUSHED_Pos)
- #define KMU_INTENSET_KEYSLOT_PUSHED_Disabled (0UL)
- #define KMU_INTENSET_KEYSLOT_PUSHED_Enabled (1UL)
- #define KMU_INTENSET_KEYSLOT_PUSHED_Set (1UL)
- #define KMU_INTENCLR_KEYSLOT_ERROR_Pos (2UL)
- #define KMU_INTENCLR_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_ERROR_Pos)
- #define KMU_INTENCLR_KEYSLOT_ERROR_Disabled (0UL)
- #define KMU_INTENCLR_KEYSLOT_ERROR_Enabled (1UL)
- #define KMU_INTENCLR_KEYSLOT_ERROR_Clear (1UL)
- #define KMU_INTENCLR_KEYSLOT_REVOKED_Pos (1UL)
- #define KMU_INTENCLR_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_REVOKED_Pos)
- #define KMU_INTENCLR_KEYSLOT_REVOKED_Disabled (0UL)
- #define KMU_INTENCLR_KEYSLOT_REVOKED_Enabled (1UL)
- #define KMU_INTENCLR_KEYSLOT_REVOKED_Clear (1UL)
- #define KMU_INTENCLR_KEYSLOT_PUSHED_Pos (0UL)
- #define KMU_INTENCLR_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_PUSHED_Pos)
- #define KMU_INTENCLR_KEYSLOT_PUSHED_Disabled (0UL)
- #define KMU_INTENCLR_KEYSLOT_PUSHED_Enabled (1UL)
- #define KMU_INTENCLR_KEYSLOT_PUSHED_Clear (1UL)
- #define KMU_INTPEND_KEYSLOT_ERROR_Pos (2UL)
- #define KMU_INTPEND_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTPEND_KEYSLOT_ERROR_Pos)
- #define KMU_INTPEND_KEYSLOT_ERROR_NotPending (0UL)
- #define KMU_INTPEND_KEYSLOT_ERROR_Pending (1UL)
- #define KMU_INTPEND_KEYSLOT_REVOKED_Pos (1UL)
- #define KMU_INTPEND_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_REVOKED_Pos)
- #define KMU_INTPEND_KEYSLOT_REVOKED_NotPending (0UL)
- #define KMU_INTPEND_KEYSLOT_REVOKED_Pending (1UL)
- #define KMU_INTPEND_KEYSLOT_PUSHED_Pos (0UL)
- #define KMU_INTPEND_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_PUSHED_Pos)
- #define KMU_INTPEND_KEYSLOT_PUSHED_NotPending (0UL)
- #define KMU_INTPEND_KEYSLOT_PUSHED_Pending (1UL)
- #define KMU_STATUS_BLOCKED_Pos (1UL)
- #define KMU_STATUS_BLOCKED_Msk (0x1UL << KMU_STATUS_BLOCKED_Pos)
- #define KMU_STATUS_BLOCKED_Disabled (0UL)
- #define KMU_STATUS_BLOCKED_Enabled (1UL)
- #define KMU_STATUS_SELECTED_Pos (0UL)
- #define KMU_STATUS_SELECTED_Msk (0x1UL << KMU_STATUS_SELECTED_Pos)
- #define KMU_STATUS_SELECTED_Disabled (0UL)
- #define KMU_STATUS_SELECTED_Enabled (1UL)
- #define KMU_SELECTKEYSLOT_ID_Pos (0UL)
- #define KMU_SELECTKEYSLOT_ID_Msk (0xFFUL << KMU_SELECTKEYSLOT_ID_Pos)
- #define LPCOMP_TASKS_START_TASKS_START_Pos (0UL)
- #define LPCOMP_TASKS_START_TASKS_START_Msk (0x1UL << LPCOMP_TASKS_START_TASKS_START_Pos)
- #define LPCOMP_TASKS_START_TASKS_START_Trigger (1UL)
- #define LPCOMP_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define LPCOMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << LPCOMP_TASKS_STOP_TASKS_STOP_Pos)
- #define LPCOMP_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL)
- #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos)
- #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL)
- #define LPCOMP_SUBSCRIBE_START_EN_Pos (31UL)
- #define LPCOMP_SUBSCRIBE_START_EN_Msk (0x1UL << LPCOMP_SUBSCRIBE_START_EN_Pos)
- #define LPCOMP_SUBSCRIBE_START_EN_Disabled (0UL)
- #define LPCOMP_SUBSCRIBE_START_EN_Enabled (1UL)
- #define LPCOMP_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define LPCOMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << LPCOMP_SUBSCRIBE_START_CHIDX_Pos)
- #define LPCOMP_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define LPCOMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << LPCOMP_SUBSCRIBE_STOP_EN_Pos)
- #define LPCOMP_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define LPCOMP_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define LPCOMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define LPCOMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << LPCOMP_SUBSCRIBE_STOP_CHIDX_Pos)
- #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Pos (31UL)
- #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << LPCOMP_SUBSCRIBE_SAMPLE_EN_Pos)
- #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Disabled (0UL)
- #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Enabled (1UL)
- #define LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL)
- #define LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Pos)
- #define LPCOMP_EVENTS_READY_EVENTS_READY_Pos (0UL)
- #define LPCOMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << LPCOMP_EVENTS_READY_EVENTS_READY_Pos)
- #define LPCOMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL)
- #define LPCOMP_EVENTS_READY_EVENTS_READY_Generated (1UL)
- #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL)
- #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos)
- #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL)
- #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL)
- #define LPCOMP_EVENTS_UP_EVENTS_UP_Pos (0UL)
- #define LPCOMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << LPCOMP_EVENTS_UP_EVENTS_UP_Pos)
- #define LPCOMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL)
- #define LPCOMP_EVENTS_UP_EVENTS_UP_Generated (1UL)
- #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL)
- #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos)
- #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL)
- #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL)
- #define LPCOMP_PUBLISH_READY_EN_Pos (31UL)
- #define LPCOMP_PUBLISH_READY_EN_Msk (0x1UL << LPCOMP_PUBLISH_READY_EN_Pos)
- #define LPCOMP_PUBLISH_READY_EN_Disabled (0UL)
- #define LPCOMP_PUBLISH_READY_EN_Enabled (1UL)
- #define LPCOMP_PUBLISH_READY_CHIDX_Pos (0UL)
- #define LPCOMP_PUBLISH_READY_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_READY_CHIDX_Pos)
- #define LPCOMP_PUBLISH_DOWN_EN_Pos (31UL)
- #define LPCOMP_PUBLISH_DOWN_EN_Msk (0x1UL << LPCOMP_PUBLISH_DOWN_EN_Pos)
- #define LPCOMP_PUBLISH_DOWN_EN_Disabled (0UL)
- #define LPCOMP_PUBLISH_DOWN_EN_Enabled (1UL)
- #define LPCOMP_PUBLISH_DOWN_CHIDX_Pos (0UL)
- #define LPCOMP_PUBLISH_DOWN_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_DOWN_CHIDX_Pos)
- #define LPCOMP_PUBLISH_UP_EN_Pos (31UL)
- #define LPCOMP_PUBLISH_UP_EN_Msk (0x1UL << LPCOMP_PUBLISH_UP_EN_Pos)
- #define LPCOMP_PUBLISH_UP_EN_Disabled (0UL)
- #define LPCOMP_PUBLISH_UP_EN_Enabled (1UL)
- #define LPCOMP_PUBLISH_UP_CHIDX_Pos (0UL)
- #define LPCOMP_PUBLISH_UP_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_UP_CHIDX_Pos)
- #define LPCOMP_PUBLISH_CROSS_EN_Pos (31UL)
- #define LPCOMP_PUBLISH_CROSS_EN_Msk (0x1UL << LPCOMP_PUBLISH_CROSS_EN_Pos)
- #define LPCOMP_PUBLISH_CROSS_EN_Disabled (0UL)
- #define LPCOMP_PUBLISH_CROSS_EN_Enabled (1UL)
- #define LPCOMP_PUBLISH_CROSS_CHIDX_Pos (0UL)
- #define LPCOMP_PUBLISH_CROSS_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_CROSS_CHIDX_Pos)
- #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL)
- #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos)
- #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL)
- #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL)
- #define LPCOMP_SHORTS_UP_STOP_Pos (3UL)
- #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos)
- #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL)
- #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL)
- #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL)
- #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos)
- #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL)
- #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL)
- #define LPCOMP_SHORTS_READY_STOP_Pos (1UL)
- #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos)
- #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL)
- #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL)
- #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL)
- #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos)
- #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL)
- #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL)
- #define LPCOMP_INTENSET_CROSS_Pos (3UL)
- #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos)
- #define LPCOMP_INTENSET_CROSS_Disabled (0UL)
- #define LPCOMP_INTENSET_CROSS_Enabled (1UL)
- #define LPCOMP_INTENSET_CROSS_Set (1UL)
- #define LPCOMP_INTENSET_UP_Pos (2UL)
- #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos)
- #define LPCOMP_INTENSET_UP_Disabled (0UL)
- #define LPCOMP_INTENSET_UP_Enabled (1UL)
- #define LPCOMP_INTENSET_UP_Set (1UL)
- #define LPCOMP_INTENSET_DOWN_Pos (1UL)
- #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos)
- #define LPCOMP_INTENSET_DOWN_Disabled (0UL)
- #define LPCOMP_INTENSET_DOWN_Enabled (1UL)
- #define LPCOMP_INTENSET_DOWN_Set (1UL)
- #define LPCOMP_INTENSET_READY_Pos (0UL)
- #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos)
- #define LPCOMP_INTENSET_READY_Disabled (0UL)
- #define LPCOMP_INTENSET_READY_Enabled (1UL)
- #define LPCOMP_INTENSET_READY_Set (1UL)
- #define LPCOMP_INTENCLR_CROSS_Pos (3UL)
- #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos)
- #define LPCOMP_INTENCLR_CROSS_Disabled (0UL)
- #define LPCOMP_INTENCLR_CROSS_Enabled (1UL)
- #define LPCOMP_INTENCLR_CROSS_Clear (1UL)
- #define LPCOMP_INTENCLR_UP_Pos (2UL)
- #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos)
- #define LPCOMP_INTENCLR_UP_Disabled (0UL)
- #define LPCOMP_INTENCLR_UP_Enabled (1UL)
- #define LPCOMP_INTENCLR_UP_Clear (1UL)
- #define LPCOMP_INTENCLR_DOWN_Pos (1UL)
- #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos)
- #define LPCOMP_INTENCLR_DOWN_Disabled (0UL)
- #define LPCOMP_INTENCLR_DOWN_Enabled (1UL)
- #define LPCOMP_INTENCLR_DOWN_Clear (1UL)
- #define LPCOMP_INTENCLR_READY_Pos (0UL)
- #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos)
- #define LPCOMP_INTENCLR_READY_Disabled (0UL)
- #define LPCOMP_INTENCLR_READY_Enabled (1UL)
- #define LPCOMP_INTENCLR_READY_Clear (1UL)
- #define LPCOMP_RESULT_RESULT_Pos (0UL)
- #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos)
- #define LPCOMP_RESULT_RESULT_Below (0UL)
- #define LPCOMP_RESULT_RESULT_Above (1UL)
- #define LPCOMP_ENABLE_ENABLE_Pos (0UL)
- #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos)
- #define LPCOMP_ENABLE_ENABLE_Disabled (0UL)
- #define LPCOMP_ENABLE_ENABLE_Enabled (1UL)
- #define LPCOMP_PSEL_PSEL_Pos (0UL)
- #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos)
- #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL)
- #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL)
- #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL)
- #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL)
- #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL)
- #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL)
- #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL)
- #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL)
- #define LPCOMP_REFSEL_REFSEL_Pos (0UL)
- #define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos)
- #define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL)
- #define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL)
- #define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL)
- #define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL)
- #define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL)
- #define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL)
- #define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL)
- #define LPCOMP_REFSEL_REFSEL_ARef (7UL)
- #define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL)
- #define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL)
- #define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL)
- #define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL)
- #define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL)
- #define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL)
- #define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL)
- #define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL)
- #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL)
- #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos)
- #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL)
- #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL)
- #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL)
- #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos)
- #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL)
- #define LPCOMP_ANADETECT_ANADETECT_Up (1UL)
- #define LPCOMP_ANADETECT_ANADETECT_Down (2UL)
- #define LPCOMP_HYST_HYST_Pos (0UL)
- #define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos)
- #define LPCOMP_HYST_HYST_Disabled (0UL)
- #define LPCOMP_HYST_HYST_Enabled (1UL)
- #define MUTEX_MUTEX_MUTEX_Pos (0UL)
- #define MUTEX_MUTEX_MUTEX_Msk (0x1UL << MUTEX_MUTEX_MUTEX_Pos)
- #define MUTEX_MUTEX_MUTEX_Unlocked (0UL)
- #define MUTEX_MUTEX_MUTEX_Locked (1UL)
- #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL)
- #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos)
- #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (1UL)
- #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL)
- #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos)
- #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL)
- #define NFCT_TASKS_SENSE_TASKS_SENSE_Pos (0UL)
- #define NFCT_TASKS_SENSE_TASKS_SENSE_Msk (0x1UL << NFCT_TASKS_SENSE_TASKS_SENSE_Pos)
- #define NFCT_TASKS_SENSE_TASKS_SENSE_Trigger (1UL)
- #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL)
- #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos)
- #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL)
- #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos (0UL)
- #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Msk (0x1UL << NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos)
- #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Trigger (1UL)
- #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos (0UL)
- #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Msk (0x1UL << NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos)
- #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Trigger (1UL)
- #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos (0UL)
- #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Msk (0x1UL << NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos)
- #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Trigger (1UL)
- #define NFCT_SUBSCRIBE_ACTIVATE_EN_Pos (31UL)
- #define NFCT_SUBSCRIBE_ACTIVATE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_ACTIVATE_EN_Pos)
- #define NFCT_SUBSCRIBE_ACTIVATE_EN_Disabled (0UL)
- #define NFCT_SUBSCRIBE_ACTIVATE_EN_Enabled (1UL)
- #define NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Pos (0UL)
- #define NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Pos)
- #define NFCT_SUBSCRIBE_DISABLE_EN_Pos (31UL)
- #define NFCT_SUBSCRIBE_DISABLE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_DISABLE_EN_Pos)
- #define NFCT_SUBSCRIBE_DISABLE_EN_Disabled (0UL)
- #define NFCT_SUBSCRIBE_DISABLE_EN_Enabled (1UL)
- #define NFCT_SUBSCRIBE_DISABLE_CHIDX_Pos (0UL)
- #define NFCT_SUBSCRIBE_DISABLE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_DISABLE_CHIDX_Pos)
- #define NFCT_SUBSCRIBE_SENSE_EN_Pos (31UL)
- #define NFCT_SUBSCRIBE_SENSE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_SENSE_EN_Pos)
- #define NFCT_SUBSCRIBE_SENSE_EN_Disabled (0UL)
- #define NFCT_SUBSCRIBE_SENSE_EN_Enabled (1UL)
- #define NFCT_SUBSCRIBE_SENSE_CHIDX_Pos (0UL)
- #define NFCT_SUBSCRIBE_SENSE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_SENSE_CHIDX_Pos)
- #define NFCT_SUBSCRIBE_STARTTX_EN_Pos (31UL)
- #define NFCT_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << NFCT_SUBSCRIBE_STARTTX_EN_Pos)
- #define NFCT_SUBSCRIBE_STARTTX_EN_Disabled (0UL)
- #define NFCT_SUBSCRIBE_STARTTX_EN_Enabled (1UL)
- #define NFCT_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL)
- #define NFCT_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_STARTTX_CHIDX_Pos)
- #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Pos (31UL)
- #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Msk (0x1UL << NFCT_SUBSCRIBE_ENABLERXDATA_EN_Pos)
- #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Disabled (0UL)
- #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Enabled (1UL)
- #define NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Pos (0UL)
- #define NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Pos)
- #define NFCT_SUBSCRIBE_GOIDLE_EN_Pos (31UL)
- #define NFCT_SUBSCRIBE_GOIDLE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_GOIDLE_EN_Pos)
- #define NFCT_SUBSCRIBE_GOIDLE_EN_Disabled (0UL)
- #define NFCT_SUBSCRIBE_GOIDLE_EN_Enabled (1UL)
- #define NFCT_SUBSCRIBE_GOIDLE_CHIDX_Pos (0UL)
- #define NFCT_SUBSCRIBE_GOIDLE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_GOIDLE_CHIDX_Pos)
- #define NFCT_SUBSCRIBE_GOSLEEP_EN_Pos (31UL)
- #define NFCT_SUBSCRIBE_GOSLEEP_EN_Msk (0x1UL << NFCT_SUBSCRIBE_GOSLEEP_EN_Pos)
- #define NFCT_SUBSCRIBE_GOSLEEP_EN_Disabled (0UL)
- #define NFCT_SUBSCRIBE_GOSLEEP_EN_Enabled (1UL)
- #define NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Pos (0UL)
- #define NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Pos)
- #define NFCT_EVENTS_READY_EVENTS_READY_Pos (0UL)
- #define NFCT_EVENTS_READY_EVENTS_READY_Msk (0x1UL << NFCT_EVENTS_READY_EVENTS_READY_Pos)
- #define NFCT_EVENTS_READY_EVENTS_READY_NotGenerated (0UL)
- #define NFCT_EVENTS_READY_EVENTS_READY_Generated (1UL)
- #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos (0UL)
- #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Msk (0x1UL << NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos)
- #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_NotGenerated (0UL)
- #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Generated (1UL)
- #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos (0UL)
- #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Msk (0x1UL << NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos)
- #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_NotGenerated (0UL)
- #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Generated (1UL)
- #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos (0UL)
- #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos)
- #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_NotGenerated (0UL)
- #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Generated (1UL)
- #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos (0UL)
- #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos)
- #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_NotGenerated (0UL)
- #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Generated (1UL)
- #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos (0UL)
- #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos)
- #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_NotGenerated (0UL)
- #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Generated (1UL)
- #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos (0UL)
- #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos)
- #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_NotGenerated (0UL)
- #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Generated (1UL)
- #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)
- #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos)
- #define NFCT_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL)
- #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL)
- #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos (0UL)
- #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Msk (0x1UL << NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos)
- #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_NotGenerated (0UL)
- #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Generated (1UL)
- #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL)
- #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos)
- #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL)
- #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL)
- #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL)
- #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos)
- #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL)
- #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL)
- #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos (0UL)
- #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos)
- #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_NotGenerated (0UL)
- #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Generated (1UL)
- #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos (0UL)
- #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Msk (0x1UL << NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos)
- #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_NotGenerated (0UL)
- #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Generated (1UL)
- #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos (0UL)
- #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Msk (0x1UL << NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos)
- #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_NotGenerated (0UL)
- #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Generated (1UL)
- #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL)
- #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos)
- #define NFCT_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL)
- #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL)
- #define NFCT_PUBLISH_READY_EN_Pos (31UL)
- #define NFCT_PUBLISH_READY_EN_Msk (0x1UL << NFCT_PUBLISH_READY_EN_Pos)
- #define NFCT_PUBLISH_READY_EN_Disabled (0UL)
- #define NFCT_PUBLISH_READY_EN_Enabled (1UL)
- #define NFCT_PUBLISH_READY_CHIDX_Pos (0UL)
- #define NFCT_PUBLISH_READY_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_READY_CHIDX_Pos)
- #define NFCT_PUBLISH_FIELDDETECTED_EN_Pos (31UL)
- #define NFCT_PUBLISH_FIELDDETECTED_EN_Msk (0x1UL << NFCT_PUBLISH_FIELDDETECTED_EN_Pos)
- #define NFCT_PUBLISH_FIELDDETECTED_EN_Disabled (0UL)
- #define NFCT_PUBLISH_FIELDDETECTED_EN_Enabled (1UL)
- #define NFCT_PUBLISH_FIELDDETECTED_CHIDX_Pos (0UL)
- #define NFCT_PUBLISH_FIELDDETECTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_FIELDDETECTED_CHIDX_Pos)
- #define NFCT_PUBLISH_FIELDLOST_EN_Pos (31UL)
- #define NFCT_PUBLISH_FIELDLOST_EN_Msk (0x1UL << NFCT_PUBLISH_FIELDLOST_EN_Pos)
- #define NFCT_PUBLISH_FIELDLOST_EN_Disabled (0UL)
- #define NFCT_PUBLISH_FIELDLOST_EN_Enabled (1UL)
- #define NFCT_PUBLISH_FIELDLOST_CHIDX_Pos (0UL)
- #define NFCT_PUBLISH_FIELDLOST_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_FIELDLOST_CHIDX_Pos)
- #define NFCT_PUBLISH_TXFRAMESTART_EN_Pos (31UL)
- #define NFCT_PUBLISH_TXFRAMESTART_EN_Msk (0x1UL << NFCT_PUBLISH_TXFRAMESTART_EN_Pos)
- #define NFCT_PUBLISH_TXFRAMESTART_EN_Disabled (0UL)
- #define NFCT_PUBLISH_TXFRAMESTART_EN_Enabled (1UL)
- #define NFCT_PUBLISH_TXFRAMESTART_CHIDX_Pos (0UL)
- #define NFCT_PUBLISH_TXFRAMESTART_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_TXFRAMESTART_CHIDX_Pos)
- #define NFCT_PUBLISH_TXFRAMEEND_EN_Pos (31UL)
- #define NFCT_PUBLISH_TXFRAMEEND_EN_Msk (0x1UL << NFCT_PUBLISH_TXFRAMEEND_EN_Pos)
- #define NFCT_PUBLISH_TXFRAMEEND_EN_Disabled (0UL)
- #define NFCT_PUBLISH_TXFRAMEEND_EN_Enabled (1UL)
- #define NFCT_PUBLISH_TXFRAMEEND_CHIDX_Pos (0UL)
- #define NFCT_PUBLISH_TXFRAMEEND_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_TXFRAMEEND_CHIDX_Pos)
- #define NFCT_PUBLISH_RXFRAMESTART_EN_Pos (31UL)
- #define NFCT_PUBLISH_RXFRAMESTART_EN_Msk (0x1UL << NFCT_PUBLISH_RXFRAMESTART_EN_Pos)
- #define NFCT_PUBLISH_RXFRAMESTART_EN_Disabled (0UL)
- #define NFCT_PUBLISH_RXFRAMESTART_EN_Enabled (1UL)
- #define NFCT_PUBLISH_RXFRAMESTART_CHIDX_Pos (0UL)
- #define NFCT_PUBLISH_RXFRAMESTART_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_RXFRAMESTART_CHIDX_Pos)
- #define NFCT_PUBLISH_RXFRAMEEND_EN_Pos (31UL)
- #define NFCT_PUBLISH_RXFRAMEEND_EN_Msk (0x1UL << NFCT_PUBLISH_RXFRAMEEND_EN_Pos)
- #define NFCT_PUBLISH_RXFRAMEEND_EN_Disabled (0UL)
- #define NFCT_PUBLISH_RXFRAMEEND_EN_Enabled (1UL)
- #define NFCT_PUBLISH_RXFRAMEEND_CHIDX_Pos (0UL)
- #define NFCT_PUBLISH_RXFRAMEEND_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_RXFRAMEEND_CHIDX_Pos)
- #define NFCT_PUBLISH_ERROR_EN_Pos (31UL)
- #define NFCT_PUBLISH_ERROR_EN_Msk (0x1UL << NFCT_PUBLISH_ERROR_EN_Pos)
- #define NFCT_PUBLISH_ERROR_EN_Disabled (0UL)
- #define NFCT_PUBLISH_ERROR_EN_Enabled (1UL)
- #define NFCT_PUBLISH_ERROR_CHIDX_Pos (0UL)
- #define NFCT_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_ERROR_CHIDX_Pos)
- #define NFCT_PUBLISH_RXERROR_EN_Pos (31UL)
- #define NFCT_PUBLISH_RXERROR_EN_Msk (0x1UL << NFCT_PUBLISH_RXERROR_EN_Pos)
- #define NFCT_PUBLISH_RXERROR_EN_Disabled (0UL)
- #define NFCT_PUBLISH_RXERROR_EN_Enabled (1UL)
- #define NFCT_PUBLISH_RXERROR_CHIDX_Pos (0UL)
- #define NFCT_PUBLISH_RXERROR_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_RXERROR_CHIDX_Pos)
- #define NFCT_PUBLISH_ENDRX_EN_Pos (31UL)
- #define NFCT_PUBLISH_ENDRX_EN_Msk (0x1UL << NFCT_PUBLISH_ENDRX_EN_Pos)
- #define NFCT_PUBLISH_ENDRX_EN_Disabled (0UL)
- #define NFCT_PUBLISH_ENDRX_EN_Enabled (1UL)
- #define NFCT_PUBLISH_ENDRX_CHIDX_Pos (0UL)
- #define NFCT_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_ENDRX_CHIDX_Pos)
- #define NFCT_PUBLISH_ENDTX_EN_Pos (31UL)
- #define NFCT_PUBLISH_ENDTX_EN_Msk (0x1UL << NFCT_PUBLISH_ENDTX_EN_Pos)
- #define NFCT_PUBLISH_ENDTX_EN_Disabled (0UL)
- #define NFCT_PUBLISH_ENDTX_EN_Enabled (1UL)
- #define NFCT_PUBLISH_ENDTX_CHIDX_Pos (0UL)
- #define NFCT_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_ENDTX_CHIDX_Pos)
- #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Pos (31UL)
- #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Msk (0x1UL << NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Pos)
- #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Disabled (0UL)
- #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Enabled (1UL)
- #define NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Pos (0UL)
- #define NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Pos)
- #define NFCT_PUBLISH_COLLISION_EN_Pos (31UL)
- #define NFCT_PUBLISH_COLLISION_EN_Msk (0x1UL << NFCT_PUBLISH_COLLISION_EN_Pos)
- #define NFCT_PUBLISH_COLLISION_EN_Disabled (0UL)
- #define NFCT_PUBLISH_COLLISION_EN_Enabled (1UL)
- #define NFCT_PUBLISH_COLLISION_CHIDX_Pos (0UL)
- #define NFCT_PUBLISH_COLLISION_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_COLLISION_CHIDX_Pos)
- #define NFCT_PUBLISH_SELECTED_EN_Pos (31UL)
- #define NFCT_PUBLISH_SELECTED_EN_Msk (0x1UL << NFCT_PUBLISH_SELECTED_EN_Pos)
- #define NFCT_PUBLISH_SELECTED_EN_Disabled (0UL)
- #define NFCT_PUBLISH_SELECTED_EN_Enabled (1UL)
- #define NFCT_PUBLISH_SELECTED_CHIDX_Pos (0UL)
- #define NFCT_PUBLISH_SELECTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_SELECTED_CHIDX_Pos)
- #define NFCT_PUBLISH_STARTED_EN_Pos (31UL)
- #define NFCT_PUBLISH_STARTED_EN_Msk (0x1UL << NFCT_PUBLISH_STARTED_EN_Pos)
- #define NFCT_PUBLISH_STARTED_EN_Disabled (0UL)
- #define NFCT_PUBLISH_STARTED_EN_Enabled (1UL)
- #define NFCT_PUBLISH_STARTED_CHIDX_Pos (0UL)
- #define NFCT_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_STARTED_CHIDX_Pos)
- #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos (5UL)
- #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk (0x1UL << NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos)
- #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Disabled (0UL)
- #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Enabled (1UL)
- #define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL)
- #define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos)
- #define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL)
- #define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL)
- #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL)
- #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos)
- #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL)
- #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL)
- #define NFCT_INTEN_STARTED_Pos (20UL)
- #define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos)
- #define NFCT_INTEN_STARTED_Disabled (0UL)
- #define NFCT_INTEN_STARTED_Enabled (1UL)
- #define NFCT_INTEN_SELECTED_Pos (19UL)
- #define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos)
- #define NFCT_INTEN_SELECTED_Disabled (0UL)
- #define NFCT_INTEN_SELECTED_Enabled (1UL)
- #define NFCT_INTEN_COLLISION_Pos (18UL)
- #define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos)
- #define NFCT_INTEN_COLLISION_Disabled (0UL)
- #define NFCT_INTEN_COLLISION_Enabled (1UL)
- #define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL)
- #define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos)
- #define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL)
- #define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL)
- #define NFCT_INTEN_ENDTX_Pos (12UL)
- #define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos)
- #define NFCT_INTEN_ENDTX_Disabled (0UL)
- #define NFCT_INTEN_ENDTX_Enabled (1UL)
- #define NFCT_INTEN_ENDRX_Pos (11UL)
- #define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos)
- #define NFCT_INTEN_ENDRX_Disabled (0UL)
- #define NFCT_INTEN_ENDRX_Enabled (1UL)
- #define NFCT_INTEN_RXERROR_Pos (10UL)
- #define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos)
- #define NFCT_INTEN_RXERROR_Disabled (0UL)
- #define NFCT_INTEN_RXERROR_Enabled (1UL)
- #define NFCT_INTEN_ERROR_Pos (7UL)
- #define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos)
- #define NFCT_INTEN_ERROR_Disabled (0UL)
- #define NFCT_INTEN_ERROR_Enabled (1UL)
- #define NFCT_INTEN_RXFRAMEEND_Pos (6UL)
- #define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos)
- #define NFCT_INTEN_RXFRAMEEND_Disabled (0UL)
- #define NFCT_INTEN_RXFRAMEEND_Enabled (1UL)
- #define NFCT_INTEN_RXFRAMESTART_Pos (5UL)
- #define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos)
- #define NFCT_INTEN_RXFRAMESTART_Disabled (0UL)
- #define NFCT_INTEN_RXFRAMESTART_Enabled (1UL)
- #define NFCT_INTEN_TXFRAMEEND_Pos (4UL)
- #define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos)
- #define NFCT_INTEN_TXFRAMEEND_Disabled (0UL)
- #define NFCT_INTEN_TXFRAMEEND_Enabled (1UL)
- #define NFCT_INTEN_TXFRAMESTART_Pos (3UL)
- #define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos)
- #define NFCT_INTEN_TXFRAMESTART_Disabled (0UL)
- #define NFCT_INTEN_TXFRAMESTART_Enabled (1UL)
- #define NFCT_INTEN_FIELDLOST_Pos (2UL)
- #define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos)
- #define NFCT_INTEN_FIELDLOST_Disabled (0UL)
- #define NFCT_INTEN_FIELDLOST_Enabled (1UL)
- #define NFCT_INTEN_FIELDDETECTED_Pos (1UL)
- #define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos)
- #define NFCT_INTEN_FIELDDETECTED_Disabled (0UL)
- #define NFCT_INTEN_FIELDDETECTED_Enabled (1UL)
- #define NFCT_INTEN_READY_Pos (0UL)
- #define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos)
- #define NFCT_INTEN_READY_Disabled (0UL)
- #define NFCT_INTEN_READY_Enabled (1UL)
- #define NFCT_INTENSET_STARTED_Pos (20UL)
- #define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos)
- #define NFCT_INTENSET_STARTED_Disabled (0UL)
- #define NFCT_INTENSET_STARTED_Enabled (1UL)
- #define NFCT_INTENSET_STARTED_Set (1UL)
- #define NFCT_INTENSET_SELECTED_Pos (19UL)
- #define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos)
- #define NFCT_INTENSET_SELECTED_Disabled (0UL)
- #define NFCT_INTENSET_SELECTED_Enabled (1UL)
- #define NFCT_INTENSET_SELECTED_Set (1UL)
- #define NFCT_INTENSET_COLLISION_Pos (18UL)
- #define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos)
- #define NFCT_INTENSET_COLLISION_Disabled (0UL)
- #define NFCT_INTENSET_COLLISION_Enabled (1UL)
- #define NFCT_INTENSET_COLLISION_Set (1UL)
- #define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL)
- #define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos)
- #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL)
- #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL)
- #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL)
- #define NFCT_INTENSET_ENDTX_Pos (12UL)
- #define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos)
- #define NFCT_INTENSET_ENDTX_Disabled (0UL)
- #define NFCT_INTENSET_ENDTX_Enabled (1UL)
- #define NFCT_INTENSET_ENDTX_Set (1UL)
- #define NFCT_INTENSET_ENDRX_Pos (11UL)
- #define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos)
- #define NFCT_INTENSET_ENDRX_Disabled (0UL)
- #define NFCT_INTENSET_ENDRX_Enabled (1UL)
- #define NFCT_INTENSET_ENDRX_Set (1UL)
- #define NFCT_INTENSET_RXERROR_Pos (10UL)
- #define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos)
- #define NFCT_INTENSET_RXERROR_Disabled (0UL)
- #define NFCT_INTENSET_RXERROR_Enabled (1UL)
- #define NFCT_INTENSET_RXERROR_Set (1UL)
- #define NFCT_INTENSET_ERROR_Pos (7UL)
- #define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos)
- #define NFCT_INTENSET_ERROR_Disabled (0UL)
- #define NFCT_INTENSET_ERROR_Enabled (1UL)
- #define NFCT_INTENSET_ERROR_Set (1UL)
- #define NFCT_INTENSET_RXFRAMEEND_Pos (6UL)
- #define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos)
- #define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL)
- #define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL)
- #define NFCT_INTENSET_RXFRAMEEND_Set (1UL)
- #define NFCT_INTENSET_RXFRAMESTART_Pos (5UL)
- #define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos)
- #define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL)
- #define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL)
- #define NFCT_INTENSET_RXFRAMESTART_Set (1UL)
- #define NFCT_INTENSET_TXFRAMEEND_Pos (4UL)
- #define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos)
- #define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL)
- #define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL)
- #define NFCT_INTENSET_TXFRAMEEND_Set (1UL)
- #define NFCT_INTENSET_TXFRAMESTART_Pos (3UL)
- #define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos)
- #define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL)
- #define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL)
- #define NFCT_INTENSET_TXFRAMESTART_Set (1UL)
- #define NFCT_INTENSET_FIELDLOST_Pos (2UL)
- #define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos)
- #define NFCT_INTENSET_FIELDLOST_Disabled (0UL)
- #define NFCT_INTENSET_FIELDLOST_Enabled (1UL)
- #define NFCT_INTENSET_FIELDLOST_Set (1UL)
- #define NFCT_INTENSET_FIELDDETECTED_Pos (1UL)
- #define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos)
- #define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL)
- #define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL)
- #define NFCT_INTENSET_FIELDDETECTED_Set (1UL)
- #define NFCT_INTENSET_READY_Pos (0UL)
- #define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos)
- #define NFCT_INTENSET_READY_Disabled (0UL)
- #define NFCT_INTENSET_READY_Enabled (1UL)
- #define NFCT_INTENSET_READY_Set (1UL)
- #define NFCT_INTENCLR_STARTED_Pos (20UL)
- #define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos)
- #define NFCT_INTENCLR_STARTED_Disabled (0UL)
- #define NFCT_INTENCLR_STARTED_Enabled (1UL)
- #define NFCT_INTENCLR_STARTED_Clear (1UL)
- #define NFCT_INTENCLR_SELECTED_Pos (19UL)
- #define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos)
- #define NFCT_INTENCLR_SELECTED_Disabled (0UL)
- #define NFCT_INTENCLR_SELECTED_Enabled (1UL)
- #define NFCT_INTENCLR_SELECTED_Clear (1UL)
- #define NFCT_INTENCLR_COLLISION_Pos (18UL)
- #define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos)
- #define NFCT_INTENCLR_COLLISION_Disabled (0UL)
- #define NFCT_INTENCLR_COLLISION_Enabled (1UL)
- #define NFCT_INTENCLR_COLLISION_Clear (1UL)
- #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL)
- #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos)
- #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL)
- #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL)
- #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL)
- #define NFCT_INTENCLR_ENDTX_Pos (12UL)
- #define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos)
- #define NFCT_INTENCLR_ENDTX_Disabled (0UL)
- #define NFCT_INTENCLR_ENDTX_Enabled (1UL)
- #define NFCT_INTENCLR_ENDTX_Clear (1UL)
- #define NFCT_INTENCLR_ENDRX_Pos (11UL)
- #define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos)
- #define NFCT_INTENCLR_ENDRX_Disabled (0UL)
- #define NFCT_INTENCLR_ENDRX_Enabled (1UL)
- #define NFCT_INTENCLR_ENDRX_Clear (1UL)
- #define NFCT_INTENCLR_RXERROR_Pos (10UL)
- #define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos)
- #define NFCT_INTENCLR_RXERROR_Disabled (0UL)
- #define NFCT_INTENCLR_RXERROR_Enabled (1UL)
- #define NFCT_INTENCLR_RXERROR_Clear (1UL)
- #define NFCT_INTENCLR_ERROR_Pos (7UL)
- #define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos)
- #define NFCT_INTENCLR_ERROR_Disabled (0UL)
- #define NFCT_INTENCLR_ERROR_Enabled (1UL)
- #define NFCT_INTENCLR_ERROR_Clear (1UL)
- #define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL)
- #define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos)
- #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL)
- #define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL)
- #define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL)
- #define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL)
- #define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos)
- #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL)
- #define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL)
- #define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL)
- #define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL)
- #define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos)
- #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL)
- #define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL)
- #define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL)
- #define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL)
- #define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos)
- #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL)
- #define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL)
- #define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL)
- #define NFCT_INTENCLR_FIELDLOST_Pos (2UL)
- #define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos)
- #define NFCT_INTENCLR_FIELDLOST_Disabled (0UL)
- #define NFCT_INTENCLR_FIELDLOST_Enabled (1UL)
- #define NFCT_INTENCLR_FIELDLOST_Clear (1UL)
- #define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL)
- #define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos)
- #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL)
- #define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL)
- #define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL)
- #define NFCT_INTENCLR_READY_Pos (0UL)
- #define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos)
- #define NFCT_INTENCLR_READY_Disabled (0UL)
- #define NFCT_INTENCLR_READY_Enabled (1UL)
- #define NFCT_INTENCLR_READY_Clear (1UL)
- #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL)
- #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos)
- #define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL)
- #define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos)
- #define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL)
- #define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL)
- #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL)
- #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos)
- #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL)
- #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL)
- #define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL)
- #define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos)
- #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL)
- #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL)
- #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos (0UL)
- #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk (0x7UL << NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos)
- #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Disabled (0UL)
- #define NFCT_NFCTAGSTATE_NFCTAGSTATE_RampUp (2UL)
- #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Idle (3UL)
- #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Receive (4UL)
- #define NFCT_NFCTAGSTATE_NFCTAGSTATE_FrameDelay (5UL)
- #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Transmit (6UL)
- #define NFCT_SLEEPSTATE_SLEEPSTATE_Pos (0UL)
- #define NFCT_SLEEPSTATE_SLEEPSTATE_Msk (0x1UL << NFCT_SLEEPSTATE_SLEEPSTATE_Pos)
- #define NFCT_SLEEPSTATE_SLEEPSTATE_Idle (0UL)
- #define NFCT_SLEEPSTATE_SLEEPSTATE_SleepA (1UL)
- #define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL)
- #define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos)
- #define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL)
- #define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL)
- #define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL)
- #define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos)
- #define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL)
- #define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL)
- #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL)
- #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos)
- #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL)
- #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos)
- #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL)
- #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos)
- #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL)
- #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL)
- #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL)
- #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL)
- #define NFCT_PACKETPTR_PTR_Pos (0UL)
- #define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos)
- #define NFCT_MAXLEN_MAXLEN_Pos (0UL)
- #define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos)
- #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL)
- #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos)
- #define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL)
- #define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL)
- #define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL)
- #define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos)
- #define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL)
- #define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL)
- #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL)
- #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos)
- #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL)
- #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL)
- #define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL)
- #define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos)
- #define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL)
- #define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL)
- #define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL)
- #define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos)
- #define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL)
- #define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos)
- #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL)
- #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos)
- #define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL)
- #define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL)
- #define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL)
- #define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos)
- #define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL)
- #define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL)
- #define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL)
- #define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos)
- #define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL)
- #define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL)
- #define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL)
- #define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos)
- #define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL)
- #define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos)
- #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Pos (0UL)
- #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Msk (0x3UL << NFCT_MODULATIONCTRL_MODULATIONCTRL_Pos)
- #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Invalid (0x0UL)
- #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Internal (0x1UL)
- #define NFCT_MODULATIONCTRL_MODULATIONCTRL_ModToGpio (0x2UL)
- #define NFCT_MODULATIONCTRL_MODULATIONCTRL_InternalAndModToGpio (0x3UL)
- #define NFCT_MODULATIONPSEL_CONNECT_Pos (31UL)
- #define NFCT_MODULATIONPSEL_CONNECT_Msk (0x1UL << NFCT_MODULATIONPSEL_CONNECT_Pos)
- #define NFCT_MODULATIONPSEL_CONNECT_Connected (0UL)
- #define NFCT_MODULATIONPSEL_CONNECT_Disconnected (1UL)
- #define NFCT_MODULATIONPSEL_PORT_Pos (5UL)
- #define NFCT_MODULATIONPSEL_PORT_Msk (0x3UL << NFCT_MODULATIONPSEL_PORT_Pos)
- #define NFCT_MODULATIONPSEL_PIN_Pos (0UL)
- #define NFCT_MODULATIONPSEL_PIN_Msk (0x1FUL << NFCT_MODULATIONPSEL_PIN_Pos)
- #define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL)
- #define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos)
- #define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL)
- #define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos)
- #define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL)
- #define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos)
- #define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL)
- #define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos)
- #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL)
- #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos)
- #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL)
- #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos)
- #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL)
- #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos)
- #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL)
- #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos)
- #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL)
- #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos)
- #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL)
- #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos)
- #define NFCT_AUTOCOLRESCONFIG_MODE_Pos (0UL)
- #define NFCT_AUTOCOLRESCONFIG_MODE_Msk (0x1UL << NFCT_AUTOCOLRESCONFIG_MODE_Pos)
- #define NFCT_AUTOCOLRESCONFIG_MODE_Enabled (0UL)
- #define NFCT_AUTOCOLRESCONFIG_MODE_Disabled (1UL)
- #define NFCT_SENSRES_RFU74_Pos (12UL)
- #define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos)
- #define NFCT_SENSRES_PLATFCONFIG_Pos (8UL)
- #define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos)
- #define NFCT_SENSRES_NFCIDSIZE_Pos (6UL)
- #define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos)
- #define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL)
- #define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL)
- #define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL)
- #define NFCT_SENSRES_RFU5_Pos (5UL)
- #define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos)
- #define NFCT_SENSRES_BITFRAMESDD_Pos (0UL)
- #define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos)
- #define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL)
- #define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL)
- #define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL)
- #define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL)
- #define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL)
- #define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL)
- #define NFCT_SELRES_RFU7_Pos (7UL)
- #define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos)
- #define NFCT_SELRES_PROTOCOL_Pos (5UL)
- #define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos)
- #define NFCT_SELRES_RFU43_Pos (3UL)
- #define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos)
- #define NFCT_SELRES_CASCADE_Pos (2UL)
- #define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos)
- #define NFCT_SELRES_RFU10_Pos (0UL)
- #define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos)
- #define NVMC_READY_READY_Pos (0UL)
- #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos)
- #define NVMC_READY_READY_Busy (0UL)
- #define NVMC_READY_READY_Ready (1UL)
- #define NVMC_READYNEXT_READYNEXT_Pos (0UL)
- #define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos)
- #define NVMC_READYNEXT_READYNEXT_Busy (0UL)
- #define NVMC_READYNEXT_READYNEXT_Ready (1UL)
- #define NVMC_CONFIG_WEN_Pos (0UL)
- #define NVMC_CONFIG_WEN_Msk (0x7UL << NVMC_CONFIG_WEN_Pos)
- #define NVMC_CONFIG_WEN_Ren (0UL)
- #define NVMC_CONFIG_WEN_Wen (1UL)
- #define NVMC_CONFIG_WEN_Een (2UL)
- #define NVMC_CONFIG_WEN_PEen (4UL)
- #define NVMC_ERASEALL_ERASEALL_Pos (0UL)
- #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos)
- #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL)
- #define NVMC_ERASEALL_ERASEALL_Erase (1UL)
- #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL)
- #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos)
- #define NVMC_CONFIGNS_WEN_Pos (0UL)
- #define NVMC_CONFIGNS_WEN_Msk (0x3UL << NVMC_CONFIGNS_WEN_Pos)
- #define NVMC_CONFIGNS_WEN_Ren (0UL)
- #define NVMC_CONFIGNS_WEN_Wen (1UL)
- #define NVMC_CONFIGNS_WEN_Een (2UL)
- #define NVMC_WRITEUICRNS_KEY_Pos (4UL)
- #define NVMC_WRITEUICRNS_KEY_Msk (0xFFFFFFFUL << NVMC_WRITEUICRNS_KEY_Pos)
- #define NVMC_WRITEUICRNS_KEY_Keyvalid (0xAFBE5A7UL)
- #define NVMC_WRITEUICRNS_SET_Pos (0UL)
- #define NVMC_WRITEUICRNS_SET_Msk (0x1UL << NVMC_WRITEUICRNS_SET_Pos)
- #define NVMC_WRITEUICRNS_SET_Set (1UL)
- #define OSCILLATORS_XOSC32MCAPS_ENABLE_Pos (8UL)
- #define OSCILLATORS_XOSC32MCAPS_ENABLE_Msk (0x1UL << OSCILLATORS_XOSC32MCAPS_ENABLE_Pos)
- #define OSCILLATORS_XOSC32MCAPS_ENABLE_Disabled (0UL)
- #define OSCILLATORS_XOSC32MCAPS_ENABLE_Enabled (1UL)
- #define OSCILLATORS_XOSC32MCAPS_CAPVALUE_Pos (0UL)
- #define OSCILLATORS_XOSC32MCAPS_CAPVALUE_Msk (0x1FUL << OSCILLATORS_XOSC32MCAPS_CAPVALUE_Pos)
- #define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Pos (0UL)
- #define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Msk (0x1UL << OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Pos)
- #define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Disabled (0UL)
- #define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Enabled (1UL)
- #define OSCILLATORS_XOSC32KI_INTCAP_INTCAP_Pos (0UL)
- #define OSCILLATORS_XOSC32KI_INTCAP_INTCAP_Msk (0x3UL << OSCILLATORS_XOSC32KI_INTCAP_INTCAP_Pos)
- #define OSCILLATORS_XOSC32KI_INTCAP_INTCAP_External (0UL)
- #define OSCILLATORS_XOSC32KI_INTCAP_INTCAP_C6PF (1UL)
- #define OSCILLATORS_XOSC32KI_INTCAP_INTCAP_C7PF (2UL)
- #define OSCILLATORS_XOSC32KI_INTCAP_INTCAP_C11PF (3UL)
- #define GPIO_OUT_PIN31_Pos (31UL)
- #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos)
- #define GPIO_OUT_PIN31_Low (0UL)
- #define GPIO_OUT_PIN31_High (1UL)
- #define GPIO_OUT_PIN30_Pos (30UL)
- #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos)
- #define GPIO_OUT_PIN30_Low (0UL)
- #define GPIO_OUT_PIN30_High (1UL)
- #define GPIO_OUT_PIN29_Pos (29UL)
- #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos)
- #define GPIO_OUT_PIN29_Low (0UL)
- #define GPIO_OUT_PIN29_High (1UL)
- #define GPIO_OUT_PIN28_Pos (28UL)
- #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos)
- #define GPIO_OUT_PIN28_Low (0UL)
- #define GPIO_OUT_PIN28_High (1UL)
- #define GPIO_OUT_PIN27_Pos (27UL)
- #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos)
- #define GPIO_OUT_PIN27_Low (0UL)
- #define GPIO_OUT_PIN27_High (1UL)
- #define GPIO_OUT_PIN26_Pos (26UL)
- #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos)
- #define GPIO_OUT_PIN26_Low (0UL)
- #define GPIO_OUT_PIN26_High (1UL)
- #define GPIO_OUT_PIN25_Pos (25UL)
- #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos)
- #define GPIO_OUT_PIN25_Low (0UL)
- #define GPIO_OUT_PIN25_High (1UL)
- #define GPIO_OUT_PIN24_Pos (24UL)
- #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos)
- #define GPIO_OUT_PIN24_Low (0UL)
- #define GPIO_OUT_PIN24_High (1UL)
- #define GPIO_OUT_PIN23_Pos (23UL)
- #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos)
- #define GPIO_OUT_PIN23_Low (0UL)
- #define GPIO_OUT_PIN23_High (1UL)
- #define GPIO_OUT_PIN22_Pos (22UL)
- #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos)
- #define GPIO_OUT_PIN22_Low (0UL)
- #define GPIO_OUT_PIN22_High (1UL)
- #define GPIO_OUT_PIN21_Pos (21UL)
- #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos)
- #define GPIO_OUT_PIN21_Low (0UL)
- #define GPIO_OUT_PIN21_High (1UL)
- #define GPIO_OUT_PIN20_Pos (20UL)
- #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos)
- #define GPIO_OUT_PIN20_Low (0UL)
- #define GPIO_OUT_PIN20_High (1UL)
- #define GPIO_OUT_PIN19_Pos (19UL)
- #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos)
- #define GPIO_OUT_PIN19_Low (0UL)
- #define GPIO_OUT_PIN19_High (1UL)
- #define GPIO_OUT_PIN18_Pos (18UL)
- #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos)
- #define GPIO_OUT_PIN18_Low (0UL)
- #define GPIO_OUT_PIN18_High (1UL)
- #define GPIO_OUT_PIN17_Pos (17UL)
- #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos)
- #define GPIO_OUT_PIN17_Low (0UL)
- #define GPIO_OUT_PIN17_High (1UL)
- #define GPIO_OUT_PIN16_Pos (16UL)
- #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos)
- #define GPIO_OUT_PIN16_Low (0UL)
- #define GPIO_OUT_PIN16_High (1UL)
- #define GPIO_OUT_PIN15_Pos (15UL)
- #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos)
- #define GPIO_OUT_PIN15_Low (0UL)
- #define GPIO_OUT_PIN15_High (1UL)
- #define GPIO_OUT_PIN14_Pos (14UL)
- #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos)
- #define GPIO_OUT_PIN14_Low (0UL)
- #define GPIO_OUT_PIN14_High (1UL)
- #define GPIO_OUT_PIN13_Pos (13UL)
- #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos)
- #define GPIO_OUT_PIN13_Low (0UL)
- #define GPIO_OUT_PIN13_High (1UL)
- #define GPIO_OUT_PIN12_Pos (12UL)
- #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos)
- #define GPIO_OUT_PIN12_Low (0UL)
- #define GPIO_OUT_PIN12_High (1UL)
- #define GPIO_OUT_PIN11_Pos (11UL)
- #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos)
- #define GPIO_OUT_PIN11_Low (0UL)
- #define GPIO_OUT_PIN11_High (1UL)
- #define GPIO_OUT_PIN10_Pos (10UL)
- #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos)
- #define GPIO_OUT_PIN10_Low (0UL)
- #define GPIO_OUT_PIN10_High (1UL)
- #define GPIO_OUT_PIN9_Pos (9UL)
- #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos)
- #define GPIO_OUT_PIN9_Low (0UL)
- #define GPIO_OUT_PIN9_High (1UL)
- #define GPIO_OUT_PIN8_Pos (8UL)
- #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos)
- #define GPIO_OUT_PIN8_Low (0UL)
- #define GPIO_OUT_PIN8_High (1UL)
- #define GPIO_OUT_PIN7_Pos (7UL)
- #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos)
- #define GPIO_OUT_PIN7_Low (0UL)
- #define GPIO_OUT_PIN7_High (1UL)
- #define GPIO_OUT_PIN6_Pos (6UL)
- #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos)
- #define GPIO_OUT_PIN6_Low (0UL)
- #define GPIO_OUT_PIN6_High (1UL)
- #define GPIO_OUT_PIN5_Pos (5UL)
- #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos)
- #define GPIO_OUT_PIN5_Low (0UL)
- #define GPIO_OUT_PIN5_High (1UL)
- #define GPIO_OUT_PIN4_Pos (4UL)
- #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos)
- #define GPIO_OUT_PIN4_Low (0UL)
- #define GPIO_OUT_PIN4_High (1UL)
- #define GPIO_OUT_PIN3_Pos (3UL)
- #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos)
- #define GPIO_OUT_PIN3_Low (0UL)
- #define GPIO_OUT_PIN3_High (1UL)
- #define GPIO_OUT_PIN2_Pos (2UL)
- #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos)
- #define GPIO_OUT_PIN2_Low (0UL)
- #define GPIO_OUT_PIN2_High (1UL)
- #define GPIO_OUT_PIN1_Pos (1UL)
- #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos)
- #define GPIO_OUT_PIN1_Low (0UL)
- #define GPIO_OUT_PIN1_High (1UL)
- #define GPIO_OUT_PIN0_Pos (0UL)
- #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos)
- #define GPIO_OUT_PIN0_Low (0UL)
- #define GPIO_OUT_PIN0_High (1UL)
- #define GPIO_OUTSET_PIN31_Pos (31UL)
- #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos)
- #define GPIO_OUTSET_PIN31_Low (0UL)
- #define GPIO_OUTSET_PIN31_High (1UL)
- #define GPIO_OUTSET_PIN31_Set (1UL)
- #define GPIO_OUTSET_PIN30_Pos (30UL)
- #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos)
- #define GPIO_OUTSET_PIN30_Low (0UL)
- #define GPIO_OUTSET_PIN30_High (1UL)
- #define GPIO_OUTSET_PIN30_Set (1UL)
- #define GPIO_OUTSET_PIN29_Pos (29UL)
- #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos)
- #define GPIO_OUTSET_PIN29_Low (0UL)
- #define GPIO_OUTSET_PIN29_High (1UL)
- #define GPIO_OUTSET_PIN29_Set (1UL)
- #define GPIO_OUTSET_PIN28_Pos (28UL)
- #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos)
- #define GPIO_OUTSET_PIN28_Low (0UL)
- #define GPIO_OUTSET_PIN28_High (1UL)
- #define GPIO_OUTSET_PIN28_Set (1UL)
- #define GPIO_OUTSET_PIN27_Pos (27UL)
- #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos)
- #define GPIO_OUTSET_PIN27_Low (0UL)
- #define GPIO_OUTSET_PIN27_High (1UL)
- #define GPIO_OUTSET_PIN27_Set (1UL)
- #define GPIO_OUTSET_PIN26_Pos (26UL)
- #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos)
- #define GPIO_OUTSET_PIN26_Low (0UL)
- #define GPIO_OUTSET_PIN26_High (1UL)
- #define GPIO_OUTSET_PIN26_Set (1UL)
- #define GPIO_OUTSET_PIN25_Pos (25UL)
- #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos)
- #define GPIO_OUTSET_PIN25_Low (0UL)
- #define GPIO_OUTSET_PIN25_High (1UL)
- #define GPIO_OUTSET_PIN25_Set (1UL)
- #define GPIO_OUTSET_PIN24_Pos (24UL)
- #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos)
- #define GPIO_OUTSET_PIN24_Low (0UL)
- #define GPIO_OUTSET_PIN24_High (1UL)
- #define GPIO_OUTSET_PIN24_Set (1UL)
- #define GPIO_OUTSET_PIN23_Pos (23UL)
- #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos)
- #define GPIO_OUTSET_PIN23_Low (0UL)
- #define GPIO_OUTSET_PIN23_High (1UL)
- #define GPIO_OUTSET_PIN23_Set (1UL)
- #define GPIO_OUTSET_PIN22_Pos (22UL)
- #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos)
- #define GPIO_OUTSET_PIN22_Low (0UL)
- #define GPIO_OUTSET_PIN22_High (1UL)
- #define GPIO_OUTSET_PIN22_Set (1UL)
- #define GPIO_OUTSET_PIN21_Pos (21UL)
- #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos)
- #define GPIO_OUTSET_PIN21_Low (0UL)
- #define GPIO_OUTSET_PIN21_High (1UL)
- #define GPIO_OUTSET_PIN21_Set (1UL)
- #define GPIO_OUTSET_PIN20_Pos (20UL)
- #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos)
- #define GPIO_OUTSET_PIN20_Low (0UL)
- #define GPIO_OUTSET_PIN20_High (1UL)
- #define GPIO_OUTSET_PIN20_Set (1UL)
- #define GPIO_OUTSET_PIN19_Pos (19UL)
- #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos)
- #define GPIO_OUTSET_PIN19_Low (0UL)
- #define GPIO_OUTSET_PIN19_High (1UL)
- #define GPIO_OUTSET_PIN19_Set (1UL)
- #define GPIO_OUTSET_PIN18_Pos (18UL)
- #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos)
- #define GPIO_OUTSET_PIN18_Low (0UL)
- #define GPIO_OUTSET_PIN18_High (1UL)
- #define GPIO_OUTSET_PIN18_Set (1UL)
- #define GPIO_OUTSET_PIN17_Pos (17UL)
- #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos)
- #define GPIO_OUTSET_PIN17_Low (0UL)
- #define GPIO_OUTSET_PIN17_High (1UL)
- #define GPIO_OUTSET_PIN17_Set (1UL)
- #define GPIO_OUTSET_PIN16_Pos (16UL)
- #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos)
- #define GPIO_OUTSET_PIN16_Low (0UL)
- #define GPIO_OUTSET_PIN16_High (1UL)
- #define GPIO_OUTSET_PIN16_Set (1UL)
- #define GPIO_OUTSET_PIN15_Pos (15UL)
- #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos)
- #define GPIO_OUTSET_PIN15_Low (0UL)
- #define GPIO_OUTSET_PIN15_High (1UL)
- #define GPIO_OUTSET_PIN15_Set (1UL)
- #define GPIO_OUTSET_PIN14_Pos (14UL)
- #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos)
- #define GPIO_OUTSET_PIN14_Low (0UL)
- #define GPIO_OUTSET_PIN14_High (1UL)
- #define GPIO_OUTSET_PIN14_Set (1UL)
- #define GPIO_OUTSET_PIN13_Pos (13UL)
- #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos)
- #define GPIO_OUTSET_PIN13_Low (0UL)
- #define GPIO_OUTSET_PIN13_High (1UL)
- #define GPIO_OUTSET_PIN13_Set (1UL)
- #define GPIO_OUTSET_PIN12_Pos (12UL)
- #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos)
- #define GPIO_OUTSET_PIN12_Low (0UL)
- #define GPIO_OUTSET_PIN12_High (1UL)
- #define GPIO_OUTSET_PIN12_Set (1UL)
- #define GPIO_OUTSET_PIN11_Pos (11UL)
- #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos)
- #define GPIO_OUTSET_PIN11_Low (0UL)
- #define GPIO_OUTSET_PIN11_High (1UL)
- #define GPIO_OUTSET_PIN11_Set (1UL)
- #define GPIO_OUTSET_PIN10_Pos (10UL)
- #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos)
- #define GPIO_OUTSET_PIN10_Low (0UL)
- #define GPIO_OUTSET_PIN10_High (1UL)
- #define GPIO_OUTSET_PIN10_Set (1UL)
- #define GPIO_OUTSET_PIN9_Pos (9UL)
- #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos)
- #define GPIO_OUTSET_PIN9_Low (0UL)
- #define GPIO_OUTSET_PIN9_High (1UL)
- #define GPIO_OUTSET_PIN9_Set (1UL)
- #define GPIO_OUTSET_PIN8_Pos (8UL)
- #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos)
- #define GPIO_OUTSET_PIN8_Low (0UL)
- #define GPIO_OUTSET_PIN8_High (1UL)
- #define GPIO_OUTSET_PIN8_Set (1UL)
- #define GPIO_OUTSET_PIN7_Pos (7UL)
- #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos)
- #define GPIO_OUTSET_PIN7_Low (0UL)
- #define GPIO_OUTSET_PIN7_High (1UL)
- #define GPIO_OUTSET_PIN7_Set (1UL)
- #define GPIO_OUTSET_PIN6_Pos (6UL)
- #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos)
- #define GPIO_OUTSET_PIN6_Low (0UL)
- #define GPIO_OUTSET_PIN6_High (1UL)
- #define GPIO_OUTSET_PIN6_Set (1UL)
- #define GPIO_OUTSET_PIN5_Pos (5UL)
- #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos)
- #define GPIO_OUTSET_PIN5_Low (0UL)
- #define GPIO_OUTSET_PIN5_High (1UL)
- #define GPIO_OUTSET_PIN5_Set (1UL)
- #define GPIO_OUTSET_PIN4_Pos (4UL)
- #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos)
- #define GPIO_OUTSET_PIN4_Low (0UL)
- #define GPIO_OUTSET_PIN4_High (1UL)
- #define GPIO_OUTSET_PIN4_Set (1UL)
- #define GPIO_OUTSET_PIN3_Pos (3UL)
- #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos)
- #define GPIO_OUTSET_PIN3_Low (0UL)
- #define GPIO_OUTSET_PIN3_High (1UL)
- #define GPIO_OUTSET_PIN3_Set (1UL)
- #define GPIO_OUTSET_PIN2_Pos (2UL)
- #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos)
- #define GPIO_OUTSET_PIN2_Low (0UL)
- #define GPIO_OUTSET_PIN2_High (1UL)
- #define GPIO_OUTSET_PIN2_Set (1UL)
- #define GPIO_OUTSET_PIN1_Pos (1UL)
- #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos)
- #define GPIO_OUTSET_PIN1_Low (0UL)
- #define GPIO_OUTSET_PIN1_High (1UL)
- #define GPIO_OUTSET_PIN1_Set (1UL)
- #define GPIO_OUTSET_PIN0_Pos (0UL)
- #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos)
- #define GPIO_OUTSET_PIN0_Low (0UL)
- #define GPIO_OUTSET_PIN0_High (1UL)
- #define GPIO_OUTSET_PIN0_Set (1UL)
- #define GPIO_OUTCLR_PIN31_Pos (31UL)
- #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos)
- #define GPIO_OUTCLR_PIN31_Low (0UL)
- #define GPIO_OUTCLR_PIN31_High (1UL)
- #define GPIO_OUTCLR_PIN31_Clear (1UL)
- #define GPIO_OUTCLR_PIN30_Pos (30UL)
- #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos)
- #define GPIO_OUTCLR_PIN30_Low (0UL)
- #define GPIO_OUTCLR_PIN30_High (1UL)
- #define GPIO_OUTCLR_PIN30_Clear (1UL)
- #define GPIO_OUTCLR_PIN29_Pos (29UL)
- #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos)
- #define GPIO_OUTCLR_PIN29_Low (0UL)
- #define GPIO_OUTCLR_PIN29_High (1UL)
- #define GPIO_OUTCLR_PIN29_Clear (1UL)
- #define GPIO_OUTCLR_PIN28_Pos (28UL)
- #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos)
- #define GPIO_OUTCLR_PIN28_Low (0UL)
- #define GPIO_OUTCLR_PIN28_High (1UL)
- #define GPIO_OUTCLR_PIN28_Clear (1UL)
- #define GPIO_OUTCLR_PIN27_Pos (27UL)
- #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos)
- #define GPIO_OUTCLR_PIN27_Low (0UL)
- #define GPIO_OUTCLR_PIN27_High (1UL)
- #define GPIO_OUTCLR_PIN27_Clear (1UL)
- #define GPIO_OUTCLR_PIN26_Pos (26UL)
- #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos)
- #define GPIO_OUTCLR_PIN26_Low (0UL)
- #define GPIO_OUTCLR_PIN26_High (1UL)
- #define GPIO_OUTCLR_PIN26_Clear (1UL)
- #define GPIO_OUTCLR_PIN25_Pos (25UL)
- #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos)
- #define GPIO_OUTCLR_PIN25_Low (0UL)
- #define GPIO_OUTCLR_PIN25_High (1UL)
- #define GPIO_OUTCLR_PIN25_Clear (1UL)
- #define GPIO_OUTCLR_PIN24_Pos (24UL)
- #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos)
- #define GPIO_OUTCLR_PIN24_Low (0UL)
- #define GPIO_OUTCLR_PIN24_High (1UL)
- #define GPIO_OUTCLR_PIN24_Clear (1UL)
- #define GPIO_OUTCLR_PIN23_Pos (23UL)
- #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos)
- #define GPIO_OUTCLR_PIN23_Low (0UL)
- #define GPIO_OUTCLR_PIN23_High (1UL)
- #define GPIO_OUTCLR_PIN23_Clear (1UL)
- #define GPIO_OUTCLR_PIN22_Pos (22UL)
- #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos)
- #define GPIO_OUTCLR_PIN22_Low (0UL)
- #define GPIO_OUTCLR_PIN22_High (1UL)
- #define GPIO_OUTCLR_PIN22_Clear (1UL)
- #define GPIO_OUTCLR_PIN21_Pos (21UL)
- #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos)
- #define GPIO_OUTCLR_PIN21_Low (0UL)
- #define GPIO_OUTCLR_PIN21_High (1UL)
- #define GPIO_OUTCLR_PIN21_Clear (1UL)
- #define GPIO_OUTCLR_PIN20_Pos (20UL)
- #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos)
- #define GPIO_OUTCLR_PIN20_Low (0UL)
- #define GPIO_OUTCLR_PIN20_High (1UL)
- #define GPIO_OUTCLR_PIN20_Clear (1UL)
- #define GPIO_OUTCLR_PIN19_Pos (19UL)
- #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos)
- #define GPIO_OUTCLR_PIN19_Low (0UL)
- #define GPIO_OUTCLR_PIN19_High (1UL)
- #define GPIO_OUTCLR_PIN19_Clear (1UL)
- #define GPIO_OUTCLR_PIN18_Pos (18UL)
- #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos)
- #define GPIO_OUTCLR_PIN18_Low (0UL)
- #define GPIO_OUTCLR_PIN18_High (1UL)
- #define GPIO_OUTCLR_PIN18_Clear (1UL)
- #define GPIO_OUTCLR_PIN17_Pos (17UL)
- #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos)
- #define GPIO_OUTCLR_PIN17_Low (0UL)
- #define GPIO_OUTCLR_PIN17_High (1UL)
- #define GPIO_OUTCLR_PIN17_Clear (1UL)
- #define GPIO_OUTCLR_PIN16_Pos (16UL)
- #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos)
- #define GPIO_OUTCLR_PIN16_Low (0UL)
- #define GPIO_OUTCLR_PIN16_High (1UL)
- #define GPIO_OUTCLR_PIN16_Clear (1UL)
- #define GPIO_OUTCLR_PIN15_Pos (15UL)
- #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos)
- #define GPIO_OUTCLR_PIN15_Low (0UL)
- #define GPIO_OUTCLR_PIN15_High (1UL)
- #define GPIO_OUTCLR_PIN15_Clear (1UL)
- #define GPIO_OUTCLR_PIN14_Pos (14UL)
- #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos)
- #define GPIO_OUTCLR_PIN14_Low (0UL)
- #define GPIO_OUTCLR_PIN14_High (1UL)
- #define GPIO_OUTCLR_PIN14_Clear (1UL)
- #define GPIO_OUTCLR_PIN13_Pos (13UL)
- #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos)
- #define GPIO_OUTCLR_PIN13_Low (0UL)
- #define GPIO_OUTCLR_PIN13_High (1UL)
- #define GPIO_OUTCLR_PIN13_Clear (1UL)
- #define GPIO_OUTCLR_PIN12_Pos (12UL)
- #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos)
- #define GPIO_OUTCLR_PIN12_Low (0UL)
- #define GPIO_OUTCLR_PIN12_High (1UL)
- #define GPIO_OUTCLR_PIN12_Clear (1UL)
- #define GPIO_OUTCLR_PIN11_Pos (11UL)
- #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos)
- #define GPIO_OUTCLR_PIN11_Low (0UL)
- #define GPIO_OUTCLR_PIN11_High (1UL)
- #define GPIO_OUTCLR_PIN11_Clear (1UL)
- #define GPIO_OUTCLR_PIN10_Pos (10UL)
- #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos)
- #define GPIO_OUTCLR_PIN10_Low (0UL)
- #define GPIO_OUTCLR_PIN10_High (1UL)
- #define GPIO_OUTCLR_PIN10_Clear (1UL)
- #define GPIO_OUTCLR_PIN9_Pos (9UL)
- #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos)
- #define GPIO_OUTCLR_PIN9_Low (0UL)
- #define GPIO_OUTCLR_PIN9_High (1UL)
- #define GPIO_OUTCLR_PIN9_Clear (1UL)
- #define GPIO_OUTCLR_PIN8_Pos (8UL)
- #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos)
- #define GPIO_OUTCLR_PIN8_Low (0UL)
- #define GPIO_OUTCLR_PIN8_High (1UL)
- #define GPIO_OUTCLR_PIN8_Clear (1UL)
- #define GPIO_OUTCLR_PIN7_Pos (7UL)
- #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos)
- #define GPIO_OUTCLR_PIN7_Low (0UL)
- #define GPIO_OUTCLR_PIN7_High (1UL)
- #define GPIO_OUTCLR_PIN7_Clear (1UL)
- #define GPIO_OUTCLR_PIN6_Pos (6UL)
- #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos)
- #define GPIO_OUTCLR_PIN6_Low (0UL)
- #define GPIO_OUTCLR_PIN6_High (1UL)
- #define GPIO_OUTCLR_PIN6_Clear (1UL)
- #define GPIO_OUTCLR_PIN5_Pos (5UL)
- #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos)
- #define GPIO_OUTCLR_PIN5_Low (0UL)
- #define GPIO_OUTCLR_PIN5_High (1UL)
- #define GPIO_OUTCLR_PIN5_Clear (1UL)
- #define GPIO_OUTCLR_PIN4_Pos (4UL)
- #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos)
- #define GPIO_OUTCLR_PIN4_Low (0UL)
- #define GPIO_OUTCLR_PIN4_High (1UL)
- #define GPIO_OUTCLR_PIN4_Clear (1UL)
- #define GPIO_OUTCLR_PIN3_Pos (3UL)
- #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos)
- #define GPIO_OUTCLR_PIN3_Low (0UL)
- #define GPIO_OUTCLR_PIN3_High (1UL)
- #define GPIO_OUTCLR_PIN3_Clear (1UL)
- #define GPIO_OUTCLR_PIN2_Pos (2UL)
- #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos)
- #define GPIO_OUTCLR_PIN2_Low (0UL)
- #define GPIO_OUTCLR_PIN2_High (1UL)
- #define GPIO_OUTCLR_PIN2_Clear (1UL)
- #define GPIO_OUTCLR_PIN1_Pos (1UL)
- #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos)
- #define GPIO_OUTCLR_PIN1_Low (0UL)
- #define GPIO_OUTCLR_PIN1_High (1UL)
- #define GPIO_OUTCLR_PIN1_Clear (1UL)
- #define GPIO_OUTCLR_PIN0_Pos (0UL)
- #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos)
- #define GPIO_OUTCLR_PIN0_Low (0UL)
- #define GPIO_OUTCLR_PIN0_High (1UL)
- #define GPIO_OUTCLR_PIN0_Clear (1UL)
- #define GPIO_IN_PIN31_Pos (31UL)
- #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos)
- #define GPIO_IN_PIN31_Low (0UL)
- #define GPIO_IN_PIN31_High (1UL)
- #define GPIO_IN_PIN30_Pos (30UL)
- #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos)
- #define GPIO_IN_PIN30_Low (0UL)
- #define GPIO_IN_PIN30_High (1UL)
- #define GPIO_IN_PIN29_Pos (29UL)
- #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos)
- #define GPIO_IN_PIN29_Low (0UL)
- #define GPIO_IN_PIN29_High (1UL)
- #define GPIO_IN_PIN28_Pos (28UL)
- #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos)
- #define GPIO_IN_PIN28_Low (0UL)
- #define GPIO_IN_PIN28_High (1UL)
- #define GPIO_IN_PIN27_Pos (27UL)
- #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos)
- #define GPIO_IN_PIN27_Low (0UL)
- #define GPIO_IN_PIN27_High (1UL)
- #define GPIO_IN_PIN26_Pos (26UL)
- #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos)
- #define GPIO_IN_PIN26_Low (0UL)
- #define GPIO_IN_PIN26_High (1UL)
- #define GPIO_IN_PIN25_Pos (25UL)
- #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos)
- #define GPIO_IN_PIN25_Low (0UL)
- #define GPIO_IN_PIN25_High (1UL)
- #define GPIO_IN_PIN24_Pos (24UL)
- #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos)
- #define GPIO_IN_PIN24_Low (0UL)
- #define GPIO_IN_PIN24_High (1UL)
- #define GPIO_IN_PIN23_Pos (23UL)
- #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos)
- #define GPIO_IN_PIN23_Low (0UL)
- #define GPIO_IN_PIN23_High (1UL)
- #define GPIO_IN_PIN22_Pos (22UL)
- #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos)
- #define GPIO_IN_PIN22_Low (0UL)
- #define GPIO_IN_PIN22_High (1UL)
- #define GPIO_IN_PIN21_Pos (21UL)
- #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos)
- #define GPIO_IN_PIN21_Low (0UL)
- #define GPIO_IN_PIN21_High (1UL)
- #define GPIO_IN_PIN20_Pos (20UL)
- #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos)
- #define GPIO_IN_PIN20_Low (0UL)
- #define GPIO_IN_PIN20_High (1UL)
- #define GPIO_IN_PIN19_Pos (19UL)
- #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos)
- #define GPIO_IN_PIN19_Low (0UL)
- #define GPIO_IN_PIN19_High (1UL)
- #define GPIO_IN_PIN18_Pos (18UL)
- #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos)
- #define GPIO_IN_PIN18_Low (0UL)
- #define GPIO_IN_PIN18_High (1UL)
- #define GPIO_IN_PIN17_Pos (17UL)
- #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos)
- #define GPIO_IN_PIN17_Low (0UL)
- #define GPIO_IN_PIN17_High (1UL)
- #define GPIO_IN_PIN16_Pos (16UL)
- #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos)
- #define GPIO_IN_PIN16_Low (0UL)
- #define GPIO_IN_PIN16_High (1UL)
- #define GPIO_IN_PIN15_Pos (15UL)
- #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos)
- #define GPIO_IN_PIN15_Low (0UL)
- #define GPIO_IN_PIN15_High (1UL)
- #define GPIO_IN_PIN14_Pos (14UL)
- #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos)
- #define GPIO_IN_PIN14_Low (0UL)
- #define GPIO_IN_PIN14_High (1UL)
- #define GPIO_IN_PIN13_Pos (13UL)
- #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos)
- #define GPIO_IN_PIN13_Low (0UL)
- #define GPIO_IN_PIN13_High (1UL)
- #define GPIO_IN_PIN12_Pos (12UL)
- #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos)
- #define GPIO_IN_PIN12_Low (0UL)
- #define GPIO_IN_PIN12_High (1UL)
- #define GPIO_IN_PIN11_Pos (11UL)
- #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos)
- #define GPIO_IN_PIN11_Low (0UL)
- #define GPIO_IN_PIN11_High (1UL)
- #define GPIO_IN_PIN10_Pos (10UL)
- #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos)
- #define GPIO_IN_PIN10_Low (0UL)
- #define GPIO_IN_PIN10_High (1UL)
- #define GPIO_IN_PIN9_Pos (9UL)
- #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos)
- #define GPIO_IN_PIN9_Low (0UL)
- #define GPIO_IN_PIN9_High (1UL)
- #define GPIO_IN_PIN8_Pos (8UL)
- #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos)
- #define GPIO_IN_PIN8_Low (0UL)
- #define GPIO_IN_PIN8_High (1UL)
- #define GPIO_IN_PIN7_Pos (7UL)
- #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos)
- #define GPIO_IN_PIN7_Low (0UL)
- #define GPIO_IN_PIN7_High (1UL)
- #define GPIO_IN_PIN6_Pos (6UL)
- #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos)
- #define GPIO_IN_PIN6_Low (0UL)
- #define GPIO_IN_PIN6_High (1UL)
- #define GPIO_IN_PIN5_Pos (5UL)
- #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos)
- #define GPIO_IN_PIN5_Low (0UL)
- #define GPIO_IN_PIN5_High (1UL)
- #define GPIO_IN_PIN4_Pos (4UL)
- #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos)
- #define GPIO_IN_PIN4_Low (0UL)
- #define GPIO_IN_PIN4_High (1UL)
- #define GPIO_IN_PIN3_Pos (3UL)
- #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos)
- #define GPIO_IN_PIN3_Low (0UL)
- #define GPIO_IN_PIN3_High (1UL)
- #define GPIO_IN_PIN2_Pos (2UL)
- #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos)
- #define GPIO_IN_PIN2_Low (0UL)
- #define GPIO_IN_PIN2_High (1UL)
- #define GPIO_IN_PIN1_Pos (1UL)
- #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos)
- #define GPIO_IN_PIN1_Low (0UL)
- #define GPIO_IN_PIN1_High (1UL)
- #define GPIO_IN_PIN0_Pos (0UL)
- #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos)
- #define GPIO_IN_PIN0_Low (0UL)
- #define GPIO_IN_PIN0_High (1UL)
- #define GPIO_DIR_PIN31_Pos (31UL)
- #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos)
- #define GPIO_DIR_PIN31_Input (0UL)
- #define GPIO_DIR_PIN31_Output (1UL)
- #define GPIO_DIR_PIN30_Pos (30UL)
- #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos)
- #define GPIO_DIR_PIN30_Input (0UL)
- #define GPIO_DIR_PIN30_Output (1UL)
- #define GPIO_DIR_PIN29_Pos (29UL)
- #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos)
- #define GPIO_DIR_PIN29_Input (0UL)
- #define GPIO_DIR_PIN29_Output (1UL)
- #define GPIO_DIR_PIN28_Pos (28UL)
- #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos)
- #define GPIO_DIR_PIN28_Input (0UL)
- #define GPIO_DIR_PIN28_Output (1UL)
- #define GPIO_DIR_PIN27_Pos (27UL)
- #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos)
- #define GPIO_DIR_PIN27_Input (0UL)
- #define GPIO_DIR_PIN27_Output (1UL)
- #define GPIO_DIR_PIN26_Pos (26UL)
- #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos)
- #define GPIO_DIR_PIN26_Input (0UL)
- #define GPIO_DIR_PIN26_Output (1UL)
- #define GPIO_DIR_PIN25_Pos (25UL)
- #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos)
- #define GPIO_DIR_PIN25_Input (0UL)
- #define GPIO_DIR_PIN25_Output (1UL)
- #define GPIO_DIR_PIN24_Pos (24UL)
- #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos)
- #define GPIO_DIR_PIN24_Input (0UL)
- #define GPIO_DIR_PIN24_Output (1UL)
- #define GPIO_DIR_PIN23_Pos (23UL)
- #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos)
- #define GPIO_DIR_PIN23_Input (0UL)
- #define GPIO_DIR_PIN23_Output (1UL)
- #define GPIO_DIR_PIN22_Pos (22UL)
- #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos)
- #define GPIO_DIR_PIN22_Input (0UL)
- #define GPIO_DIR_PIN22_Output (1UL)
- #define GPIO_DIR_PIN21_Pos (21UL)
- #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos)
- #define GPIO_DIR_PIN21_Input (0UL)
- #define GPIO_DIR_PIN21_Output (1UL)
- #define GPIO_DIR_PIN20_Pos (20UL)
- #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos)
- #define GPIO_DIR_PIN20_Input (0UL)
- #define GPIO_DIR_PIN20_Output (1UL)
- #define GPIO_DIR_PIN19_Pos (19UL)
- #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos)
- #define GPIO_DIR_PIN19_Input (0UL)
- #define GPIO_DIR_PIN19_Output (1UL)
- #define GPIO_DIR_PIN18_Pos (18UL)
- #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos)
- #define GPIO_DIR_PIN18_Input (0UL)
- #define GPIO_DIR_PIN18_Output (1UL)
- #define GPIO_DIR_PIN17_Pos (17UL)
- #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos)
- #define GPIO_DIR_PIN17_Input (0UL)
- #define GPIO_DIR_PIN17_Output (1UL)
- #define GPIO_DIR_PIN16_Pos (16UL)
- #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos)
- #define GPIO_DIR_PIN16_Input (0UL)
- #define GPIO_DIR_PIN16_Output (1UL)
- #define GPIO_DIR_PIN15_Pos (15UL)
- #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos)
- #define GPIO_DIR_PIN15_Input (0UL)
- #define GPIO_DIR_PIN15_Output (1UL)
- #define GPIO_DIR_PIN14_Pos (14UL)
- #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos)
- #define GPIO_DIR_PIN14_Input (0UL)
- #define GPIO_DIR_PIN14_Output (1UL)
- #define GPIO_DIR_PIN13_Pos (13UL)
- #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos)
- #define GPIO_DIR_PIN13_Input (0UL)
- #define GPIO_DIR_PIN13_Output (1UL)
- #define GPIO_DIR_PIN12_Pos (12UL)
- #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos)
- #define GPIO_DIR_PIN12_Input (0UL)
- #define GPIO_DIR_PIN12_Output (1UL)
- #define GPIO_DIR_PIN11_Pos (11UL)
- #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos)
- #define GPIO_DIR_PIN11_Input (0UL)
- #define GPIO_DIR_PIN11_Output (1UL)
- #define GPIO_DIR_PIN10_Pos (10UL)
- #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos)
- #define GPIO_DIR_PIN10_Input (0UL)
- #define GPIO_DIR_PIN10_Output (1UL)
- #define GPIO_DIR_PIN9_Pos (9UL)
- #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos)
- #define GPIO_DIR_PIN9_Input (0UL)
- #define GPIO_DIR_PIN9_Output (1UL)
- #define GPIO_DIR_PIN8_Pos (8UL)
- #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos)
- #define GPIO_DIR_PIN8_Input (0UL)
- #define GPIO_DIR_PIN8_Output (1UL)
- #define GPIO_DIR_PIN7_Pos (7UL)
- #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos)
- #define GPIO_DIR_PIN7_Input (0UL)
- #define GPIO_DIR_PIN7_Output (1UL)
- #define GPIO_DIR_PIN6_Pos (6UL)
- #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos)
- #define GPIO_DIR_PIN6_Input (0UL)
- #define GPIO_DIR_PIN6_Output (1UL)
- #define GPIO_DIR_PIN5_Pos (5UL)
- #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos)
- #define GPIO_DIR_PIN5_Input (0UL)
- #define GPIO_DIR_PIN5_Output (1UL)
- #define GPIO_DIR_PIN4_Pos (4UL)
- #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos)
- #define GPIO_DIR_PIN4_Input (0UL)
- #define GPIO_DIR_PIN4_Output (1UL)
- #define GPIO_DIR_PIN3_Pos (3UL)
- #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos)
- #define GPIO_DIR_PIN3_Input (0UL)
- #define GPIO_DIR_PIN3_Output (1UL)
- #define GPIO_DIR_PIN2_Pos (2UL)
- #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos)
- #define GPIO_DIR_PIN2_Input (0UL)
- #define GPIO_DIR_PIN2_Output (1UL)
- #define GPIO_DIR_PIN1_Pos (1UL)
- #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos)
- #define GPIO_DIR_PIN1_Input (0UL)
- #define GPIO_DIR_PIN1_Output (1UL)
- #define GPIO_DIR_PIN0_Pos (0UL)
- #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos)
- #define GPIO_DIR_PIN0_Input (0UL)
- #define GPIO_DIR_PIN0_Output (1UL)
- #define GPIO_DIRSET_PIN31_Pos (31UL)
- #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos)
- #define GPIO_DIRSET_PIN31_Input (0UL)
- #define GPIO_DIRSET_PIN31_Output (1UL)
- #define GPIO_DIRSET_PIN31_Set (1UL)
- #define GPIO_DIRSET_PIN30_Pos (30UL)
- #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos)
- #define GPIO_DIRSET_PIN30_Input (0UL)
- #define GPIO_DIRSET_PIN30_Output (1UL)
- #define GPIO_DIRSET_PIN30_Set (1UL)
- #define GPIO_DIRSET_PIN29_Pos (29UL)
- #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos)
- #define GPIO_DIRSET_PIN29_Input (0UL)
- #define GPIO_DIRSET_PIN29_Output (1UL)
- #define GPIO_DIRSET_PIN29_Set (1UL)
- #define GPIO_DIRSET_PIN28_Pos (28UL)
- #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos)
- #define GPIO_DIRSET_PIN28_Input (0UL)
- #define GPIO_DIRSET_PIN28_Output (1UL)
- #define GPIO_DIRSET_PIN28_Set (1UL)
- #define GPIO_DIRSET_PIN27_Pos (27UL)
- #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos)
- #define GPIO_DIRSET_PIN27_Input (0UL)
- #define GPIO_DIRSET_PIN27_Output (1UL)
- #define GPIO_DIRSET_PIN27_Set (1UL)
- #define GPIO_DIRSET_PIN26_Pos (26UL)
- #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos)
- #define GPIO_DIRSET_PIN26_Input (0UL)
- #define GPIO_DIRSET_PIN26_Output (1UL)
- #define GPIO_DIRSET_PIN26_Set (1UL)
- #define GPIO_DIRSET_PIN25_Pos (25UL)
- #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos)
- #define GPIO_DIRSET_PIN25_Input (0UL)
- #define GPIO_DIRSET_PIN25_Output (1UL)
- #define GPIO_DIRSET_PIN25_Set (1UL)
- #define GPIO_DIRSET_PIN24_Pos (24UL)
- #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos)
- #define GPIO_DIRSET_PIN24_Input (0UL)
- #define GPIO_DIRSET_PIN24_Output (1UL)
- #define GPIO_DIRSET_PIN24_Set (1UL)
- #define GPIO_DIRSET_PIN23_Pos (23UL)
- #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos)
- #define GPIO_DIRSET_PIN23_Input (0UL)
- #define GPIO_DIRSET_PIN23_Output (1UL)
- #define GPIO_DIRSET_PIN23_Set (1UL)
- #define GPIO_DIRSET_PIN22_Pos (22UL)
- #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos)
- #define GPIO_DIRSET_PIN22_Input (0UL)
- #define GPIO_DIRSET_PIN22_Output (1UL)
- #define GPIO_DIRSET_PIN22_Set (1UL)
- #define GPIO_DIRSET_PIN21_Pos (21UL)
- #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos)
- #define GPIO_DIRSET_PIN21_Input (0UL)
- #define GPIO_DIRSET_PIN21_Output (1UL)
- #define GPIO_DIRSET_PIN21_Set (1UL)
- #define GPIO_DIRSET_PIN20_Pos (20UL)
- #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos)
- #define GPIO_DIRSET_PIN20_Input (0UL)
- #define GPIO_DIRSET_PIN20_Output (1UL)
- #define GPIO_DIRSET_PIN20_Set (1UL)
- #define GPIO_DIRSET_PIN19_Pos (19UL)
- #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos)
- #define GPIO_DIRSET_PIN19_Input (0UL)
- #define GPIO_DIRSET_PIN19_Output (1UL)
- #define GPIO_DIRSET_PIN19_Set (1UL)
- #define GPIO_DIRSET_PIN18_Pos (18UL)
- #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos)
- #define GPIO_DIRSET_PIN18_Input (0UL)
- #define GPIO_DIRSET_PIN18_Output (1UL)
- #define GPIO_DIRSET_PIN18_Set (1UL)
- #define GPIO_DIRSET_PIN17_Pos (17UL)
- #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos)
- #define GPIO_DIRSET_PIN17_Input (0UL)
- #define GPIO_DIRSET_PIN17_Output (1UL)
- #define GPIO_DIRSET_PIN17_Set (1UL)
- #define GPIO_DIRSET_PIN16_Pos (16UL)
- #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos)
- #define GPIO_DIRSET_PIN16_Input (0UL)
- #define GPIO_DIRSET_PIN16_Output (1UL)
- #define GPIO_DIRSET_PIN16_Set (1UL)
- #define GPIO_DIRSET_PIN15_Pos (15UL)
- #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos)
- #define GPIO_DIRSET_PIN15_Input (0UL)
- #define GPIO_DIRSET_PIN15_Output (1UL)
- #define GPIO_DIRSET_PIN15_Set (1UL)
- #define GPIO_DIRSET_PIN14_Pos (14UL)
- #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos)
- #define GPIO_DIRSET_PIN14_Input (0UL)
- #define GPIO_DIRSET_PIN14_Output (1UL)
- #define GPIO_DIRSET_PIN14_Set (1UL)
- #define GPIO_DIRSET_PIN13_Pos (13UL)
- #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos)
- #define GPIO_DIRSET_PIN13_Input (0UL)
- #define GPIO_DIRSET_PIN13_Output (1UL)
- #define GPIO_DIRSET_PIN13_Set (1UL)
- #define GPIO_DIRSET_PIN12_Pos (12UL)
- #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos)
- #define GPIO_DIRSET_PIN12_Input (0UL)
- #define GPIO_DIRSET_PIN12_Output (1UL)
- #define GPIO_DIRSET_PIN12_Set (1UL)
- #define GPIO_DIRSET_PIN11_Pos (11UL)
- #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos)
- #define GPIO_DIRSET_PIN11_Input (0UL)
- #define GPIO_DIRSET_PIN11_Output (1UL)
- #define GPIO_DIRSET_PIN11_Set (1UL)
- #define GPIO_DIRSET_PIN10_Pos (10UL)
- #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos)
- #define GPIO_DIRSET_PIN10_Input (0UL)
- #define GPIO_DIRSET_PIN10_Output (1UL)
- #define GPIO_DIRSET_PIN10_Set (1UL)
- #define GPIO_DIRSET_PIN9_Pos (9UL)
- #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos)
- #define GPIO_DIRSET_PIN9_Input (0UL)
- #define GPIO_DIRSET_PIN9_Output (1UL)
- #define GPIO_DIRSET_PIN9_Set (1UL)
- #define GPIO_DIRSET_PIN8_Pos (8UL)
- #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos)
- #define GPIO_DIRSET_PIN8_Input (0UL)
- #define GPIO_DIRSET_PIN8_Output (1UL)
- #define GPIO_DIRSET_PIN8_Set (1UL)
- #define GPIO_DIRSET_PIN7_Pos (7UL)
- #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos)
- #define GPIO_DIRSET_PIN7_Input (0UL)
- #define GPIO_DIRSET_PIN7_Output (1UL)
- #define GPIO_DIRSET_PIN7_Set (1UL)
- #define GPIO_DIRSET_PIN6_Pos (6UL)
- #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos)
- #define GPIO_DIRSET_PIN6_Input (0UL)
- #define GPIO_DIRSET_PIN6_Output (1UL)
- #define GPIO_DIRSET_PIN6_Set (1UL)
- #define GPIO_DIRSET_PIN5_Pos (5UL)
- #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos)
- #define GPIO_DIRSET_PIN5_Input (0UL)
- #define GPIO_DIRSET_PIN5_Output (1UL)
- #define GPIO_DIRSET_PIN5_Set (1UL)
- #define GPIO_DIRSET_PIN4_Pos (4UL)
- #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos)
- #define GPIO_DIRSET_PIN4_Input (0UL)
- #define GPIO_DIRSET_PIN4_Output (1UL)
- #define GPIO_DIRSET_PIN4_Set (1UL)
- #define GPIO_DIRSET_PIN3_Pos (3UL)
- #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos)
- #define GPIO_DIRSET_PIN3_Input (0UL)
- #define GPIO_DIRSET_PIN3_Output (1UL)
- #define GPIO_DIRSET_PIN3_Set (1UL)
- #define GPIO_DIRSET_PIN2_Pos (2UL)
- #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos)
- #define GPIO_DIRSET_PIN2_Input (0UL)
- #define GPIO_DIRSET_PIN2_Output (1UL)
- #define GPIO_DIRSET_PIN2_Set (1UL)
- #define GPIO_DIRSET_PIN1_Pos (1UL)
- #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos)
- #define GPIO_DIRSET_PIN1_Input (0UL)
- #define GPIO_DIRSET_PIN1_Output (1UL)
- #define GPIO_DIRSET_PIN1_Set (1UL)
- #define GPIO_DIRSET_PIN0_Pos (0UL)
- #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos)
- #define GPIO_DIRSET_PIN0_Input (0UL)
- #define GPIO_DIRSET_PIN0_Output (1UL)
- #define GPIO_DIRSET_PIN0_Set (1UL)
- #define GPIO_DIRCLR_PIN31_Pos (31UL)
- #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos)
- #define GPIO_DIRCLR_PIN31_Input (0UL)
- #define GPIO_DIRCLR_PIN31_Output (1UL)
- #define GPIO_DIRCLR_PIN31_Clear (1UL)
- #define GPIO_DIRCLR_PIN30_Pos (30UL)
- #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos)
- #define GPIO_DIRCLR_PIN30_Input (0UL)
- #define GPIO_DIRCLR_PIN30_Output (1UL)
- #define GPIO_DIRCLR_PIN30_Clear (1UL)
- #define GPIO_DIRCLR_PIN29_Pos (29UL)
- #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos)
- #define GPIO_DIRCLR_PIN29_Input (0UL)
- #define GPIO_DIRCLR_PIN29_Output (1UL)
- #define GPIO_DIRCLR_PIN29_Clear (1UL)
- #define GPIO_DIRCLR_PIN28_Pos (28UL)
- #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos)
- #define GPIO_DIRCLR_PIN28_Input (0UL)
- #define GPIO_DIRCLR_PIN28_Output (1UL)
- #define GPIO_DIRCLR_PIN28_Clear (1UL)
- #define GPIO_DIRCLR_PIN27_Pos (27UL)
- #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos)
- #define GPIO_DIRCLR_PIN27_Input (0UL)
- #define GPIO_DIRCLR_PIN27_Output (1UL)
- #define GPIO_DIRCLR_PIN27_Clear (1UL)
- #define GPIO_DIRCLR_PIN26_Pos (26UL)
- #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos)
- #define GPIO_DIRCLR_PIN26_Input (0UL)
- #define GPIO_DIRCLR_PIN26_Output (1UL)
- #define GPIO_DIRCLR_PIN26_Clear (1UL)
- #define GPIO_DIRCLR_PIN25_Pos (25UL)
- #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos)
- #define GPIO_DIRCLR_PIN25_Input (0UL)
- #define GPIO_DIRCLR_PIN25_Output (1UL)
- #define GPIO_DIRCLR_PIN25_Clear (1UL)
- #define GPIO_DIRCLR_PIN24_Pos (24UL)
- #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos)
- #define GPIO_DIRCLR_PIN24_Input (0UL)
- #define GPIO_DIRCLR_PIN24_Output (1UL)
- #define GPIO_DIRCLR_PIN24_Clear (1UL)
- #define GPIO_DIRCLR_PIN23_Pos (23UL)
- #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos)
- #define GPIO_DIRCLR_PIN23_Input (0UL)
- #define GPIO_DIRCLR_PIN23_Output (1UL)
- #define GPIO_DIRCLR_PIN23_Clear (1UL)
- #define GPIO_DIRCLR_PIN22_Pos (22UL)
- #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos)
- #define GPIO_DIRCLR_PIN22_Input (0UL)
- #define GPIO_DIRCLR_PIN22_Output (1UL)
- #define GPIO_DIRCLR_PIN22_Clear (1UL)
- #define GPIO_DIRCLR_PIN21_Pos (21UL)
- #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos)
- #define GPIO_DIRCLR_PIN21_Input (0UL)
- #define GPIO_DIRCLR_PIN21_Output (1UL)
- #define GPIO_DIRCLR_PIN21_Clear (1UL)
- #define GPIO_DIRCLR_PIN20_Pos (20UL)
- #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos)
- #define GPIO_DIRCLR_PIN20_Input (0UL)
- #define GPIO_DIRCLR_PIN20_Output (1UL)
- #define GPIO_DIRCLR_PIN20_Clear (1UL)
- #define GPIO_DIRCLR_PIN19_Pos (19UL)
- #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos)
- #define GPIO_DIRCLR_PIN19_Input (0UL)
- #define GPIO_DIRCLR_PIN19_Output (1UL)
- #define GPIO_DIRCLR_PIN19_Clear (1UL)
- #define GPIO_DIRCLR_PIN18_Pos (18UL)
- #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos)
- #define GPIO_DIRCLR_PIN18_Input (0UL)
- #define GPIO_DIRCLR_PIN18_Output (1UL)
- #define GPIO_DIRCLR_PIN18_Clear (1UL)
- #define GPIO_DIRCLR_PIN17_Pos (17UL)
- #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos)
- #define GPIO_DIRCLR_PIN17_Input (0UL)
- #define GPIO_DIRCLR_PIN17_Output (1UL)
- #define GPIO_DIRCLR_PIN17_Clear (1UL)
- #define GPIO_DIRCLR_PIN16_Pos (16UL)
- #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos)
- #define GPIO_DIRCLR_PIN16_Input (0UL)
- #define GPIO_DIRCLR_PIN16_Output (1UL)
- #define GPIO_DIRCLR_PIN16_Clear (1UL)
- #define GPIO_DIRCLR_PIN15_Pos (15UL)
- #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos)
- #define GPIO_DIRCLR_PIN15_Input (0UL)
- #define GPIO_DIRCLR_PIN15_Output (1UL)
- #define GPIO_DIRCLR_PIN15_Clear (1UL)
- #define GPIO_DIRCLR_PIN14_Pos (14UL)
- #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos)
- #define GPIO_DIRCLR_PIN14_Input (0UL)
- #define GPIO_DIRCLR_PIN14_Output (1UL)
- #define GPIO_DIRCLR_PIN14_Clear (1UL)
- #define GPIO_DIRCLR_PIN13_Pos (13UL)
- #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos)
- #define GPIO_DIRCLR_PIN13_Input (0UL)
- #define GPIO_DIRCLR_PIN13_Output (1UL)
- #define GPIO_DIRCLR_PIN13_Clear (1UL)
- #define GPIO_DIRCLR_PIN12_Pos (12UL)
- #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos)
- #define GPIO_DIRCLR_PIN12_Input (0UL)
- #define GPIO_DIRCLR_PIN12_Output (1UL)
- #define GPIO_DIRCLR_PIN12_Clear (1UL)
- #define GPIO_DIRCLR_PIN11_Pos (11UL)
- #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos)
- #define GPIO_DIRCLR_PIN11_Input (0UL)
- #define GPIO_DIRCLR_PIN11_Output (1UL)
- #define GPIO_DIRCLR_PIN11_Clear (1UL)
- #define GPIO_DIRCLR_PIN10_Pos (10UL)
- #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos)
- #define GPIO_DIRCLR_PIN10_Input (0UL)
- #define GPIO_DIRCLR_PIN10_Output (1UL)
- #define GPIO_DIRCLR_PIN10_Clear (1UL)
- #define GPIO_DIRCLR_PIN9_Pos (9UL)
- #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos)
- #define GPIO_DIRCLR_PIN9_Input (0UL)
- #define GPIO_DIRCLR_PIN9_Output (1UL)
- #define GPIO_DIRCLR_PIN9_Clear (1UL)
- #define GPIO_DIRCLR_PIN8_Pos (8UL)
- #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos)
- #define GPIO_DIRCLR_PIN8_Input (0UL)
- #define GPIO_DIRCLR_PIN8_Output (1UL)
- #define GPIO_DIRCLR_PIN8_Clear (1UL)
- #define GPIO_DIRCLR_PIN7_Pos (7UL)
- #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos)
- #define GPIO_DIRCLR_PIN7_Input (0UL)
- #define GPIO_DIRCLR_PIN7_Output (1UL)
- #define GPIO_DIRCLR_PIN7_Clear (1UL)
- #define GPIO_DIRCLR_PIN6_Pos (6UL)
- #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos)
- #define GPIO_DIRCLR_PIN6_Input (0UL)
- #define GPIO_DIRCLR_PIN6_Output (1UL)
- #define GPIO_DIRCLR_PIN6_Clear (1UL)
- #define GPIO_DIRCLR_PIN5_Pos (5UL)
- #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos)
- #define GPIO_DIRCLR_PIN5_Input (0UL)
- #define GPIO_DIRCLR_PIN5_Output (1UL)
- #define GPIO_DIRCLR_PIN5_Clear (1UL)
- #define GPIO_DIRCLR_PIN4_Pos (4UL)
- #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos)
- #define GPIO_DIRCLR_PIN4_Input (0UL)
- #define GPIO_DIRCLR_PIN4_Output (1UL)
- #define GPIO_DIRCLR_PIN4_Clear (1UL)
- #define GPIO_DIRCLR_PIN3_Pos (3UL)
- #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos)
- #define GPIO_DIRCLR_PIN3_Input (0UL)
- #define GPIO_DIRCLR_PIN3_Output (1UL)
- #define GPIO_DIRCLR_PIN3_Clear (1UL)
- #define GPIO_DIRCLR_PIN2_Pos (2UL)
- #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos)
- #define GPIO_DIRCLR_PIN2_Input (0UL)
- #define GPIO_DIRCLR_PIN2_Output (1UL)
- #define GPIO_DIRCLR_PIN2_Clear (1UL)
- #define GPIO_DIRCLR_PIN1_Pos (1UL)
- #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos)
- #define GPIO_DIRCLR_PIN1_Input (0UL)
- #define GPIO_DIRCLR_PIN1_Output (1UL)
- #define GPIO_DIRCLR_PIN1_Clear (1UL)
- #define GPIO_DIRCLR_PIN0_Pos (0UL)
- #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos)
- #define GPIO_DIRCLR_PIN0_Input (0UL)
- #define GPIO_DIRCLR_PIN0_Output (1UL)
- #define GPIO_DIRCLR_PIN0_Clear (1UL)
- #define GPIO_LATCH_PIN31_Pos (31UL)
- #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos)
- #define GPIO_LATCH_PIN31_NotLatched (0UL)
- #define GPIO_LATCH_PIN31_Latched (1UL)
- #define GPIO_LATCH_PIN30_Pos (30UL)
- #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos)
- #define GPIO_LATCH_PIN30_NotLatched (0UL)
- #define GPIO_LATCH_PIN30_Latched (1UL)
- #define GPIO_LATCH_PIN29_Pos (29UL)
- #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos)
- #define GPIO_LATCH_PIN29_NotLatched (0UL)
- #define GPIO_LATCH_PIN29_Latched (1UL)
- #define GPIO_LATCH_PIN28_Pos (28UL)
- #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos)
- #define GPIO_LATCH_PIN28_NotLatched (0UL)
- #define GPIO_LATCH_PIN28_Latched (1UL)
- #define GPIO_LATCH_PIN27_Pos (27UL)
- #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos)
- #define GPIO_LATCH_PIN27_NotLatched (0UL)
- #define GPIO_LATCH_PIN27_Latched (1UL)
- #define GPIO_LATCH_PIN26_Pos (26UL)
- #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos)
- #define GPIO_LATCH_PIN26_NotLatched (0UL)
- #define GPIO_LATCH_PIN26_Latched (1UL)
- #define GPIO_LATCH_PIN25_Pos (25UL)
- #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos)
- #define GPIO_LATCH_PIN25_NotLatched (0UL)
- #define GPIO_LATCH_PIN25_Latched (1UL)
- #define GPIO_LATCH_PIN24_Pos (24UL)
- #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos)
- #define GPIO_LATCH_PIN24_NotLatched (0UL)
- #define GPIO_LATCH_PIN24_Latched (1UL)
- #define GPIO_LATCH_PIN23_Pos (23UL)
- #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos)
- #define GPIO_LATCH_PIN23_NotLatched (0UL)
- #define GPIO_LATCH_PIN23_Latched (1UL)
- #define GPIO_LATCH_PIN22_Pos (22UL)
- #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos)
- #define GPIO_LATCH_PIN22_NotLatched (0UL)
- #define GPIO_LATCH_PIN22_Latched (1UL)
- #define GPIO_LATCH_PIN21_Pos (21UL)
- #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos)
- #define GPIO_LATCH_PIN21_NotLatched (0UL)
- #define GPIO_LATCH_PIN21_Latched (1UL)
- #define GPIO_LATCH_PIN20_Pos (20UL)
- #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos)
- #define GPIO_LATCH_PIN20_NotLatched (0UL)
- #define GPIO_LATCH_PIN20_Latched (1UL)
- #define GPIO_LATCH_PIN19_Pos (19UL)
- #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos)
- #define GPIO_LATCH_PIN19_NotLatched (0UL)
- #define GPIO_LATCH_PIN19_Latched (1UL)
- #define GPIO_LATCH_PIN18_Pos (18UL)
- #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos)
- #define GPIO_LATCH_PIN18_NotLatched (0UL)
- #define GPIO_LATCH_PIN18_Latched (1UL)
- #define GPIO_LATCH_PIN17_Pos (17UL)
- #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos)
- #define GPIO_LATCH_PIN17_NotLatched (0UL)
- #define GPIO_LATCH_PIN17_Latched (1UL)
- #define GPIO_LATCH_PIN16_Pos (16UL)
- #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos)
- #define GPIO_LATCH_PIN16_NotLatched (0UL)
- #define GPIO_LATCH_PIN16_Latched (1UL)
- #define GPIO_LATCH_PIN15_Pos (15UL)
- #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos)
- #define GPIO_LATCH_PIN15_NotLatched (0UL)
- #define GPIO_LATCH_PIN15_Latched (1UL)
- #define GPIO_LATCH_PIN14_Pos (14UL)
- #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos)
- #define GPIO_LATCH_PIN14_NotLatched (0UL)
- #define GPIO_LATCH_PIN14_Latched (1UL)
- #define GPIO_LATCH_PIN13_Pos (13UL)
- #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos)
- #define GPIO_LATCH_PIN13_NotLatched (0UL)
- #define GPIO_LATCH_PIN13_Latched (1UL)
- #define GPIO_LATCH_PIN12_Pos (12UL)
- #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos)
- #define GPIO_LATCH_PIN12_NotLatched (0UL)
- #define GPIO_LATCH_PIN12_Latched (1UL)
- #define GPIO_LATCH_PIN11_Pos (11UL)
- #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos)
- #define GPIO_LATCH_PIN11_NotLatched (0UL)
- #define GPIO_LATCH_PIN11_Latched (1UL)
- #define GPIO_LATCH_PIN10_Pos (10UL)
- #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos)
- #define GPIO_LATCH_PIN10_NotLatched (0UL)
- #define GPIO_LATCH_PIN10_Latched (1UL)
- #define GPIO_LATCH_PIN9_Pos (9UL)
- #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos)
- #define GPIO_LATCH_PIN9_NotLatched (0UL)
- #define GPIO_LATCH_PIN9_Latched (1UL)
- #define GPIO_LATCH_PIN8_Pos (8UL)
- #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos)
- #define GPIO_LATCH_PIN8_NotLatched (0UL)
- #define GPIO_LATCH_PIN8_Latched (1UL)
- #define GPIO_LATCH_PIN7_Pos (7UL)
- #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos)
- #define GPIO_LATCH_PIN7_NotLatched (0UL)
- #define GPIO_LATCH_PIN7_Latched (1UL)
- #define GPIO_LATCH_PIN6_Pos (6UL)
- #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos)
- #define GPIO_LATCH_PIN6_NotLatched (0UL)
- #define GPIO_LATCH_PIN6_Latched (1UL)
- #define GPIO_LATCH_PIN5_Pos (5UL)
- #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos)
- #define GPIO_LATCH_PIN5_NotLatched (0UL)
- #define GPIO_LATCH_PIN5_Latched (1UL)
- #define GPIO_LATCH_PIN4_Pos (4UL)
- #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos)
- #define GPIO_LATCH_PIN4_NotLatched (0UL)
- #define GPIO_LATCH_PIN4_Latched (1UL)
- #define GPIO_LATCH_PIN3_Pos (3UL)
- #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos)
- #define GPIO_LATCH_PIN3_NotLatched (0UL)
- #define GPIO_LATCH_PIN3_Latched (1UL)
- #define GPIO_LATCH_PIN2_Pos (2UL)
- #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos)
- #define GPIO_LATCH_PIN2_NotLatched (0UL)
- #define GPIO_LATCH_PIN2_Latched (1UL)
- #define GPIO_LATCH_PIN1_Pos (1UL)
- #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos)
- #define GPIO_LATCH_PIN1_NotLatched (0UL)
- #define GPIO_LATCH_PIN1_Latched (1UL)
- #define GPIO_LATCH_PIN0_Pos (0UL)
- #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos)
- #define GPIO_LATCH_PIN0_NotLatched (0UL)
- #define GPIO_LATCH_PIN0_Latched (1UL)
- #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL)
- #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos)
- #define GPIO_DETECTMODE_DETECTMODE_Default (0UL)
- #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL)
- #define GPIO_DETECTMODE_SEC_DETECTMODE_Pos (0UL)
- #define GPIO_DETECTMODE_SEC_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_SEC_DETECTMODE_Pos)
- #define GPIO_DETECTMODE_SEC_DETECTMODE_Default (0UL)
- #define GPIO_DETECTMODE_SEC_DETECTMODE_LDETECT (1UL)
- #define GPIO_PIN_CNF_MCUSEL_Pos (28UL)
- #define GPIO_PIN_CNF_MCUSEL_Msk (0x7UL << GPIO_PIN_CNF_MCUSEL_Pos)
- #define GPIO_PIN_CNF_MCUSEL_AppMCU (0x0UL)
- #define GPIO_PIN_CNF_MCUSEL_NetworkMCU (0x1UL)
- #define GPIO_PIN_CNF_MCUSEL_Peripheral (0x3UL)
- #define GPIO_PIN_CNF_MCUSEL_TND (0x7UL)
- #define GPIO_PIN_CNF_SENSE_Pos (16UL)
- #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos)
- #define GPIO_PIN_CNF_SENSE_Disabled (0UL)
- #define GPIO_PIN_CNF_SENSE_High (2UL)
- #define GPIO_PIN_CNF_SENSE_Low (3UL)
- #define GPIO_PIN_CNF_DRIVE_Pos (8UL)
- #define GPIO_PIN_CNF_DRIVE_Msk (0xFUL << GPIO_PIN_CNF_DRIVE_Pos)
- #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL)
- #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL)
- #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL)
- #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL)
- #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL)
- #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL)
- #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL)
- #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL)
- #define GPIO_PIN_CNF_DRIVE_E0E1 (11UL)
- #define GPIO_PIN_CNF_PULL_Pos (2UL)
- #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos)
- #define GPIO_PIN_CNF_PULL_Disabled (0UL)
- #define GPIO_PIN_CNF_PULL_Pulldown (1UL)
- #define GPIO_PIN_CNF_PULL_Pullup (3UL)
- #define GPIO_PIN_CNF_INPUT_Pos (1UL)
- #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos)
- #define GPIO_PIN_CNF_INPUT_Connect (0UL)
- #define GPIO_PIN_CNF_INPUT_Disconnect (1UL)
- #define GPIO_PIN_CNF_DIR_Pos (0UL)
- #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos)
- #define GPIO_PIN_CNF_DIR_Input (0UL)
- #define GPIO_PIN_CNF_DIR_Output (1UL)
- #define PDM_TASKS_START_TASKS_START_Pos (0UL)
- #define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos)
- #define PDM_TASKS_START_TASKS_START_Trigger (1UL)
- #define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos)
- #define PDM_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define PDM_SUBSCRIBE_START_EN_Pos (31UL)
- #define PDM_SUBSCRIBE_START_EN_Msk (0x1UL << PDM_SUBSCRIBE_START_EN_Pos)
- #define PDM_SUBSCRIBE_START_EN_Disabled (0UL)
- #define PDM_SUBSCRIBE_START_EN_Enabled (1UL)
- #define PDM_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define PDM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_START_CHIDX_Pos)
- #define PDM_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define PDM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PDM_SUBSCRIBE_STOP_EN_Pos)
- #define PDM_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define PDM_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define PDM_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define PDM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_STOP_CHIDX_Pos)
- #define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL)
- #define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos)
- #define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL)
- #define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL)
- #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL)
- #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos)
- #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL)
- #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL)
- #define PDM_EVENTS_END_EVENTS_END_Pos (0UL)
- #define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos)
- #define PDM_EVENTS_END_EVENTS_END_NotGenerated (0UL)
- #define PDM_EVENTS_END_EVENTS_END_Generated (1UL)
- #define PDM_PUBLISH_STARTED_EN_Pos (31UL)
- #define PDM_PUBLISH_STARTED_EN_Msk (0x1UL << PDM_PUBLISH_STARTED_EN_Pos)
- #define PDM_PUBLISH_STARTED_EN_Disabled (0UL)
- #define PDM_PUBLISH_STARTED_EN_Enabled (1UL)
- #define PDM_PUBLISH_STARTED_CHIDX_Pos (0UL)
- #define PDM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STARTED_CHIDX_Pos)
- #define PDM_PUBLISH_STOPPED_EN_Pos (31UL)
- #define PDM_PUBLISH_STOPPED_EN_Msk (0x1UL << PDM_PUBLISH_STOPPED_EN_Pos)
- #define PDM_PUBLISH_STOPPED_EN_Disabled (0UL)
- #define PDM_PUBLISH_STOPPED_EN_Enabled (1UL)
- #define PDM_PUBLISH_STOPPED_CHIDX_Pos (0UL)
- #define PDM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STOPPED_CHIDX_Pos)
- #define PDM_PUBLISH_END_EN_Pos (31UL)
- #define PDM_PUBLISH_END_EN_Msk (0x1UL << PDM_PUBLISH_END_EN_Pos)
- #define PDM_PUBLISH_END_EN_Disabled (0UL)
- #define PDM_PUBLISH_END_EN_Enabled (1UL)
- #define PDM_PUBLISH_END_CHIDX_Pos (0UL)
- #define PDM_PUBLISH_END_CHIDX_Msk (0xFFUL << PDM_PUBLISH_END_CHIDX_Pos)
- #define PDM_INTEN_END_Pos (2UL)
- #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos)
- #define PDM_INTEN_END_Disabled (0UL)
- #define PDM_INTEN_END_Enabled (1UL)
- #define PDM_INTEN_STOPPED_Pos (1UL)
- #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos)
- #define PDM_INTEN_STOPPED_Disabled (0UL)
- #define PDM_INTEN_STOPPED_Enabled (1UL)
- #define PDM_INTEN_STARTED_Pos (0UL)
- #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos)
- #define PDM_INTEN_STARTED_Disabled (0UL)
- #define PDM_INTEN_STARTED_Enabled (1UL)
- #define PDM_INTENSET_END_Pos (2UL)
- #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos)
- #define PDM_INTENSET_END_Disabled (0UL)
- #define PDM_INTENSET_END_Enabled (1UL)
- #define PDM_INTENSET_END_Set (1UL)
- #define PDM_INTENSET_STOPPED_Pos (1UL)
- #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos)
- #define PDM_INTENSET_STOPPED_Disabled (0UL)
- #define PDM_INTENSET_STOPPED_Enabled (1UL)
- #define PDM_INTENSET_STOPPED_Set (1UL)
- #define PDM_INTENSET_STARTED_Pos (0UL)
- #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos)
- #define PDM_INTENSET_STARTED_Disabled (0UL)
- #define PDM_INTENSET_STARTED_Enabled (1UL)
- #define PDM_INTENSET_STARTED_Set (1UL)
- #define PDM_INTENCLR_END_Pos (2UL)
- #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos)
- #define PDM_INTENCLR_END_Disabled (0UL)
- #define PDM_INTENCLR_END_Enabled (1UL)
- #define PDM_INTENCLR_END_Clear (1UL)
- #define PDM_INTENCLR_STOPPED_Pos (1UL)
- #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos)
- #define PDM_INTENCLR_STOPPED_Disabled (0UL)
- #define PDM_INTENCLR_STOPPED_Enabled (1UL)
- #define PDM_INTENCLR_STOPPED_Clear (1UL)
- #define PDM_INTENCLR_STARTED_Pos (0UL)
- #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos)
- #define PDM_INTENCLR_STARTED_Disabled (0UL)
- #define PDM_INTENCLR_STARTED_Enabled (1UL)
- #define PDM_INTENCLR_STARTED_Clear (1UL)
- #define PDM_ENABLE_ENABLE_Pos (0UL)
- #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos)
- #define PDM_ENABLE_ENABLE_Disabled (0UL)
- #define PDM_ENABLE_ENABLE_Enabled (1UL)
- #define PDM_PDMCLKCTRL_FREQ_Pos (0UL)
- #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos)
- #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL)
- #define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL)
- #define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL)
- #define PDM_PDMCLKCTRL_FREQ_1231K (0x09800000UL)
- #define PDM_PDMCLKCTRL_FREQ_1280K (0x0A000000UL)
- #define PDM_PDMCLKCTRL_FREQ_1333K (0x0A800000UL)
- #define PDM_MODE_EDGE_Pos (1UL)
- #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos)
- #define PDM_MODE_EDGE_LeftFalling (0UL)
- #define PDM_MODE_EDGE_LeftRising (1UL)
- #define PDM_MODE_OPERATION_Pos (0UL)
- #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos)
- #define PDM_MODE_OPERATION_Stereo (0UL)
- #define PDM_MODE_OPERATION_Mono (1UL)
- #define PDM_GAINL_GAINL_Pos (0UL)
- #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos)
- #define PDM_GAINL_GAINL_MinGain (0x00UL)
- #define PDM_GAINL_GAINL_DefaultGain (0x28UL)
- #define PDM_GAINL_GAINL_MaxGain (0x50UL)
- #define PDM_GAINR_GAINR_Pos (0UL)
- #define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos)
- #define PDM_GAINR_GAINR_MinGain (0x00UL)
- #define PDM_GAINR_GAINR_DefaultGain (0x28UL)
- #define PDM_GAINR_GAINR_MaxGain (0x50UL)
- #define PDM_RATIO_RATIO_Pos (0UL)
- #define PDM_RATIO_RATIO_Msk (0x1UL << PDM_RATIO_RATIO_Pos)
- #define PDM_RATIO_RATIO_Ratio64 (0UL)
- #define PDM_RATIO_RATIO_Ratio80 (1UL)
- #define PDM_PSEL_CLK_CONNECT_Pos (31UL)
- #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos)
- #define PDM_PSEL_CLK_CONNECT_Connected (0UL)
- #define PDM_PSEL_CLK_CONNECT_Disconnected (1UL)
- #define PDM_PSEL_CLK_PORT_Pos (5UL)
- #define PDM_PSEL_CLK_PORT_Msk (0x1UL << PDM_PSEL_CLK_PORT_Pos)
- #define PDM_PSEL_CLK_PIN_Pos (0UL)
- #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos)
- #define PDM_PSEL_DIN_CONNECT_Pos (31UL)
- #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos)
- #define PDM_PSEL_DIN_CONNECT_Connected (0UL)
- #define PDM_PSEL_DIN_CONNECT_Disconnected (1UL)
- #define PDM_PSEL_DIN_PORT_Pos (5UL)
- #define PDM_PSEL_DIN_PORT_Msk (0x1UL << PDM_PSEL_DIN_PORT_Pos)
- #define PDM_PSEL_DIN_PIN_Pos (0UL)
- #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos)
- #define PDM_MCLKCONFIG_SRC_Pos (0UL)
- #define PDM_MCLKCONFIG_SRC_Msk (0x1UL << PDM_MCLKCONFIG_SRC_Pos)
- #define PDM_MCLKCONFIG_SRC_PCLK32M (0UL)
- #define PDM_MCLKCONFIG_SRC_ACLK (1UL)
- #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL)
- #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos)
- #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL)
- #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos)
- #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL)
- #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos)
- #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL)
- #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL)
- #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos)
- #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL)
- #define POWER_SUBSCRIBE_CONSTLAT_EN_Pos (31UL)
- #define POWER_SUBSCRIBE_CONSTLAT_EN_Msk (0x1UL << POWER_SUBSCRIBE_CONSTLAT_EN_Pos)
- #define POWER_SUBSCRIBE_CONSTLAT_EN_Disabled (0UL)
- #define POWER_SUBSCRIBE_CONSTLAT_EN_Enabled (1UL)
- #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos (0UL)
- #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos)
- #define POWER_SUBSCRIBE_LOWPWR_EN_Pos (31UL)
- #define POWER_SUBSCRIBE_LOWPWR_EN_Msk (0x1UL << POWER_SUBSCRIBE_LOWPWR_EN_Pos)
- #define POWER_SUBSCRIBE_LOWPWR_EN_Disabled (0UL)
- #define POWER_SUBSCRIBE_LOWPWR_EN_Enabled (1UL)
- #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos (0UL)
- #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos)
- #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL)
- #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos)
- #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL)
- #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL)
- #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL)
- #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos)
- #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL)
- #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL)
- #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL)
- #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos)
- #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL)
- #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL)
- #define POWER_PUBLISH_POFWARN_EN_Pos (31UL)
- #define POWER_PUBLISH_POFWARN_EN_Msk (0x1UL << POWER_PUBLISH_POFWARN_EN_Pos)
- #define POWER_PUBLISH_POFWARN_EN_Disabled (0UL)
- #define POWER_PUBLISH_POFWARN_EN_Enabled (1UL)
- #define POWER_PUBLISH_POFWARN_CHIDX_Pos (0UL)
- #define POWER_PUBLISH_POFWARN_CHIDX_Msk (0xFFUL << POWER_PUBLISH_POFWARN_CHIDX_Pos)
- #define POWER_PUBLISH_SLEEPENTER_EN_Pos (31UL)
- #define POWER_PUBLISH_SLEEPENTER_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPENTER_EN_Pos)
- #define POWER_PUBLISH_SLEEPENTER_EN_Disabled (0UL)
- #define POWER_PUBLISH_SLEEPENTER_EN_Enabled (1UL)
- #define POWER_PUBLISH_SLEEPENTER_CHIDX_Pos (0UL)
- #define POWER_PUBLISH_SLEEPENTER_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPENTER_CHIDX_Pos)
- #define POWER_PUBLISH_SLEEPEXIT_EN_Pos (31UL)
- #define POWER_PUBLISH_SLEEPEXIT_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPEXIT_EN_Pos)
- #define POWER_PUBLISH_SLEEPEXIT_EN_Disabled (0UL)
- #define POWER_PUBLISH_SLEEPEXIT_EN_Enabled (1UL)
- #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos (0UL)
- #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos)
- #define POWER_INTEN_SLEEPEXIT_Pos (6UL)
- #define POWER_INTEN_SLEEPEXIT_Msk (0x1UL << POWER_INTEN_SLEEPEXIT_Pos)
- #define POWER_INTEN_SLEEPEXIT_Disabled (0UL)
- #define POWER_INTEN_SLEEPEXIT_Enabled (1UL)
- #define POWER_INTEN_SLEEPENTER_Pos (5UL)
- #define POWER_INTEN_SLEEPENTER_Msk (0x1UL << POWER_INTEN_SLEEPENTER_Pos)
- #define POWER_INTEN_SLEEPENTER_Disabled (0UL)
- #define POWER_INTEN_SLEEPENTER_Enabled (1UL)
- #define POWER_INTEN_POFWARN_Pos (2UL)
- #define POWER_INTEN_POFWARN_Msk (0x1UL << POWER_INTEN_POFWARN_Pos)
- #define POWER_INTEN_POFWARN_Disabled (0UL)
- #define POWER_INTEN_POFWARN_Enabled (1UL)
- #define POWER_INTENSET_SLEEPEXIT_Pos (6UL)
- #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos)
- #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL)
- #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL)
- #define POWER_INTENSET_SLEEPEXIT_Set (1UL)
- #define POWER_INTENSET_SLEEPENTER_Pos (5UL)
- #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos)
- #define POWER_INTENSET_SLEEPENTER_Disabled (0UL)
- #define POWER_INTENSET_SLEEPENTER_Enabled (1UL)
- #define POWER_INTENSET_SLEEPENTER_Set (1UL)
- #define POWER_INTENSET_POFWARN_Pos (2UL)
- #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos)
- #define POWER_INTENSET_POFWARN_Disabled (0UL)
- #define POWER_INTENSET_POFWARN_Enabled (1UL)
- #define POWER_INTENSET_POFWARN_Set (1UL)
- #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL)
- #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos)
- #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL)
- #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL)
- #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL)
- #define POWER_INTENCLR_SLEEPENTER_Pos (5UL)
- #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos)
- #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL)
- #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL)
- #define POWER_INTENCLR_SLEEPENTER_Clear (1UL)
- #define POWER_INTENCLR_POFWARN_Pos (2UL)
- #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos)
- #define POWER_INTENCLR_POFWARN_Disabled (0UL)
- #define POWER_INTENCLR_POFWARN_Enabled (1UL)
- #define POWER_INTENCLR_POFWARN_Clear (1UL)
- #define POWER_GPREGRET_GPREGRET_Pos (0UL)
- #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos)
- #define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos)
- #define PWM_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL)
- #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos)
- #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (1UL)
- #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL)
- #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos)
- #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (1UL)
- #define PWM_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define PWM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PWM_SUBSCRIBE_STOP_EN_Pos)
- #define PWM_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define PWM_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define PWM_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define PWM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_STOP_CHIDX_Pos)
- #define PWM_SUBSCRIBE_SEQSTART_EN_Pos (31UL)
- #define PWM_SUBSCRIBE_SEQSTART_EN_Msk (0x1UL << PWM_SUBSCRIBE_SEQSTART_EN_Pos)
- #define PWM_SUBSCRIBE_SEQSTART_EN_Disabled (0UL)
- #define PWM_SUBSCRIBE_SEQSTART_EN_Enabled (1UL)
- #define PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos (0UL)
- #define PWM_SUBSCRIBE_SEQSTART_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos)
- #define PWM_SUBSCRIBE_NEXTSTEP_EN_Pos (31UL)
- #define PWM_SUBSCRIBE_NEXTSTEP_EN_Msk (0x1UL << PWM_SUBSCRIBE_NEXTSTEP_EN_Pos)
- #define PWM_SUBSCRIBE_NEXTSTEP_EN_Disabled (0UL)
- #define PWM_SUBSCRIBE_NEXTSTEP_EN_Enabled (1UL)
- #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos (0UL)
- #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos)
- #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL)
- #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos)
- #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL)
- #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL)
- #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL)
- #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos)
- #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0UL)
- #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (1UL)
- #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL)
- #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos)
- #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0UL)
- #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (1UL)
- #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL)
- #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos)
- #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0UL)
- #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (1UL)
- #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL)
- #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos)
- #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0UL)
- #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (1UL)
- #define PWM_PUBLISH_STOPPED_EN_Pos (31UL)
- #define PWM_PUBLISH_STOPPED_EN_Msk (0x1UL << PWM_PUBLISH_STOPPED_EN_Pos)
- #define PWM_PUBLISH_STOPPED_EN_Disabled (0UL)
- #define PWM_PUBLISH_STOPPED_EN_Enabled (1UL)
- #define PWM_PUBLISH_STOPPED_CHIDX_Pos (0UL)
- #define PWM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_STOPPED_CHIDX_Pos)
- #define PWM_PUBLISH_SEQSTARTED_EN_Pos (31UL)
- #define PWM_PUBLISH_SEQSTARTED_EN_Msk (0x1UL << PWM_PUBLISH_SEQSTARTED_EN_Pos)
- #define PWM_PUBLISH_SEQSTARTED_EN_Disabled (0UL)
- #define PWM_PUBLISH_SEQSTARTED_EN_Enabled (1UL)
- #define PWM_PUBLISH_SEQSTARTED_CHIDX_Pos (0UL)
- #define PWM_PUBLISH_SEQSTARTED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQSTARTED_CHIDX_Pos)
- #define PWM_PUBLISH_SEQEND_EN_Pos (31UL)
- #define PWM_PUBLISH_SEQEND_EN_Msk (0x1UL << PWM_PUBLISH_SEQEND_EN_Pos)
- #define PWM_PUBLISH_SEQEND_EN_Disabled (0UL)
- #define PWM_PUBLISH_SEQEND_EN_Enabled (1UL)
- #define PWM_PUBLISH_SEQEND_CHIDX_Pos (0UL)
- #define PWM_PUBLISH_SEQEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQEND_CHIDX_Pos)
- #define PWM_PUBLISH_PWMPERIODEND_EN_Pos (31UL)
- #define PWM_PUBLISH_PWMPERIODEND_EN_Msk (0x1UL << PWM_PUBLISH_PWMPERIODEND_EN_Pos)
- #define PWM_PUBLISH_PWMPERIODEND_EN_Disabled (0UL)
- #define PWM_PUBLISH_PWMPERIODEND_EN_Enabled (1UL)
- #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos (0UL)
- #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos)
- #define PWM_PUBLISH_LOOPSDONE_EN_Pos (31UL)
- #define PWM_PUBLISH_LOOPSDONE_EN_Msk (0x1UL << PWM_PUBLISH_LOOPSDONE_EN_Pos)
- #define PWM_PUBLISH_LOOPSDONE_EN_Disabled (0UL)
- #define PWM_PUBLISH_LOOPSDONE_EN_Enabled (1UL)
- #define PWM_PUBLISH_LOOPSDONE_CHIDX_Pos (0UL)
- #define PWM_PUBLISH_LOOPSDONE_CHIDX_Msk (0xFFUL << PWM_PUBLISH_LOOPSDONE_CHIDX_Pos)
- #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL)
- #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos)
- #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL)
- #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL)
- #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL)
- #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos)
- #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL)
- #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL)
- #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL)
- #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos)
- #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL)
- #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL)
- #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL)
- #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos)
- #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL)
- #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL)
- #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL)
- #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos)
- #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL)
- #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL)
- #define PWM_INTEN_LOOPSDONE_Pos (7UL)
- #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos)
- #define PWM_INTEN_LOOPSDONE_Disabled (0UL)
- #define PWM_INTEN_LOOPSDONE_Enabled (1UL)
- #define PWM_INTEN_PWMPERIODEND_Pos (6UL)
- #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos)
- #define PWM_INTEN_PWMPERIODEND_Disabled (0UL)
- #define PWM_INTEN_PWMPERIODEND_Enabled (1UL)
- #define PWM_INTEN_SEQEND1_Pos (5UL)
- #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos)
- #define PWM_INTEN_SEQEND1_Disabled (0UL)
- #define PWM_INTEN_SEQEND1_Enabled (1UL)
- #define PWM_INTEN_SEQEND0_Pos (4UL)
- #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos)
- #define PWM_INTEN_SEQEND0_Disabled (0UL)
- #define PWM_INTEN_SEQEND0_Enabled (1UL)
- #define PWM_INTEN_SEQSTARTED1_Pos (3UL)
- #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos)
- #define PWM_INTEN_SEQSTARTED1_Disabled (0UL)
- #define PWM_INTEN_SEQSTARTED1_Enabled (1UL)
- #define PWM_INTEN_SEQSTARTED0_Pos (2UL)
- #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos)
- #define PWM_INTEN_SEQSTARTED0_Disabled (0UL)
- #define PWM_INTEN_SEQSTARTED0_Enabled (1UL)
- #define PWM_INTEN_STOPPED_Pos (1UL)
- #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos)
- #define PWM_INTEN_STOPPED_Disabled (0UL)
- #define PWM_INTEN_STOPPED_Enabled (1UL)
- #define PWM_INTENSET_LOOPSDONE_Pos (7UL)
- #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos)
- #define PWM_INTENSET_LOOPSDONE_Disabled (0UL)
- #define PWM_INTENSET_LOOPSDONE_Enabled (1UL)
- #define PWM_INTENSET_LOOPSDONE_Set (1UL)
- #define PWM_INTENSET_PWMPERIODEND_Pos (6UL)
- #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos)
- #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL)
- #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL)
- #define PWM_INTENSET_PWMPERIODEND_Set (1UL)
- #define PWM_INTENSET_SEQEND1_Pos (5UL)
- #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos)
- #define PWM_INTENSET_SEQEND1_Disabled (0UL)
- #define PWM_INTENSET_SEQEND1_Enabled (1UL)
- #define PWM_INTENSET_SEQEND1_Set (1UL)
- #define PWM_INTENSET_SEQEND0_Pos (4UL)
- #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos)
- #define PWM_INTENSET_SEQEND0_Disabled (0UL)
- #define PWM_INTENSET_SEQEND0_Enabled (1UL)
- #define PWM_INTENSET_SEQEND0_Set (1UL)
- #define PWM_INTENSET_SEQSTARTED1_Pos (3UL)
- #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos)
- #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL)
- #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL)
- #define PWM_INTENSET_SEQSTARTED1_Set (1UL)
- #define PWM_INTENSET_SEQSTARTED0_Pos (2UL)
- #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos)
- #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL)
- #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL)
- #define PWM_INTENSET_SEQSTARTED0_Set (1UL)
- #define PWM_INTENSET_STOPPED_Pos (1UL)
- #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos)
- #define PWM_INTENSET_STOPPED_Disabled (0UL)
- #define PWM_INTENSET_STOPPED_Enabled (1UL)
- #define PWM_INTENSET_STOPPED_Set (1UL)
- #define PWM_INTENCLR_LOOPSDONE_Pos (7UL)
- #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos)
- #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL)
- #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL)
- #define PWM_INTENCLR_LOOPSDONE_Clear (1UL)
- #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL)
- #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos)
- #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL)
- #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL)
- #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL)
- #define PWM_INTENCLR_SEQEND1_Pos (5UL)
- #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos)
- #define PWM_INTENCLR_SEQEND1_Disabled (0UL)
- #define PWM_INTENCLR_SEQEND1_Enabled (1UL)
- #define PWM_INTENCLR_SEQEND1_Clear (1UL)
- #define PWM_INTENCLR_SEQEND0_Pos (4UL)
- #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos)
- #define PWM_INTENCLR_SEQEND0_Disabled (0UL)
- #define PWM_INTENCLR_SEQEND0_Enabled (1UL)
- #define PWM_INTENCLR_SEQEND0_Clear (1UL)
- #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL)
- #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos)
- #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL)
- #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL)
- #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL)
- #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL)
- #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos)
- #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL)
- #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL)
- #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL)
- #define PWM_INTENCLR_STOPPED_Pos (1UL)
- #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos)
- #define PWM_INTENCLR_STOPPED_Disabled (0UL)
- #define PWM_INTENCLR_STOPPED_Enabled (1UL)
- #define PWM_INTENCLR_STOPPED_Clear (1UL)
- #define PWM_ENABLE_ENABLE_Pos (0UL)
- #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos)
- #define PWM_ENABLE_ENABLE_Disabled (0UL)
- #define PWM_ENABLE_ENABLE_Enabled (1UL)
- #define PWM_MODE_UPDOWN_Pos (0UL)
- #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos)
- #define PWM_MODE_UPDOWN_Up (0UL)
- #define PWM_MODE_UPDOWN_UpAndDown (1UL)
- #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL)
- #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos)
- #define PWM_PRESCALER_PRESCALER_Pos (0UL)
- #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos)
- #define PWM_PRESCALER_PRESCALER_DIV_1 (0UL)
- #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL)
- #define PWM_PRESCALER_PRESCALER_DIV_4 (2UL)
- #define PWM_PRESCALER_PRESCALER_DIV_8 (3UL)
- #define PWM_PRESCALER_PRESCALER_DIV_16 (4UL)
- #define PWM_PRESCALER_PRESCALER_DIV_32 (5UL)
- #define PWM_PRESCALER_PRESCALER_DIV_64 (6UL)
- #define PWM_PRESCALER_PRESCALER_DIV_128 (7UL)
- #define PWM_DECODER_MODE_Pos (8UL)
- #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos)
- #define PWM_DECODER_MODE_RefreshCount (0UL)
- #define PWM_DECODER_MODE_NextStep (1UL)
- #define PWM_DECODER_LOAD_Pos (0UL)
- #define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos)
- #define PWM_DECODER_LOAD_Common (0UL)
- #define PWM_DECODER_LOAD_Grouped (1UL)
- #define PWM_DECODER_LOAD_Individual (2UL)
- #define PWM_DECODER_LOAD_WaveForm (3UL)
- #define PWM_LOOP_CNT_Pos (0UL)
- #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos)
- #define PWM_LOOP_CNT_Disabled (0UL)
- #define PWM_SEQ_PTR_PTR_Pos (0UL)
- #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos)
- #define PWM_SEQ_CNT_CNT_Pos (0UL)
- #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos)
- #define PWM_SEQ_CNT_CNT_Disabled (0UL)
- #define PWM_SEQ_REFRESH_CNT_Pos (0UL)
- #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos)
- #define PWM_SEQ_REFRESH_CNT_Continuous (0UL)
- #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL)
- #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos)
- #define PWM_PSEL_OUT_CONNECT_Pos (31UL)
- #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos)
- #define PWM_PSEL_OUT_CONNECT_Connected (0UL)
- #define PWM_PSEL_OUT_CONNECT_Disconnected (1UL)
- #define PWM_PSEL_OUT_PORT_Pos (5UL)
- #define PWM_PSEL_OUT_PORT_Msk (0x1UL << PWM_PSEL_OUT_PORT_Pos)
- #define PWM_PSEL_OUT_PIN_Pos (0UL)
- #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos)
- #define QDEC_TASKS_START_TASKS_START_Pos (0UL)
- #define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos)
- #define QDEC_TASKS_START_TASKS_START_Trigger (1UL)
- #define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos)
- #define QDEC_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL)
- #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos)
- #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (1UL)
- #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL)
- #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos)
- #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (1UL)
- #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL)
- #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos)
- #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (1UL)
- #define QDEC_SUBSCRIBE_START_EN_Pos (31UL)
- #define QDEC_SUBSCRIBE_START_EN_Msk (0x1UL << QDEC_SUBSCRIBE_START_EN_Pos)
- #define QDEC_SUBSCRIBE_START_EN_Disabled (0UL)
- #define QDEC_SUBSCRIBE_START_EN_Enabled (1UL)
- #define QDEC_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define QDEC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_START_CHIDX_Pos)
- #define QDEC_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define QDEC_SUBSCRIBE_STOP_EN_Msk (0x1UL << QDEC_SUBSCRIBE_STOP_EN_Pos)
- #define QDEC_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define QDEC_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define QDEC_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define QDEC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_STOP_CHIDX_Pos)
- #define QDEC_SUBSCRIBE_READCLRACC_EN_Pos (31UL)
- #define QDEC_SUBSCRIBE_READCLRACC_EN_Msk (0x1UL << QDEC_SUBSCRIBE_READCLRACC_EN_Pos)
- #define QDEC_SUBSCRIBE_READCLRACC_EN_Disabled (0UL)
- #define QDEC_SUBSCRIBE_READCLRACC_EN_Enabled (1UL)
- #define QDEC_SUBSCRIBE_READCLRACC_CHIDX_Pos (0UL)
- #define QDEC_SUBSCRIBE_READCLRACC_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_READCLRACC_CHIDX_Pos)
- #define QDEC_SUBSCRIBE_RDCLRACC_EN_Pos (31UL)
- #define QDEC_SUBSCRIBE_RDCLRACC_EN_Msk (0x1UL << QDEC_SUBSCRIBE_RDCLRACC_EN_Pos)
- #define QDEC_SUBSCRIBE_RDCLRACC_EN_Disabled (0UL)
- #define QDEC_SUBSCRIBE_RDCLRACC_EN_Enabled (1UL)
- #define QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Pos (0UL)
- #define QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Pos)
- #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Pos (31UL)
- #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Msk (0x1UL << QDEC_SUBSCRIBE_RDCLRDBL_EN_Pos)
- #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Disabled (0UL)
- #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Enabled (1UL)
- #define QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Pos (0UL)
- #define QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Pos)
- #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL)
- #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos)
- #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0UL)
- #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (1UL)
- #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL)
- #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos)
- #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0UL)
- #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (1UL)
- #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL)
- #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos)
- #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0UL)
- #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (1UL)
- #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL)
- #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos)
- #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0UL)
- #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (1UL)
- #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL)
- #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos)
- #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL)
- #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL)
- #define QDEC_PUBLISH_SAMPLERDY_EN_Pos (31UL)
- #define QDEC_PUBLISH_SAMPLERDY_EN_Msk (0x1UL << QDEC_PUBLISH_SAMPLERDY_EN_Pos)
- #define QDEC_PUBLISH_SAMPLERDY_EN_Disabled (0UL)
- #define QDEC_PUBLISH_SAMPLERDY_EN_Enabled (1UL)
- #define QDEC_PUBLISH_SAMPLERDY_CHIDX_Pos (0UL)
- #define QDEC_PUBLISH_SAMPLERDY_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_SAMPLERDY_CHIDX_Pos)
- #define QDEC_PUBLISH_REPORTRDY_EN_Pos (31UL)
- #define QDEC_PUBLISH_REPORTRDY_EN_Msk (0x1UL << QDEC_PUBLISH_REPORTRDY_EN_Pos)
- #define QDEC_PUBLISH_REPORTRDY_EN_Disabled (0UL)
- #define QDEC_PUBLISH_REPORTRDY_EN_Enabled (1UL)
- #define QDEC_PUBLISH_REPORTRDY_CHIDX_Pos (0UL)
- #define QDEC_PUBLISH_REPORTRDY_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_REPORTRDY_CHIDX_Pos)
- #define QDEC_PUBLISH_ACCOF_EN_Pos (31UL)
- #define QDEC_PUBLISH_ACCOF_EN_Msk (0x1UL << QDEC_PUBLISH_ACCOF_EN_Pos)
- #define QDEC_PUBLISH_ACCOF_EN_Disabled (0UL)
- #define QDEC_PUBLISH_ACCOF_EN_Enabled (1UL)
- #define QDEC_PUBLISH_ACCOF_CHIDX_Pos (0UL)
- #define QDEC_PUBLISH_ACCOF_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_ACCOF_CHIDX_Pos)
- #define QDEC_PUBLISH_DBLRDY_EN_Pos (31UL)
- #define QDEC_PUBLISH_DBLRDY_EN_Msk (0x1UL << QDEC_PUBLISH_DBLRDY_EN_Pos)
- #define QDEC_PUBLISH_DBLRDY_EN_Disabled (0UL)
- #define QDEC_PUBLISH_DBLRDY_EN_Enabled (1UL)
- #define QDEC_PUBLISH_DBLRDY_CHIDX_Pos (0UL)
- #define QDEC_PUBLISH_DBLRDY_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_DBLRDY_CHIDX_Pos)
- #define QDEC_PUBLISH_STOPPED_EN_Pos (31UL)
- #define QDEC_PUBLISH_STOPPED_EN_Msk (0x1UL << QDEC_PUBLISH_STOPPED_EN_Pos)
- #define QDEC_PUBLISH_STOPPED_EN_Disabled (0UL)
- #define QDEC_PUBLISH_STOPPED_EN_Enabled (1UL)
- #define QDEC_PUBLISH_STOPPED_CHIDX_Pos (0UL)
- #define QDEC_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_STOPPED_CHIDX_Pos)
- #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL)
- #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos)
- #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL)
- #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL)
- #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL)
- #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos)
- #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL)
- #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL)
- #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL)
- #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos)
- #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL)
- #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL)
- #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL)
- #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos)
- #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL)
- #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL)
- #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL)
- #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos)
- #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL)
- #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL)
- #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL)
- #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos)
- #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL)
- #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL)
- #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL)
- #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos)
- #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL)
- #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL)
- #define QDEC_INTENSET_STOPPED_Pos (4UL)
- #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos)
- #define QDEC_INTENSET_STOPPED_Disabled (0UL)
- #define QDEC_INTENSET_STOPPED_Enabled (1UL)
- #define QDEC_INTENSET_STOPPED_Set (1UL)
- #define QDEC_INTENSET_DBLRDY_Pos (3UL)
- #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos)
- #define QDEC_INTENSET_DBLRDY_Disabled (0UL)
- #define QDEC_INTENSET_DBLRDY_Enabled (1UL)
- #define QDEC_INTENSET_DBLRDY_Set (1UL)
- #define QDEC_INTENSET_ACCOF_Pos (2UL)
- #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos)
- #define QDEC_INTENSET_ACCOF_Disabled (0UL)
- #define QDEC_INTENSET_ACCOF_Enabled (1UL)
- #define QDEC_INTENSET_ACCOF_Set (1UL)
- #define QDEC_INTENSET_REPORTRDY_Pos (1UL)
- #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos)
- #define QDEC_INTENSET_REPORTRDY_Disabled (0UL)
- #define QDEC_INTENSET_REPORTRDY_Enabled (1UL)
- #define QDEC_INTENSET_REPORTRDY_Set (1UL)
- #define QDEC_INTENSET_SAMPLERDY_Pos (0UL)
- #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos)
- #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL)
- #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL)
- #define QDEC_INTENSET_SAMPLERDY_Set (1UL)
- #define QDEC_INTENCLR_STOPPED_Pos (4UL)
- #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos)
- #define QDEC_INTENCLR_STOPPED_Disabled (0UL)
- #define QDEC_INTENCLR_STOPPED_Enabled (1UL)
- #define QDEC_INTENCLR_STOPPED_Clear (1UL)
- #define QDEC_INTENCLR_DBLRDY_Pos (3UL)
- #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos)
- #define QDEC_INTENCLR_DBLRDY_Disabled (0UL)
- #define QDEC_INTENCLR_DBLRDY_Enabled (1UL)
- #define QDEC_INTENCLR_DBLRDY_Clear (1UL)
- #define QDEC_INTENCLR_ACCOF_Pos (2UL)
- #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos)
- #define QDEC_INTENCLR_ACCOF_Disabled (0UL)
- #define QDEC_INTENCLR_ACCOF_Enabled (1UL)
- #define QDEC_INTENCLR_ACCOF_Clear (1UL)
- #define QDEC_INTENCLR_REPORTRDY_Pos (1UL)
- #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos)
- #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL)
- #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL)
- #define QDEC_INTENCLR_REPORTRDY_Clear (1UL)
- #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL)
- #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos)
- #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL)
- #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL)
- #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL)
- #define QDEC_ENABLE_ENABLE_Pos (0UL)
- #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos)
- #define QDEC_ENABLE_ENABLE_Disabled (0UL)
- #define QDEC_ENABLE_ENABLE_Enabled (1UL)
- #define QDEC_LEDPOL_LEDPOL_Pos (0UL)
- #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos)
- #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL)
- #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL)
- #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL)
- #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos)
- #define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL)
- #define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL)
- #define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL)
- #define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL)
- #define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL)
- #define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL)
- #define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL)
- #define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL)
- #define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL)
- #define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL)
- #define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL)
- #define QDEC_SAMPLE_SAMPLE_Pos (0UL)
- #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos)
- #define QDEC_REPORTPER_REPORTPER_Pos (0UL)
- #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos)
- #define QDEC_REPORTPER_REPORTPER_10Smpl (0UL)
- #define QDEC_REPORTPER_REPORTPER_40Smpl (1UL)
- #define QDEC_REPORTPER_REPORTPER_80Smpl (2UL)
- #define QDEC_REPORTPER_REPORTPER_120Smpl (3UL)
- #define QDEC_REPORTPER_REPORTPER_160Smpl (4UL)
- #define QDEC_REPORTPER_REPORTPER_200Smpl (5UL)
- #define QDEC_REPORTPER_REPORTPER_240Smpl (6UL)
- #define QDEC_REPORTPER_REPORTPER_280Smpl (7UL)
- #define QDEC_REPORTPER_REPORTPER_1Smpl (8UL)
- #define QDEC_ACC_ACC_Pos (0UL)
- #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos)
- #define QDEC_ACCREAD_ACCREAD_Pos (0UL)
- #define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos)
- #define QDEC_PSEL_LED_CONNECT_Pos (31UL)
- #define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos)
- #define QDEC_PSEL_LED_CONNECT_Connected (0UL)
- #define QDEC_PSEL_LED_CONNECT_Disconnected (1UL)
- #define QDEC_PSEL_LED_PORT_Pos (5UL)
- #define QDEC_PSEL_LED_PORT_Msk (0x1UL << QDEC_PSEL_LED_PORT_Pos)
- #define QDEC_PSEL_LED_PIN_Pos (0UL)
- #define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos)
- #define QDEC_PSEL_A_CONNECT_Pos (31UL)
- #define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos)
- #define QDEC_PSEL_A_CONNECT_Connected (0UL)
- #define QDEC_PSEL_A_CONNECT_Disconnected (1UL)
- #define QDEC_PSEL_A_PORT_Pos (5UL)
- #define QDEC_PSEL_A_PORT_Msk (0x1UL << QDEC_PSEL_A_PORT_Pos)
- #define QDEC_PSEL_A_PIN_Pos (0UL)
- #define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos)
- #define QDEC_PSEL_B_CONNECT_Pos (31UL)
- #define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos)
- #define QDEC_PSEL_B_CONNECT_Connected (0UL)
- #define QDEC_PSEL_B_CONNECT_Disconnected (1UL)
- #define QDEC_PSEL_B_PORT_Pos (5UL)
- #define QDEC_PSEL_B_PORT_Msk (0x1UL << QDEC_PSEL_B_PORT_Pos)
- #define QDEC_PSEL_B_PIN_Pos (0UL)
- #define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos)
- #define QDEC_DBFEN_DBFEN_Pos (0UL)
- #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos)
- #define QDEC_DBFEN_DBFEN_Disabled (0UL)
- #define QDEC_DBFEN_DBFEN_Enabled (1UL)
- #define QDEC_LEDPRE_LEDPRE_Pos (0UL)
- #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos)
- #define QDEC_ACCDBL_ACCDBL_Pos (0UL)
- #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos)
- #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL)
- #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos)
- #define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL)
- #define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos)
- #define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (1UL)
- #define QSPI_TASKS_READSTART_TASKS_READSTART_Pos (0UL)
- #define QSPI_TASKS_READSTART_TASKS_READSTART_Msk (0x1UL << QSPI_TASKS_READSTART_TASKS_READSTART_Pos)
- #define QSPI_TASKS_READSTART_TASKS_READSTART_Trigger (1UL)
- #define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Pos (0UL)
- #define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Msk (0x1UL << QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Pos)
- #define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Trigger (1UL)
- #define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Pos (0UL)
- #define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Msk (0x1UL << QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Pos)
- #define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Trigger (1UL)
- #define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Pos (0UL)
- #define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Msk (0x1UL << QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Pos)
- #define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Trigger (1UL)
- #define QSPI_SUBSCRIBE_ACTIVATE_EN_Pos (31UL)
- #define QSPI_SUBSCRIBE_ACTIVATE_EN_Msk (0x1UL << QSPI_SUBSCRIBE_ACTIVATE_EN_Pos)
- #define QSPI_SUBSCRIBE_ACTIVATE_EN_Disabled (0UL)
- #define QSPI_SUBSCRIBE_ACTIVATE_EN_Enabled (1UL)
- #define QSPI_SUBSCRIBE_ACTIVATE_CHIDX_Pos (0UL)
- #define QSPI_SUBSCRIBE_ACTIVATE_CHIDX_Msk (0xFFUL << QSPI_SUBSCRIBE_ACTIVATE_CHIDX_Pos)
- #define QSPI_SUBSCRIBE_READSTART_EN_Pos (31UL)
- #define QSPI_SUBSCRIBE_READSTART_EN_Msk (0x1UL << QSPI_SUBSCRIBE_READSTART_EN_Pos)
- #define QSPI_SUBSCRIBE_READSTART_EN_Disabled (0UL)
- #define QSPI_SUBSCRIBE_READSTART_EN_Enabled (1UL)
- #define QSPI_SUBSCRIBE_READSTART_CHIDX_Pos (0UL)
- #define QSPI_SUBSCRIBE_READSTART_CHIDX_Msk (0xFFUL << QSPI_SUBSCRIBE_READSTART_CHIDX_Pos)
- #define QSPI_SUBSCRIBE_WRITESTART_EN_Pos (31UL)
- #define QSPI_SUBSCRIBE_WRITESTART_EN_Msk (0x1UL << QSPI_SUBSCRIBE_WRITESTART_EN_Pos)
- #define QSPI_SUBSCRIBE_WRITESTART_EN_Disabled (0UL)
- #define QSPI_SUBSCRIBE_WRITESTART_EN_Enabled (1UL)
- #define QSPI_SUBSCRIBE_WRITESTART_CHIDX_Pos (0UL)
- #define QSPI_SUBSCRIBE_WRITESTART_CHIDX_Msk (0xFFUL << QSPI_SUBSCRIBE_WRITESTART_CHIDX_Pos)
- #define QSPI_SUBSCRIBE_ERASESTART_EN_Pos (31UL)
- #define QSPI_SUBSCRIBE_ERASESTART_EN_Msk (0x1UL << QSPI_SUBSCRIBE_ERASESTART_EN_Pos)
- #define QSPI_SUBSCRIBE_ERASESTART_EN_Disabled (0UL)
- #define QSPI_SUBSCRIBE_ERASESTART_EN_Enabled (1UL)
- #define QSPI_SUBSCRIBE_ERASESTART_CHIDX_Pos (0UL)
- #define QSPI_SUBSCRIBE_ERASESTART_CHIDX_Msk (0xFFUL << QSPI_SUBSCRIBE_ERASESTART_CHIDX_Pos)
- #define QSPI_SUBSCRIBE_DEACTIVATE_EN_Pos (31UL)
- #define QSPI_SUBSCRIBE_DEACTIVATE_EN_Msk (0x1UL << QSPI_SUBSCRIBE_DEACTIVATE_EN_Pos)
- #define QSPI_SUBSCRIBE_DEACTIVATE_EN_Disabled (0UL)
- #define QSPI_SUBSCRIBE_DEACTIVATE_EN_Enabled (1UL)
- #define QSPI_SUBSCRIBE_DEACTIVATE_CHIDX_Pos (0UL)
- #define QSPI_SUBSCRIBE_DEACTIVATE_CHIDX_Msk (0xFFUL << QSPI_SUBSCRIBE_DEACTIVATE_CHIDX_Pos)
- #define QSPI_EVENTS_READY_EVENTS_READY_Pos (0UL)
- #define QSPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << QSPI_EVENTS_READY_EVENTS_READY_Pos)
- #define QSPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL)
- #define QSPI_EVENTS_READY_EVENTS_READY_Generated (1UL)
- #define QSPI_PUBLISH_READY_EN_Pos (31UL)
- #define QSPI_PUBLISH_READY_EN_Msk (0x1UL << QSPI_PUBLISH_READY_EN_Pos)
- #define QSPI_PUBLISH_READY_EN_Disabled (0UL)
- #define QSPI_PUBLISH_READY_EN_Enabled (1UL)
- #define QSPI_PUBLISH_READY_CHIDX_Pos (0UL)
- #define QSPI_PUBLISH_READY_CHIDX_Msk (0xFFUL << QSPI_PUBLISH_READY_CHIDX_Pos)
- #define QSPI_INTEN_READY_Pos (0UL)
- #define QSPI_INTEN_READY_Msk (0x1UL << QSPI_INTEN_READY_Pos)
- #define QSPI_INTEN_READY_Disabled (0UL)
- #define QSPI_INTEN_READY_Enabled (1UL)
- #define QSPI_INTENSET_READY_Pos (0UL)
- #define QSPI_INTENSET_READY_Msk (0x1UL << QSPI_INTENSET_READY_Pos)
- #define QSPI_INTENSET_READY_Disabled (0UL)
- #define QSPI_INTENSET_READY_Enabled (1UL)
- #define QSPI_INTENSET_READY_Set (1UL)
- #define QSPI_INTENCLR_READY_Pos (0UL)
- #define QSPI_INTENCLR_READY_Msk (0x1UL << QSPI_INTENCLR_READY_Pos)
- #define QSPI_INTENCLR_READY_Disabled (0UL)
- #define QSPI_INTENCLR_READY_Enabled (1UL)
- #define QSPI_INTENCLR_READY_Clear (1UL)
- #define QSPI_ENABLE_ENABLE_Pos (0UL)
- #define QSPI_ENABLE_ENABLE_Msk (0x1UL << QSPI_ENABLE_ENABLE_Pos)
- #define QSPI_ENABLE_ENABLE_Disabled (0UL)
- #define QSPI_ENABLE_ENABLE_Enabled (1UL)
- #define QSPI_READ_SRC_SRC_Pos (0UL)
- #define QSPI_READ_SRC_SRC_Msk (0xFFFFFFFFUL << QSPI_READ_SRC_SRC_Pos)
- #define QSPI_READ_DST_DST_Pos (0UL)
- #define QSPI_READ_DST_DST_Msk (0xFFFFFFFFUL << QSPI_READ_DST_DST_Pos)
- #define QSPI_READ_CNT_CNT_Pos (0UL)
- #define QSPI_READ_CNT_CNT_Msk (0x1FFFFFUL << QSPI_READ_CNT_CNT_Pos)
- #define QSPI_WRITE_DST_DST_Pos (0UL)
- #define QSPI_WRITE_DST_DST_Msk (0xFFFFFFFFUL << QSPI_WRITE_DST_DST_Pos)
- #define QSPI_WRITE_SRC_SRC_Pos (0UL)
- #define QSPI_WRITE_SRC_SRC_Msk (0xFFFFFFFFUL << QSPI_WRITE_SRC_SRC_Pos)
- #define QSPI_WRITE_CNT_CNT_Pos (0UL)
- #define QSPI_WRITE_CNT_CNT_Msk (0x1FFFFFUL << QSPI_WRITE_CNT_CNT_Pos)
- #define QSPI_ERASE_PTR_PTR_Pos (0UL)
- #define QSPI_ERASE_PTR_PTR_Msk (0xFFFFFFFFUL << QSPI_ERASE_PTR_PTR_Pos)
- #define QSPI_ERASE_LEN_LEN_Pos (0UL)
- #define QSPI_ERASE_LEN_LEN_Msk (0x3UL << QSPI_ERASE_LEN_LEN_Pos)
- #define QSPI_ERASE_LEN_LEN_4KB (0UL)
- #define QSPI_ERASE_LEN_LEN_64KB (1UL)
- #define QSPI_ERASE_LEN_LEN_All (2UL)
- #define QSPI_PSEL_SCK_CONNECT_Pos (31UL)
- #define QSPI_PSEL_SCK_CONNECT_Msk (0x1UL << QSPI_PSEL_SCK_CONNECT_Pos)
- #define QSPI_PSEL_SCK_CONNECT_Connected (0UL)
- #define QSPI_PSEL_SCK_CONNECT_Disconnected (1UL)
- #define QSPI_PSEL_SCK_PORT_Pos (5UL)
- #define QSPI_PSEL_SCK_PORT_Msk (0x1UL << QSPI_PSEL_SCK_PORT_Pos)
- #define QSPI_PSEL_SCK_PIN_Pos (0UL)
- #define QSPI_PSEL_SCK_PIN_Msk (0x1FUL << QSPI_PSEL_SCK_PIN_Pos)
- #define QSPI_PSEL_CSN_CONNECT_Pos (31UL)
- #define QSPI_PSEL_CSN_CONNECT_Msk (0x1UL << QSPI_PSEL_CSN_CONNECT_Pos)
- #define QSPI_PSEL_CSN_CONNECT_Connected (0UL)
- #define QSPI_PSEL_CSN_CONNECT_Disconnected (1UL)
- #define QSPI_PSEL_CSN_PORT_Pos (5UL)
- #define QSPI_PSEL_CSN_PORT_Msk (0x1UL << QSPI_PSEL_CSN_PORT_Pos)
- #define QSPI_PSEL_CSN_PIN_Pos (0UL)
- #define QSPI_PSEL_CSN_PIN_Msk (0x1FUL << QSPI_PSEL_CSN_PIN_Pos)
- #define QSPI_PSEL_IO0_CONNECT_Pos (31UL)
- #define QSPI_PSEL_IO0_CONNECT_Msk (0x1UL << QSPI_PSEL_IO0_CONNECT_Pos)
- #define QSPI_PSEL_IO0_CONNECT_Connected (0UL)
- #define QSPI_PSEL_IO0_CONNECT_Disconnected (1UL)
- #define QSPI_PSEL_IO0_PORT_Pos (5UL)
- #define QSPI_PSEL_IO0_PORT_Msk (0x1UL << QSPI_PSEL_IO0_PORT_Pos)
- #define QSPI_PSEL_IO0_PIN_Pos (0UL)
- #define QSPI_PSEL_IO0_PIN_Msk (0x1FUL << QSPI_PSEL_IO0_PIN_Pos)
- #define QSPI_PSEL_IO1_CONNECT_Pos (31UL)
- #define QSPI_PSEL_IO1_CONNECT_Msk (0x1UL << QSPI_PSEL_IO1_CONNECT_Pos)
- #define QSPI_PSEL_IO1_CONNECT_Connected (0UL)
- #define QSPI_PSEL_IO1_CONNECT_Disconnected (1UL)
- #define QSPI_PSEL_IO1_PORT_Pos (5UL)
- #define QSPI_PSEL_IO1_PORT_Msk (0x1UL << QSPI_PSEL_IO1_PORT_Pos)
- #define QSPI_PSEL_IO1_PIN_Pos (0UL)
- #define QSPI_PSEL_IO1_PIN_Msk (0x1FUL << QSPI_PSEL_IO1_PIN_Pos)
- #define QSPI_PSEL_IO2_CONNECT_Pos (31UL)
- #define QSPI_PSEL_IO2_CONNECT_Msk (0x1UL << QSPI_PSEL_IO2_CONNECT_Pos)
- #define QSPI_PSEL_IO2_CONNECT_Connected (0UL)
- #define QSPI_PSEL_IO2_CONNECT_Disconnected (1UL)
- #define QSPI_PSEL_IO2_PORT_Pos (5UL)
- #define QSPI_PSEL_IO2_PORT_Msk (0x1UL << QSPI_PSEL_IO2_PORT_Pos)
- #define QSPI_PSEL_IO2_PIN_Pos (0UL)
- #define QSPI_PSEL_IO2_PIN_Msk (0x1FUL << QSPI_PSEL_IO2_PIN_Pos)
- #define QSPI_PSEL_IO3_CONNECT_Pos (31UL)
- #define QSPI_PSEL_IO3_CONNECT_Msk (0x1UL << QSPI_PSEL_IO3_CONNECT_Pos)
- #define QSPI_PSEL_IO3_CONNECT_Connected (0UL)
- #define QSPI_PSEL_IO3_CONNECT_Disconnected (1UL)
- #define QSPI_PSEL_IO3_PORT_Pos (5UL)
- #define QSPI_PSEL_IO3_PORT_Msk (0x1UL << QSPI_PSEL_IO3_PORT_Pos)
- #define QSPI_PSEL_IO3_PIN_Pos (0UL)
- #define QSPI_PSEL_IO3_PIN_Msk (0x1FUL << QSPI_PSEL_IO3_PIN_Pos)
- #define QSPI_XIPOFFSET_XIPOFFSET_Pos (0UL)
- #define QSPI_XIPOFFSET_XIPOFFSET_Msk (0xFFFFFFFFUL << QSPI_XIPOFFSET_XIPOFFSET_Pos)
- #define QSPI_IFCONFIG0_PPSIZE_Pos (12UL)
- #define QSPI_IFCONFIG0_PPSIZE_Msk (0x1UL << QSPI_IFCONFIG0_PPSIZE_Pos)
- #define QSPI_IFCONFIG0_PPSIZE_256Bytes (0UL)
- #define QSPI_IFCONFIG0_PPSIZE_512Bytes (1UL)
- #define QSPI_IFCONFIG0_DPMENABLE_Pos (7UL)
- #define QSPI_IFCONFIG0_DPMENABLE_Msk (0x1UL << QSPI_IFCONFIG0_DPMENABLE_Pos)
- #define QSPI_IFCONFIG0_DPMENABLE_Disable (0UL)
- #define QSPI_IFCONFIG0_DPMENABLE_Enable (1UL)
- #define QSPI_IFCONFIG0_ADDRMODE_Pos (6UL)
- #define QSPI_IFCONFIG0_ADDRMODE_Msk (0x1UL << QSPI_IFCONFIG0_ADDRMODE_Pos)
- #define QSPI_IFCONFIG0_ADDRMODE_24BIT (0UL)
- #define QSPI_IFCONFIG0_ADDRMODE_32BIT (1UL)
- #define QSPI_IFCONFIG0_WRITEOC_Pos (3UL)
- #define QSPI_IFCONFIG0_WRITEOC_Msk (0x7UL << QSPI_IFCONFIG0_WRITEOC_Pos)
- #define QSPI_IFCONFIG0_WRITEOC_PP (0UL)
- #define QSPI_IFCONFIG0_WRITEOC_PP2O (1UL)
- #define QSPI_IFCONFIG0_WRITEOC_PP4O (2UL)
- #define QSPI_IFCONFIG0_WRITEOC_PP4IO (3UL)
- #define QSPI_IFCONFIG0_READOC_Pos (0UL)
- #define QSPI_IFCONFIG0_READOC_Msk (0x7UL << QSPI_IFCONFIG0_READOC_Pos)
- #define QSPI_IFCONFIG0_READOC_FASTREAD (0UL)
- #define QSPI_IFCONFIG0_READOC_READ2O (1UL)
- #define QSPI_IFCONFIG0_READOC_READ2IO (2UL)
- #define QSPI_IFCONFIG0_READOC_READ4O (3UL)
- #define QSPI_IFCONFIG0_READOC_READ4IO (4UL)
- #define QSPI_XIPEN_XIPEN_Pos (0UL)
- #define QSPI_XIPEN_XIPEN_Msk (0x1UL << QSPI_XIPEN_XIPEN_Pos)
- #define QSPI_XIPEN_XIPEN_Disable (0UL)
- #define QSPI_XIPEN_XIPEN_Enable (1UL)
- #define QSPI_XIP_ENC_KEY0_KEY0_Pos (0UL)
- #define QSPI_XIP_ENC_KEY0_KEY0_Msk (0xFFFFFFFFUL << QSPI_XIP_ENC_KEY0_KEY0_Pos)
- #define QSPI_XIP_ENC_KEY1_KEY1_Pos (0UL)
- #define QSPI_XIP_ENC_KEY1_KEY1_Msk (0xFFFFFFFFUL << QSPI_XIP_ENC_KEY1_KEY1_Pos)
- #define QSPI_XIP_ENC_KEY2_KEY2_Pos (0UL)
- #define QSPI_XIP_ENC_KEY2_KEY2_Msk (0xFFFFFFFFUL << QSPI_XIP_ENC_KEY2_KEY2_Pos)
- #define QSPI_XIP_ENC_KEY3_KEY3_Pos (0UL)
- #define QSPI_XIP_ENC_KEY3_KEY3_Msk (0xFFFFFFFFUL << QSPI_XIP_ENC_KEY3_KEY3_Pos)
- #define QSPI_XIP_ENC_NONCE0_NONCE0_Pos (0UL)
- #define QSPI_XIP_ENC_NONCE0_NONCE0_Msk (0xFFFFFFFFUL << QSPI_XIP_ENC_NONCE0_NONCE0_Pos)
- #define QSPI_XIP_ENC_NONCE1_NONCE1_Pos (0UL)
- #define QSPI_XIP_ENC_NONCE1_NONCE1_Msk (0xFFFFFFFFUL << QSPI_XIP_ENC_NONCE1_NONCE1_Pos)
- #define QSPI_XIP_ENC_NONCE2_NONCE2_Pos (0UL)
- #define QSPI_XIP_ENC_NONCE2_NONCE2_Msk (0xFFFFFFFFUL << QSPI_XIP_ENC_NONCE2_NONCE2_Pos)
- #define QSPI_XIP_ENC_ENABLE_ENABLE_Pos (0UL)
- #define QSPI_XIP_ENC_ENABLE_ENABLE_Msk (0x1UL << QSPI_XIP_ENC_ENABLE_ENABLE_Pos)
- #define QSPI_XIP_ENC_ENABLE_ENABLE_Disabled (0UL)
- #define QSPI_XIP_ENC_ENABLE_ENABLE_Enabled (1UL)
- #define QSPI_DMA_ENC_KEY0_KEY0_Pos (0UL)
- #define QSPI_DMA_ENC_KEY0_KEY0_Msk (0xFFFFFFFFUL << QSPI_DMA_ENC_KEY0_KEY0_Pos)
- #define QSPI_DMA_ENC_KEY1_KEY1_Pos (0UL)
- #define QSPI_DMA_ENC_KEY1_KEY1_Msk (0xFFFFFFFFUL << QSPI_DMA_ENC_KEY1_KEY1_Pos)
- #define QSPI_DMA_ENC_KEY2_KEY2_Pos (0UL)
- #define QSPI_DMA_ENC_KEY2_KEY2_Msk (0xFFFFFFFFUL << QSPI_DMA_ENC_KEY2_KEY2_Pos)
- #define QSPI_DMA_ENC_KEY3_KEY3_Pos (0UL)
- #define QSPI_DMA_ENC_KEY3_KEY3_Msk (0xFFFFFFFFUL << QSPI_DMA_ENC_KEY3_KEY3_Pos)
- #define QSPI_DMA_ENC_NONCE0_NONCE0_Pos (0UL)
- #define QSPI_DMA_ENC_NONCE0_NONCE0_Msk (0xFFFFFFFFUL << QSPI_DMA_ENC_NONCE0_NONCE0_Pos)
- #define QSPI_DMA_ENC_NONCE1_NONCE1_Pos (0UL)
- #define QSPI_DMA_ENC_NONCE1_NONCE1_Msk (0xFFFFFFFFUL << QSPI_DMA_ENC_NONCE1_NONCE1_Pos)
- #define QSPI_DMA_ENC_NONCE2_NONCE2_Pos (0UL)
- #define QSPI_DMA_ENC_NONCE2_NONCE2_Msk (0xFFFFFFFFUL << QSPI_DMA_ENC_NONCE2_NONCE2_Pos)
- #define QSPI_DMA_ENC_ENABLE_ENABLE_Pos (0UL)
- #define QSPI_DMA_ENC_ENABLE_ENABLE_Msk (0x1UL << QSPI_DMA_ENC_ENABLE_ENABLE_Pos)
- #define QSPI_DMA_ENC_ENABLE_ENABLE_Disabled (0UL)
- #define QSPI_DMA_ENC_ENABLE_ENABLE_Enabled (1UL)
- #define QSPI_IFCONFIG1_SCKFREQ_Pos (28UL)
- #define QSPI_IFCONFIG1_SCKFREQ_Msk (0xFUL << QSPI_IFCONFIG1_SCKFREQ_Pos)
- #define QSPI_IFCONFIG1_SPIMODE_Pos (25UL)
- #define QSPI_IFCONFIG1_SPIMODE_Msk (0x1UL << QSPI_IFCONFIG1_SPIMODE_Pos)
- #define QSPI_IFCONFIG1_SPIMODE_MODE0 (0UL)
- #define QSPI_IFCONFIG1_DPMEN_Pos (24UL)
- #define QSPI_IFCONFIG1_DPMEN_Msk (0x1UL << QSPI_IFCONFIG1_DPMEN_Pos)
- #define QSPI_IFCONFIG1_DPMEN_Exit (0UL)
- #define QSPI_IFCONFIG1_DPMEN_Enter (1UL)
- #define QSPI_IFCONFIG1_SCKDELAY_Pos (0UL)
- #define QSPI_IFCONFIG1_SCKDELAY_Msk (0xFFUL << QSPI_IFCONFIG1_SCKDELAY_Pos)
- #define QSPI_STATUS_SREG_Pos (24UL)
- #define QSPI_STATUS_SREG_Msk (0xFFUL << QSPI_STATUS_SREG_Pos)
- #define QSPI_STATUS_READY_Pos (3UL)
- #define QSPI_STATUS_READY_Msk (0x1UL << QSPI_STATUS_READY_Pos)
- #define QSPI_STATUS_READY_BUSY (0UL)
- #define QSPI_STATUS_READY_READY (1UL)
- #define QSPI_STATUS_DPM_Pos (2UL)
- #define QSPI_STATUS_DPM_Msk (0x1UL << QSPI_STATUS_DPM_Pos)
- #define QSPI_STATUS_DPM_Disabled (0UL)
- #define QSPI_STATUS_DPM_Enabled (1UL)
- #define QSPI_DPMDUR_EXIT_Pos (16UL)
- #define QSPI_DPMDUR_EXIT_Msk (0xFFFFUL << QSPI_DPMDUR_EXIT_Pos)
- #define QSPI_DPMDUR_ENTER_Pos (0UL)
- #define QSPI_DPMDUR_ENTER_Msk (0xFFFFUL << QSPI_DPMDUR_ENTER_Pos)
- #define QSPI_ADDRCONF_WREN_Pos (27UL)
- #define QSPI_ADDRCONF_WREN_Msk (0x1UL << QSPI_ADDRCONF_WREN_Pos)
- #define QSPI_ADDRCONF_WREN_Disable (0UL)
- #define QSPI_ADDRCONF_WREN_Enable (1UL)
- #define QSPI_ADDRCONF_WIPWAIT_Pos (26UL)
- #define QSPI_ADDRCONF_WIPWAIT_Msk (0x1UL << QSPI_ADDRCONF_WIPWAIT_Pos)
- #define QSPI_ADDRCONF_WIPWAIT_Disable (0UL)
- #define QSPI_ADDRCONF_WIPWAIT_Enable (1UL)
- #define QSPI_ADDRCONF_MODE_Pos (24UL)
- #define QSPI_ADDRCONF_MODE_Msk (0x3UL << QSPI_ADDRCONF_MODE_Pos)
- #define QSPI_ADDRCONF_MODE_NoInstr (0UL)
- #define QSPI_ADDRCONF_MODE_Opcode (1UL)
- #define QSPI_ADDRCONF_MODE_OpByte0 (2UL)
- #define QSPI_ADDRCONF_MODE_All (3UL)
- #define QSPI_ADDRCONF_BYTE1_Pos (16UL)
- #define QSPI_ADDRCONF_BYTE1_Msk (0xFFUL << QSPI_ADDRCONF_BYTE1_Pos)
- #define QSPI_ADDRCONF_BYTE0_Pos (8UL)
- #define QSPI_ADDRCONF_BYTE0_Msk (0xFFUL << QSPI_ADDRCONF_BYTE0_Pos)
- #define QSPI_ADDRCONF_OPCODE_Pos (0UL)
- #define QSPI_ADDRCONF_OPCODE_Msk (0xFFUL << QSPI_ADDRCONF_OPCODE_Pos)
- #define QSPI_CINSTRCONF_LFSTOP_Pos (17UL)
- #define QSPI_CINSTRCONF_LFSTOP_Msk (0x1UL << QSPI_CINSTRCONF_LFSTOP_Pos)
- #define QSPI_CINSTRCONF_LFSTOP_Stop (1UL)
- #define QSPI_CINSTRCONF_LFEN_Pos (16UL)
- #define QSPI_CINSTRCONF_LFEN_Msk (0x1UL << QSPI_CINSTRCONF_LFEN_Pos)
- #define QSPI_CINSTRCONF_LFEN_Disable (0UL)
- #define QSPI_CINSTRCONF_LFEN_Enable (1UL)
- #define QSPI_CINSTRCONF_WREN_Pos (15UL)
- #define QSPI_CINSTRCONF_WREN_Msk (0x1UL << QSPI_CINSTRCONF_WREN_Pos)
- #define QSPI_CINSTRCONF_WREN_Disable (0UL)
- #define QSPI_CINSTRCONF_WREN_Enable (1UL)
- #define QSPI_CINSTRCONF_WIPWAIT_Pos (14UL)
- #define QSPI_CINSTRCONF_WIPWAIT_Msk (0x1UL << QSPI_CINSTRCONF_WIPWAIT_Pos)
- #define QSPI_CINSTRCONF_WIPWAIT_Disable (0UL)
- #define QSPI_CINSTRCONF_WIPWAIT_Enable (1UL)
- #define QSPI_CINSTRCONF_LIO3_Pos (13UL)
- #define QSPI_CINSTRCONF_LIO3_Msk (0x1UL << QSPI_CINSTRCONF_LIO3_Pos)
- #define QSPI_CINSTRCONF_LIO2_Pos (12UL)
- #define QSPI_CINSTRCONF_LIO2_Msk (0x1UL << QSPI_CINSTRCONF_LIO2_Pos)
- #define QSPI_CINSTRCONF_LENGTH_Pos (8UL)
- #define QSPI_CINSTRCONF_LENGTH_Msk (0xFUL << QSPI_CINSTRCONF_LENGTH_Pos)
- #define QSPI_CINSTRCONF_LENGTH_1B (1UL)
- #define QSPI_CINSTRCONF_LENGTH_2B (2UL)
- #define QSPI_CINSTRCONF_LENGTH_3B (3UL)
- #define QSPI_CINSTRCONF_LENGTH_4B (4UL)
- #define QSPI_CINSTRCONF_LENGTH_5B (5UL)
- #define QSPI_CINSTRCONF_LENGTH_6B (6UL)
- #define QSPI_CINSTRCONF_LENGTH_7B (7UL)
- #define QSPI_CINSTRCONF_LENGTH_8B (8UL)
- #define QSPI_CINSTRCONF_LENGTH_9B (9UL)
- #define QSPI_CINSTRCONF_OPCODE_Pos (0UL)
- #define QSPI_CINSTRCONF_OPCODE_Msk (0xFFUL << QSPI_CINSTRCONF_OPCODE_Pos)
- #define QSPI_CINSTRDAT0_BYTE3_Pos (24UL)
- #define QSPI_CINSTRDAT0_BYTE3_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE3_Pos)
- #define QSPI_CINSTRDAT0_BYTE2_Pos (16UL)
- #define QSPI_CINSTRDAT0_BYTE2_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE2_Pos)
- #define QSPI_CINSTRDAT0_BYTE1_Pos (8UL)
- #define QSPI_CINSTRDAT0_BYTE1_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE1_Pos)
- #define QSPI_CINSTRDAT0_BYTE0_Pos (0UL)
- #define QSPI_CINSTRDAT0_BYTE0_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE0_Pos)
- #define QSPI_CINSTRDAT1_BYTE7_Pos (24UL)
- #define QSPI_CINSTRDAT1_BYTE7_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE7_Pos)
- #define QSPI_CINSTRDAT1_BYTE6_Pos (16UL)
- #define QSPI_CINSTRDAT1_BYTE6_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE6_Pos)
- #define QSPI_CINSTRDAT1_BYTE5_Pos (8UL)
- #define QSPI_CINSTRDAT1_BYTE5_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE5_Pos)
- #define QSPI_CINSTRDAT1_BYTE4_Pos (0UL)
- #define QSPI_CINSTRDAT1_BYTE4_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE4_Pos)
- #define REGULATORS_MAINREGSTATUS_VREGH_Pos (0UL)
- #define REGULATORS_MAINREGSTATUS_VREGH_Msk (0x1UL << REGULATORS_MAINREGSTATUS_VREGH_Pos)
- #define REGULATORS_MAINREGSTATUS_VREGH_Inactive (0UL)
- #define REGULATORS_MAINREGSTATUS_VREGH_Active (1UL)
- #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos (0UL)
- #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos)
- #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Enter (1UL)
- #define REGULATORS_POFCON_THRESHOLDVDDH_Pos (8UL)
- #define REGULATORS_POFCON_THRESHOLDVDDH_Msk (0xFUL << REGULATORS_POFCON_THRESHOLDVDDH_Pos)
- #define REGULATORS_POFCON_THRESHOLDVDDH_V27 (0UL)
- #define REGULATORS_POFCON_THRESHOLDVDDH_V28 (1UL)
- #define REGULATORS_POFCON_THRESHOLDVDDH_V29 (2UL)
- #define REGULATORS_POFCON_THRESHOLDVDDH_V30 (3UL)
- #define REGULATORS_POFCON_THRESHOLDVDDH_V31 (4UL)
- #define REGULATORS_POFCON_THRESHOLDVDDH_V32 (5UL)
- #define REGULATORS_POFCON_THRESHOLDVDDH_V33 (6UL)
- #define REGULATORS_POFCON_THRESHOLDVDDH_V34 (7UL)
- #define REGULATORS_POFCON_THRESHOLDVDDH_V35 (8UL)
- #define REGULATORS_POFCON_THRESHOLDVDDH_V36 (9UL)
- #define REGULATORS_POFCON_THRESHOLDVDDH_V37 (10UL)
- #define REGULATORS_POFCON_THRESHOLDVDDH_V38 (11UL)
- #define REGULATORS_POFCON_THRESHOLDVDDH_V39 (12UL)
- #define REGULATORS_POFCON_THRESHOLDVDDH_V40 (13UL)
- #define REGULATORS_POFCON_THRESHOLDVDDH_V41 (14UL)
- #define REGULATORS_POFCON_THRESHOLDVDDH_V42 (15UL)
- #define REGULATORS_POFCON_THRESHOLD_Pos (1UL)
- #define REGULATORS_POFCON_THRESHOLD_Msk (0xFUL << REGULATORS_POFCON_THRESHOLD_Pos)
- #define REGULATORS_POFCON_THRESHOLD_V19 (6UL)
- #define REGULATORS_POFCON_THRESHOLD_V20 (7UL)
- #define REGULATORS_POFCON_THRESHOLD_V21 (8UL)
- #define REGULATORS_POFCON_THRESHOLD_V22 (9UL)
- #define REGULATORS_POFCON_THRESHOLD_V23 (10UL)
- #define REGULATORS_POFCON_THRESHOLD_V24 (11UL)
- #define REGULATORS_POFCON_THRESHOLD_V25 (12UL)
- #define REGULATORS_POFCON_THRESHOLD_V26 (13UL)
- #define REGULATORS_POFCON_THRESHOLD_V27 (14UL)
- #define REGULATORS_POFCON_THRESHOLD_V28 (15UL)
- #define REGULATORS_POFCON_POF_Pos (0UL)
- #define REGULATORS_POFCON_POF_Msk (0x1UL << REGULATORS_POFCON_POF_Pos)
- #define REGULATORS_POFCON_POF_Disabled (0UL)
- #define REGULATORS_POFCON_POF_Enabled (1UL)
- #define REGULATORS_VREGMAIN_DCDCEN_DCDCEN_Pos (0UL)
- #define REGULATORS_VREGMAIN_DCDCEN_DCDCEN_Msk (0x1UL << REGULATORS_VREGMAIN_DCDCEN_DCDCEN_Pos)
- #define REGULATORS_VREGMAIN_DCDCEN_DCDCEN_Disabled (0UL)
- #define REGULATORS_VREGMAIN_DCDCEN_DCDCEN_Enabled (1UL)
- #define REGULATORS_VREGRADIO_DCDCEN_DCDCEN_Pos (0UL)
- #define REGULATORS_VREGRADIO_DCDCEN_DCDCEN_Msk (0x1UL << REGULATORS_VREGRADIO_DCDCEN_DCDCEN_Pos)
- #define REGULATORS_VREGRADIO_DCDCEN_DCDCEN_Disabled (0UL)
- #define REGULATORS_VREGRADIO_DCDCEN_DCDCEN_Enabled (1UL)
- #define REGULATORS_VREGH_DCDCEN_DCDCEN_Pos (0UL)
- #define REGULATORS_VREGH_DCDCEN_DCDCEN_Msk (0x1UL << REGULATORS_VREGH_DCDCEN_DCDCEN_Pos)
- #define REGULATORS_VREGH_DCDCEN_DCDCEN_Disabled (0UL)
- #define REGULATORS_VREGH_DCDCEN_DCDCEN_Enabled (1UL)
- #define RESET_RESETREAS_VBUS_Pos (26UL)
- #define RESET_RESETREAS_VBUS_Msk (0x1UL << RESET_RESETREAS_VBUS_Pos)
- #define RESET_RESETREAS_VBUS_NotDetected (0UL)
- #define RESET_RESETREAS_VBUS_Detected (1UL)
- #define RESET_RESETREAS_DOG1_Pos (25UL)
- #define RESET_RESETREAS_DOG1_Msk (0x1UL << RESET_RESETREAS_DOG1_Pos)
- #define RESET_RESETREAS_DOG1_NotDetected (0UL)
- #define RESET_RESETREAS_DOG1_Detected (1UL)
- #define RESET_RESETREAS_NFC_Pos (24UL)
- #define RESET_RESETREAS_NFC_Msk (0x1UL << RESET_RESETREAS_NFC_Pos)
- #define RESET_RESETREAS_NFC_NotDetected (0UL)
- #define RESET_RESETREAS_NFC_Detected (1UL)
- #define RESET_RESETREAS_DIF_Pos (7UL)
- #define RESET_RESETREAS_DIF_Msk (0x1UL << RESET_RESETREAS_DIF_Pos)
- #define RESET_RESETREAS_DIF_NotDetected (0UL)
- #define RESET_RESETREAS_DIF_Detected (1UL)
- #define RESET_RESETREAS_LPCOMP_Pos (6UL)
- #define RESET_RESETREAS_LPCOMP_Msk (0x1UL << RESET_RESETREAS_LPCOMP_Pos)
- #define RESET_RESETREAS_LPCOMP_NotDetected (0UL)
- #define RESET_RESETREAS_LPCOMP_Detected (1UL)
- #define RESET_RESETREAS_OFF_Pos (5UL)
- #define RESET_RESETREAS_OFF_Msk (0x1UL << RESET_RESETREAS_OFF_Pos)
- #define RESET_RESETREAS_OFF_NotDetected (0UL)
- #define RESET_RESETREAS_OFF_Detected (1UL)
- #define RESET_RESETREAS_LOCKUP_Pos (4UL)
- #define RESET_RESETREAS_LOCKUP_Msk (0x1UL << RESET_RESETREAS_LOCKUP_Pos)
- #define RESET_RESETREAS_LOCKUP_NotDetected (0UL)
- #define RESET_RESETREAS_LOCKUP_Detected (1UL)
- #define RESET_RESETREAS_SREQ_Pos (3UL)
- #define RESET_RESETREAS_SREQ_Msk (0x1UL << RESET_RESETREAS_SREQ_Pos)
- #define RESET_RESETREAS_SREQ_NotDetected (0UL)
- #define RESET_RESETREAS_SREQ_Detected (1UL)
- #define RESET_RESETREAS_CTRLAP_Pos (2UL)
- #define RESET_RESETREAS_CTRLAP_Msk (0x1UL << RESET_RESETREAS_CTRLAP_Pos)
- #define RESET_RESETREAS_CTRLAP_NotDetected (0UL)
- #define RESET_RESETREAS_CTRLAP_Detected (1UL)
- #define RESET_RESETREAS_DOG0_Pos (1UL)
- #define RESET_RESETREAS_DOG0_Msk (0x1UL << RESET_RESETREAS_DOG0_Pos)
- #define RESET_RESETREAS_DOG0_NotDetected (0UL)
- #define RESET_RESETREAS_DOG0_Detected (1UL)
- #define RESET_RESETREAS_RESETPIN_Pos (0UL)
- #define RESET_RESETREAS_RESETPIN_Msk (0x1UL << RESET_RESETREAS_RESETPIN_Pos)
- #define RESET_RESETREAS_RESETPIN_NotDetected (0UL)
- #define RESET_RESETREAS_RESETPIN_Detected (1UL)
- #define RESET_NETWORK_FORCEOFF_FORCEOFF_Pos (0UL)
- #define RESET_NETWORK_FORCEOFF_FORCEOFF_Msk (0x1UL << RESET_NETWORK_FORCEOFF_FORCEOFF_Pos)
- #define RESET_NETWORK_FORCEOFF_FORCEOFF_Release (0UL)
- #define RESET_NETWORK_FORCEOFF_FORCEOFF_Hold (1UL)
- #define RTC_TASKS_START_TASKS_START_Pos (0UL)
- #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos)
- #define RTC_TASKS_START_TASKS_START_Trigger (1UL)
- #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos)
- #define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL)
- #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos)
- #define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL)
- #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL)
- #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos)
- #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL)
- #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL)
- #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << RTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos)
- #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL)
- #define RTC_SUBSCRIBE_START_EN_Pos (31UL)
- #define RTC_SUBSCRIBE_START_EN_Msk (0x1UL << RTC_SUBSCRIBE_START_EN_Pos)
- #define RTC_SUBSCRIBE_START_EN_Disabled (0UL)
- #define RTC_SUBSCRIBE_START_EN_Enabled (1UL)
- #define RTC_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define RTC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_START_CHIDX_Pos)
- #define RTC_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define RTC_SUBSCRIBE_STOP_EN_Msk (0x1UL << RTC_SUBSCRIBE_STOP_EN_Pos)
- #define RTC_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define RTC_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define RTC_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define RTC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_STOP_CHIDX_Pos)
- #define RTC_SUBSCRIBE_CLEAR_EN_Pos (31UL)
- #define RTC_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << RTC_SUBSCRIBE_CLEAR_EN_Pos)
- #define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0UL)
- #define RTC_SUBSCRIBE_CLEAR_EN_Enabled (1UL)
- #define RTC_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL)
- #define RTC_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CLEAR_CHIDX_Pos)
- #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos (31UL)
- #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Msk (0x1UL << RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos)
- #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0UL)
- #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (1UL)
- #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos (0UL)
- #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos)
- #define RTC_SUBSCRIBE_CAPTURE_EN_Pos (31UL)
- #define RTC_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << RTC_SUBSCRIBE_CAPTURE_EN_Pos)
- #define RTC_SUBSCRIBE_CAPTURE_EN_Disabled (0UL)
- #define RTC_SUBSCRIBE_CAPTURE_EN_Enabled (1UL)
- #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL)
- #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CAPTURE_CHIDX_Pos)
- #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL)
- #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos)
- #define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL)
- #define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL)
- #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL)
- #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos)
- #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL)
- #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL)
- #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL)
- #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos)
- #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL)
- #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL)
- #define RTC_PUBLISH_TICK_EN_Pos (31UL)
- #define RTC_PUBLISH_TICK_EN_Msk (0x1UL << RTC_PUBLISH_TICK_EN_Pos)
- #define RTC_PUBLISH_TICK_EN_Disabled (0UL)
- #define RTC_PUBLISH_TICK_EN_Enabled (1UL)
- #define RTC_PUBLISH_TICK_CHIDX_Pos (0UL)
- #define RTC_PUBLISH_TICK_CHIDX_Msk (0xFFUL << RTC_PUBLISH_TICK_CHIDX_Pos)
- #define RTC_PUBLISH_OVRFLW_EN_Pos (31UL)
- #define RTC_PUBLISH_OVRFLW_EN_Msk (0x1UL << RTC_PUBLISH_OVRFLW_EN_Pos)
- #define RTC_PUBLISH_OVRFLW_EN_Disabled (0UL)
- #define RTC_PUBLISH_OVRFLW_EN_Enabled (1UL)
- #define RTC_PUBLISH_OVRFLW_CHIDX_Pos (0UL)
- #define RTC_PUBLISH_OVRFLW_CHIDX_Msk (0xFFUL << RTC_PUBLISH_OVRFLW_CHIDX_Pos)
- #define RTC_PUBLISH_COMPARE_EN_Pos (31UL)
- #define RTC_PUBLISH_COMPARE_EN_Msk (0x1UL << RTC_PUBLISH_COMPARE_EN_Pos)
- #define RTC_PUBLISH_COMPARE_EN_Disabled (0UL)
- #define RTC_PUBLISH_COMPARE_EN_Enabled (1UL)
- #define RTC_PUBLISH_COMPARE_CHIDX_Pos (0UL)
- #define RTC_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << RTC_PUBLISH_COMPARE_CHIDX_Pos)
- #define RTC_SHORTS_COMPARE3_CLEAR_Pos (3UL)
- #define RTC_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE3_CLEAR_Pos)
- #define RTC_SHORTS_COMPARE3_CLEAR_Disabled (0UL)
- #define RTC_SHORTS_COMPARE3_CLEAR_Enabled (1UL)
- #define RTC_SHORTS_COMPARE2_CLEAR_Pos (2UL)
- #define RTC_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE2_CLEAR_Pos)
- #define RTC_SHORTS_COMPARE2_CLEAR_Disabled (0UL)
- #define RTC_SHORTS_COMPARE2_CLEAR_Enabled (1UL)
- #define RTC_SHORTS_COMPARE1_CLEAR_Pos (1UL)
- #define RTC_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE1_CLEAR_Pos)
- #define RTC_SHORTS_COMPARE1_CLEAR_Disabled (0UL)
- #define RTC_SHORTS_COMPARE1_CLEAR_Enabled (1UL)
- #define RTC_SHORTS_COMPARE0_CLEAR_Pos (0UL)
- #define RTC_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE0_CLEAR_Pos)
- #define RTC_SHORTS_COMPARE0_CLEAR_Disabled (0UL)
- #define RTC_SHORTS_COMPARE0_CLEAR_Enabled (1UL)
- #define RTC_INTENSET_COMPARE3_Pos (19UL)
- #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos)
- #define RTC_INTENSET_COMPARE3_Disabled (0UL)
- #define RTC_INTENSET_COMPARE3_Enabled (1UL)
- #define RTC_INTENSET_COMPARE3_Set (1UL)
- #define RTC_INTENSET_COMPARE2_Pos (18UL)
- #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos)
- #define RTC_INTENSET_COMPARE2_Disabled (0UL)
- #define RTC_INTENSET_COMPARE2_Enabled (1UL)
- #define RTC_INTENSET_COMPARE2_Set (1UL)
- #define RTC_INTENSET_COMPARE1_Pos (17UL)
- #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos)
- #define RTC_INTENSET_COMPARE1_Disabled (0UL)
- #define RTC_INTENSET_COMPARE1_Enabled (1UL)
- #define RTC_INTENSET_COMPARE1_Set (1UL)
- #define RTC_INTENSET_COMPARE0_Pos (16UL)
- #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos)
- #define RTC_INTENSET_COMPARE0_Disabled (0UL)
- #define RTC_INTENSET_COMPARE0_Enabled (1UL)
- #define RTC_INTENSET_COMPARE0_Set (1UL)
- #define RTC_INTENSET_OVRFLW_Pos (1UL)
- #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos)
- #define RTC_INTENSET_OVRFLW_Disabled (0UL)
- #define RTC_INTENSET_OVRFLW_Enabled (1UL)
- #define RTC_INTENSET_OVRFLW_Set (1UL)
- #define RTC_INTENSET_TICK_Pos (0UL)
- #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos)
- #define RTC_INTENSET_TICK_Disabled (0UL)
- #define RTC_INTENSET_TICK_Enabled (1UL)
- #define RTC_INTENSET_TICK_Set (1UL)
- #define RTC_INTENCLR_COMPARE3_Pos (19UL)
- #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos)
- #define RTC_INTENCLR_COMPARE3_Disabled (0UL)
- #define RTC_INTENCLR_COMPARE3_Enabled (1UL)
- #define RTC_INTENCLR_COMPARE3_Clear (1UL)
- #define RTC_INTENCLR_COMPARE2_Pos (18UL)
- #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos)
- #define RTC_INTENCLR_COMPARE2_Disabled (0UL)
- #define RTC_INTENCLR_COMPARE2_Enabled (1UL)
- #define RTC_INTENCLR_COMPARE2_Clear (1UL)
- #define RTC_INTENCLR_COMPARE1_Pos (17UL)
- #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos)
- #define RTC_INTENCLR_COMPARE1_Disabled (0UL)
- #define RTC_INTENCLR_COMPARE1_Enabled (1UL)
- #define RTC_INTENCLR_COMPARE1_Clear (1UL)
- #define RTC_INTENCLR_COMPARE0_Pos (16UL)
- #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos)
- #define RTC_INTENCLR_COMPARE0_Disabled (0UL)
- #define RTC_INTENCLR_COMPARE0_Enabled (1UL)
- #define RTC_INTENCLR_COMPARE0_Clear (1UL)
- #define RTC_INTENCLR_OVRFLW_Pos (1UL)
- #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos)
- #define RTC_INTENCLR_OVRFLW_Disabled (0UL)
- #define RTC_INTENCLR_OVRFLW_Enabled (1UL)
- #define RTC_INTENCLR_OVRFLW_Clear (1UL)
- #define RTC_INTENCLR_TICK_Pos (0UL)
- #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos)
- #define RTC_INTENCLR_TICK_Disabled (0UL)
- #define RTC_INTENCLR_TICK_Enabled (1UL)
- #define RTC_INTENCLR_TICK_Clear (1UL)
- #define RTC_EVTEN_COMPARE3_Pos (19UL)
- #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos)
- #define RTC_EVTEN_COMPARE3_Disabled (0UL)
- #define RTC_EVTEN_COMPARE3_Enabled (1UL)
- #define RTC_EVTEN_COMPARE2_Pos (18UL)
- #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos)
- #define RTC_EVTEN_COMPARE2_Disabled (0UL)
- #define RTC_EVTEN_COMPARE2_Enabled (1UL)
- #define RTC_EVTEN_COMPARE1_Pos (17UL)
- #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos)
- #define RTC_EVTEN_COMPARE1_Disabled (0UL)
- #define RTC_EVTEN_COMPARE1_Enabled (1UL)
- #define RTC_EVTEN_COMPARE0_Pos (16UL)
- #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos)
- #define RTC_EVTEN_COMPARE0_Disabled (0UL)
- #define RTC_EVTEN_COMPARE0_Enabled (1UL)
- #define RTC_EVTEN_OVRFLW_Pos (1UL)
- #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos)
- #define RTC_EVTEN_OVRFLW_Disabled (0UL)
- #define RTC_EVTEN_OVRFLW_Enabled (1UL)
- #define RTC_EVTEN_TICK_Pos (0UL)
- #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos)
- #define RTC_EVTEN_TICK_Disabled (0UL)
- #define RTC_EVTEN_TICK_Enabled (1UL)
- #define RTC_EVTENSET_COMPARE3_Pos (19UL)
- #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos)
- #define RTC_EVTENSET_COMPARE3_Disabled (0UL)
- #define RTC_EVTENSET_COMPARE3_Enabled (1UL)
- #define RTC_EVTENSET_COMPARE3_Set (1UL)
- #define RTC_EVTENSET_COMPARE2_Pos (18UL)
- #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos)
- #define RTC_EVTENSET_COMPARE2_Disabled (0UL)
- #define RTC_EVTENSET_COMPARE2_Enabled (1UL)
- #define RTC_EVTENSET_COMPARE2_Set (1UL)
- #define RTC_EVTENSET_COMPARE1_Pos (17UL)
- #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos)
- #define RTC_EVTENSET_COMPARE1_Disabled (0UL)
- #define RTC_EVTENSET_COMPARE1_Enabled (1UL)
- #define RTC_EVTENSET_COMPARE1_Set (1UL)
- #define RTC_EVTENSET_COMPARE0_Pos (16UL)
- #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos)
- #define RTC_EVTENSET_COMPARE0_Disabled (0UL)
- #define RTC_EVTENSET_COMPARE0_Enabled (1UL)
- #define RTC_EVTENSET_COMPARE0_Set (1UL)
- #define RTC_EVTENSET_OVRFLW_Pos (1UL)
- #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos)
- #define RTC_EVTENSET_OVRFLW_Disabled (0UL)
- #define RTC_EVTENSET_OVRFLW_Enabled (1UL)
- #define RTC_EVTENSET_OVRFLW_Set (1UL)
- #define RTC_EVTENSET_TICK_Pos (0UL)
- #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos)
- #define RTC_EVTENSET_TICK_Disabled (0UL)
- #define RTC_EVTENSET_TICK_Enabled (1UL)
- #define RTC_EVTENSET_TICK_Set (1UL)
- #define RTC_EVTENCLR_COMPARE3_Pos (19UL)
- #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos)
- #define RTC_EVTENCLR_COMPARE3_Disabled (0UL)
- #define RTC_EVTENCLR_COMPARE3_Enabled (1UL)
- #define RTC_EVTENCLR_COMPARE3_Clear (1UL)
- #define RTC_EVTENCLR_COMPARE2_Pos (18UL)
- #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos)
- #define RTC_EVTENCLR_COMPARE2_Disabled (0UL)
- #define RTC_EVTENCLR_COMPARE2_Enabled (1UL)
- #define RTC_EVTENCLR_COMPARE2_Clear (1UL)
- #define RTC_EVTENCLR_COMPARE1_Pos (17UL)
- #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos)
- #define RTC_EVTENCLR_COMPARE1_Disabled (0UL)
- #define RTC_EVTENCLR_COMPARE1_Enabled (1UL)
- #define RTC_EVTENCLR_COMPARE1_Clear (1UL)
- #define RTC_EVTENCLR_COMPARE0_Pos (16UL)
- #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos)
- #define RTC_EVTENCLR_COMPARE0_Disabled (0UL)
- #define RTC_EVTENCLR_COMPARE0_Enabled (1UL)
- #define RTC_EVTENCLR_COMPARE0_Clear (1UL)
- #define RTC_EVTENCLR_OVRFLW_Pos (1UL)
- #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos)
- #define RTC_EVTENCLR_OVRFLW_Disabled (0UL)
- #define RTC_EVTENCLR_OVRFLW_Enabled (1UL)
- #define RTC_EVTENCLR_OVRFLW_Clear (1UL)
- #define RTC_EVTENCLR_TICK_Pos (0UL)
- #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos)
- #define RTC_EVTENCLR_TICK_Disabled (0UL)
- #define RTC_EVTENCLR_TICK_Enabled (1UL)
- #define RTC_EVTENCLR_TICK_Clear (1UL)
- #define RTC_COUNTER_COUNTER_Pos (0UL)
- #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos)
- #define RTC_PRESCALER_PRESCALER_Pos (0UL)
- #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos)
- #define RTC_CC_COMPARE_Pos (0UL)
- #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos)
- #define SAADC_TASKS_START_TASKS_START_Pos (0UL)
- #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos)
- #define SAADC_TASKS_START_TASKS_START_Trigger (1UL)
- #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL)
- #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos)
- #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL)
- #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos)
- #define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL)
- #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos)
- #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL)
- #define SAADC_SUBSCRIBE_START_EN_Pos (31UL)
- #define SAADC_SUBSCRIBE_START_EN_Msk (0x1UL << SAADC_SUBSCRIBE_START_EN_Pos)
- #define SAADC_SUBSCRIBE_START_EN_Disabled (0UL)
- #define SAADC_SUBSCRIBE_START_EN_Enabled (1UL)
- #define SAADC_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define SAADC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_START_CHIDX_Pos)
- #define SAADC_SUBSCRIBE_SAMPLE_EN_Pos (31UL)
- #define SAADC_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << SAADC_SUBSCRIBE_SAMPLE_EN_Pos)
- #define SAADC_SUBSCRIBE_SAMPLE_EN_Disabled (0UL)
- #define SAADC_SUBSCRIBE_SAMPLE_EN_Enabled (1UL)
- #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL)
- #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos)
- #define SAADC_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define SAADC_SUBSCRIBE_STOP_EN_Msk (0x1UL << SAADC_SUBSCRIBE_STOP_EN_Pos)
- #define SAADC_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define SAADC_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define SAADC_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define SAADC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_STOP_CHIDX_Pos)
- #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos (31UL)
- #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Msk (0x1UL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos)
- #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Disabled (0UL)
- #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Enabled (1UL)
- #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos (0UL)
- #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos)
- #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL)
- #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos)
- #define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL)
- #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL)
- #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL)
- #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos)
- #define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL)
- #define SAADC_EVENTS_END_EVENTS_END_Generated (1UL)
- #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL)
- #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos)
- #define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL)
- #define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL)
- #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL)
- #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos)
- #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL)
- #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL)
- #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL)
- #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos)
- #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL)
- #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL)
- #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL)
- #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos)
- #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL)
- #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL)
- #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL)
- #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos)
- #define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL)
- #define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL)
- #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL)
- #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos)
- #define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL)
- #define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL)
- #define SAADC_PUBLISH_STARTED_EN_Pos (31UL)
- #define SAADC_PUBLISH_STARTED_EN_Msk (0x1UL << SAADC_PUBLISH_STARTED_EN_Pos)
- #define SAADC_PUBLISH_STARTED_EN_Disabled (0UL)
- #define SAADC_PUBLISH_STARTED_EN_Enabled (1UL)
- #define SAADC_PUBLISH_STARTED_CHIDX_Pos (0UL)
- #define SAADC_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STARTED_CHIDX_Pos)
- #define SAADC_PUBLISH_END_EN_Pos (31UL)
- #define SAADC_PUBLISH_END_EN_Msk (0x1UL << SAADC_PUBLISH_END_EN_Pos)
- #define SAADC_PUBLISH_END_EN_Disabled (0UL)
- #define SAADC_PUBLISH_END_EN_Enabled (1UL)
- #define SAADC_PUBLISH_END_CHIDX_Pos (0UL)
- #define SAADC_PUBLISH_END_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_END_CHIDX_Pos)
- #define SAADC_PUBLISH_DONE_EN_Pos (31UL)
- #define SAADC_PUBLISH_DONE_EN_Msk (0x1UL << SAADC_PUBLISH_DONE_EN_Pos)
- #define SAADC_PUBLISH_DONE_EN_Disabled (0UL)
- #define SAADC_PUBLISH_DONE_EN_Enabled (1UL)
- #define SAADC_PUBLISH_DONE_CHIDX_Pos (0UL)
- #define SAADC_PUBLISH_DONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_DONE_CHIDX_Pos)
- #define SAADC_PUBLISH_RESULTDONE_EN_Pos (31UL)
- #define SAADC_PUBLISH_RESULTDONE_EN_Msk (0x1UL << SAADC_PUBLISH_RESULTDONE_EN_Pos)
- #define SAADC_PUBLISH_RESULTDONE_EN_Disabled (0UL)
- #define SAADC_PUBLISH_RESULTDONE_EN_Enabled (1UL)
- #define SAADC_PUBLISH_RESULTDONE_CHIDX_Pos (0UL)
- #define SAADC_PUBLISH_RESULTDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_RESULTDONE_CHIDX_Pos)
- #define SAADC_PUBLISH_CALIBRATEDONE_EN_Pos (31UL)
- #define SAADC_PUBLISH_CALIBRATEDONE_EN_Msk (0x1UL << SAADC_PUBLISH_CALIBRATEDONE_EN_Pos)
- #define SAADC_PUBLISH_CALIBRATEDONE_EN_Disabled (0UL)
- #define SAADC_PUBLISH_CALIBRATEDONE_EN_Enabled (1UL)
- #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos (0UL)
- #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos)
- #define SAADC_PUBLISH_STOPPED_EN_Pos (31UL)
- #define SAADC_PUBLISH_STOPPED_EN_Msk (0x1UL << SAADC_PUBLISH_STOPPED_EN_Pos)
- #define SAADC_PUBLISH_STOPPED_EN_Disabled (0UL)
- #define SAADC_PUBLISH_STOPPED_EN_Enabled (1UL)
- #define SAADC_PUBLISH_STOPPED_CHIDX_Pos (0UL)
- #define SAADC_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STOPPED_CHIDX_Pos)
- #define SAADC_PUBLISH_CH_LIMITH_EN_Pos (31UL)
- #define SAADC_PUBLISH_CH_LIMITH_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITH_EN_Pos)
- #define SAADC_PUBLISH_CH_LIMITH_EN_Disabled (0UL)
- #define SAADC_PUBLISH_CH_LIMITH_EN_Enabled (1UL)
- #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos (0UL)
- #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos)
- #define SAADC_PUBLISH_CH_LIMITL_EN_Pos (31UL)
- #define SAADC_PUBLISH_CH_LIMITL_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITL_EN_Pos)
- #define SAADC_PUBLISH_CH_LIMITL_EN_Disabled (0UL)
- #define SAADC_PUBLISH_CH_LIMITL_EN_Enabled (1UL)
- #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos (0UL)
- #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos)
- #define SAADC_INTEN_CH7LIMITL_Pos (21UL)
- #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos)
- #define SAADC_INTEN_CH7LIMITL_Disabled (0UL)
- #define SAADC_INTEN_CH7LIMITL_Enabled (1UL)
- #define SAADC_INTEN_CH7LIMITH_Pos (20UL)
- #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos)
- #define SAADC_INTEN_CH7LIMITH_Disabled (0UL)
- #define SAADC_INTEN_CH7LIMITH_Enabled (1UL)
- #define SAADC_INTEN_CH6LIMITL_Pos (19UL)
- #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos)
- #define SAADC_INTEN_CH6LIMITL_Disabled (0UL)
- #define SAADC_INTEN_CH6LIMITL_Enabled (1UL)
- #define SAADC_INTEN_CH6LIMITH_Pos (18UL)
- #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos)
- #define SAADC_INTEN_CH6LIMITH_Disabled (0UL)
- #define SAADC_INTEN_CH6LIMITH_Enabled (1UL)
- #define SAADC_INTEN_CH5LIMITL_Pos (17UL)
- #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos)
- #define SAADC_INTEN_CH5LIMITL_Disabled (0UL)
- #define SAADC_INTEN_CH5LIMITL_Enabled (1UL)
- #define SAADC_INTEN_CH5LIMITH_Pos (16UL)
- #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos)
- #define SAADC_INTEN_CH5LIMITH_Disabled (0UL)
- #define SAADC_INTEN_CH5LIMITH_Enabled (1UL)
- #define SAADC_INTEN_CH4LIMITL_Pos (15UL)
- #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos)
- #define SAADC_INTEN_CH4LIMITL_Disabled (0UL)
- #define SAADC_INTEN_CH4LIMITL_Enabled (1UL)
- #define SAADC_INTEN_CH4LIMITH_Pos (14UL)
- #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos)
- #define SAADC_INTEN_CH4LIMITH_Disabled (0UL)
- #define SAADC_INTEN_CH4LIMITH_Enabled (1UL)
- #define SAADC_INTEN_CH3LIMITL_Pos (13UL)
- #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos)
- #define SAADC_INTEN_CH3LIMITL_Disabled (0UL)
- #define SAADC_INTEN_CH3LIMITL_Enabled (1UL)
- #define SAADC_INTEN_CH3LIMITH_Pos (12UL)
- #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos)
- #define SAADC_INTEN_CH3LIMITH_Disabled (0UL)
- #define SAADC_INTEN_CH3LIMITH_Enabled (1UL)
- #define SAADC_INTEN_CH2LIMITL_Pos (11UL)
- #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos)
- #define SAADC_INTEN_CH2LIMITL_Disabled (0UL)
- #define SAADC_INTEN_CH2LIMITL_Enabled (1UL)
- #define SAADC_INTEN_CH2LIMITH_Pos (10UL)
- #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos)
- #define SAADC_INTEN_CH2LIMITH_Disabled (0UL)
- #define SAADC_INTEN_CH2LIMITH_Enabled (1UL)
- #define SAADC_INTEN_CH1LIMITL_Pos (9UL)
- #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos)
- #define SAADC_INTEN_CH1LIMITL_Disabled (0UL)
- #define SAADC_INTEN_CH1LIMITL_Enabled (1UL)
- #define SAADC_INTEN_CH1LIMITH_Pos (8UL)
- #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos)
- #define SAADC_INTEN_CH1LIMITH_Disabled (0UL)
- #define SAADC_INTEN_CH1LIMITH_Enabled (1UL)
- #define SAADC_INTEN_CH0LIMITL_Pos (7UL)
- #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos)
- #define SAADC_INTEN_CH0LIMITL_Disabled (0UL)
- #define SAADC_INTEN_CH0LIMITL_Enabled (1UL)
- #define SAADC_INTEN_CH0LIMITH_Pos (6UL)
- #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos)
- #define SAADC_INTEN_CH0LIMITH_Disabled (0UL)
- #define SAADC_INTEN_CH0LIMITH_Enabled (1UL)
- #define SAADC_INTEN_STOPPED_Pos (5UL)
- #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos)
- #define SAADC_INTEN_STOPPED_Disabled (0UL)
- #define SAADC_INTEN_STOPPED_Enabled (1UL)
- #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL)
- #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos)
- #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL)
- #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL)
- #define SAADC_INTEN_RESULTDONE_Pos (3UL)
- #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos)
- #define SAADC_INTEN_RESULTDONE_Disabled (0UL)
- #define SAADC_INTEN_RESULTDONE_Enabled (1UL)
- #define SAADC_INTEN_DONE_Pos (2UL)
- #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos)
- #define SAADC_INTEN_DONE_Disabled (0UL)
- #define SAADC_INTEN_DONE_Enabled (1UL)
- #define SAADC_INTEN_END_Pos (1UL)
- #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos)
- #define SAADC_INTEN_END_Disabled (0UL)
- #define SAADC_INTEN_END_Enabled (1UL)
- #define SAADC_INTEN_STARTED_Pos (0UL)
- #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos)
- #define SAADC_INTEN_STARTED_Disabled (0UL)
- #define SAADC_INTEN_STARTED_Enabled (1UL)
- #define SAADC_INTENSET_CH7LIMITL_Pos (21UL)
- #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos)
- #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL)
- #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL)
- #define SAADC_INTENSET_CH7LIMITL_Set (1UL)
- #define SAADC_INTENSET_CH7LIMITH_Pos (20UL)
- #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos)
- #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL)
- #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL)
- #define SAADC_INTENSET_CH7LIMITH_Set (1UL)
- #define SAADC_INTENSET_CH6LIMITL_Pos (19UL)
- #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos)
- #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL)
- #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL)
- #define SAADC_INTENSET_CH6LIMITL_Set (1UL)
- #define SAADC_INTENSET_CH6LIMITH_Pos (18UL)
- #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos)
- #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL)
- #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL)
- #define SAADC_INTENSET_CH6LIMITH_Set (1UL)
- #define SAADC_INTENSET_CH5LIMITL_Pos (17UL)
- #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos)
- #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL)
- #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL)
- #define SAADC_INTENSET_CH5LIMITL_Set (1UL)
- #define SAADC_INTENSET_CH5LIMITH_Pos (16UL)
- #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos)
- #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL)
- #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL)
- #define SAADC_INTENSET_CH5LIMITH_Set (1UL)
- #define SAADC_INTENSET_CH4LIMITL_Pos (15UL)
- #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos)
- #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL)
- #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL)
- #define SAADC_INTENSET_CH4LIMITL_Set (1UL)
- #define SAADC_INTENSET_CH4LIMITH_Pos (14UL)
- #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos)
- #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL)
- #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL)
- #define SAADC_INTENSET_CH4LIMITH_Set (1UL)
- #define SAADC_INTENSET_CH3LIMITL_Pos (13UL)
- #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos)
- #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL)
- #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL)
- #define SAADC_INTENSET_CH3LIMITL_Set (1UL)
- #define SAADC_INTENSET_CH3LIMITH_Pos (12UL)
- #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos)
- #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL)
- #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL)
- #define SAADC_INTENSET_CH3LIMITH_Set (1UL)
- #define SAADC_INTENSET_CH2LIMITL_Pos (11UL)
- #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos)
- #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL)
- #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL)
- #define SAADC_INTENSET_CH2LIMITL_Set (1UL)
- #define SAADC_INTENSET_CH2LIMITH_Pos (10UL)
- #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos)
- #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL)
- #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL)
- #define SAADC_INTENSET_CH2LIMITH_Set (1UL)
- #define SAADC_INTENSET_CH1LIMITL_Pos (9UL)
- #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos)
- #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL)
- #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL)
- #define SAADC_INTENSET_CH1LIMITL_Set (1UL)
- #define SAADC_INTENSET_CH1LIMITH_Pos (8UL)
- #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos)
- #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL)
- #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL)
- #define SAADC_INTENSET_CH1LIMITH_Set (1UL)
- #define SAADC_INTENSET_CH0LIMITL_Pos (7UL)
- #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos)
- #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL)
- #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL)
- #define SAADC_INTENSET_CH0LIMITL_Set (1UL)
- #define SAADC_INTENSET_CH0LIMITH_Pos (6UL)
- #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos)
- #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL)
- #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL)
- #define SAADC_INTENSET_CH0LIMITH_Set (1UL)
- #define SAADC_INTENSET_STOPPED_Pos (5UL)
- #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos)
- #define SAADC_INTENSET_STOPPED_Disabled (0UL)
- #define SAADC_INTENSET_STOPPED_Enabled (1UL)
- #define SAADC_INTENSET_STOPPED_Set (1UL)
- #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL)
- #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos)
- #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL)
- #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL)
- #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL)
- #define SAADC_INTENSET_RESULTDONE_Pos (3UL)
- #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos)
- #define SAADC_INTENSET_RESULTDONE_Disabled (0UL)
- #define SAADC_INTENSET_RESULTDONE_Enabled (1UL)
- #define SAADC_INTENSET_RESULTDONE_Set (1UL)
- #define SAADC_INTENSET_DONE_Pos (2UL)
- #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos)
- #define SAADC_INTENSET_DONE_Disabled (0UL)
- #define SAADC_INTENSET_DONE_Enabled (1UL)
- #define SAADC_INTENSET_DONE_Set (1UL)
- #define SAADC_INTENSET_END_Pos (1UL)
- #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos)
- #define SAADC_INTENSET_END_Disabled (0UL)
- #define SAADC_INTENSET_END_Enabled (1UL)
- #define SAADC_INTENSET_END_Set (1UL)
- #define SAADC_INTENSET_STARTED_Pos (0UL)
- #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos)
- #define SAADC_INTENSET_STARTED_Disabled (0UL)
- #define SAADC_INTENSET_STARTED_Enabled (1UL)
- #define SAADC_INTENSET_STARTED_Set (1UL)
- #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL)
- #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos)
- #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL)
- #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL)
- #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL)
- #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL)
- #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos)
- #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL)
- #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL)
- #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL)
- #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL)
- #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos)
- #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL)
- #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL)
- #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL)
- #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL)
- #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos)
- #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL)
- #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL)
- #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL)
- #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL)
- #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos)
- #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL)
- #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL)
- #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL)
- #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL)
- #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos)
- #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL)
- #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL)
- #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL)
- #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL)
- #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos)
- #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL)
- #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL)
- #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL)
- #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL)
- #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos)
- #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL)
- #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL)
- #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL)
- #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL)
- #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos)
- #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL)
- #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL)
- #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL)
- #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL)
- #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos)
- #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL)
- #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL)
- #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL)
- #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL)
- #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos)
- #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL)
- #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL)
- #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL)
- #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL)
- #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos)
- #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL)
- #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL)
- #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL)
- #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL)
- #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos)
- #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL)
- #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL)
- #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL)
- #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL)
- #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos)
- #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL)
- #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL)
- #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL)
- #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL)
- #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos)
- #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL)
- #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL)
- #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL)
- #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL)
- #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos)
- #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL)
- #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL)
- #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL)
- #define SAADC_INTENCLR_STOPPED_Pos (5UL)
- #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos)
- #define SAADC_INTENCLR_STOPPED_Disabled (0UL)
- #define SAADC_INTENCLR_STOPPED_Enabled (1UL)
- #define SAADC_INTENCLR_STOPPED_Clear (1UL)
- #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL)
- #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos)
- #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL)
- #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL)
- #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL)
- #define SAADC_INTENCLR_RESULTDONE_Pos (3UL)
- #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos)
- #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL)
- #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL)
- #define SAADC_INTENCLR_RESULTDONE_Clear (1UL)
- #define SAADC_INTENCLR_DONE_Pos (2UL)
- #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos)
- #define SAADC_INTENCLR_DONE_Disabled (0UL)
- #define SAADC_INTENCLR_DONE_Enabled (1UL)
- #define SAADC_INTENCLR_DONE_Clear (1UL)
- #define SAADC_INTENCLR_END_Pos (1UL)
- #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos)
- #define SAADC_INTENCLR_END_Disabled (0UL)
- #define SAADC_INTENCLR_END_Enabled (1UL)
- #define SAADC_INTENCLR_END_Clear (1UL)
- #define SAADC_INTENCLR_STARTED_Pos (0UL)
- #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos)
- #define SAADC_INTENCLR_STARTED_Disabled (0UL)
- #define SAADC_INTENCLR_STARTED_Enabled (1UL)
- #define SAADC_INTENCLR_STARTED_Clear (1UL)
- #define SAADC_STATUS_STATUS_Pos (0UL)
- #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos)
- #define SAADC_STATUS_STATUS_Ready (0UL)
- #define SAADC_STATUS_STATUS_Busy (1UL)
- #define SAADC_ENABLE_ENABLE_Pos (0UL)
- #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos)
- #define SAADC_ENABLE_ENABLE_Disabled (0UL)
- #define SAADC_ENABLE_ENABLE_Enabled (1UL)
- #define SAADC_CH_PSELP_PSELP_Pos (0UL)
- #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos)
- #define SAADC_CH_PSELP_PSELP_NC (0UL)
- #define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL)
- #define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL)
- #define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL)
- #define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL)
- #define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL)
- #define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL)
- #define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL)
- #define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL)
- #define SAADC_CH_PSELP_PSELP_VDD (9UL)
- #define SAADC_CH_PSELP_PSELP_VDDHDIV5 (0xDUL)
- #define SAADC_CH_PSELN_PSELN_Pos (0UL)
- #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos)
- #define SAADC_CH_PSELN_PSELN_NC (0UL)
- #define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL)
- #define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL)
- #define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL)
- #define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL)
- #define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL)
- #define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL)
- #define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL)
- #define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL)
- #define SAADC_CH_PSELN_PSELN_VDD (9UL)
- #define SAADC_CH_PSELN_PSELN_VDDHDIV5 (0xDUL)
- #define SAADC_CH_CONFIG_BURST_Pos (24UL)
- #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos)
- #define SAADC_CH_CONFIG_BURST_Disabled (0UL)
- #define SAADC_CH_CONFIG_BURST_Enabled (1UL)
- #define SAADC_CH_CONFIG_MODE_Pos (20UL)
- #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos)
- #define SAADC_CH_CONFIG_MODE_SE (0UL)
- #define SAADC_CH_CONFIG_MODE_Diff (1UL)
- #define SAADC_CH_CONFIG_TACQ_Pos (16UL)
- #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos)
- #define SAADC_CH_CONFIG_TACQ_3us (0UL)
- #define SAADC_CH_CONFIG_TACQ_5us (1UL)
- #define SAADC_CH_CONFIG_TACQ_10us (2UL)
- #define SAADC_CH_CONFIG_TACQ_15us (3UL)
- #define SAADC_CH_CONFIG_TACQ_20us (4UL)
- #define SAADC_CH_CONFIG_TACQ_40us (5UL)
- #define SAADC_CH_CONFIG_REFSEL_Pos (12UL)
- #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos)
- #define SAADC_CH_CONFIG_REFSEL_Internal (0UL)
- #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL)
- #define SAADC_CH_CONFIG_GAIN_Pos (8UL)
- #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos)
- #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL)
- #define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL)
- #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL)
- #define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL)
- #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL)
- #define SAADC_CH_CONFIG_GAIN_Gain1 (5UL)
- #define SAADC_CH_CONFIG_GAIN_Gain2 (6UL)
- #define SAADC_CH_CONFIG_GAIN_Gain4 (7UL)
- #define SAADC_CH_CONFIG_RESN_Pos (4UL)
- #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos)
- #define SAADC_CH_CONFIG_RESN_Bypass (0UL)
- #define SAADC_CH_CONFIG_RESN_Pulldown (1UL)
- #define SAADC_CH_CONFIG_RESN_Pullup (2UL)
- #define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL)
- #define SAADC_CH_CONFIG_RESP_Pos (0UL)
- #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos)
- #define SAADC_CH_CONFIG_RESP_Bypass (0UL)
- #define SAADC_CH_CONFIG_RESP_Pulldown (1UL)
- #define SAADC_CH_CONFIG_RESP_Pullup (2UL)
- #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL)
- #define SAADC_CH_LIMIT_HIGH_Pos (16UL)
- #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos)
- #define SAADC_CH_LIMIT_LOW_Pos (0UL)
- #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos)
- #define SAADC_RESOLUTION_VAL_Pos (0UL)
- #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos)
- #define SAADC_RESOLUTION_VAL_8bit (0UL)
- #define SAADC_RESOLUTION_VAL_10bit (1UL)
- #define SAADC_RESOLUTION_VAL_12bit (2UL)
- #define SAADC_RESOLUTION_VAL_14bit (3UL)
- #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL)
- #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos)
- #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL)
- #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL)
- #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL)
- #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL)
- #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL)
- #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL)
- #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL)
- #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL)
- #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL)
- #define SAADC_SAMPLERATE_MODE_Pos (12UL)
- #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos)
- #define SAADC_SAMPLERATE_MODE_Task (0UL)
- #define SAADC_SAMPLERATE_MODE_Timers (1UL)
- #define SAADC_SAMPLERATE_CC_Pos (0UL)
- #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos)
- #define SAADC_RESULT_PTR_PTR_Pos (0UL)
- #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos)
- #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL)
- #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos)
- #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL)
- #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos)
- #define SPIM_TASKS_START_TASKS_START_Pos (0UL)
- #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos)
- #define SPIM_TASKS_START_TASKS_START_Trigger (1UL)
- #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos)
- #define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL)
- #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos)
- #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL)
- #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL)
- #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos)
- #define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL)
- #define SPIM_SUBSCRIBE_START_EN_Pos (31UL)
- #define SPIM_SUBSCRIBE_START_EN_Msk (0x1UL << SPIM_SUBSCRIBE_START_EN_Pos)
- #define SPIM_SUBSCRIBE_START_EN_Disabled (0UL)
- #define SPIM_SUBSCRIBE_START_EN_Enabled (1UL)
- #define SPIM_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define SPIM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_START_CHIDX_Pos)
- #define SPIM_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define SPIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << SPIM_SUBSCRIBE_STOP_EN_Pos)
- #define SPIM_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define SPIM_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define SPIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define SPIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_STOP_CHIDX_Pos)
- #define SPIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL)
- #define SPIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << SPIM_SUBSCRIBE_SUSPEND_EN_Pos)
- #define SPIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL)
- #define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL)
- #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL)
- #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos)
- #define SPIM_SUBSCRIBE_RESUME_EN_Pos (31UL)
- #define SPIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << SPIM_SUBSCRIBE_RESUME_EN_Pos)
- #define SPIM_SUBSCRIBE_RESUME_EN_Disabled (0UL)
- #define SPIM_SUBSCRIBE_RESUME_EN_Enabled (1UL)
- #define SPIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL)
- #define SPIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_RESUME_CHIDX_Pos)
- #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL)
- #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos)
- #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL)
- #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL)
- #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL)
- #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos)
- #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL)
- #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL)
- #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL)
- #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos)
- #define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL)
- #define SPIM_EVENTS_END_EVENTS_END_Generated (1UL)
- #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL)
- #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos)
- #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL)
- #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL)
- #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL)
- #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos)
- #define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL)
- #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL)
- #define SPIM_PUBLISH_STOPPED_EN_Pos (31UL)
- #define SPIM_PUBLISH_STOPPED_EN_Msk (0x1UL << SPIM_PUBLISH_STOPPED_EN_Pos)
- #define SPIM_PUBLISH_STOPPED_EN_Disabled (0UL)
- #define SPIM_PUBLISH_STOPPED_EN_Enabled (1UL)
- #define SPIM_PUBLISH_STOPPED_CHIDX_Pos (0UL)
- #define SPIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STOPPED_CHIDX_Pos)
- #define SPIM_PUBLISH_ENDRX_EN_Pos (31UL)
- #define SPIM_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDRX_EN_Pos)
- #define SPIM_PUBLISH_ENDRX_EN_Disabled (0UL)
- #define SPIM_PUBLISH_ENDRX_EN_Enabled (1UL)
- #define SPIM_PUBLISH_ENDRX_CHIDX_Pos (0UL)
- #define SPIM_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDRX_CHIDX_Pos)
- #define SPIM_PUBLISH_END_EN_Pos (31UL)
- #define SPIM_PUBLISH_END_EN_Msk (0x1UL << SPIM_PUBLISH_END_EN_Pos)
- #define SPIM_PUBLISH_END_EN_Disabled (0UL)
- #define SPIM_PUBLISH_END_EN_Enabled (1UL)
- #define SPIM_PUBLISH_END_CHIDX_Pos (0UL)
- #define SPIM_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_END_CHIDX_Pos)
- #define SPIM_PUBLISH_ENDTX_EN_Pos (31UL)
- #define SPIM_PUBLISH_ENDTX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDTX_EN_Pos)
- #define SPIM_PUBLISH_ENDTX_EN_Disabled (0UL)
- #define SPIM_PUBLISH_ENDTX_EN_Enabled (1UL)
- #define SPIM_PUBLISH_ENDTX_CHIDX_Pos (0UL)
- #define SPIM_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDTX_CHIDX_Pos)
- #define SPIM_PUBLISH_STARTED_EN_Pos (31UL)
- #define SPIM_PUBLISH_STARTED_EN_Msk (0x1UL << SPIM_PUBLISH_STARTED_EN_Pos)
- #define SPIM_PUBLISH_STARTED_EN_Disabled (0UL)
- #define SPIM_PUBLISH_STARTED_EN_Enabled (1UL)
- #define SPIM_PUBLISH_STARTED_CHIDX_Pos (0UL)
- #define SPIM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STARTED_CHIDX_Pos)
- #define SPIM_SHORTS_END_START_Pos (17UL)
- #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos)
- #define SPIM_SHORTS_END_START_Disabled (0UL)
- #define SPIM_SHORTS_END_START_Enabled (1UL)
- #define SPIM_INTENSET_STARTED_Pos (19UL)
- #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos)
- #define SPIM_INTENSET_STARTED_Disabled (0UL)
- #define SPIM_INTENSET_STARTED_Enabled (1UL)
- #define SPIM_INTENSET_STARTED_Set (1UL)
- #define SPIM_INTENSET_ENDTX_Pos (8UL)
- #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos)
- #define SPIM_INTENSET_ENDTX_Disabled (0UL)
- #define SPIM_INTENSET_ENDTX_Enabled (1UL)
- #define SPIM_INTENSET_ENDTX_Set (1UL)
- #define SPIM_INTENSET_END_Pos (6UL)
- #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos)
- #define SPIM_INTENSET_END_Disabled (0UL)
- #define SPIM_INTENSET_END_Enabled (1UL)
- #define SPIM_INTENSET_END_Set (1UL)
- #define SPIM_INTENSET_ENDRX_Pos (4UL)
- #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos)
- #define SPIM_INTENSET_ENDRX_Disabled (0UL)
- #define SPIM_INTENSET_ENDRX_Enabled (1UL)
- #define SPIM_INTENSET_ENDRX_Set (1UL)
- #define SPIM_INTENSET_STOPPED_Pos (1UL)
- #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos)
- #define SPIM_INTENSET_STOPPED_Disabled (0UL)
- #define SPIM_INTENSET_STOPPED_Enabled (1UL)
- #define SPIM_INTENSET_STOPPED_Set (1UL)
- #define SPIM_INTENCLR_STARTED_Pos (19UL)
- #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos)
- #define SPIM_INTENCLR_STARTED_Disabled (0UL)
- #define SPIM_INTENCLR_STARTED_Enabled (1UL)
- #define SPIM_INTENCLR_STARTED_Clear (1UL)
- #define SPIM_INTENCLR_ENDTX_Pos (8UL)
- #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos)
- #define SPIM_INTENCLR_ENDTX_Disabled (0UL)
- #define SPIM_INTENCLR_ENDTX_Enabled (1UL)
- #define SPIM_INTENCLR_ENDTX_Clear (1UL)
- #define SPIM_INTENCLR_END_Pos (6UL)
- #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos)
- #define SPIM_INTENCLR_END_Disabled (0UL)
- #define SPIM_INTENCLR_END_Enabled (1UL)
- #define SPIM_INTENCLR_END_Clear (1UL)
- #define SPIM_INTENCLR_ENDRX_Pos (4UL)
- #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos)
- #define SPIM_INTENCLR_ENDRX_Disabled (0UL)
- #define SPIM_INTENCLR_ENDRX_Enabled (1UL)
- #define SPIM_INTENCLR_ENDRX_Clear (1UL)
- #define SPIM_INTENCLR_STOPPED_Pos (1UL)
- #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos)
- #define SPIM_INTENCLR_STOPPED_Disabled (0UL)
- #define SPIM_INTENCLR_STOPPED_Enabled (1UL)
- #define SPIM_INTENCLR_STOPPED_Clear (1UL)
- #define SPIM_STALLSTAT_RX_Pos (1UL)
- #define SPIM_STALLSTAT_RX_Msk (0x1UL << SPIM_STALLSTAT_RX_Pos)
- #define SPIM_STALLSTAT_RX_NOSTALL (0UL)
- #define SPIM_STALLSTAT_RX_STALL (1UL)
- #define SPIM_STALLSTAT_TX_Pos (0UL)
- #define SPIM_STALLSTAT_TX_Msk (0x1UL << SPIM_STALLSTAT_TX_Pos)
- #define SPIM_STALLSTAT_TX_NOSTALL (0UL)
- #define SPIM_STALLSTAT_TX_STALL (1UL)
- #define SPIM_ENABLE_ENABLE_Pos (0UL)
- #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos)
- #define SPIM_ENABLE_ENABLE_Disabled (0UL)
- #define SPIM_ENABLE_ENABLE_Enabled (7UL)
- #define SPIM_PSEL_SCK_CONNECT_Pos (31UL)
- #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos)
- #define SPIM_PSEL_SCK_CONNECT_Connected (0UL)
- #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL)
- #define SPIM_PSEL_SCK_PORT_Pos (5UL)
- #define SPIM_PSEL_SCK_PORT_Msk (0x1UL << SPIM_PSEL_SCK_PORT_Pos)
- #define SPIM_PSEL_SCK_PIN_Pos (0UL)
- #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos)
- #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL)
- #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos)
- #define SPIM_PSEL_MOSI_CONNECT_Connected (0UL)
- #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL)
- #define SPIM_PSEL_MOSI_PORT_Pos (5UL)
- #define SPIM_PSEL_MOSI_PORT_Msk (0x1UL << SPIM_PSEL_MOSI_PORT_Pos)
- #define SPIM_PSEL_MOSI_PIN_Pos (0UL)
- #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos)
- #define SPIM_PSEL_MISO_CONNECT_Pos (31UL)
- #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos)
- #define SPIM_PSEL_MISO_CONNECT_Connected (0UL)
- #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL)
- #define SPIM_PSEL_MISO_PORT_Pos (5UL)
- #define SPIM_PSEL_MISO_PORT_Msk (0x1UL << SPIM_PSEL_MISO_PORT_Pos)
- #define SPIM_PSEL_MISO_PIN_Pos (0UL)
- #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos)
- #define SPIM_PSEL_CSN_CONNECT_Pos (31UL)
- #define SPIM_PSEL_CSN_CONNECT_Msk (0x1UL << SPIM_PSEL_CSN_CONNECT_Pos)
- #define SPIM_PSEL_CSN_CONNECT_Connected (0UL)
- #define SPIM_PSEL_CSN_CONNECT_Disconnected (1UL)
- #define SPIM_PSEL_CSN_PORT_Pos (5UL)
- #define SPIM_PSEL_CSN_PORT_Msk (0x1UL << SPIM_PSEL_CSN_PORT_Pos)
- #define SPIM_PSEL_CSN_PIN_Pos (0UL)
- #define SPIM_PSEL_CSN_PIN_Msk (0x1FUL << SPIM_PSEL_CSN_PIN_Pos)
- #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL)
- #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos)
- #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL)
- #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL)
- #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL)
- #define SPIM_FREQUENCY_FREQUENCY_M16 (0x0A000000UL)
- #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL)
- #define SPIM_FREQUENCY_FREQUENCY_M32 (0x14000000UL)
- #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL)
- #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL)
- #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL)
- #define SPIM_RXD_PTR_PTR_Pos (0UL)
- #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos)
- #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL)
- #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos)
- #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL)
- #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos)
- #define SPIM_RXD_LIST_LIST_Pos (0UL)
- #define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos)
- #define SPIM_RXD_LIST_LIST_Disabled (0UL)
- #define SPIM_RXD_LIST_LIST_ArrayList (1UL)
- #define SPIM_TXD_PTR_PTR_Pos (0UL)
- #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos)
- #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL)
- #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos)
- #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL)
- #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos)
- #define SPIM_TXD_LIST_LIST_Pos (0UL)
- #define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos)
- #define SPIM_TXD_LIST_LIST_Disabled (0UL)
- #define SPIM_TXD_LIST_LIST_ArrayList (1UL)
- #define SPIM_CONFIG_CPOL_Pos (2UL)
- #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos)
- #define SPIM_CONFIG_CPOL_ActiveHigh (0UL)
- #define SPIM_CONFIG_CPOL_ActiveLow (1UL)
- #define SPIM_CONFIG_CPHA_Pos (1UL)
- #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos)
- #define SPIM_CONFIG_CPHA_Leading (0UL)
- #define SPIM_CONFIG_CPHA_Trailing (1UL)
- #define SPIM_CONFIG_ORDER_Pos (0UL)
- #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos)
- #define SPIM_CONFIG_ORDER_MsbFirst (0UL)
- #define SPIM_CONFIG_ORDER_LsbFirst (1UL)
- #define SPIM_IFTIMING_RXDELAY_RXDELAY_Pos (0UL)
- #define SPIM_IFTIMING_RXDELAY_RXDELAY_Msk (0x7UL << SPIM_IFTIMING_RXDELAY_RXDELAY_Pos)
- #define SPIM_IFTIMING_CSNDUR_CSNDUR_Pos (0UL)
- #define SPIM_IFTIMING_CSNDUR_CSNDUR_Msk (0xFFUL << SPIM_IFTIMING_CSNDUR_CSNDUR_Pos)
- #define SPIM_CSNPOL_CSNPOL_Pos (0UL)
- #define SPIM_CSNPOL_CSNPOL_Msk (0x1UL << SPIM_CSNPOL_CSNPOL_Pos)
- #define SPIM_CSNPOL_CSNPOL_LOW (0UL)
- #define SPIM_CSNPOL_CSNPOL_HIGH (1UL)
- #define SPIM_PSELDCX_CONNECT_Pos (31UL)
- #define SPIM_PSELDCX_CONNECT_Msk (0x1UL << SPIM_PSELDCX_CONNECT_Pos)
- #define SPIM_PSELDCX_CONNECT_Connected (0UL)
- #define SPIM_PSELDCX_CONNECT_Disconnected (1UL)
- #define SPIM_PSELDCX_PORT_Pos (5UL)
- #define SPIM_PSELDCX_PORT_Msk (0x1UL << SPIM_PSELDCX_PORT_Pos)
- #define SPIM_PSELDCX_PIN_Pos (0UL)
- #define SPIM_PSELDCX_PIN_Msk (0x1FUL << SPIM_PSELDCX_PIN_Pos)
- #define SPIM_DCXCNT_DCXCNT_Pos (0UL)
- #define SPIM_DCXCNT_DCXCNT_Msk (0xFUL << SPIM_DCXCNT_DCXCNT_Pos)
- #define SPIM_ORC_ORC_Pos (0UL)
- #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos)
- #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL)
- #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos)
- #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL)
- #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL)
- #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos)
- #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL)
- #define SPIS_SUBSCRIBE_ACQUIRE_EN_Pos (31UL)
- #define SPIS_SUBSCRIBE_ACQUIRE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_ACQUIRE_EN_Pos)
- #define SPIS_SUBSCRIBE_ACQUIRE_EN_Disabled (0UL)
- #define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (1UL)
- #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos (0UL)
- #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos)
- #define SPIS_SUBSCRIBE_RELEASE_EN_Pos (31UL)
- #define SPIS_SUBSCRIBE_RELEASE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_RELEASE_EN_Pos)
- #define SPIS_SUBSCRIBE_RELEASE_EN_Disabled (0UL)
- #define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (1UL)
- #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos (0UL)
- #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos)
- #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL)
- #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos)
- #define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL)
- #define SPIS_EVENTS_END_EVENTS_END_Generated (1UL)
- #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL)
- #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos)
- #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL)
- #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL)
- #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL)
- #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos)
- #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL)
- #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL)
- #define SPIS_PUBLISH_END_EN_Pos (31UL)
- #define SPIS_PUBLISH_END_EN_Msk (0x1UL << SPIS_PUBLISH_END_EN_Pos)
- #define SPIS_PUBLISH_END_EN_Disabled (0UL)
- #define SPIS_PUBLISH_END_EN_Enabled (1UL)
- #define SPIS_PUBLISH_END_CHIDX_Pos (0UL)
- #define SPIS_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_END_CHIDX_Pos)
- #define SPIS_PUBLISH_ENDRX_EN_Pos (31UL)
- #define SPIS_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIS_PUBLISH_ENDRX_EN_Pos)
- #define SPIS_PUBLISH_ENDRX_EN_Disabled (0UL)
- #define SPIS_PUBLISH_ENDRX_EN_Enabled (1UL)
- #define SPIS_PUBLISH_ENDRX_CHIDX_Pos (0UL)
- #define SPIS_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ENDRX_CHIDX_Pos)
- #define SPIS_PUBLISH_ACQUIRED_EN_Pos (31UL)
- #define SPIS_PUBLISH_ACQUIRED_EN_Msk (0x1UL << SPIS_PUBLISH_ACQUIRED_EN_Pos)
- #define SPIS_PUBLISH_ACQUIRED_EN_Disabled (0UL)
- #define SPIS_PUBLISH_ACQUIRED_EN_Enabled (1UL)
- #define SPIS_PUBLISH_ACQUIRED_CHIDX_Pos (0UL)
- #define SPIS_PUBLISH_ACQUIRED_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ACQUIRED_CHIDX_Pos)
- #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL)
- #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos)
- #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL)
- #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL)
- #define SPIS_INTENSET_ACQUIRED_Pos (10UL)
- #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos)
- #define SPIS_INTENSET_ACQUIRED_Disabled (0UL)
- #define SPIS_INTENSET_ACQUIRED_Enabled (1UL)
- #define SPIS_INTENSET_ACQUIRED_Set (1UL)
- #define SPIS_INTENSET_ENDRX_Pos (4UL)
- #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos)
- #define SPIS_INTENSET_ENDRX_Disabled (0UL)
- #define SPIS_INTENSET_ENDRX_Enabled (1UL)
- #define SPIS_INTENSET_ENDRX_Set (1UL)
- #define SPIS_INTENSET_END_Pos (1UL)
- #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos)
- #define SPIS_INTENSET_END_Disabled (0UL)
- #define SPIS_INTENSET_END_Enabled (1UL)
- #define SPIS_INTENSET_END_Set (1UL)
- #define SPIS_INTENCLR_ACQUIRED_Pos (10UL)
- #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos)
- #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL)
- #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL)
- #define SPIS_INTENCLR_ACQUIRED_Clear (1UL)
- #define SPIS_INTENCLR_ENDRX_Pos (4UL)
- #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos)
- #define SPIS_INTENCLR_ENDRX_Disabled (0UL)
- #define SPIS_INTENCLR_ENDRX_Enabled (1UL)
- #define SPIS_INTENCLR_ENDRX_Clear (1UL)
- #define SPIS_INTENCLR_END_Pos (1UL)
- #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos)
- #define SPIS_INTENCLR_END_Disabled (0UL)
- #define SPIS_INTENCLR_END_Enabled (1UL)
- #define SPIS_INTENCLR_END_Clear (1UL)
- #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL)
- #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos)
- #define SPIS_SEMSTAT_SEMSTAT_Free (0UL)
- #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL)
- #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL)
- #define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL)
- #define SPIS_STATUS_OVERFLOW_Pos (1UL)
- #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos)
- #define SPIS_STATUS_OVERFLOW_NotPresent (0UL)
- #define SPIS_STATUS_OVERFLOW_Present (1UL)
- #define SPIS_STATUS_OVERFLOW_Clear (1UL)
- #define SPIS_STATUS_OVERREAD_Pos (0UL)
- #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos)
- #define SPIS_STATUS_OVERREAD_NotPresent (0UL)
- #define SPIS_STATUS_OVERREAD_Present (1UL)
- #define SPIS_STATUS_OVERREAD_Clear (1UL)
- #define SPIS_ENABLE_ENABLE_Pos (0UL)
- #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos)
- #define SPIS_ENABLE_ENABLE_Disabled (0UL)
- #define SPIS_ENABLE_ENABLE_Enabled (2UL)
- #define SPIS_PSEL_SCK_CONNECT_Pos (31UL)
- #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos)
- #define SPIS_PSEL_SCK_CONNECT_Connected (0UL)
- #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL)
- #define SPIS_PSEL_SCK_PORT_Pos (5UL)
- #define SPIS_PSEL_SCK_PORT_Msk (0x1UL << SPIS_PSEL_SCK_PORT_Pos)
- #define SPIS_PSEL_SCK_PIN_Pos (0UL)
- #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos)
- #define SPIS_PSEL_MISO_CONNECT_Pos (31UL)
- #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos)
- #define SPIS_PSEL_MISO_CONNECT_Connected (0UL)
- #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL)
- #define SPIS_PSEL_MISO_PORT_Pos (5UL)
- #define SPIS_PSEL_MISO_PORT_Msk (0x1UL << SPIS_PSEL_MISO_PORT_Pos)
- #define SPIS_PSEL_MISO_PIN_Pos (0UL)
- #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos)
- #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL)
- #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos)
- #define SPIS_PSEL_MOSI_CONNECT_Connected (0UL)
- #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL)
- #define SPIS_PSEL_MOSI_PORT_Pos (5UL)
- #define SPIS_PSEL_MOSI_PORT_Msk (0x1UL << SPIS_PSEL_MOSI_PORT_Pos)
- #define SPIS_PSEL_MOSI_PIN_Pos (0UL)
- #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos)
- #define SPIS_PSEL_CSN_CONNECT_Pos (31UL)
- #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos)
- #define SPIS_PSEL_CSN_CONNECT_Connected (0UL)
- #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL)
- #define SPIS_PSEL_CSN_PORT_Pos (5UL)
- #define SPIS_PSEL_CSN_PORT_Msk (0x1UL << SPIS_PSEL_CSN_PORT_Pos)
- #define SPIS_PSEL_CSN_PIN_Pos (0UL)
- #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos)
- #define SPIS_RXD_PTR_PTR_Pos (0UL)
- #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos)
- #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL)
- #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos)
- #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL)
- #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos)
- #define SPIS_RXD_LIST_LIST_Pos (0UL)
- #define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos)
- #define SPIS_RXD_LIST_LIST_Disabled (0UL)
- #define SPIS_RXD_LIST_LIST_ArrayList (1UL)
- #define SPIS_TXD_PTR_PTR_Pos (0UL)
- #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos)
- #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL)
- #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos)
- #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL)
- #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos)
- #define SPIS_TXD_LIST_LIST_Pos (0UL)
- #define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos)
- #define SPIS_TXD_LIST_LIST_Disabled (0UL)
- #define SPIS_TXD_LIST_LIST_ArrayList (1UL)
- #define SPIS_CONFIG_CPOL_Pos (2UL)
- #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos)
- #define SPIS_CONFIG_CPOL_ActiveHigh (0UL)
- #define SPIS_CONFIG_CPOL_ActiveLow (1UL)
- #define SPIS_CONFIG_CPHA_Pos (1UL)
- #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos)
- #define SPIS_CONFIG_CPHA_Leading (0UL)
- #define SPIS_CONFIG_CPHA_Trailing (1UL)
- #define SPIS_CONFIG_ORDER_Pos (0UL)
- #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos)
- #define SPIS_CONFIG_ORDER_MsbFirst (0UL)
- #define SPIS_CONFIG_ORDER_LsbFirst (1UL)
- #define SPIS_DEF_DEF_Pos (0UL)
- #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos)
- #define SPIS_ORC_ORC_Pos (0UL)
- #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos)
- #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos (0UL)
- #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Msk (0x1UL << SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos)
- #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_NotGenerated (0UL)
- #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Generated (1UL)
- #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos (0UL)
- #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Msk (0x1UL << SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos)
- #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_NotGenerated (0UL)
- #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Generated (1UL)
- #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos (0UL)
- #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Msk (0x1UL << SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos)
- #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_NotGenerated (0UL)
- #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Generated (1UL)
- #define SPU_PUBLISH_RAMACCERR_EN_Pos (31UL)
- #define SPU_PUBLISH_RAMACCERR_EN_Msk (0x1UL << SPU_PUBLISH_RAMACCERR_EN_Pos)
- #define SPU_PUBLISH_RAMACCERR_EN_Disabled (0UL)
- #define SPU_PUBLISH_RAMACCERR_EN_Enabled (1UL)
- #define SPU_PUBLISH_RAMACCERR_CHIDX_Pos (0UL)
- #define SPU_PUBLISH_RAMACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_RAMACCERR_CHIDX_Pos)
- #define SPU_PUBLISH_FLASHACCERR_EN_Pos (31UL)
- #define SPU_PUBLISH_FLASHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_FLASHACCERR_EN_Pos)
- #define SPU_PUBLISH_FLASHACCERR_EN_Disabled (0UL)
- #define SPU_PUBLISH_FLASHACCERR_EN_Enabled (1UL)
- #define SPU_PUBLISH_FLASHACCERR_CHIDX_Pos (0UL)
- #define SPU_PUBLISH_FLASHACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_FLASHACCERR_CHIDX_Pos)
- #define SPU_PUBLISH_PERIPHACCERR_EN_Pos (31UL)
- #define SPU_PUBLISH_PERIPHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_PERIPHACCERR_EN_Pos)
- #define SPU_PUBLISH_PERIPHACCERR_EN_Disabled (0UL)
- #define SPU_PUBLISH_PERIPHACCERR_EN_Enabled (1UL)
- #define SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos (0UL)
- #define SPU_PUBLISH_PERIPHACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos)
- #define SPU_INTEN_PERIPHACCERR_Pos (2UL)
- #define SPU_INTEN_PERIPHACCERR_Msk (0x1UL << SPU_INTEN_PERIPHACCERR_Pos)
- #define SPU_INTEN_PERIPHACCERR_Disabled (0UL)
- #define SPU_INTEN_PERIPHACCERR_Enabled (1UL)
- #define SPU_INTEN_FLASHACCERR_Pos (1UL)
- #define SPU_INTEN_FLASHACCERR_Msk (0x1UL << SPU_INTEN_FLASHACCERR_Pos)
- #define SPU_INTEN_FLASHACCERR_Disabled (0UL)
- #define SPU_INTEN_FLASHACCERR_Enabled (1UL)
- #define SPU_INTEN_RAMACCERR_Pos (0UL)
- #define SPU_INTEN_RAMACCERR_Msk (0x1UL << SPU_INTEN_RAMACCERR_Pos)
- #define SPU_INTEN_RAMACCERR_Disabled (0UL)
- #define SPU_INTEN_RAMACCERR_Enabled (1UL)
- #define SPU_INTENSET_PERIPHACCERR_Pos (2UL)
- #define SPU_INTENSET_PERIPHACCERR_Msk (0x1UL << SPU_INTENSET_PERIPHACCERR_Pos)
- #define SPU_INTENSET_PERIPHACCERR_Disabled (0UL)
- #define SPU_INTENSET_PERIPHACCERR_Enabled (1UL)
- #define SPU_INTENSET_PERIPHACCERR_Set (1UL)
- #define SPU_INTENSET_FLASHACCERR_Pos (1UL)
- #define SPU_INTENSET_FLASHACCERR_Msk (0x1UL << SPU_INTENSET_FLASHACCERR_Pos)
- #define SPU_INTENSET_FLASHACCERR_Disabled (0UL)
- #define SPU_INTENSET_FLASHACCERR_Enabled (1UL)
- #define SPU_INTENSET_FLASHACCERR_Set (1UL)
- #define SPU_INTENSET_RAMACCERR_Pos (0UL)
- #define SPU_INTENSET_RAMACCERR_Msk (0x1UL << SPU_INTENSET_RAMACCERR_Pos)
- #define SPU_INTENSET_RAMACCERR_Disabled (0UL)
- #define SPU_INTENSET_RAMACCERR_Enabled (1UL)
- #define SPU_INTENSET_RAMACCERR_Set (1UL)
- #define SPU_INTENCLR_PERIPHACCERR_Pos (2UL)
- #define SPU_INTENCLR_PERIPHACCERR_Msk (0x1UL << SPU_INTENCLR_PERIPHACCERR_Pos)
- #define SPU_INTENCLR_PERIPHACCERR_Disabled (0UL)
- #define SPU_INTENCLR_PERIPHACCERR_Enabled (1UL)
- #define SPU_INTENCLR_PERIPHACCERR_Clear (1UL)
- #define SPU_INTENCLR_FLASHACCERR_Pos (1UL)
- #define SPU_INTENCLR_FLASHACCERR_Msk (0x1UL << SPU_INTENCLR_FLASHACCERR_Pos)
- #define SPU_INTENCLR_FLASHACCERR_Disabled (0UL)
- #define SPU_INTENCLR_FLASHACCERR_Enabled (1UL)
- #define SPU_INTENCLR_FLASHACCERR_Clear (1UL)
- #define SPU_INTENCLR_RAMACCERR_Pos (0UL)
- #define SPU_INTENCLR_RAMACCERR_Msk (0x1UL << SPU_INTENCLR_RAMACCERR_Pos)
- #define SPU_INTENCLR_RAMACCERR_Disabled (0UL)
- #define SPU_INTENCLR_RAMACCERR_Enabled (1UL)
- #define SPU_INTENCLR_RAMACCERR_Clear (1UL)
- #define SPU_CAP_TZM_Pos (0UL)
- #define SPU_CAP_TZM_Msk (0x1UL << SPU_CAP_TZM_Pos)
- #define SPU_CAP_TZM_NotAvailable (0UL)
- #define SPU_CAP_TZM_Enabled (1UL)
- #define SPU_CPULOCK_LOCKSAU_Pos (4UL)
- #define SPU_CPULOCK_LOCKSAU_Msk (0x1UL << SPU_CPULOCK_LOCKSAU_Pos)
- #define SPU_CPULOCK_LOCKSAU_Unlocked (0UL)
- #define SPU_CPULOCK_LOCKSAU_Locked (1UL)
- #define SPU_CPULOCK_LOCKNSMPU_Pos (3UL)
- #define SPU_CPULOCK_LOCKNSMPU_Msk (0x1UL << SPU_CPULOCK_LOCKNSMPU_Pos)
- #define SPU_CPULOCK_LOCKNSMPU_Unlocked (0UL)
- #define SPU_CPULOCK_LOCKNSMPU_Locked (1UL)
- #define SPU_CPULOCK_LOCKSMPU_Pos (2UL)
- #define SPU_CPULOCK_LOCKSMPU_Msk (0x1UL << SPU_CPULOCK_LOCKSMPU_Pos)
- #define SPU_CPULOCK_LOCKSMPU_Unlocked (0UL)
- #define SPU_CPULOCK_LOCKSMPU_Locked (1UL)
- #define SPU_CPULOCK_LOCKNSVTOR_Pos (1UL)
- #define SPU_CPULOCK_LOCKNSVTOR_Msk (0x1UL << SPU_CPULOCK_LOCKNSVTOR_Pos)
- #define SPU_CPULOCK_LOCKNSVTOR_Unlocked (0UL)
- #define SPU_CPULOCK_LOCKNSVTOR_Locked (1UL)
- #define SPU_CPULOCK_LOCKSVTAIRCR_Pos (0UL)
- #define SPU_CPULOCK_LOCKSVTAIRCR_Msk (0x1UL << SPU_CPULOCK_LOCKSVTAIRCR_Pos)
- #define SPU_CPULOCK_LOCKSVTAIRCR_Unlocked (0UL)
- #define SPU_CPULOCK_LOCKSVTAIRCR_Locked (1UL)
- #define SPU_EXTDOMAIN_PERM_LOCK_Pos (8UL)
- #define SPU_EXTDOMAIN_PERM_LOCK_Msk (0x1UL << SPU_EXTDOMAIN_PERM_LOCK_Pos)
- #define SPU_EXTDOMAIN_PERM_LOCK_Unlocked (0UL)
- #define SPU_EXTDOMAIN_PERM_LOCK_Locked (1UL)
- #define SPU_EXTDOMAIN_PERM_SECATTR_Pos (4UL)
- #define SPU_EXTDOMAIN_PERM_SECATTR_Msk (0x1UL << SPU_EXTDOMAIN_PERM_SECATTR_Pos)
- #define SPU_EXTDOMAIN_PERM_SECATTR_NonSecure (0UL)
- #define SPU_EXTDOMAIN_PERM_SECATTR_Secure (1UL)
- #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos (0UL)
- #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Msk (0x3UL << SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos)
- #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_NonSecure (0UL)
- #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Secure (1UL)
- #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_UserSelectable (2UL)
- #define SPU_DPPI_PERM_CHANNEL31_Pos (31UL)
- #define SPU_DPPI_PERM_CHANNEL31_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL31_Pos)
- #define SPU_DPPI_PERM_CHANNEL31_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL31_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL30_Pos (30UL)
- #define SPU_DPPI_PERM_CHANNEL30_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL30_Pos)
- #define SPU_DPPI_PERM_CHANNEL30_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL30_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL29_Pos (29UL)
- #define SPU_DPPI_PERM_CHANNEL29_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL29_Pos)
- #define SPU_DPPI_PERM_CHANNEL29_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL29_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL28_Pos (28UL)
- #define SPU_DPPI_PERM_CHANNEL28_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL28_Pos)
- #define SPU_DPPI_PERM_CHANNEL28_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL28_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL27_Pos (27UL)
- #define SPU_DPPI_PERM_CHANNEL27_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL27_Pos)
- #define SPU_DPPI_PERM_CHANNEL27_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL27_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL26_Pos (26UL)
- #define SPU_DPPI_PERM_CHANNEL26_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL26_Pos)
- #define SPU_DPPI_PERM_CHANNEL26_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL26_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL25_Pos (25UL)
- #define SPU_DPPI_PERM_CHANNEL25_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL25_Pos)
- #define SPU_DPPI_PERM_CHANNEL25_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL25_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL24_Pos (24UL)
- #define SPU_DPPI_PERM_CHANNEL24_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL24_Pos)
- #define SPU_DPPI_PERM_CHANNEL24_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL24_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL23_Pos (23UL)
- #define SPU_DPPI_PERM_CHANNEL23_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL23_Pos)
- #define SPU_DPPI_PERM_CHANNEL23_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL23_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL22_Pos (22UL)
- #define SPU_DPPI_PERM_CHANNEL22_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL22_Pos)
- #define SPU_DPPI_PERM_CHANNEL22_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL22_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL21_Pos (21UL)
- #define SPU_DPPI_PERM_CHANNEL21_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL21_Pos)
- #define SPU_DPPI_PERM_CHANNEL21_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL21_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL20_Pos (20UL)
- #define SPU_DPPI_PERM_CHANNEL20_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL20_Pos)
- #define SPU_DPPI_PERM_CHANNEL20_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL20_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL19_Pos (19UL)
- #define SPU_DPPI_PERM_CHANNEL19_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL19_Pos)
- #define SPU_DPPI_PERM_CHANNEL19_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL19_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL18_Pos (18UL)
- #define SPU_DPPI_PERM_CHANNEL18_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL18_Pos)
- #define SPU_DPPI_PERM_CHANNEL18_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL18_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL17_Pos (17UL)
- #define SPU_DPPI_PERM_CHANNEL17_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL17_Pos)
- #define SPU_DPPI_PERM_CHANNEL17_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL17_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL16_Pos (16UL)
- #define SPU_DPPI_PERM_CHANNEL16_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL16_Pos)
- #define SPU_DPPI_PERM_CHANNEL16_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL16_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL15_Pos (15UL)
- #define SPU_DPPI_PERM_CHANNEL15_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL15_Pos)
- #define SPU_DPPI_PERM_CHANNEL15_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL15_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL14_Pos (14UL)
- #define SPU_DPPI_PERM_CHANNEL14_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL14_Pos)
- #define SPU_DPPI_PERM_CHANNEL14_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL14_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL13_Pos (13UL)
- #define SPU_DPPI_PERM_CHANNEL13_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL13_Pos)
- #define SPU_DPPI_PERM_CHANNEL13_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL13_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL12_Pos (12UL)
- #define SPU_DPPI_PERM_CHANNEL12_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL12_Pos)
- #define SPU_DPPI_PERM_CHANNEL12_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL12_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL11_Pos (11UL)
- #define SPU_DPPI_PERM_CHANNEL11_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL11_Pos)
- #define SPU_DPPI_PERM_CHANNEL11_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL11_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL10_Pos (10UL)
- #define SPU_DPPI_PERM_CHANNEL10_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL10_Pos)
- #define SPU_DPPI_PERM_CHANNEL10_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL10_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL9_Pos (9UL)
- #define SPU_DPPI_PERM_CHANNEL9_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL9_Pos)
- #define SPU_DPPI_PERM_CHANNEL9_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL9_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL8_Pos (8UL)
- #define SPU_DPPI_PERM_CHANNEL8_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL8_Pos)
- #define SPU_DPPI_PERM_CHANNEL8_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL8_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL7_Pos (7UL)
- #define SPU_DPPI_PERM_CHANNEL7_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL7_Pos)
- #define SPU_DPPI_PERM_CHANNEL7_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL7_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL6_Pos (6UL)
- #define SPU_DPPI_PERM_CHANNEL6_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL6_Pos)
- #define SPU_DPPI_PERM_CHANNEL6_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL6_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL5_Pos (5UL)
- #define SPU_DPPI_PERM_CHANNEL5_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL5_Pos)
- #define SPU_DPPI_PERM_CHANNEL5_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL5_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL4_Pos (4UL)
- #define SPU_DPPI_PERM_CHANNEL4_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL4_Pos)
- #define SPU_DPPI_PERM_CHANNEL4_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL4_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL3_Pos (3UL)
- #define SPU_DPPI_PERM_CHANNEL3_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL3_Pos)
- #define SPU_DPPI_PERM_CHANNEL3_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL3_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL2_Pos (2UL)
- #define SPU_DPPI_PERM_CHANNEL2_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL2_Pos)
- #define SPU_DPPI_PERM_CHANNEL2_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL2_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL1_Pos (1UL)
- #define SPU_DPPI_PERM_CHANNEL1_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL1_Pos)
- #define SPU_DPPI_PERM_CHANNEL1_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL1_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL0_Pos (0UL)
- #define SPU_DPPI_PERM_CHANNEL0_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL0_Pos)
- #define SPU_DPPI_PERM_CHANNEL0_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL0_Secure (1UL)
- #define SPU_DPPI_LOCK_LOCK_Pos (0UL)
- #define SPU_DPPI_LOCK_LOCK_Msk (0x1UL << SPU_DPPI_LOCK_LOCK_Pos)
- #define SPU_DPPI_LOCK_LOCK_Unlocked (0UL)
- #define SPU_DPPI_LOCK_LOCK_Locked (1UL)
- #define SPU_GPIOPORT_PERM_PIN31_Pos (31UL)
- #define SPU_GPIOPORT_PERM_PIN31_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN31_Pos)
- #define SPU_GPIOPORT_PERM_PIN31_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN31_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN30_Pos (30UL)
- #define SPU_GPIOPORT_PERM_PIN30_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN30_Pos)
- #define SPU_GPIOPORT_PERM_PIN30_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN30_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN29_Pos (29UL)
- #define SPU_GPIOPORT_PERM_PIN29_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN29_Pos)
- #define SPU_GPIOPORT_PERM_PIN29_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN29_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN28_Pos (28UL)
- #define SPU_GPIOPORT_PERM_PIN28_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN28_Pos)
- #define SPU_GPIOPORT_PERM_PIN28_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN28_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN27_Pos (27UL)
- #define SPU_GPIOPORT_PERM_PIN27_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN27_Pos)
- #define SPU_GPIOPORT_PERM_PIN27_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN27_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN26_Pos (26UL)
- #define SPU_GPIOPORT_PERM_PIN26_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN26_Pos)
- #define SPU_GPIOPORT_PERM_PIN26_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN26_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN25_Pos (25UL)
- #define SPU_GPIOPORT_PERM_PIN25_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN25_Pos)
- #define SPU_GPIOPORT_PERM_PIN25_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN25_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN24_Pos (24UL)
- #define SPU_GPIOPORT_PERM_PIN24_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN24_Pos)
- #define SPU_GPIOPORT_PERM_PIN24_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN24_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN23_Pos (23UL)
- #define SPU_GPIOPORT_PERM_PIN23_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN23_Pos)
- #define SPU_GPIOPORT_PERM_PIN23_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN23_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN22_Pos (22UL)
- #define SPU_GPIOPORT_PERM_PIN22_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN22_Pos)
- #define SPU_GPIOPORT_PERM_PIN22_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN22_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN21_Pos (21UL)
- #define SPU_GPIOPORT_PERM_PIN21_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN21_Pos)
- #define SPU_GPIOPORT_PERM_PIN21_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN21_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN20_Pos (20UL)
- #define SPU_GPIOPORT_PERM_PIN20_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN20_Pos)
- #define SPU_GPIOPORT_PERM_PIN20_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN20_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN19_Pos (19UL)
- #define SPU_GPIOPORT_PERM_PIN19_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN19_Pos)
- #define SPU_GPIOPORT_PERM_PIN19_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN19_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN18_Pos (18UL)
- #define SPU_GPIOPORT_PERM_PIN18_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN18_Pos)
- #define SPU_GPIOPORT_PERM_PIN18_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN18_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN17_Pos (17UL)
- #define SPU_GPIOPORT_PERM_PIN17_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN17_Pos)
- #define SPU_GPIOPORT_PERM_PIN17_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN17_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN16_Pos (16UL)
- #define SPU_GPIOPORT_PERM_PIN16_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN16_Pos)
- #define SPU_GPIOPORT_PERM_PIN16_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN16_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN15_Pos (15UL)
- #define SPU_GPIOPORT_PERM_PIN15_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN15_Pos)
- #define SPU_GPIOPORT_PERM_PIN15_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN15_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN14_Pos (14UL)
- #define SPU_GPIOPORT_PERM_PIN14_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN14_Pos)
- #define SPU_GPIOPORT_PERM_PIN14_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN14_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN13_Pos (13UL)
- #define SPU_GPIOPORT_PERM_PIN13_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN13_Pos)
- #define SPU_GPIOPORT_PERM_PIN13_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN13_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN12_Pos (12UL)
- #define SPU_GPIOPORT_PERM_PIN12_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN12_Pos)
- #define SPU_GPIOPORT_PERM_PIN12_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN12_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN11_Pos (11UL)
- #define SPU_GPIOPORT_PERM_PIN11_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN11_Pos)
- #define SPU_GPIOPORT_PERM_PIN11_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN11_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN10_Pos (10UL)
- #define SPU_GPIOPORT_PERM_PIN10_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN10_Pos)
- #define SPU_GPIOPORT_PERM_PIN10_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN10_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN9_Pos (9UL)
- #define SPU_GPIOPORT_PERM_PIN9_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN9_Pos)
- #define SPU_GPIOPORT_PERM_PIN9_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN9_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN8_Pos (8UL)
- #define SPU_GPIOPORT_PERM_PIN8_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN8_Pos)
- #define SPU_GPIOPORT_PERM_PIN8_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN8_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN7_Pos (7UL)
- #define SPU_GPIOPORT_PERM_PIN7_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN7_Pos)
- #define SPU_GPIOPORT_PERM_PIN7_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN7_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN6_Pos (6UL)
- #define SPU_GPIOPORT_PERM_PIN6_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN6_Pos)
- #define SPU_GPIOPORT_PERM_PIN6_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN6_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN5_Pos (5UL)
- #define SPU_GPIOPORT_PERM_PIN5_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN5_Pos)
- #define SPU_GPIOPORT_PERM_PIN5_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN5_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN4_Pos (4UL)
- #define SPU_GPIOPORT_PERM_PIN4_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN4_Pos)
- #define SPU_GPIOPORT_PERM_PIN4_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN4_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN3_Pos (3UL)
- #define SPU_GPIOPORT_PERM_PIN3_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN3_Pos)
- #define SPU_GPIOPORT_PERM_PIN3_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN3_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN2_Pos (2UL)
- #define SPU_GPIOPORT_PERM_PIN2_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN2_Pos)
- #define SPU_GPIOPORT_PERM_PIN2_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN2_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN1_Pos (1UL)
- #define SPU_GPIOPORT_PERM_PIN1_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN1_Pos)
- #define SPU_GPIOPORT_PERM_PIN1_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN1_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN0_Pos (0UL)
- #define SPU_GPIOPORT_PERM_PIN0_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN0_Pos)
- #define SPU_GPIOPORT_PERM_PIN0_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN0_Secure (1UL)
- #define SPU_GPIOPORT_LOCK_LOCK_Pos (0UL)
- #define SPU_GPIOPORT_LOCK_LOCK_Msk (0x1UL << SPU_GPIOPORT_LOCK_LOCK_Pos)
- #define SPU_GPIOPORT_LOCK_LOCK_Unlocked (0UL)
- #define SPU_GPIOPORT_LOCK_LOCK_Locked (1UL)
- #define SPU_FLASHNSC_REGION_LOCK_Pos (8UL)
- #define SPU_FLASHNSC_REGION_LOCK_Msk (0x1UL << SPU_FLASHNSC_REGION_LOCK_Pos)
- #define SPU_FLASHNSC_REGION_LOCK_Unlocked (0UL)
- #define SPU_FLASHNSC_REGION_LOCK_Locked (1UL)
- #define SPU_FLASHNSC_REGION_REGION_Pos (0UL)
- #define SPU_FLASHNSC_REGION_REGION_Msk (0x3FUL << SPU_FLASHNSC_REGION_REGION_Pos)
- #define SPU_FLASHNSC_SIZE_LOCK_Pos (8UL)
- #define SPU_FLASHNSC_SIZE_LOCK_Msk (0x1UL << SPU_FLASHNSC_SIZE_LOCK_Pos)
- #define SPU_FLASHNSC_SIZE_LOCK_Unlocked (0UL)
- #define SPU_FLASHNSC_SIZE_LOCK_Locked (1UL)
- #define SPU_FLASHNSC_SIZE_SIZE_Pos (0UL)
- #define SPU_FLASHNSC_SIZE_SIZE_Msk (0xFUL << SPU_FLASHNSC_SIZE_SIZE_Pos)
- #define SPU_FLASHNSC_SIZE_SIZE_Disabled (0UL)
- #define SPU_FLASHNSC_SIZE_SIZE_32 (1UL)
- #define SPU_FLASHNSC_SIZE_SIZE_64 (2UL)
- #define SPU_FLASHNSC_SIZE_SIZE_128 (3UL)
- #define SPU_FLASHNSC_SIZE_SIZE_256 (4UL)
- #define SPU_FLASHNSC_SIZE_SIZE_512 (5UL)
- #define SPU_FLASHNSC_SIZE_SIZE_1024 (6UL)
- #define SPU_FLASHNSC_SIZE_SIZE_2048 (7UL)
- #define SPU_FLASHNSC_SIZE_SIZE_4096 (8UL)
- #define SPU_RAMNSC_REGION_LOCK_Pos (8UL)
- #define SPU_RAMNSC_REGION_LOCK_Msk (0x1UL << SPU_RAMNSC_REGION_LOCK_Pos)
- #define SPU_RAMNSC_REGION_LOCK_Unlocked (0UL)
- #define SPU_RAMNSC_REGION_LOCK_Locked (1UL)
- #define SPU_RAMNSC_REGION_REGION_Pos (0UL)
- #define SPU_RAMNSC_REGION_REGION_Msk (0x3FUL << SPU_RAMNSC_REGION_REGION_Pos)
- #define SPU_RAMNSC_SIZE_LOCK_Pos (8UL)
- #define SPU_RAMNSC_SIZE_LOCK_Msk (0x1UL << SPU_RAMNSC_SIZE_LOCK_Pos)
- #define SPU_RAMNSC_SIZE_LOCK_Unlocked (0UL)
- #define SPU_RAMNSC_SIZE_LOCK_Locked (1UL)
- #define SPU_RAMNSC_SIZE_SIZE_Pos (0UL)
- #define SPU_RAMNSC_SIZE_SIZE_Msk (0xFUL << SPU_RAMNSC_SIZE_SIZE_Pos)
- #define SPU_RAMNSC_SIZE_SIZE_Disabled (0UL)
- #define SPU_RAMNSC_SIZE_SIZE_32 (1UL)
- #define SPU_RAMNSC_SIZE_SIZE_64 (2UL)
- #define SPU_RAMNSC_SIZE_SIZE_128 (3UL)
- #define SPU_RAMNSC_SIZE_SIZE_256 (4UL)
- #define SPU_RAMNSC_SIZE_SIZE_512 (5UL)
- #define SPU_RAMNSC_SIZE_SIZE_1024 (6UL)
- #define SPU_RAMNSC_SIZE_SIZE_2048 (7UL)
- #define SPU_RAMNSC_SIZE_SIZE_4096 (8UL)
- #define SPU_FLASHREGION_PERM_LOCK_Pos (8UL)
- #define SPU_FLASHREGION_PERM_LOCK_Msk (0x1UL << SPU_FLASHREGION_PERM_LOCK_Pos)
- #define SPU_FLASHREGION_PERM_LOCK_Unlocked (0UL)
- #define SPU_FLASHREGION_PERM_LOCK_Locked (1UL)
- #define SPU_FLASHREGION_PERM_SECATTR_Pos (4UL)
- #define SPU_FLASHREGION_PERM_SECATTR_Msk (0x1UL << SPU_FLASHREGION_PERM_SECATTR_Pos)
- #define SPU_FLASHREGION_PERM_SECATTR_Non_Secure (0UL)
- #define SPU_FLASHREGION_PERM_SECATTR_Secure (1UL)
- #define SPU_FLASHREGION_PERM_READ_Pos (2UL)
- #define SPU_FLASHREGION_PERM_READ_Msk (0x1UL << SPU_FLASHREGION_PERM_READ_Pos)
- #define SPU_FLASHREGION_PERM_READ_Disable (0UL)
- #define SPU_FLASHREGION_PERM_READ_Enable (1UL)
- #define SPU_FLASHREGION_PERM_WRITE_Pos (1UL)
- #define SPU_FLASHREGION_PERM_WRITE_Msk (0x1UL << SPU_FLASHREGION_PERM_WRITE_Pos)
- #define SPU_FLASHREGION_PERM_WRITE_Disable (0UL)
- #define SPU_FLASHREGION_PERM_WRITE_Enable (1UL)
- #define SPU_FLASHREGION_PERM_EXECUTE_Pos (0UL)
- #define SPU_FLASHREGION_PERM_EXECUTE_Msk (0x1UL << SPU_FLASHREGION_PERM_EXECUTE_Pos)
- #define SPU_FLASHREGION_PERM_EXECUTE_Disable (0UL)
- #define SPU_FLASHREGION_PERM_EXECUTE_Enable (1UL)
- #define SPU_RAMREGION_PERM_LOCK_Pos (8UL)
- #define SPU_RAMREGION_PERM_LOCK_Msk (0x1UL << SPU_RAMREGION_PERM_LOCK_Pos)
- #define SPU_RAMREGION_PERM_LOCK_Unlocked (0UL)
- #define SPU_RAMREGION_PERM_LOCK_Locked (1UL)
- #define SPU_RAMREGION_PERM_SECATTR_Pos (4UL)
- #define SPU_RAMREGION_PERM_SECATTR_Msk (0x1UL << SPU_RAMREGION_PERM_SECATTR_Pos)
- #define SPU_RAMREGION_PERM_SECATTR_Non_Secure (0UL)
- #define SPU_RAMREGION_PERM_SECATTR_Secure (1UL)
- #define SPU_RAMREGION_PERM_READ_Pos (2UL)
- #define SPU_RAMREGION_PERM_READ_Msk (0x1UL << SPU_RAMREGION_PERM_READ_Pos)
- #define SPU_RAMREGION_PERM_READ_Disable (0UL)
- #define SPU_RAMREGION_PERM_READ_Enable (1UL)
- #define SPU_RAMREGION_PERM_WRITE_Pos (1UL)
- #define SPU_RAMREGION_PERM_WRITE_Msk (0x1UL << SPU_RAMREGION_PERM_WRITE_Pos)
- #define SPU_RAMREGION_PERM_WRITE_Disable (0UL)
- #define SPU_RAMREGION_PERM_WRITE_Enable (1UL)
- #define SPU_RAMREGION_PERM_EXECUTE_Pos (0UL)
- #define SPU_RAMREGION_PERM_EXECUTE_Msk (0x1UL << SPU_RAMREGION_PERM_EXECUTE_Pos)
- #define SPU_RAMREGION_PERM_EXECUTE_Disable (0UL)
- #define SPU_RAMREGION_PERM_EXECUTE_Enable (1UL)
- #define SPU_PERIPHID_PERM_PRESENT_Pos (31UL)
- #define SPU_PERIPHID_PERM_PRESENT_Msk (0x1UL << SPU_PERIPHID_PERM_PRESENT_Pos)
- #define SPU_PERIPHID_PERM_PRESENT_NotPresent (0UL)
- #define SPU_PERIPHID_PERM_PRESENT_IsPresent (1UL)
- #define SPU_PERIPHID_PERM_LOCK_Pos (8UL)
- #define SPU_PERIPHID_PERM_LOCK_Msk (0x1UL << SPU_PERIPHID_PERM_LOCK_Pos)
- #define SPU_PERIPHID_PERM_LOCK_Unlocked (0UL)
- #define SPU_PERIPHID_PERM_LOCK_Locked (1UL)
- #define SPU_PERIPHID_PERM_DMASEC_Pos (5UL)
- #define SPU_PERIPHID_PERM_DMASEC_Msk (0x1UL << SPU_PERIPHID_PERM_DMASEC_Pos)
- #define SPU_PERIPHID_PERM_DMASEC_NonSecure (0UL)
- #define SPU_PERIPHID_PERM_DMASEC_Secure (1UL)
- #define SPU_PERIPHID_PERM_SECATTR_Pos (4UL)
- #define SPU_PERIPHID_PERM_SECATTR_Msk (0x1UL << SPU_PERIPHID_PERM_SECATTR_Pos)
- #define SPU_PERIPHID_PERM_SECATTR_NonSecure (0UL)
- #define SPU_PERIPHID_PERM_SECATTR_Secure (1UL)
- #define SPU_PERIPHID_PERM_DMA_Pos (2UL)
- #define SPU_PERIPHID_PERM_DMA_Msk (0x3UL << SPU_PERIPHID_PERM_DMA_Pos)
- #define SPU_PERIPHID_PERM_DMA_NoDMA (0UL)
- #define SPU_PERIPHID_PERM_DMA_NoSeparateAttribute (1UL)
- #define SPU_PERIPHID_PERM_DMA_SeparateAttribute (2UL)
- #define SPU_PERIPHID_PERM_SECUREMAPPING_Pos (0UL)
- #define SPU_PERIPHID_PERM_SECUREMAPPING_Msk (0x3UL << SPU_PERIPHID_PERM_SECUREMAPPING_Pos)
- #define SPU_PERIPHID_PERM_SECUREMAPPING_NonSecure (0UL)
- #define SPU_PERIPHID_PERM_SECUREMAPPING_Secure (1UL)
- #define SPU_PERIPHID_PERM_SECUREMAPPING_UserSelectable (2UL)
- #define SPU_PERIPHID_PERM_SECUREMAPPING_Split (3UL)
- #define TAD_CLOCKSTART_START_Pos (0UL)
- #define TAD_CLOCKSTART_START_Msk (0x1UL << TAD_CLOCKSTART_START_Pos)
- #define TAD_CLOCKSTART_START_Start (1UL)
- #define TAD_CLOCKSTOP_STOP_Pos (0UL)
- #define TAD_CLOCKSTOP_STOP_Msk (0x1UL << TAD_CLOCKSTOP_STOP_Pos)
- #define TAD_CLOCKSTOP_STOP_Stop (1UL)
- #define TAD_ENABLE_ENABLE_Pos (0UL)
- #define TAD_ENABLE_ENABLE_Msk (0x1UL << TAD_ENABLE_ENABLE_Pos)
- #define TAD_ENABLE_ENABLE_DISABLED (0UL)
- #define TAD_ENABLE_ENABLE_ENABLED (1UL)
- #define TAD_PSEL_TRACECLK_CONNECT_Pos (31UL)
- #define TAD_PSEL_TRACECLK_CONNECT_Msk (0x1UL << TAD_PSEL_TRACECLK_CONNECT_Pos)
- #define TAD_PSEL_TRACECLK_CONNECT_Connected (0UL)
- #define TAD_PSEL_TRACECLK_CONNECT_Disconnected (1UL)
- #define TAD_PSEL_TRACECLK_PIN_Pos (0UL)
- #define TAD_PSEL_TRACECLK_PIN_Msk (0x1FUL << TAD_PSEL_TRACECLK_PIN_Pos)
- #define TAD_PSEL_TRACECLK_PIN_Traceclk (12UL)
- #define TAD_PSEL_TRACEDATA0_CONNECT_Pos (31UL)
- #define TAD_PSEL_TRACEDATA0_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA0_CONNECT_Pos)
- #define TAD_PSEL_TRACEDATA0_CONNECT_Connected (0UL)
- #define TAD_PSEL_TRACEDATA0_CONNECT_Disconnected (1UL)
- #define TAD_PSEL_TRACEDATA0_PIN_Pos (0UL)
- #define TAD_PSEL_TRACEDATA0_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA0_PIN_Pos)
- #define TAD_PSEL_TRACEDATA0_PIN_Tracedata0 (11UL)
- #define TAD_PSEL_TRACEDATA1_CONNECT_Pos (31UL)
- #define TAD_PSEL_TRACEDATA1_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA1_CONNECT_Pos)
- #define TAD_PSEL_TRACEDATA1_CONNECT_Connected (0UL)
- #define TAD_PSEL_TRACEDATA1_CONNECT_Disconnected (1UL)
- #define TAD_PSEL_TRACEDATA1_PIN_Pos (0UL)
- #define TAD_PSEL_TRACEDATA1_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA1_PIN_Pos)
- #define TAD_PSEL_TRACEDATA1_PIN_Tracedata1 (10UL)
- #define TAD_PSEL_TRACEDATA2_CONNECT_Pos (31UL)
- #define TAD_PSEL_TRACEDATA2_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA2_CONNECT_Pos)
- #define TAD_PSEL_TRACEDATA2_CONNECT_Connected (0UL)
- #define TAD_PSEL_TRACEDATA2_CONNECT_Disconnected (1UL)
- #define TAD_PSEL_TRACEDATA2_PIN_Pos (0UL)
- #define TAD_PSEL_TRACEDATA2_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA2_PIN_Pos)
- #define TAD_PSEL_TRACEDATA2_PIN_Tracedata2 (9UL)
- #define TAD_PSEL_TRACEDATA3_CONNECT_Pos (31UL)
- #define TAD_PSEL_TRACEDATA3_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA3_CONNECT_Pos)
- #define TAD_PSEL_TRACEDATA3_CONNECT_Connected (0UL)
- #define TAD_PSEL_TRACEDATA3_CONNECT_Disconnected (1UL)
- #define TAD_PSEL_TRACEDATA3_PIN_Pos (0UL)
- #define TAD_PSEL_TRACEDATA3_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA3_PIN_Pos)
- #define TAD_PSEL_TRACEDATA3_PIN_Tracedata3 (8UL)
- #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos (0UL)
- #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Msk (0x3UL << TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos)
- #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_64MHz (0UL)
- #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz (1UL)
- #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_8MHz (2UL)
- #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_4MHz (3UL)
- #define TIMER_TASKS_START_TASKS_START_Pos (0UL)
- #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos)
- #define TIMER_TASKS_START_TASKS_START_Trigger (1UL)
- #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos)
- #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL)
- #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos)
- #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL)
- #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL)
- #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos)
- #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL)
- #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL)
- #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos)
- #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL)
- #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL)
- #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos)
- #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL)
- #define TIMER_SUBSCRIBE_START_EN_Pos (31UL)
- #define TIMER_SUBSCRIBE_START_EN_Msk (0x1UL << TIMER_SUBSCRIBE_START_EN_Pos)
- #define TIMER_SUBSCRIBE_START_EN_Disabled (0UL)
- #define TIMER_SUBSCRIBE_START_EN_Enabled (1UL)
- #define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos)
- #define TIMER_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define TIMER_SUBSCRIBE_STOP_EN_Msk (0x1UL << TIMER_SUBSCRIBE_STOP_EN_Pos)
- #define TIMER_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define TIMER_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos)
- #define TIMER_SUBSCRIBE_COUNT_EN_Pos (31UL)
- #define TIMER_SUBSCRIBE_COUNT_EN_Msk (0x1UL << TIMER_SUBSCRIBE_COUNT_EN_Pos)
- #define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0UL)
- #define TIMER_SUBSCRIBE_COUNT_EN_Enabled (1UL)
- #define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL)
- #define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos)
- #define TIMER_SUBSCRIBE_CLEAR_EN_Pos (31UL)
- #define TIMER_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CLEAR_EN_Pos)
- #define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0UL)
- #define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (1UL)
- #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL)
- #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos)
- #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos (31UL)
- #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Msk (0x1UL << TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos)
- #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0UL)
- #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (1UL)
- #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos (0UL)
- #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos)
- #define TIMER_SUBSCRIBE_CAPTURE_EN_Pos (31UL)
- #define TIMER_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CAPTURE_EN_Pos)
- #define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0UL)
- #define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (1UL)
- #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL)
- #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos)
- #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL)
- #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos)
- #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL)
- #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL)
- #define TIMER_PUBLISH_COMPARE_EN_Pos (31UL)
- #define TIMER_PUBLISH_COMPARE_EN_Msk (0x1UL << TIMER_PUBLISH_COMPARE_EN_Pos)
- #define TIMER_PUBLISH_COMPARE_EN_Disabled (0UL)
- #define TIMER_PUBLISH_COMPARE_EN_Enabled (1UL)
- #define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL)
- #define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos)
- #define TIMER_SHORTS_COMPARE5_STOP_Pos (21UL)
- #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos)
- #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE4_STOP_Pos (20UL)
- #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos)
- #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE3_STOP_Pos (19UL)
- #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos)
- #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE2_STOP_Pos (18UL)
- #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos)
- #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE1_STOP_Pos (17UL)
- #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos)
- #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE0_STOP_Pos (16UL)
- #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos)
- #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL)
- #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos)
- #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL)
- #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos)
- #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL)
- #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos)
- #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL)
- #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos)
- #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL)
- #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos)
- #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL)
- #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos)
- #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL)
- #define TIMER_INTEN_COMPARE5_Pos (21UL)
- #define TIMER_INTEN_COMPARE5_Msk (0x1UL << TIMER_INTEN_COMPARE5_Pos)
- #define TIMER_INTEN_COMPARE5_Disabled (0UL)
- #define TIMER_INTEN_COMPARE5_Enabled (1UL)
- #define TIMER_INTEN_COMPARE4_Pos (20UL)
- #define TIMER_INTEN_COMPARE4_Msk (0x1UL << TIMER_INTEN_COMPARE4_Pos)
- #define TIMER_INTEN_COMPARE4_Disabled (0UL)
- #define TIMER_INTEN_COMPARE4_Enabled (1UL)
- #define TIMER_INTEN_COMPARE3_Pos (19UL)
- #define TIMER_INTEN_COMPARE3_Msk (0x1UL << TIMER_INTEN_COMPARE3_Pos)
- #define TIMER_INTEN_COMPARE3_Disabled (0UL)
- #define TIMER_INTEN_COMPARE3_Enabled (1UL)
- #define TIMER_INTEN_COMPARE2_Pos (18UL)
- #define TIMER_INTEN_COMPARE2_Msk (0x1UL << TIMER_INTEN_COMPARE2_Pos)
- #define TIMER_INTEN_COMPARE2_Disabled (0UL)
- #define TIMER_INTEN_COMPARE2_Enabled (1UL)
- #define TIMER_INTEN_COMPARE1_Pos (17UL)
- #define TIMER_INTEN_COMPARE1_Msk (0x1UL << TIMER_INTEN_COMPARE1_Pos)
- #define TIMER_INTEN_COMPARE1_Disabled (0UL)
- #define TIMER_INTEN_COMPARE1_Enabled (1UL)
- #define TIMER_INTEN_COMPARE0_Pos (16UL)
- #define TIMER_INTEN_COMPARE0_Msk (0x1UL << TIMER_INTEN_COMPARE0_Pos)
- #define TIMER_INTEN_COMPARE0_Disabled (0UL)
- #define TIMER_INTEN_COMPARE0_Enabled (1UL)
- #define TIMER_INTENSET_COMPARE5_Pos (21UL)
- #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos)
- #define TIMER_INTENSET_COMPARE5_Disabled (0UL)
- #define TIMER_INTENSET_COMPARE5_Enabled (1UL)
- #define TIMER_INTENSET_COMPARE5_Set (1UL)
- #define TIMER_INTENSET_COMPARE4_Pos (20UL)
- #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos)
- #define TIMER_INTENSET_COMPARE4_Disabled (0UL)
- #define TIMER_INTENSET_COMPARE4_Enabled (1UL)
- #define TIMER_INTENSET_COMPARE4_Set (1UL)
- #define TIMER_INTENSET_COMPARE3_Pos (19UL)
- #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos)
- #define TIMER_INTENSET_COMPARE3_Disabled (0UL)
- #define TIMER_INTENSET_COMPARE3_Enabled (1UL)
- #define TIMER_INTENSET_COMPARE3_Set (1UL)
- #define TIMER_INTENSET_COMPARE2_Pos (18UL)
- #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos)
- #define TIMER_INTENSET_COMPARE2_Disabled (0UL)
- #define TIMER_INTENSET_COMPARE2_Enabled (1UL)
- #define TIMER_INTENSET_COMPARE2_Set (1UL)
- #define TIMER_INTENSET_COMPARE1_Pos (17UL)
- #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos)
- #define TIMER_INTENSET_COMPARE1_Disabled (0UL)
- #define TIMER_INTENSET_COMPARE1_Enabled (1UL)
- #define TIMER_INTENSET_COMPARE1_Set (1UL)
- #define TIMER_INTENSET_COMPARE0_Pos (16UL)
- #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos)
- #define TIMER_INTENSET_COMPARE0_Disabled (0UL)
- #define TIMER_INTENSET_COMPARE0_Enabled (1UL)
- #define TIMER_INTENSET_COMPARE0_Set (1UL)
- #define TIMER_INTENCLR_COMPARE5_Pos (21UL)
- #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos)
- #define TIMER_INTENCLR_COMPARE5_Disabled (0UL)
- #define TIMER_INTENCLR_COMPARE5_Enabled (1UL)
- #define TIMER_INTENCLR_COMPARE5_Clear (1UL)
- #define TIMER_INTENCLR_COMPARE4_Pos (20UL)
- #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos)
- #define TIMER_INTENCLR_COMPARE4_Disabled (0UL)
- #define TIMER_INTENCLR_COMPARE4_Enabled (1UL)
- #define TIMER_INTENCLR_COMPARE4_Clear (1UL)
- #define TIMER_INTENCLR_COMPARE3_Pos (19UL)
- #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos)
- #define TIMER_INTENCLR_COMPARE3_Disabled (0UL)
- #define TIMER_INTENCLR_COMPARE3_Enabled (1UL)
- #define TIMER_INTENCLR_COMPARE3_Clear (1UL)
- #define TIMER_INTENCLR_COMPARE2_Pos (18UL)
- #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos)
- #define TIMER_INTENCLR_COMPARE2_Disabled (0UL)
- #define TIMER_INTENCLR_COMPARE2_Enabled (1UL)
- #define TIMER_INTENCLR_COMPARE2_Clear (1UL)
- #define TIMER_INTENCLR_COMPARE1_Pos (17UL)
- #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos)
- #define TIMER_INTENCLR_COMPARE1_Disabled (0UL)
- #define TIMER_INTENCLR_COMPARE1_Enabled (1UL)
- #define TIMER_INTENCLR_COMPARE1_Clear (1UL)
- #define TIMER_INTENCLR_COMPARE0_Pos (16UL)
- #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos)
- #define TIMER_INTENCLR_COMPARE0_Disabled (0UL)
- #define TIMER_INTENCLR_COMPARE0_Enabled (1UL)
- #define TIMER_INTENCLR_COMPARE0_Clear (1UL)
- #define TIMER_MODE_MODE_Pos (0UL)
- #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos)
- #define TIMER_MODE_MODE_Timer (0UL)
- #define TIMER_MODE_MODE_Counter (1UL)
- #define TIMER_MODE_MODE_LowPowerCounter (2UL)
- #define TIMER_BITMODE_BITMODE_Pos (0UL)
- #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos)
- #define TIMER_BITMODE_BITMODE_16Bit (0UL)
- #define TIMER_BITMODE_BITMODE_08Bit (1UL)
- #define TIMER_BITMODE_BITMODE_24Bit (2UL)
- #define TIMER_BITMODE_BITMODE_32Bit (3UL)
- #define TIMER_PRESCALER_PRESCALER_Pos (0UL)
- #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos)
- #define TIMER_CC_CC_Pos (0UL)
- #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos)
- #define TIMER_ONESHOTEN_ONESHOTEN_Pos (0UL)
- #define TIMER_ONESHOTEN_ONESHOTEN_Msk (0x1UL << TIMER_ONESHOTEN_ONESHOTEN_Pos)
- #define TIMER_ONESHOTEN_ONESHOTEN_Disable (0UL)
- #define TIMER_ONESHOTEN_ONESHOTEN_Enable (1UL)
- #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL)
- #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos)
- #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL)
- #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL)
- #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos)
- #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL)
- #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos)
- #define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL)
- #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos)
- #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL)
- #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL)
- #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos)
- #define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL)
- #define TWIM_SUBSCRIBE_STARTRX_EN_Pos (31UL)
- #define TWIM_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTRX_EN_Pos)
- #define TWIM_SUBSCRIBE_STARTRX_EN_Disabled (0UL)
- #define TWIM_SUBSCRIBE_STARTRX_EN_Enabled (1UL)
- #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL)
- #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos)
- #define TWIM_SUBSCRIBE_STARTTX_EN_Pos (31UL)
- #define TWIM_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTTX_EN_Pos)
- #define TWIM_SUBSCRIBE_STARTTX_EN_Disabled (0UL)
- #define TWIM_SUBSCRIBE_STARTTX_EN_Enabled (1UL)
- #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL)
- #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos)
- #define TWIM_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define TWIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STOP_EN_Pos)
- #define TWIM_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define TWIM_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define TWIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define TWIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STOP_CHIDX_Pos)
- #define TWIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL)
- #define TWIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIM_SUBSCRIBE_SUSPEND_EN_Pos)
- #define TWIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL)
- #define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL)
- #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL)
- #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos)
- #define TWIM_SUBSCRIBE_RESUME_EN_Pos (31UL)
- #define TWIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIM_SUBSCRIBE_RESUME_EN_Pos)
- #define TWIM_SUBSCRIBE_RESUME_EN_Disabled (0UL)
- #define TWIM_SUBSCRIBE_RESUME_EN_Enabled (1UL)
- #define TWIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL)
- #define TWIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_RESUME_CHIDX_Pos)
- #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL)
- #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos)
- #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL)
- #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL)
- #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)
- #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos)
- #define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL)
- #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL)
- #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL)
- #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos)
- #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL)
- #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL)
- #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL)
- #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos)
- #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL)
- #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL)
- #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL)
- #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos)
- #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL)
- #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL)
- #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL)
- #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos)
- #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL)
- #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL)
- #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL)
- #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos)
- #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL)
- #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL)
- #define TWIM_PUBLISH_STOPPED_EN_Pos (31UL)
- #define TWIM_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIM_PUBLISH_STOPPED_EN_Pos)
- #define TWIM_PUBLISH_STOPPED_EN_Disabled (0UL)
- #define TWIM_PUBLISH_STOPPED_EN_Enabled (1UL)
- #define TWIM_PUBLISH_STOPPED_CHIDX_Pos (0UL)
- #define TWIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_STOPPED_CHIDX_Pos)
- #define TWIM_PUBLISH_ERROR_EN_Pos (31UL)
- #define TWIM_PUBLISH_ERROR_EN_Msk (0x1UL << TWIM_PUBLISH_ERROR_EN_Pos)
- #define TWIM_PUBLISH_ERROR_EN_Disabled (0UL)
- #define TWIM_PUBLISH_ERROR_EN_Enabled (1UL)
- #define TWIM_PUBLISH_ERROR_CHIDX_Pos (0UL)
- #define TWIM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_ERROR_CHIDX_Pos)
- #define TWIM_PUBLISH_SUSPENDED_EN_Pos (31UL)
- #define TWIM_PUBLISH_SUSPENDED_EN_Msk (0x1UL << TWIM_PUBLISH_SUSPENDED_EN_Pos)
- #define TWIM_PUBLISH_SUSPENDED_EN_Disabled (0UL)
- #define TWIM_PUBLISH_SUSPENDED_EN_Enabled (1UL)
- #define TWIM_PUBLISH_SUSPENDED_CHIDX_Pos (0UL)
- #define TWIM_PUBLISH_SUSPENDED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_SUSPENDED_CHIDX_Pos)
- #define TWIM_PUBLISH_RXSTARTED_EN_Pos (31UL)
- #define TWIM_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_RXSTARTED_EN_Pos)
- #define TWIM_PUBLISH_RXSTARTED_EN_Disabled (0UL)
- #define TWIM_PUBLISH_RXSTARTED_EN_Enabled (1UL)
- #define TWIM_PUBLISH_RXSTARTED_CHIDX_Pos (0UL)
- #define TWIM_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_RXSTARTED_CHIDX_Pos)
- #define TWIM_PUBLISH_TXSTARTED_EN_Pos (31UL)
- #define TWIM_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_TXSTARTED_EN_Pos)
- #define TWIM_PUBLISH_TXSTARTED_EN_Disabled (0UL)
- #define TWIM_PUBLISH_TXSTARTED_EN_Enabled (1UL)
- #define TWIM_PUBLISH_TXSTARTED_CHIDX_Pos (0UL)
- #define TWIM_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_TXSTARTED_CHIDX_Pos)
- #define TWIM_PUBLISH_LASTRX_EN_Pos (31UL)
- #define TWIM_PUBLISH_LASTRX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTRX_EN_Pos)
- #define TWIM_PUBLISH_LASTRX_EN_Disabled (0UL)
- #define TWIM_PUBLISH_LASTRX_EN_Enabled (1UL)
- #define TWIM_PUBLISH_LASTRX_CHIDX_Pos (0UL)
- #define TWIM_PUBLISH_LASTRX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTRX_CHIDX_Pos)
- #define TWIM_PUBLISH_LASTTX_EN_Pos (31UL)
- #define TWIM_PUBLISH_LASTTX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTTX_EN_Pos)
- #define TWIM_PUBLISH_LASTTX_EN_Disabled (0UL)
- #define TWIM_PUBLISH_LASTTX_EN_Enabled (1UL)
- #define TWIM_PUBLISH_LASTTX_CHIDX_Pos (0UL)
- #define TWIM_PUBLISH_LASTTX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTTX_CHIDX_Pos)
- #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL)
- #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos)
- #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL)
- #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL)
- #define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL)
- #define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos)
- #define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL)
- #define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL)
- #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL)
- #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos)
- #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL)
- #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL)
- #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL)
- #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos)
- #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL)
- #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL)
- #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL)
- #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos)
- #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL)
- #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL)
- #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL)
- #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos)
- #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL)
- #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL)
- #define TWIM_INTEN_LASTTX_Pos (24UL)
- #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos)
- #define TWIM_INTEN_LASTTX_Disabled (0UL)
- #define TWIM_INTEN_LASTTX_Enabled (1UL)
- #define TWIM_INTEN_LASTRX_Pos (23UL)
- #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos)
- #define TWIM_INTEN_LASTRX_Disabled (0UL)
- #define TWIM_INTEN_LASTRX_Enabled (1UL)
- #define TWIM_INTEN_TXSTARTED_Pos (20UL)
- #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos)
- #define TWIM_INTEN_TXSTARTED_Disabled (0UL)
- #define TWIM_INTEN_TXSTARTED_Enabled (1UL)
- #define TWIM_INTEN_RXSTARTED_Pos (19UL)
- #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos)
- #define TWIM_INTEN_RXSTARTED_Disabled (0UL)
- #define TWIM_INTEN_RXSTARTED_Enabled (1UL)
- #define TWIM_INTEN_SUSPENDED_Pos (18UL)
- #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos)
- #define TWIM_INTEN_SUSPENDED_Disabled (0UL)
- #define TWIM_INTEN_SUSPENDED_Enabled (1UL)
- #define TWIM_INTEN_ERROR_Pos (9UL)
- #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos)
- #define TWIM_INTEN_ERROR_Disabled (0UL)
- #define TWIM_INTEN_ERROR_Enabled (1UL)
- #define TWIM_INTEN_STOPPED_Pos (1UL)
- #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos)
- #define TWIM_INTEN_STOPPED_Disabled (0UL)
- #define TWIM_INTEN_STOPPED_Enabled (1UL)
- #define TWIM_INTENSET_LASTTX_Pos (24UL)
- #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos)
- #define TWIM_INTENSET_LASTTX_Disabled (0UL)
- #define TWIM_INTENSET_LASTTX_Enabled (1UL)
- #define TWIM_INTENSET_LASTTX_Set (1UL)
- #define TWIM_INTENSET_LASTRX_Pos (23UL)
- #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos)
- #define TWIM_INTENSET_LASTRX_Disabled (0UL)
- #define TWIM_INTENSET_LASTRX_Enabled (1UL)
- #define TWIM_INTENSET_LASTRX_Set (1UL)
- #define TWIM_INTENSET_TXSTARTED_Pos (20UL)
- #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos)
- #define TWIM_INTENSET_TXSTARTED_Disabled (0UL)
- #define TWIM_INTENSET_TXSTARTED_Enabled (1UL)
- #define TWIM_INTENSET_TXSTARTED_Set (1UL)
- #define TWIM_INTENSET_RXSTARTED_Pos (19UL)
- #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos)
- #define TWIM_INTENSET_RXSTARTED_Disabled (0UL)
- #define TWIM_INTENSET_RXSTARTED_Enabled (1UL)
- #define TWIM_INTENSET_RXSTARTED_Set (1UL)
- #define TWIM_INTENSET_SUSPENDED_Pos (18UL)
- #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos)
- #define TWIM_INTENSET_SUSPENDED_Disabled (0UL)
- #define TWIM_INTENSET_SUSPENDED_Enabled (1UL)
- #define TWIM_INTENSET_SUSPENDED_Set (1UL)
- #define TWIM_INTENSET_ERROR_Pos (9UL)
- #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos)
- #define TWIM_INTENSET_ERROR_Disabled (0UL)
- #define TWIM_INTENSET_ERROR_Enabled (1UL)
- #define TWIM_INTENSET_ERROR_Set (1UL)
- #define TWIM_INTENSET_STOPPED_Pos (1UL)
- #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos)
- #define TWIM_INTENSET_STOPPED_Disabled (0UL)
- #define TWIM_INTENSET_STOPPED_Enabled (1UL)
- #define TWIM_INTENSET_STOPPED_Set (1UL)
- #define TWIM_INTENCLR_LASTTX_Pos (24UL)
- #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos)
- #define TWIM_INTENCLR_LASTTX_Disabled (0UL)
- #define TWIM_INTENCLR_LASTTX_Enabled (1UL)
- #define TWIM_INTENCLR_LASTTX_Clear (1UL)
- #define TWIM_INTENCLR_LASTRX_Pos (23UL)
- #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos)
- #define TWIM_INTENCLR_LASTRX_Disabled (0UL)
- #define TWIM_INTENCLR_LASTRX_Enabled (1UL)
- #define TWIM_INTENCLR_LASTRX_Clear (1UL)
- #define TWIM_INTENCLR_TXSTARTED_Pos (20UL)
- #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos)
- #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL)
- #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL)
- #define TWIM_INTENCLR_TXSTARTED_Clear (1UL)
- #define TWIM_INTENCLR_RXSTARTED_Pos (19UL)
- #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos)
- #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL)
- #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL)
- #define TWIM_INTENCLR_RXSTARTED_Clear (1UL)
- #define TWIM_INTENCLR_SUSPENDED_Pos (18UL)
- #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos)
- #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL)
- #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL)
- #define TWIM_INTENCLR_SUSPENDED_Clear (1UL)
- #define TWIM_INTENCLR_ERROR_Pos (9UL)
- #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos)
- #define TWIM_INTENCLR_ERROR_Disabled (0UL)
- #define TWIM_INTENCLR_ERROR_Enabled (1UL)
- #define TWIM_INTENCLR_ERROR_Clear (1UL)
- #define TWIM_INTENCLR_STOPPED_Pos (1UL)
- #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos)
- #define TWIM_INTENCLR_STOPPED_Disabled (0UL)
- #define TWIM_INTENCLR_STOPPED_Enabled (1UL)
- #define TWIM_INTENCLR_STOPPED_Clear (1UL)
- #define TWIM_ERRORSRC_DNACK_Pos (2UL)
- #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos)
- #define TWIM_ERRORSRC_DNACK_NotReceived (0UL)
- #define TWIM_ERRORSRC_DNACK_Received (1UL)
- #define TWIM_ERRORSRC_ANACK_Pos (1UL)
- #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos)
- #define TWIM_ERRORSRC_ANACK_NotReceived (0UL)
- #define TWIM_ERRORSRC_ANACK_Received (1UL)
- #define TWIM_ERRORSRC_OVERRUN_Pos (0UL)
- #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos)
- #define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL)
- #define TWIM_ERRORSRC_OVERRUN_Received (1UL)
- #define TWIM_ENABLE_ENABLE_Pos (0UL)
- #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos)
- #define TWIM_ENABLE_ENABLE_Disabled (0UL)
- #define TWIM_ENABLE_ENABLE_Enabled (6UL)
- #define TWIM_PSEL_SCL_CONNECT_Pos (31UL)
- #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos)
- #define TWIM_PSEL_SCL_CONNECT_Connected (0UL)
- #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL)
- #define TWIM_PSEL_SCL_PORT_Pos (5UL)
- #define TWIM_PSEL_SCL_PORT_Msk (0x1UL << TWIM_PSEL_SCL_PORT_Pos)
- #define TWIM_PSEL_SCL_PIN_Pos (0UL)
- #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos)
- #define TWIM_PSEL_SDA_CONNECT_Pos (31UL)
- #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos)
- #define TWIM_PSEL_SDA_CONNECT_Connected (0UL)
- #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL)
- #define TWIM_PSEL_SDA_PORT_Pos (5UL)
- #define TWIM_PSEL_SDA_PORT_Msk (0x1UL << TWIM_PSEL_SDA_PORT_Pos)
- #define TWIM_PSEL_SDA_PIN_Pos (0UL)
- #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos)
- #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL)
- #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos)
- #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL)
- #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL)
- #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL)
- #define TWIM_FREQUENCY_FREQUENCY_K1000 (0x0FF00000UL)
- #define TWIM_RXD_PTR_PTR_Pos (0UL)
- #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos)
- #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL)
- #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos)
- #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL)
- #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos)
- #define TWIM_RXD_LIST_LIST_Pos (0UL)
- #define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos)
- #define TWIM_RXD_LIST_LIST_Disabled (0UL)
- #define TWIM_RXD_LIST_LIST_ArrayList (1UL)
- #define TWIM_TXD_PTR_PTR_Pos (0UL)
- #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos)
- #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL)
- #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos)
- #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL)
- #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos)
- #define TWIM_TXD_LIST_LIST_Pos (0UL)
- #define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos)
- #define TWIM_TXD_LIST_LIST_Disabled (0UL)
- #define TWIM_TXD_LIST_LIST_ArrayList (1UL)
- #define TWIM_ADDRESS_ADDRESS_Pos (0UL)
- #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos)
- #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos)
- #define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL)
- #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos)
- #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL)
- #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL)
- #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos)
- #define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL)
- #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL)
- #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos)
- #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL)
- #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL)
- #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos)
- #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL)
- #define TWIS_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define TWIS_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIS_SUBSCRIBE_STOP_EN_Pos)
- #define TWIS_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define TWIS_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define TWIS_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define TWIS_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_STOP_CHIDX_Pos)
- #define TWIS_SUBSCRIBE_SUSPEND_EN_Pos (31UL)
- #define TWIS_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIS_SUBSCRIBE_SUSPEND_EN_Pos)
- #define TWIS_SUBSCRIBE_SUSPEND_EN_Disabled (0UL)
- #define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (1UL)
- #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL)
- #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos)
- #define TWIS_SUBSCRIBE_RESUME_EN_Pos (31UL)
- #define TWIS_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIS_SUBSCRIBE_RESUME_EN_Pos)
- #define TWIS_SUBSCRIBE_RESUME_EN_Disabled (0UL)
- #define TWIS_SUBSCRIBE_RESUME_EN_Enabled (1UL)
- #define TWIS_SUBSCRIBE_RESUME_CHIDX_Pos (0UL)
- #define TWIS_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_RESUME_CHIDX_Pos)
- #define TWIS_SUBSCRIBE_PREPARERX_EN_Pos (31UL)
- #define TWIS_SUBSCRIBE_PREPARERX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARERX_EN_Pos)
- #define TWIS_SUBSCRIBE_PREPARERX_EN_Disabled (0UL)
- #define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (1UL)
- #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos (0UL)
- #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos)
- #define TWIS_SUBSCRIBE_PREPARETX_EN_Pos (31UL)
- #define TWIS_SUBSCRIBE_PREPARETX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARETX_EN_Pos)
- #define TWIS_SUBSCRIBE_PREPARETX_EN_Disabled (0UL)
- #define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (1UL)
- #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos (0UL)
- #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos)
- #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL)
- #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos)
- #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL)
- #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL)
- #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)
- #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos)
- #define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL)
- #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL)
- #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL)
- #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos)
- #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL)
- #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL)
- #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL)
- #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos)
- #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL)
- #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL)
- #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL)
- #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos)
- #define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL)
- #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL)
- #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL)
- #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos)
- #define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL)
- #define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL)
- #define TWIS_PUBLISH_STOPPED_EN_Pos (31UL)
- #define TWIS_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIS_PUBLISH_STOPPED_EN_Pos)
- #define TWIS_PUBLISH_STOPPED_EN_Disabled (0UL)
- #define TWIS_PUBLISH_STOPPED_EN_Enabled (1UL)
- #define TWIS_PUBLISH_STOPPED_CHIDX_Pos (0UL)
- #define TWIS_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_STOPPED_CHIDX_Pos)
- #define TWIS_PUBLISH_ERROR_EN_Pos (31UL)
- #define TWIS_PUBLISH_ERROR_EN_Msk (0x1UL << TWIS_PUBLISH_ERROR_EN_Pos)
- #define TWIS_PUBLISH_ERROR_EN_Disabled (0UL)
- #define TWIS_PUBLISH_ERROR_EN_Enabled (1UL)
- #define TWIS_PUBLISH_ERROR_CHIDX_Pos (0UL)
- #define TWIS_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_ERROR_CHIDX_Pos)
- #define TWIS_PUBLISH_RXSTARTED_EN_Pos (31UL)
- #define TWIS_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_RXSTARTED_EN_Pos)
- #define TWIS_PUBLISH_RXSTARTED_EN_Disabled (0UL)
- #define TWIS_PUBLISH_RXSTARTED_EN_Enabled (1UL)
- #define TWIS_PUBLISH_RXSTARTED_CHIDX_Pos (0UL)
- #define TWIS_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_RXSTARTED_CHIDX_Pos)
- #define TWIS_PUBLISH_TXSTARTED_EN_Pos (31UL)
- #define TWIS_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_TXSTARTED_EN_Pos)
- #define TWIS_PUBLISH_TXSTARTED_EN_Disabled (0UL)
- #define TWIS_PUBLISH_TXSTARTED_EN_Enabled (1UL)
- #define TWIS_PUBLISH_TXSTARTED_CHIDX_Pos (0UL)
- #define TWIS_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_TXSTARTED_CHIDX_Pos)
- #define TWIS_PUBLISH_WRITE_EN_Pos (31UL)
- #define TWIS_PUBLISH_WRITE_EN_Msk (0x1UL << TWIS_PUBLISH_WRITE_EN_Pos)
- #define TWIS_PUBLISH_WRITE_EN_Disabled (0UL)
- #define TWIS_PUBLISH_WRITE_EN_Enabled (1UL)
- #define TWIS_PUBLISH_WRITE_CHIDX_Pos (0UL)
- #define TWIS_PUBLISH_WRITE_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_WRITE_CHIDX_Pos)
- #define TWIS_PUBLISH_READ_EN_Pos (31UL)
- #define TWIS_PUBLISH_READ_EN_Msk (0x1UL << TWIS_PUBLISH_READ_EN_Pos)
- #define TWIS_PUBLISH_READ_EN_Disabled (0UL)
- #define TWIS_PUBLISH_READ_EN_Enabled (1UL)
- #define TWIS_PUBLISH_READ_CHIDX_Pos (0UL)
- #define TWIS_PUBLISH_READ_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_READ_CHIDX_Pos)
- #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL)
- #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos)
- #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL)
- #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL)
- #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL)
- #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos)
- #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL)
- #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL)
- #define TWIS_INTEN_READ_Pos (26UL)
- #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos)
- #define TWIS_INTEN_READ_Disabled (0UL)
- #define TWIS_INTEN_READ_Enabled (1UL)
- #define TWIS_INTEN_WRITE_Pos (25UL)
- #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos)
- #define TWIS_INTEN_WRITE_Disabled (0UL)
- #define TWIS_INTEN_WRITE_Enabled (1UL)
- #define TWIS_INTEN_TXSTARTED_Pos (20UL)
- #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos)
- #define TWIS_INTEN_TXSTARTED_Disabled (0UL)
- #define TWIS_INTEN_TXSTARTED_Enabled (1UL)
- #define TWIS_INTEN_RXSTARTED_Pos (19UL)
- #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos)
- #define TWIS_INTEN_RXSTARTED_Disabled (0UL)
- #define TWIS_INTEN_RXSTARTED_Enabled (1UL)
- #define TWIS_INTEN_ERROR_Pos (9UL)
- #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos)
- #define TWIS_INTEN_ERROR_Disabled (0UL)
- #define TWIS_INTEN_ERROR_Enabled (1UL)
- #define TWIS_INTEN_STOPPED_Pos (1UL)
- #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos)
- #define TWIS_INTEN_STOPPED_Disabled (0UL)
- #define TWIS_INTEN_STOPPED_Enabled (1UL)
- #define TWIS_INTENSET_READ_Pos (26UL)
- #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos)
- #define TWIS_INTENSET_READ_Disabled (0UL)
- #define TWIS_INTENSET_READ_Enabled (1UL)
- #define TWIS_INTENSET_READ_Set (1UL)
- #define TWIS_INTENSET_WRITE_Pos (25UL)
- #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos)
- #define TWIS_INTENSET_WRITE_Disabled (0UL)
- #define TWIS_INTENSET_WRITE_Enabled (1UL)
- #define TWIS_INTENSET_WRITE_Set (1UL)
- #define TWIS_INTENSET_TXSTARTED_Pos (20UL)
- #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos)
- #define TWIS_INTENSET_TXSTARTED_Disabled (0UL)
- #define TWIS_INTENSET_TXSTARTED_Enabled (1UL)
- #define TWIS_INTENSET_TXSTARTED_Set (1UL)
- #define TWIS_INTENSET_RXSTARTED_Pos (19UL)
- #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos)
- #define TWIS_INTENSET_RXSTARTED_Disabled (0UL)
- #define TWIS_INTENSET_RXSTARTED_Enabled (1UL)
- #define TWIS_INTENSET_RXSTARTED_Set (1UL)
- #define TWIS_INTENSET_ERROR_Pos (9UL)
- #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos)
- #define TWIS_INTENSET_ERROR_Disabled (0UL)
- #define TWIS_INTENSET_ERROR_Enabled (1UL)
- #define TWIS_INTENSET_ERROR_Set (1UL)
- #define TWIS_INTENSET_STOPPED_Pos (1UL)
- #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos)
- #define TWIS_INTENSET_STOPPED_Disabled (0UL)
- #define TWIS_INTENSET_STOPPED_Enabled (1UL)
- #define TWIS_INTENSET_STOPPED_Set (1UL)
- #define TWIS_INTENCLR_READ_Pos (26UL)
- #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos)
- #define TWIS_INTENCLR_READ_Disabled (0UL)
- #define TWIS_INTENCLR_READ_Enabled (1UL)
- #define TWIS_INTENCLR_READ_Clear (1UL)
- #define TWIS_INTENCLR_WRITE_Pos (25UL)
- #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos)
- #define TWIS_INTENCLR_WRITE_Disabled (0UL)
- #define TWIS_INTENCLR_WRITE_Enabled (1UL)
- #define TWIS_INTENCLR_WRITE_Clear (1UL)
- #define TWIS_INTENCLR_TXSTARTED_Pos (20UL)
- #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos)
- #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL)
- #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL)
- #define TWIS_INTENCLR_TXSTARTED_Clear (1UL)
- #define TWIS_INTENCLR_RXSTARTED_Pos (19UL)
- #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos)
- #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL)
- #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL)
- #define TWIS_INTENCLR_RXSTARTED_Clear (1UL)
- #define TWIS_INTENCLR_ERROR_Pos (9UL)
- #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos)
- #define TWIS_INTENCLR_ERROR_Disabled (0UL)
- #define TWIS_INTENCLR_ERROR_Enabled (1UL)
- #define TWIS_INTENCLR_ERROR_Clear (1UL)
- #define TWIS_INTENCLR_STOPPED_Pos (1UL)
- #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos)
- #define TWIS_INTENCLR_STOPPED_Disabled (0UL)
- #define TWIS_INTENCLR_STOPPED_Enabled (1UL)
- #define TWIS_INTENCLR_STOPPED_Clear (1UL)
- #define TWIS_ERRORSRC_OVERREAD_Pos (3UL)
- #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos)
- #define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL)
- #define TWIS_ERRORSRC_OVERREAD_Detected (1UL)
- #define TWIS_ERRORSRC_DNACK_Pos (2UL)
- #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos)
- #define TWIS_ERRORSRC_DNACK_NotReceived (0UL)
- #define TWIS_ERRORSRC_DNACK_Received (1UL)
- #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL)
- #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos)
- #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL)
- #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL)
- #define TWIS_MATCH_MATCH_Pos (0UL)
- #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos)
- #define TWIS_ENABLE_ENABLE_Pos (0UL)
- #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos)
- #define TWIS_ENABLE_ENABLE_Disabled (0UL)
- #define TWIS_ENABLE_ENABLE_Enabled (9UL)
- #define TWIS_PSEL_SCL_CONNECT_Pos (31UL)
- #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos)
- #define TWIS_PSEL_SCL_CONNECT_Connected (0UL)
- #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL)
- #define TWIS_PSEL_SCL_PORT_Pos (5UL)
- #define TWIS_PSEL_SCL_PORT_Msk (0x1UL << TWIS_PSEL_SCL_PORT_Pos)
- #define TWIS_PSEL_SCL_PIN_Pos (0UL)
- #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos)
- #define TWIS_PSEL_SDA_CONNECT_Pos (31UL)
- #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos)
- #define TWIS_PSEL_SDA_CONNECT_Connected (0UL)
- #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL)
- #define TWIS_PSEL_SDA_PORT_Pos (5UL)
- #define TWIS_PSEL_SDA_PORT_Msk (0x1UL << TWIS_PSEL_SDA_PORT_Pos)
- #define TWIS_PSEL_SDA_PIN_Pos (0UL)
- #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos)
- #define TWIS_RXD_PTR_PTR_Pos (0UL)
- #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos)
- #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL)
- #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos)
- #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL)
- #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos)
- #define TWIS_RXD_LIST_LIST_Pos (0UL)
- #define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos)
- #define TWIS_RXD_LIST_LIST_Disabled (0UL)
- #define TWIS_RXD_LIST_LIST_ArrayList (1UL)
- #define TWIS_TXD_PTR_PTR_Pos (0UL)
- #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos)
- #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL)
- #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos)
- #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL)
- #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos)
- #define TWIS_TXD_LIST_LIST_Pos (0UL)
- #define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos)
- #define TWIS_TXD_LIST_LIST_Disabled (0UL)
- #define TWIS_TXD_LIST_LIST_ArrayList (1UL)
- #define TWIS_ADDRESS_ADDRESS_Pos (0UL)
- #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos)
- #define TWIS_CONFIG_ADDRESS1_Pos (1UL)
- #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos)
- #define TWIS_CONFIG_ADDRESS1_Disabled (0UL)
- #define TWIS_CONFIG_ADDRESS1_Enabled (1UL)
- #define TWIS_CONFIG_ADDRESS0_Pos (0UL)
- #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos)
- #define TWIS_CONFIG_ADDRESS0_Disabled (0UL)
- #define TWIS_CONFIG_ADDRESS0_Enabled (1UL)
- #define TWIS_ORC_ORC_Pos (0UL)
- #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos)
- #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL)
- #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos)
- #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL)
- #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL)
- #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos)
- #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL)
- #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL)
- #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos)
- #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL)
- #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL)
- #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos)
- #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL)
- #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL)
- #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos)
- #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL)
- #define UARTE_SUBSCRIBE_STARTRX_EN_Pos (31UL)
- #define UARTE_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTRX_EN_Pos)
- #define UARTE_SUBSCRIBE_STARTRX_EN_Disabled (0UL)
- #define UARTE_SUBSCRIBE_STARTRX_EN_Enabled (1UL)
- #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL)
- #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos)
- #define UARTE_SUBSCRIBE_STOPRX_EN_Pos (31UL)
- #define UARTE_SUBSCRIBE_STOPRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPRX_EN_Pos)
- #define UARTE_SUBSCRIBE_STOPRX_EN_Disabled (0UL)
- #define UARTE_SUBSCRIBE_STOPRX_EN_Enabled (1UL)
- #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos (0UL)
- #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos)
- #define UARTE_SUBSCRIBE_STARTTX_EN_Pos (31UL)
- #define UARTE_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTTX_EN_Pos)
- #define UARTE_SUBSCRIBE_STARTTX_EN_Disabled (0UL)
- #define UARTE_SUBSCRIBE_STARTTX_EN_Enabled (1UL)
- #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL)
- #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos)
- #define UARTE_SUBSCRIBE_STOPTX_EN_Pos (31UL)
- #define UARTE_SUBSCRIBE_STOPTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPTX_EN_Pos)
- #define UARTE_SUBSCRIBE_STOPTX_EN_Disabled (0UL)
- #define UARTE_SUBSCRIBE_STOPTX_EN_Enabled (1UL)
- #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos (0UL)
- #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos)
- #define UARTE_SUBSCRIBE_FLUSHRX_EN_Pos (31UL)
- #define UARTE_SUBSCRIBE_FLUSHRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_FLUSHRX_EN_Pos)
- #define UARTE_SUBSCRIBE_FLUSHRX_EN_Disabled (0UL)
- #define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (1UL)
- #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos (0UL)
- #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos)
- #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL)
- #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos)
- #define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL)
- #define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL)
- #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL)
- #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos)
- #define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL)
- #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL)
- #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL)
- #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos)
- #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL)
- #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL)
- #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL)
- #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos)
- #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL)
- #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL)
- #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL)
- #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos)
- #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL)
- #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL)
- #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL)
- #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos)
- #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL)
- #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL)
- #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)
- #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos)
- #define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL)
- #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL)
- #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL)
- #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos)
- #define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL)
- #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL)
- #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL)
- #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos)
- #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL)
- #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL)
- #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL)
- #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos)
- #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL)
- #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL)
- #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL)
- #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos)
- #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL)
- #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL)
- #define UARTE_PUBLISH_CTS_EN_Pos (31UL)
- #define UARTE_PUBLISH_CTS_EN_Msk (0x1UL << UARTE_PUBLISH_CTS_EN_Pos)
- #define UARTE_PUBLISH_CTS_EN_Disabled (0UL)
- #define UARTE_PUBLISH_CTS_EN_Enabled (1UL)
- #define UARTE_PUBLISH_CTS_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_CTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_CTS_CHIDX_Pos)
- #define UARTE_PUBLISH_NCTS_EN_Pos (31UL)
- #define UARTE_PUBLISH_NCTS_EN_Msk (0x1UL << UARTE_PUBLISH_NCTS_EN_Pos)
- #define UARTE_PUBLISH_NCTS_EN_Disabled (0UL)
- #define UARTE_PUBLISH_NCTS_EN_Enabled (1UL)
- #define UARTE_PUBLISH_NCTS_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_NCTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_NCTS_CHIDX_Pos)
- #define UARTE_PUBLISH_RXDRDY_EN_Pos (31UL)
- #define UARTE_PUBLISH_RXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_RXDRDY_EN_Pos)
- #define UARTE_PUBLISH_RXDRDY_EN_Disabled (0UL)
- #define UARTE_PUBLISH_RXDRDY_EN_Enabled (1UL)
- #define UARTE_PUBLISH_RXDRDY_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_RXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXDRDY_CHIDX_Pos)
- #define UARTE_PUBLISH_ENDRX_EN_Pos (31UL)
- #define UARTE_PUBLISH_ENDRX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDRX_EN_Pos)
- #define UARTE_PUBLISH_ENDRX_EN_Disabled (0UL)
- #define UARTE_PUBLISH_ENDRX_EN_Enabled (1UL)
- #define UARTE_PUBLISH_ENDRX_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDRX_CHIDX_Pos)
- #define UARTE_PUBLISH_TXDRDY_EN_Pos (31UL)
- #define UARTE_PUBLISH_TXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_TXDRDY_EN_Pos)
- #define UARTE_PUBLISH_TXDRDY_EN_Disabled (0UL)
- #define UARTE_PUBLISH_TXDRDY_EN_Enabled (1UL)
- #define UARTE_PUBLISH_TXDRDY_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_TXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXDRDY_CHIDX_Pos)
- #define UARTE_PUBLISH_ENDTX_EN_Pos (31UL)
- #define UARTE_PUBLISH_ENDTX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDTX_EN_Pos)
- #define UARTE_PUBLISH_ENDTX_EN_Disabled (0UL)
- #define UARTE_PUBLISH_ENDTX_EN_Enabled (1UL)
- #define UARTE_PUBLISH_ENDTX_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDTX_CHIDX_Pos)
- #define UARTE_PUBLISH_ERROR_EN_Pos (31UL)
- #define UARTE_PUBLISH_ERROR_EN_Msk (0x1UL << UARTE_PUBLISH_ERROR_EN_Pos)
- #define UARTE_PUBLISH_ERROR_EN_Disabled (0UL)
- #define UARTE_PUBLISH_ERROR_EN_Enabled (1UL)
- #define UARTE_PUBLISH_ERROR_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ERROR_CHIDX_Pos)
- #define UARTE_PUBLISH_RXTO_EN_Pos (31UL)
- #define UARTE_PUBLISH_RXTO_EN_Msk (0x1UL << UARTE_PUBLISH_RXTO_EN_Pos)
- #define UARTE_PUBLISH_RXTO_EN_Disabled (0UL)
- #define UARTE_PUBLISH_RXTO_EN_Enabled (1UL)
- #define UARTE_PUBLISH_RXTO_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_RXTO_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXTO_CHIDX_Pos)
- #define UARTE_PUBLISH_RXSTARTED_EN_Pos (31UL)
- #define UARTE_PUBLISH_RXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_RXSTARTED_EN_Pos)
- #define UARTE_PUBLISH_RXSTARTED_EN_Disabled (0UL)
- #define UARTE_PUBLISH_RXSTARTED_EN_Enabled (1UL)
- #define UARTE_PUBLISH_RXSTARTED_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXSTARTED_CHIDX_Pos)
- #define UARTE_PUBLISH_TXSTARTED_EN_Pos (31UL)
- #define UARTE_PUBLISH_TXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTARTED_EN_Pos)
- #define UARTE_PUBLISH_TXSTARTED_EN_Disabled (0UL)
- #define UARTE_PUBLISH_TXSTARTED_EN_Enabled (1UL)
- #define UARTE_PUBLISH_TXSTARTED_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTARTED_CHIDX_Pos)
- #define UARTE_PUBLISH_TXSTOPPED_EN_Pos (31UL)
- #define UARTE_PUBLISH_TXSTOPPED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTOPPED_EN_Pos)
- #define UARTE_PUBLISH_TXSTOPPED_EN_Disabled (0UL)
- #define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (1UL)
- #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos)
- #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL)
- #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos)
- #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL)
- #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL)
- #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL)
- #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos)
- #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL)
- #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL)
- #define UARTE_INTEN_TXSTOPPED_Pos (22UL)
- #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos)
- #define UARTE_INTEN_TXSTOPPED_Disabled (0UL)
- #define UARTE_INTEN_TXSTOPPED_Enabled (1UL)
- #define UARTE_INTEN_TXSTARTED_Pos (20UL)
- #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos)
- #define UARTE_INTEN_TXSTARTED_Disabled (0UL)
- #define UARTE_INTEN_TXSTARTED_Enabled (1UL)
- #define UARTE_INTEN_RXSTARTED_Pos (19UL)
- #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos)
- #define UARTE_INTEN_RXSTARTED_Disabled (0UL)
- #define UARTE_INTEN_RXSTARTED_Enabled (1UL)
- #define UARTE_INTEN_RXTO_Pos (17UL)
- #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos)
- #define UARTE_INTEN_RXTO_Disabled (0UL)
- #define UARTE_INTEN_RXTO_Enabled (1UL)
- #define UARTE_INTEN_ERROR_Pos (9UL)
- #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos)
- #define UARTE_INTEN_ERROR_Disabled (0UL)
- #define UARTE_INTEN_ERROR_Enabled (1UL)
- #define UARTE_INTEN_ENDTX_Pos (8UL)
- #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos)
- #define UARTE_INTEN_ENDTX_Disabled (0UL)
- #define UARTE_INTEN_ENDTX_Enabled (1UL)
- #define UARTE_INTEN_TXDRDY_Pos (7UL)
- #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos)
- #define UARTE_INTEN_TXDRDY_Disabled (0UL)
- #define UARTE_INTEN_TXDRDY_Enabled (1UL)
- #define UARTE_INTEN_ENDRX_Pos (4UL)
- #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos)
- #define UARTE_INTEN_ENDRX_Disabled (0UL)
- #define UARTE_INTEN_ENDRX_Enabled (1UL)
- #define UARTE_INTEN_RXDRDY_Pos (2UL)
- #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos)
- #define UARTE_INTEN_RXDRDY_Disabled (0UL)
- #define UARTE_INTEN_RXDRDY_Enabled (1UL)
- #define UARTE_INTEN_NCTS_Pos (1UL)
- #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos)
- #define UARTE_INTEN_NCTS_Disabled (0UL)
- #define UARTE_INTEN_NCTS_Enabled (1UL)
- #define UARTE_INTEN_CTS_Pos (0UL)
- #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos)
- #define UARTE_INTEN_CTS_Disabled (0UL)
- #define UARTE_INTEN_CTS_Enabled (1UL)
- #define UARTE_INTENSET_TXSTOPPED_Pos (22UL)
- #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos)
- #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL)
- #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL)
- #define UARTE_INTENSET_TXSTOPPED_Set (1UL)
- #define UARTE_INTENSET_TXSTARTED_Pos (20UL)
- #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos)
- #define UARTE_INTENSET_TXSTARTED_Disabled (0UL)
- #define UARTE_INTENSET_TXSTARTED_Enabled (1UL)
- #define UARTE_INTENSET_TXSTARTED_Set (1UL)
- #define UARTE_INTENSET_RXSTARTED_Pos (19UL)
- #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos)
- #define UARTE_INTENSET_RXSTARTED_Disabled (0UL)
- #define UARTE_INTENSET_RXSTARTED_Enabled (1UL)
- #define UARTE_INTENSET_RXSTARTED_Set (1UL)
- #define UARTE_INTENSET_RXTO_Pos (17UL)
- #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos)
- #define UARTE_INTENSET_RXTO_Disabled (0UL)
- #define UARTE_INTENSET_RXTO_Enabled (1UL)
- #define UARTE_INTENSET_RXTO_Set (1UL)
- #define UARTE_INTENSET_ERROR_Pos (9UL)
- #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos)
- #define UARTE_INTENSET_ERROR_Disabled (0UL)
- #define UARTE_INTENSET_ERROR_Enabled (1UL)
- #define UARTE_INTENSET_ERROR_Set (1UL)
- #define UARTE_INTENSET_ENDTX_Pos (8UL)
- #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos)
- #define UARTE_INTENSET_ENDTX_Disabled (0UL)
- #define UARTE_INTENSET_ENDTX_Enabled (1UL)
- #define UARTE_INTENSET_ENDTX_Set (1UL)
- #define UARTE_INTENSET_TXDRDY_Pos (7UL)
- #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos)
- #define UARTE_INTENSET_TXDRDY_Disabled (0UL)
- #define UARTE_INTENSET_TXDRDY_Enabled (1UL)
- #define UARTE_INTENSET_TXDRDY_Set (1UL)
- #define UARTE_INTENSET_ENDRX_Pos (4UL)
- #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos)
- #define UARTE_INTENSET_ENDRX_Disabled (0UL)
- #define UARTE_INTENSET_ENDRX_Enabled (1UL)
- #define UARTE_INTENSET_ENDRX_Set (1UL)
- #define UARTE_INTENSET_RXDRDY_Pos (2UL)
- #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos)
- #define UARTE_INTENSET_RXDRDY_Disabled (0UL)
- #define UARTE_INTENSET_RXDRDY_Enabled (1UL)
- #define UARTE_INTENSET_RXDRDY_Set (1UL)
- #define UARTE_INTENSET_NCTS_Pos (1UL)
- #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos)
- #define UARTE_INTENSET_NCTS_Disabled (0UL)
- #define UARTE_INTENSET_NCTS_Enabled (1UL)
- #define UARTE_INTENSET_NCTS_Set (1UL)
- #define UARTE_INTENSET_CTS_Pos (0UL)
- #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos)
- #define UARTE_INTENSET_CTS_Disabled (0UL)
- #define UARTE_INTENSET_CTS_Enabled (1UL)
- #define UARTE_INTENSET_CTS_Set (1UL)
- #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL)
- #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos)
- #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL)
- #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL)
- #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL)
- #define UARTE_INTENCLR_TXSTARTED_Pos (20UL)
- #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos)
- #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL)
- #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL)
- #define UARTE_INTENCLR_TXSTARTED_Clear (1UL)
- #define UARTE_INTENCLR_RXSTARTED_Pos (19UL)
- #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos)
- #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL)
- #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL)
- #define UARTE_INTENCLR_RXSTARTED_Clear (1UL)
- #define UARTE_INTENCLR_RXTO_Pos (17UL)
- #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos)
- #define UARTE_INTENCLR_RXTO_Disabled (0UL)
- #define UARTE_INTENCLR_RXTO_Enabled (1UL)
- #define UARTE_INTENCLR_RXTO_Clear (1UL)
- #define UARTE_INTENCLR_ERROR_Pos (9UL)
- #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos)
- #define UARTE_INTENCLR_ERROR_Disabled (0UL)
- #define UARTE_INTENCLR_ERROR_Enabled (1UL)
- #define UARTE_INTENCLR_ERROR_Clear (1UL)
- #define UARTE_INTENCLR_ENDTX_Pos (8UL)
- #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos)
- #define UARTE_INTENCLR_ENDTX_Disabled (0UL)
- #define UARTE_INTENCLR_ENDTX_Enabled (1UL)
- #define UARTE_INTENCLR_ENDTX_Clear (1UL)
- #define UARTE_INTENCLR_TXDRDY_Pos (7UL)
- #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos)
- #define UARTE_INTENCLR_TXDRDY_Disabled (0UL)
- #define UARTE_INTENCLR_TXDRDY_Enabled (1UL)
- #define UARTE_INTENCLR_TXDRDY_Clear (1UL)
- #define UARTE_INTENCLR_ENDRX_Pos (4UL)
- #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos)
- #define UARTE_INTENCLR_ENDRX_Disabled (0UL)
- #define UARTE_INTENCLR_ENDRX_Enabled (1UL)
- #define UARTE_INTENCLR_ENDRX_Clear (1UL)
- #define UARTE_INTENCLR_RXDRDY_Pos (2UL)
- #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos)
- #define UARTE_INTENCLR_RXDRDY_Disabled (0UL)
- #define UARTE_INTENCLR_RXDRDY_Enabled (1UL)
- #define UARTE_INTENCLR_RXDRDY_Clear (1UL)
- #define UARTE_INTENCLR_NCTS_Pos (1UL)
- #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos)
- #define UARTE_INTENCLR_NCTS_Disabled (0UL)
- #define UARTE_INTENCLR_NCTS_Enabled (1UL)
- #define UARTE_INTENCLR_NCTS_Clear (1UL)
- #define UARTE_INTENCLR_CTS_Pos (0UL)
- #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos)
- #define UARTE_INTENCLR_CTS_Disabled (0UL)
- #define UARTE_INTENCLR_CTS_Enabled (1UL)
- #define UARTE_INTENCLR_CTS_Clear (1UL)
- #define UARTE_ERRORSRC_BREAK_Pos (3UL)
- #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos)
- #define UARTE_ERRORSRC_BREAK_NotPresent (0UL)
- #define UARTE_ERRORSRC_BREAK_Present (1UL)
- #define UARTE_ERRORSRC_FRAMING_Pos (2UL)
- #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos)
- #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL)
- #define UARTE_ERRORSRC_FRAMING_Present (1UL)
- #define UARTE_ERRORSRC_PARITY_Pos (1UL)
- #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos)
- #define UARTE_ERRORSRC_PARITY_NotPresent (0UL)
- #define UARTE_ERRORSRC_PARITY_Present (1UL)
- #define UARTE_ERRORSRC_OVERRUN_Pos (0UL)
- #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos)
- #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL)
- #define UARTE_ERRORSRC_OVERRUN_Present (1UL)
- #define UARTE_ENABLE_ENABLE_Pos (0UL)
- #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos)
- #define UARTE_ENABLE_ENABLE_Disabled (0UL)
- #define UARTE_ENABLE_ENABLE_Enabled (8UL)
- #define UARTE_PSEL_RTS_CONNECT_Pos (31UL)
- #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos)
- #define UARTE_PSEL_RTS_CONNECT_Connected (0UL)
- #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL)
- #define UARTE_PSEL_RTS_PORT_Pos (5UL)
- #define UARTE_PSEL_RTS_PORT_Msk (0x1UL << UARTE_PSEL_RTS_PORT_Pos)
- #define UARTE_PSEL_RTS_PIN_Pos (0UL)
- #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos)
- #define UARTE_PSEL_TXD_CONNECT_Pos (31UL)
- #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos)
- #define UARTE_PSEL_TXD_CONNECT_Connected (0UL)
- #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL)
- #define UARTE_PSEL_TXD_PORT_Pos (5UL)
- #define UARTE_PSEL_TXD_PORT_Msk (0x1UL << UARTE_PSEL_TXD_PORT_Pos)
- #define UARTE_PSEL_TXD_PIN_Pos (0UL)
- #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos)
- #define UARTE_PSEL_CTS_CONNECT_Pos (31UL)
- #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos)
- #define UARTE_PSEL_CTS_CONNECT_Connected (0UL)
- #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL)
- #define UARTE_PSEL_CTS_PORT_Pos (5UL)
- #define UARTE_PSEL_CTS_PORT_Msk (0x1UL << UARTE_PSEL_CTS_PORT_Pos)
- #define UARTE_PSEL_CTS_PIN_Pos (0UL)
- #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos)
- #define UARTE_PSEL_RXD_CONNECT_Pos (31UL)
- #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos)
- #define UARTE_PSEL_RXD_CONNECT_Connected (0UL)
- #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL)
- #define UARTE_PSEL_RXD_PORT_Pos (5UL)
- #define UARTE_PSEL_RXD_PORT_Msk (0x1UL << UARTE_PSEL_RXD_PORT_Pos)
- #define UARTE_PSEL_RXD_PIN_Pos (0UL)
- #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos)
- #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL)
- #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos)
- #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL)
- #define UARTE_RXD_PTR_PTR_Pos (0UL)
- #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos)
- #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL)
- #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos)
- #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL)
- #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos)
- #define UARTE_TXD_PTR_PTR_Pos (0UL)
- #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos)
- #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL)
- #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos)
- #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL)
- #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos)
- #define UARTE_CONFIG_PARITYTYPE_Pos (8UL)
- #define UARTE_CONFIG_PARITYTYPE_Msk (0x1UL << UARTE_CONFIG_PARITYTYPE_Pos)
- #define UARTE_CONFIG_PARITYTYPE_Even (0UL)
- #define UARTE_CONFIG_PARITYTYPE_Odd (1UL)
- #define UARTE_CONFIG_STOP_Pos (4UL)
- #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos)
- #define UARTE_CONFIG_STOP_One (0UL)
- #define UARTE_CONFIG_STOP_Two (1UL)
- #define UARTE_CONFIG_PARITY_Pos (1UL)
- #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos)
- #define UARTE_CONFIG_PARITY_Excluded (0x0UL)
- #define UARTE_CONFIG_PARITY_Included (0x7UL)
- #define UARTE_CONFIG_HWFC_Pos (0UL)
- #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos)
- #define UARTE_CONFIG_HWFC_Disabled (0UL)
- #define UARTE_CONFIG_HWFC_Enabled (1UL)
- #define UICR_APPROTECT_PALL_Pos (0UL)
- #define UICR_APPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_APPROTECT_PALL_Pos)
- #define UICR_APPROTECT_PALL_Protected (0x00000000UL)
- #define UICR_APPROTECT_PALL_Unprotected (0xFFFFFFFFUL)
- #define UICR_EXTSUPPLY_EXTSUPPLY_Pos (0UL)
- #define UICR_EXTSUPPLY_EXTSUPPLY_Msk (0x1UL << UICR_EXTSUPPLY_EXTSUPPLY_Pos)
- #define UICR_EXTSUPPLY_EXTSUPPLY_Enabled (0UL)
- #define UICR_EXTSUPPLY_EXTSUPPLY_Disabled (1UL)
- #define UICR_VREGHVOUT_VREGHVOUT_Pos (0UL)
- #define UICR_VREGHVOUT_VREGHVOUT_Msk (0x7UL << UICR_VREGHVOUT_VREGHVOUT_Pos)
- #define UICR_VREGHVOUT_VREGHVOUT_1V8 (0UL)
- #define UICR_VREGHVOUT_VREGHVOUT_2V1 (1UL)
- #define UICR_VREGHVOUT_VREGHVOUT_2V4 (2UL)
- #define UICR_VREGHVOUT_VREGHVOUT_2V7 (3UL)
- #define UICR_VREGHVOUT_VREGHVOUT_3V0 (4UL)
- #define UICR_VREGHVOUT_VREGHVOUT_3V3 (5UL)
- #define UICR_VREGHVOUT_VREGHVOUT_DEFAULT (7UL)
- #define UICR_HFXOCNT_HFXOCNT_Pos (0UL)
- #define UICR_HFXOCNT_HFXOCNT_Msk (0xFFUL << UICR_HFXOCNT_HFXOCNT_Pos)
- #define UICR_HFXOCNT_HFXOCNT_MinDebounceTime (0UL)
- #define UICR_HFXOCNT_HFXOCNT_MaxDebounceTime (254UL)
- #define UICR_HFXOCNT_HFXOCNT_DefaultDebounceTime (255UL)
- #define UICR_SECUREAPPROTECT_PALL_Pos (0UL)
- #define UICR_SECUREAPPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_SECUREAPPROTECT_PALL_Pos)
- #define UICR_SECUREAPPROTECT_PALL_Protected (0x00000000UL)
- #define UICR_SECUREAPPROTECT_PALL_Unprotected (0xFFFFFFFFUL)
- #define UICR_ERASEPROTECT_PALL_Pos (0UL)
- #define UICR_ERASEPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_ERASEPROTECT_PALL_Pos)
- #define UICR_ERASEPROTECT_PALL_Protected (0x00000000UL)
- #define UICR_ERASEPROTECT_PALL_Unprotected (0xFFFFFFFFUL)
- #define UICR_TINSTANCE_TINSTANCE_Pos (28UL)
- #define UICR_TINSTANCE_TINSTANCE_Msk (0xFUL << UICR_TINSTANCE_TINSTANCE_Pos)
- #define UICR_NFCPINS_PROTECT_Pos (0UL)
- #define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos)
- #define UICR_NFCPINS_PROTECT_Disabled (0UL)
- #define UICR_NFCPINS_PROTECT_NFC (1UL)
- #define UICR_OTP_UPPER_Pos (16UL)
- #define UICR_OTP_UPPER_Msk (0xFFFFUL << UICR_OTP_UPPER_Pos)
- #define UICR_OTP_LOWER_Pos (0UL)
- #define UICR_OTP_LOWER_Msk (0xFFFFUL << UICR_OTP_LOWER_Pos)
- #define UICR_KEYSLOT_CONFIG_DEST_DEST_Pos (0UL)
- #define UICR_KEYSLOT_CONFIG_DEST_DEST_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_CONFIG_DEST_DEST_Pos)
- #define UICR_KEYSLOT_CONFIG_PERM_STATE_Pos (16UL)
- #define UICR_KEYSLOT_CONFIG_PERM_STATE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_STATE_Pos)
- #define UICR_KEYSLOT_CONFIG_PERM_STATE_Revoked (0UL)
- #define UICR_KEYSLOT_CONFIG_PERM_STATE_Active (1UL)
- #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos (2UL)
- #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos)
- #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Disabled (0UL)
- #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Enabled (1UL)
- #define UICR_KEYSLOT_CONFIG_PERM_READ_Pos (1UL)
- #define UICR_KEYSLOT_CONFIG_PERM_READ_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_READ_Pos)
- #define UICR_KEYSLOT_CONFIG_PERM_READ_Disabled (0UL)
- #define UICR_KEYSLOT_CONFIG_PERM_READ_Enabled (1UL)
- #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos (0UL)
- #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos)
- #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Disabled (0UL)
- #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Enabled (1UL)
- #define UICR_KEYSLOT_KEY_VALUE_VALUE_Pos (0UL)
- #define UICR_KEYSLOT_KEY_VALUE_VALUE_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_KEY_VALUE_VALUE_Pos)
- #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos (0UL)
- #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Msk (0x1UL << USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos)
- #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Trigger (1UL)
- #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos (0UL)
- #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Msk (0x1UL << USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos)
- #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Trigger (1UL)
- #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos (0UL)
- #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Msk (0x1UL << USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos)
- #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Trigger (1UL)
- #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos (0UL)
- #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Msk (0x1UL << USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos)
- #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Trigger (1UL)
- #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos (0UL)
- #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Msk (0x1UL << USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos)
- #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Trigger (1UL)
- #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos (0UL)
- #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Msk (0x1UL << USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos)
- #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger (1UL)
- #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos (0UL)
- #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Msk (0x1UL << USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos)
- #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Trigger (1UL)
- #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos (0UL)
- #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Msk (0x1UL << USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos)
- #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Trigger (1UL)
- #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos (0UL)
- #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Msk (0x1UL << USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos)
- #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Trigger (1UL)
- #define USBD_SUBSCRIBE_STARTEPIN_EN_Pos (31UL)
- #define USBD_SUBSCRIBE_STARTEPIN_EN_Msk (0x1UL << USBD_SUBSCRIBE_STARTEPIN_EN_Pos)
- #define USBD_SUBSCRIBE_STARTEPIN_EN_Disabled (0UL)
- #define USBD_SUBSCRIBE_STARTEPIN_EN_Enabled (1UL)
- #define USBD_SUBSCRIBE_STARTEPIN_CHIDX_Pos (0UL)
- #define USBD_SUBSCRIBE_STARTEPIN_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_STARTEPIN_CHIDX_Pos)
- #define USBD_SUBSCRIBE_STARTISOIN_EN_Pos (31UL)
- #define USBD_SUBSCRIBE_STARTISOIN_EN_Msk (0x1UL << USBD_SUBSCRIBE_STARTISOIN_EN_Pos)
- #define USBD_SUBSCRIBE_STARTISOIN_EN_Disabled (0UL)
- #define USBD_SUBSCRIBE_STARTISOIN_EN_Enabled (1UL)
- #define USBD_SUBSCRIBE_STARTISOIN_CHIDX_Pos (0UL)
- #define USBD_SUBSCRIBE_STARTISOIN_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_STARTISOIN_CHIDX_Pos)
- #define USBD_SUBSCRIBE_STARTEPOUT_EN_Pos (31UL)
- #define USBD_SUBSCRIBE_STARTEPOUT_EN_Msk (0x1UL << USBD_SUBSCRIBE_STARTEPOUT_EN_Pos)
- #define USBD_SUBSCRIBE_STARTEPOUT_EN_Disabled (0UL)
- #define USBD_SUBSCRIBE_STARTEPOUT_EN_Enabled (1UL)
- #define USBD_SUBSCRIBE_STARTEPOUT_CHIDX_Pos (0UL)
- #define USBD_SUBSCRIBE_STARTEPOUT_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_STARTEPOUT_CHIDX_Pos)
- #define USBD_SUBSCRIBE_STARTISOOUT_EN_Pos (31UL)
- #define USBD_SUBSCRIBE_STARTISOOUT_EN_Msk (0x1UL << USBD_SUBSCRIBE_STARTISOOUT_EN_Pos)
- #define USBD_SUBSCRIBE_STARTISOOUT_EN_Disabled (0UL)
- #define USBD_SUBSCRIBE_STARTISOOUT_EN_Enabled (1UL)
- #define USBD_SUBSCRIBE_STARTISOOUT_CHIDX_Pos (0UL)
- #define USBD_SUBSCRIBE_STARTISOOUT_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_STARTISOOUT_CHIDX_Pos)
- #define USBD_SUBSCRIBE_EP0RCVOUT_EN_Pos (31UL)
- #define USBD_SUBSCRIBE_EP0RCVOUT_EN_Msk (0x1UL << USBD_SUBSCRIBE_EP0RCVOUT_EN_Pos)
- #define USBD_SUBSCRIBE_EP0RCVOUT_EN_Disabled (0UL)
- #define USBD_SUBSCRIBE_EP0RCVOUT_EN_Enabled (1UL)
- #define USBD_SUBSCRIBE_EP0RCVOUT_CHIDX_Pos (0UL)
- #define USBD_SUBSCRIBE_EP0RCVOUT_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_EP0RCVOUT_CHIDX_Pos)
- #define USBD_SUBSCRIBE_EP0STATUS_EN_Pos (31UL)
- #define USBD_SUBSCRIBE_EP0STATUS_EN_Msk (0x1UL << USBD_SUBSCRIBE_EP0STATUS_EN_Pos)
- #define USBD_SUBSCRIBE_EP0STATUS_EN_Disabled (0UL)
- #define USBD_SUBSCRIBE_EP0STATUS_EN_Enabled (1UL)
- #define USBD_SUBSCRIBE_EP0STATUS_CHIDX_Pos (0UL)
- #define USBD_SUBSCRIBE_EP0STATUS_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_EP0STATUS_CHIDX_Pos)
- #define USBD_SUBSCRIBE_EP0STALL_EN_Pos (31UL)
- #define USBD_SUBSCRIBE_EP0STALL_EN_Msk (0x1UL << USBD_SUBSCRIBE_EP0STALL_EN_Pos)
- #define USBD_SUBSCRIBE_EP0STALL_EN_Disabled (0UL)
- #define USBD_SUBSCRIBE_EP0STALL_EN_Enabled (1UL)
- #define USBD_SUBSCRIBE_EP0STALL_CHIDX_Pos (0UL)
- #define USBD_SUBSCRIBE_EP0STALL_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_EP0STALL_CHIDX_Pos)
- #define USBD_SUBSCRIBE_DPDMDRIVE_EN_Pos (31UL)
- #define USBD_SUBSCRIBE_DPDMDRIVE_EN_Msk (0x1UL << USBD_SUBSCRIBE_DPDMDRIVE_EN_Pos)
- #define USBD_SUBSCRIBE_DPDMDRIVE_EN_Disabled (0UL)
- #define USBD_SUBSCRIBE_DPDMDRIVE_EN_Enabled (1UL)
- #define USBD_SUBSCRIBE_DPDMDRIVE_CHIDX_Pos (0UL)
- #define USBD_SUBSCRIBE_DPDMDRIVE_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_DPDMDRIVE_CHIDX_Pos)
- #define USBD_SUBSCRIBE_DPDMNODRIVE_EN_Pos (31UL)
- #define USBD_SUBSCRIBE_DPDMNODRIVE_EN_Msk (0x1UL << USBD_SUBSCRIBE_DPDMNODRIVE_EN_Pos)
- #define USBD_SUBSCRIBE_DPDMNODRIVE_EN_Disabled (0UL)
- #define USBD_SUBSCRIBE_DPDMNODRIVE_EN_Enabled (1UL)
- #define USBD_SUBSCRIBE_DPDMNODRIVE_CHIDX_Pos (0UL)
- #define USBD_SUBSCRIBE_DPDMNODRIVE_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_DPDMNODRIVE_CHIDX_Pos)
- #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos (0UL)
- #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Msk (0x1UL << USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos)
- #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_NotGenerated (0UL)
- #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Generated (1UL)
- #define USBD_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL)
- #define USBD_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << USBD_EVENTS_STARTED_EVENTS_STARTED_Pos)
- #define USBD_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL)
- #define USBD_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL)
- #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos (0UL)
- #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Msk (0x1UL << USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos)
- #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_NotGenerated (0UL)
- #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Generated (1UL)
- #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos (0UL)
- #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Msk (0x1UL << USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos)
- #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_NotGenerated (0UL)
- #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Generated (1UL)
- #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos (0UL)
- #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Msk (0x1UL << USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos)
- #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_NotGenerated (0UL)
- #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Generated (1UL)
- #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos (0UL)
- #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Msk (0x1UL << USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos)
- #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_NotGenerated (0UL)
- #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Generated (1UL)
- #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos (0UL)
- #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Msk (0x1UL << USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos)
- #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_NotGenerated (0UL)
- #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Generated (1UL)
- #define USBD_EVENTS_SOF_EVENTS_SOF_Pos (0UL)
- #define USBD_EVENTS_SOF_EVENTS_SOF_Msk (0x1UL << USBD_EVENTS_SOF_EVENTS_SOF_Pos)
- #define USBD_EVENTS_SOF_EVENTS_SOF_NotGenerated (0UL)
- #define USBD_EVENTS_SOF_EVENTS_SOF_Generated (1UL)
- #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos (0UL)
- #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Msk (0x1UL << USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos)
- #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_NotGenerated (0UL)
- #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Generated (1UL)
- #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos (0UL)
- #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Msk (0x1UL << USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos)
- #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_NotGenerated (0UL)
- #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Generated (1UL)
- #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos (0UL)
- #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Msk (0x1UL << USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos)
- #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_NotGenerated (0UL)
- #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Generated (1UL)
- #define USBD_PUBLISH_USBRESET_EN_Pos (31UL)
- #define USBD_PUBLISH_USBRESET_EN_Msk (0x1UL << USBD_PUBLISH_USBRESET_EN_Pos)
- #define USBD_PUBLISH_USBRESET_EN_Disabled (0UL)
- #define USBD_PUBLISH_USBRESET_EN_Enabled (1UL)
- #define USBD_PUBLISH_USBRESET_CHIDX_Pos (0UL)
- #define USBD_PUBLISH_USBRESET_CHIDX_Msk (0xFFUL << USBD_PUBLISH_USBRESET_CHIDX_Pos)
- #define USBD_PUBLISH_STARTED_EN_Pos (31UL)
- #define USBD_PUBLISH_STARTED_EN_Msk (0x1UL << USBD_PUBLISH_STARTED_EN_Pos)
- #define USBD_PUBLISH_STARTED_EN_Disabled (0UL)
- #define USBD_PUBLISH_STARTED_EN_Enabled (1UL)
- #define USBD_PUBLISH_STARTED_CHIDX_Pos (0UL)
- #define USBD_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << USBD_PUBLISH_STARTED_CHIDX_Pos)
- #define USBD_PUBLISH_ENDEPIN_EN_Pos (31UL)
- #define USBD_PUBLISH_ENDEPIN_EN_Msk (0x1UL << USBD_PUBLISH_ENDEPIN_EN_Pos)
- #define USBD_PUBLISH_ENDEPIN_EN_Disabled (0UL)
- #define USBD_PUBLISH_ENDEPIN_EN_Enabled (1UL)
- #define USBD_PUBLISH_ENDEPIN_CHIDX_Pos (0UL)
- #define USBD_PUBLISH_ENDEPIN_CHIDX_Msk (0xFFUL << USBD_PUBLISH_ENDEPIN_CHIDX_Pos)
- #define USBD_PUBLISH_EP0DATADONE_EN_Pos (31UL)
- #define USBD_PUBLISH_EP0DATADONE_EN_Msk (0x1UL << USBD_PUBLISH_EP0DATADONE_EN_Pos)
- #define USBD_PUBLISH_EP0DATADONE_EN_Disabled (0UL)
- #define USBD_PUBLISH_EP0DATADONE_EN_Enabled (1UL)
- #define USBD_PUBLISH_EP0DATADONE_CHIDX_Pos (0UL)
- #define USBD_PUBLISH_EP0DATADONE_CHIDX_Msk (0xFFUL << USBD_PUBLISH_EP0DATADONE_CHIDX_Pos)
- #define USBD_PUBLISH_ENDISOIN_EN_Pos (31UL)
- #define USBD_PUBLISH_ENDISOIN_EN_Msk (0x1UL << USBD_PUBLISH_ENDISOIN_EN_Pos)
- #define USBD_PUBLISH_ENDISOIN_EN_Disabled (0UL)
- #define USBD_PUBLISH_ENDISOIN_EN_Enabled (1UL)
- #define USBD_PUBLISH_ENDISOIN_CHIDX_Pos (0UL)
- #define USBD_PUBLISH_ENDISOIN_CHIDX_Msk (0xFFUL << USBD_PUBLISH_ENDISOIN_CHIDX_Pos)
- #define USBD_PUBLISH_ENDEPOUT_EN_Pos (31UL)
- #define USBD_PUBLISH_ENDEPOUT_EN_Msk (0x1UL << USBD_PUBLISH_ENDEPOUT_EN_Pos)
- #define USBD_PUBLISH_ENDEPOUT_EN_Disabled (0UL)
- #define USBD_PUBLISH_ENDEPOUT_EN_Enabled (1UL)
- #define USBD_PUBLISH_ENDEPOUT_CHIDX_Pos (0UL)
- #define USBD_PUBLISH_ENDEPOUT_CHIDX_Msk (0xFFUL << USBD_PUBLISH_ENDEPOUT_CHIDX_Pos)
- #define USBD_PUBLISH_ENDISOOUT_EN_Pos (31UL)
- #define USBD_PUBLISH_ENDISOOUT_EN_Msk (0x1UL << USBD_PUBLISH_ENDISOOUT_EN_Pos)
- #define USBD_PUBLISH_ENDISOOUT_EN_Disabled (0UL)
- #define USBD_PUBLISH_ENDISOOUT_EN_Enabled (1UL)
- #define USBD_PUBLISH_ENDISOOUT_CHIDX_Pos (0UL)
- #define USBD_PUBLISH_ENDISOOUT_CHIDX_Msk (0xFFUL << USBD_PUBLISH_ENDISOOUT_CHIDX_Pos)
- #define USBD_PUBLISH_SOF_EN_Pos (31UL)
- #define USBD_PUBLISH_SOF_EN_Msk (0x1UL << USBD_PUBLISH_SOF_EN_Pos)
- #define USBD_PUBLISH_SOF_EN_Disabled (0UL)
- #define USBD_PUBLISH_SOF_EN_Enabled (1UL)
- #define USBD_PUBLISH_SOF_CHIDX_Pos (0UL)
- #define USBD_PUBLISH_SOF_CHIDX_Msk (0xFFUL << USBD_PUBLISH_SOF_CHIDX_Pos)
- #define USBD_PUBLISH_USBEVENT_EN_Pos (31UL)
- #define USBD_PUBLISH_USBEVENT_EN_Msk (0x1UL << USBD_PUBLISH_USBEVENT_EN_Pos)
- #define USBD_PUBLISH_USBEVENT_EN_Disabled (0UL)
- #define USBD_PUBLISH_USBEVENT_EN_Enabled (1UL)
- #define USBD_PUBLISH_USBEVENT_CHIDX_Pos (0UL)
- #define USBD_PUBLISH_USBEVENT_CHIDX_Msk (0xFFUL << USBD_PUBLISH_USBEVENT_CHIDX_Pos)
- #define USBD_PUBLISH_EP0SETUP_EN_Pos (31UL)
- #define USBD_PUBLISH_EP0SETUP_EN_Msk (0x1UL << USBD_PUBLISH_EP0SETUP_EN_Pos)
- #define USBD_PUBLISH_EP0SETUP_EN_Disabled (0UL)
- #define USBD_PUBLISH_EP0SETUP_EN_Enabled (1UL)
- #define USBD_PUBLISH_EP0SETUP_CHIDX_Pos (0UL)
- #define USBD_PUBLISH_EP0SETUP_CHIDX_Msk (0xFFUL << USBD_PUBLISH_EP0SETUP_CHIDX_Pos)
- #define USBD_PUBLISH_EPDATA_EN_Pos (31UL)
- #define USBD_PUBLISH_EPDATA_EN_Msk (0x1UL << USBD_PUBLISH_EPDATA_EN_Pos)
- #define USBD_PUBLISH_EPDATA_EN_Disabled (0UL)
- #define USBD_PUBLISH_EPDATA_EN_Enabled (1UL)
- #define USBD_PUBLISH_EPDATA_CHIDX_Pos (0UL)
- #define USBD_PUBLISH_EPDATA_CHIDX_Msk (0xFFUL << USBD_PUBLISH_EPDATA_CHIDX_Pos)
- #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos (4UL)
- #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos)
- #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Disabled (0UL)
- #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Enabled (1UL)
- #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos (3UL)
- #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos)
- #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Disabled (0UL)
- #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Enabled (1UL)
- #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos (2UL)
- #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos)
- #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Disabled (0UL)
- #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Enabled (1UL)
- #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos (1UL)
- #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos)
- #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Disabled (0UL)
- #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Enabled (1UL)
- #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos (0UL)
- #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos)
- #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Disabled (0UL)
- #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Enabled (1UL)
- #define USBD_INTEN_EPDATA_Pos (24UL)
- #define USBD_INTEN_EPDATA_Msk (0x1UL << USBD_INTEN_EPDATA_Pos)
- #define USBD_INTEN_EPDATA_Disabled (0UL)
- #define USBD_INTEN_EPDATA_Enabled (1UL)
- #define USBD_INTEN_EP0SETUP_Pos (23UL)
- #define USBD_INTEN_EP0SETUP_Msk (0x1UL << USBD_INTEN_EP0SETUP_Pos)
- #define USBD_INTEN_EP0SETUP_Disabled (0UL)
- #define USBD_INTEN_EP0SETUP_Enabled (1UL)
- #define USBD_INTEN_USBEVENT_Pos (22UL)
- #define USBD_INTEN_USBEVENT_Msk (0x1UL << USBD_INTEN_USBEVENT_Pos)
- #define USBD_INTEN_USBEVENT_Disabled (0UL)
- #define USBD_INTEN_USBEVENT_Enabled (1UL)
- #define USBD_INTEN_SOF_Pos (21UL)
- #define USBD_INTEN_SOF_Msk (0x1UL << USBD_INTEN_SOF_Pos)
- #define USBD_INTEN_SOF_Disabled (0UL)
- #define USBD_INTEN_SOF_Enabled (1UL)
- #define USBD_INTEN_ENDISOOUT_Pos (20UL)
- #define USBD_INTEN_ENDISOOUT_Msk (0x1UL << USBD_INTEN_ENDISOOUT_Pos)
- #define USBD_INTEN_ENDISOOUT_Disabled (0UL)
- #define USBD_INTEN_ENDISOOUT_Enabled (1UL)
- #define USBD_INTEN_ENDEPOUT7_Pos (19UL)
- #define USBD_INTEN_ENDEPOUT7_Msk (0x1UL << USBD_INTEN_ENDEPOUT7_Pos)
- #define USBD_INTEN_ENDEPOUT7_Disabled (0UL)
- #define USBD_INTEN_ENDEPOUT7_Enabled (1UL)
- #define USBD_INTEN_ENDEPOUT6_Pos (18UL)
- #define USBD_INTEN_ENDEPOUT6_Msk (0x1UL << USBD_INTEN_ENDEPOUT6_Pos)
- #define USBD_INTEN_ENDEPOUT6_Disabled (0UL)
- #define USBD_INTEN_ENDEPOUT6_Enabled (1UL)
- #define USBD_INTEN_ENDEPOUT5_Pos (17UL)
- #define USBD_INTEN_ENDEPOUT5_Msk (0x1UL << USBD_INTEN_ENDEPOUT5_Pos)
- #define USBD_INTEN_ENDEPOUT5_Disabled (0UL)
- #define USBD_INTEN_ENDEPOUT5_Enabled (1UL)
- #define USBD_INTEN_ENDEPOUT4_Pos (16UL)
- #define USBD_INTEN_ENDEPOUT4_Msk (0x1UL << USBD_INTEN_ENDEPOUT4_Pos)
- #define USBD_INTEN_ENDEPOUT4_Disabled (0UL)
- #define USBD_INTEN_ENDEPOUT4_Enabled (1UL)
- #define USBD_INTEN_ENDEPOUT3_Pos (15UL)
- #define USBD_INTEN_ENDEPOUT3_Msk (0x1UL << USBD_INTEN_ENDEPOUT3_Pos)
- #define USBD_INTEN_ENDEPOUT3_Disabled (0UL)
- #define USBD_INTEN_ENDEPOUT3_Enabled (1UL)
- #define USBD_INTEN_ENDEPOUT2_Pos (14UL)
- #define USBD_INTEN_ENDEPOUT2_Msk (0x1UL << USBD_INTEN_ENDEPOUT2_Pos)
- #define USBD_INTEN_ENDEPOUT2_Disabled (0UL)
- #define USBD_INTEN_ENDEPOUT2_Enabled (1UL)
- #define USBD_INTEN_ENDEPOUT1_Pos (13UL)
- #define USBD_INTEN_ENDEPOUT1_Msk (0x1UL << USBD_INTEN_ENDEPOUT1_Pos)
- #define USBD_INTEN_ENDEPOUT1_Disabled (0UL)
- #define USBD_INTEN_ENDEPOUT1_Enabled (1UL)
- #define USBD_INTEN_ENDEPOUT0_Pos (12UL)
- #define USBD_INTEN_ENDEPOUT0_Msk (0x1UL << USBD_INTEN_ENDEPOUT0_Pos)
- #define USBD_INTEN_ENDEPOUT0_Disabled (0UL)
- #define USBD_INTEN_ENDEPOUT0_Enabled (1UL)
- #define USBD_INTEN_ENDISOIN_Pos (11UL)
- #define USBD_INTEN_ENDISOIN_Msk (0x1UL << USBD_INTEN_ENDISOIN_Pos)
- #define USBD_INTEN_ENDISOIN_Disabled (0UL)
- #define USBD_INTEN_ENDISOIN_Enabled (1UL)
- #define USBD_INTEN_EP0DATADONE_Pos (10UL)
- #define USBD_INTEN_EP0DATADONE_Msk (0x1UL << USBD_INTEN_EP0DATADONE_Pos)
- #define USBD_INTEN_EP0DATADONE_Disabled (0UL)
- #define USBD_INTEN_EP0DATADONE_Enabled (1UL)
- #define USBD_INTEN_ENDEPIN7_Pos (9UL)
- #define USBD_INTEN_ENDEPIN7_Msk (0x1UL << USBD_INTEN_ENDEPIN7_Pos)
- #define USBD_INTEN_ENDEPIN7_Disabled (0UL)
- #define USBD_INTEN_ENDEPIN7_Enabled (1UL)
- #define USBD_INTEN_ENDEPIN6_Pos (8UL)
- #define USBD_INTEN_ENDEPIN6_Msk (0x1UL << USBD_INTEN_ENDEPIN6_Pos)
- #define USBD_INTEN_ENDEPIN6_Disabled (0UL)
- #define USBD_INTEN_ENDEPIN6_Enabled (1UL)
- #define USBD_INTEN_ENDEPIN5_Pos (7UL)
- #define USBD_INTEN_ENDEPIN5_Msk (0x1UL << USBD_INTEN_ENDEPIN5_Pos)
- #define USBD_INTEN_ENDEPIN5_Disabled (0UL)
- #define USBD_INTEN_ENDEPIN5_Enabled (1UL)
- #define USBD_INTEN_ENDEPIN4_Pos (6UL)
- #define USBD_INTEN_ENDEPIN4_Msk (0x1UL << USBD_INTEN_ENDEPIN4_Pos)
- #define USBD_INTEN_ENDEPIN4_Disabled (0UL)
- #define USBD_INTEN_ENDEPIN4_Enabled (1UL)
- #define USBD_INTEN_ENDEPIN3_Pos (5UL)
- #define USBD_INTEN_ENDEPIN3_Msk (0x1UL << USBD_INTEN_ENDEPIN3_Pos)
- #define USBD_INTEN_ENDEPIN3_Disabled (0UL)
- #define USBD_INTEN_ENDEPIN3_Enabled (1UL)
- #define USBD_INTEN_ENDEPIN2_Pos (4UL)
- #define USBD_INTEN_ENDEPIN2_Msk (0x1UL << USBD_INTEN_ENDEPIN2_Pos)
- #define USBD_INTEN_ENDEPIN2_Disabled (0UL)
- #define USBD_INTEN_ENDEPIN2_Enabled (1UL)
- #define USBD_INTEN_ENDEPIN1_Pos (3UL)
- #define USBD_INTEN_ENDEPIN1_Msk (0x1UL << USBD_INTEN_ENDEPIN1_Pos)
- #define USBD_INTEN_ENDEPIN1_Disabled (0UL)
- #define USBD_INTEN_ENDEPIN1_Enabled (1UL)
- #define USBD_INTEN_ENDEPIN0_Pos (2UL)
- #define USBD_INTEN_ENDEPIN0_Msk (0x1UL << USBD_INTEN_ENDEPIN0_Pos)
- #define USBD_INTEN_ENDEPIN0_Disabled (0UL)
- #define USBD_INTEN_ENDEPIN0_Enabled (1UL)
- #define USBD_INTEN_STARTED_Pos (1UL)
- #define USBD_INTEN_STARTED_Msk (0x1UL << USBD_INTEN_STARTED_Pos)
- #define USBD_INTEN_STARTED_Disabled (0UL)
- #define USBD_INTEN_STARTED_Enabled (1UL)
- #define USBD_INTEN_USBRESET_Pos (0UL)
- #define USBD_INTEN_USBRESET_Msk (0x1UL << USBD_INTEN_USBRESET_Pos)
- #define USBD_INTEN_USBRESET_Disabled (0UL)
- #define USBD_INTEN_USBRESET_Enabled (1UL)
- #define USBD_INTENSET_EPDATA_Pos (24UL)
- #define USBD_INTENSET_EPDATA_Msk (0x1UL << USBD_INTENSET_EPDATA_Pos)
- #define USBD_INTENSET_EPDATA_Disabled (0UL)
- #define USBD_INTENSET_EPDATA_Enabled (1UL)
- #define USBD_INTENSET_EPDATA_Set (1UL)
- #define USBD_INTENSET_EP0SETUP_Pos (23UL)
- #define USBD_INTENSET_EP0SETUP_Msk (0x1UL << USBD_INTENSET_EP0SETUP_Pos)
- #define USBD_INTENSET_EP0SETUP_Disabled (0UL)
- #define USBD_INTENSET_EP0SETUP_Enabled (1UL)
- #define USBD_INTENSET_EP0SETUP_Set (1UL)
- #define USBD_INTENSET_USBEVENT_Pos (22UL)
- #define USBD_INTENSET_USBEVENT_Msk (0x1UL << USBD_INTENSET_USBEVENT_Pos)
- #define USBD_INTENSET_USBEVENT_Disabled (0UL)
- #define USBD_INTENSET_USBEVENT_Enabled (1UL)
- #define USBD_INTENSET_USBEVENT_Set (1UL)
- #define USBD_INTENSET_SOF_Pos (21UL)
- #define USBD_INTENSET_SOF_Msk (0x1UL << USBD_INTENSET_SOF_Pos)
- #define USBD_INTENSET_SOF_Disabled (0UL)
- #define USBD_INTENSET_SOF_Enabled (1UL)
- #define USBD_INTENSET_SOF_Set (1UL)
- #define USBD_INTENSET_ENDISOOUT_Pos (20UL)
- #define USBD_INTENSET_ENDISOOUT_Msk (0x1UL << USBD_INTENSET_ENDISOOUT_Pos)
- #define USBD_INTENSET_ENDISOOUT_Disabled (0UL)
- #define USBD_INTENSET_ENDISOOUT_Enabled (1UL)
- #define USBD_INTENSET_ENDISOOUT_Set (1UL)
- #define USBD_INTENSET_ENDEPOUT7_Pos (19UL)
- #define USBD_INTENSET_ENDEPOUT7_Msk (0x1UL << USBD_INTENSET_ENDEPOUT7_Pos)
- #define USBD_INTENSET_ENDEPOUT7_Disabled (0UL)
- #define USBD_INTENSET_ENDEPOUT7_Enabled (1UL)
- #define USBD_INTENSET_ENDEPOUT7_Set (1UL)
- #define USBD_INTENSET_ENDEPOUT6_Pos (18UL)
- #define USBD_INTENSET_ENDEPOUT6_Msk (0x1UL << USBD_INTENSET_ENDEPOUT6_Pos)
- #define USBD_INTENSET_ENDEPOUT6_Disabled (0UL)
- #define USBD_INTENSET_ENDEPOUT6_Enabled (1UL)
- #define USBD_INTENSET_ENDEPOUT6_Set (1UL)
- #define USBD_INTENSET_ENDEPOUT5_Pos (17UL)
- #define USBD_INTENSET_ENDEPOUT5_Msk (0x1UL << USBD_INTENSET_ENDEPOUT5_Pos)
- #define USBD_INTENSET_ENDEPOUT5_Disabled (0UL)
- #define USBD_INTENSET_ENDEPOUT5_Enabled (1UL)
- #define USBD_INTENSET_ENDEPOUT5_Set (1UL)
- #define USBD_INTENSET_ENDEPOUT4_Pos (16UL)
- #define USBD_INTENSET_ENDEPOUT4_Msk (0x1UL << USBD_INTENSET_ENDEPOUT4_Pos)
- #define USBD_INTENSET_ENDEPOUT4_Disabled (0UL)
- #define USBD_INTENSET_ENDEPOUT4_Enabled (1UL)
- #define USBD_INTENSET_ENDEPOUT4_Set (1UL)
- #define USBD_INTENSET_ENDEPOUT3_Pos (15UL)
- #define USBD_INTENSET_ENDEPOUT3_Msk (0x1UL << USBD_INTENSET_ENDEPOUT3_Pos)
- #define USBD_INTENSET_ENDEPOUT3_Disabled (0UL)
- #define USBD_INTENSET_ENDEPOUT3_Enabled (1UL)
- #define USBD_INTENSET_ENDEPOUT3_Set (1UL)
- #define USBD_INTENSET_ENDEPOUT2_Pos (14UL)
- #define USBD_INTENSET_ENDEPOUT2_Msk (0x1UL << USBD_INTENSET_ENDEPOUT2_Pos)
- #define USBD_INTENSET_ENDEPOUT2_Disabled (0UL)
- #define USBD_INTENSET_ENDEPOUT2_Enabled (1UL)
- #define USBD_INTENSET_ENDEPOUT2_Set (1UL)
- #define USBD_INTENSET_ENDEPOUT1_Pos (13UL)
- #define USBD_INTENSET_ENDEPOUT1_Msk (0x1UL << USBD_INTENSET_ENDEPOUT1_Pos)
- #define USBD_INTENSET_ENDEPOUT1_Disabled (0UL)
- #define USBD_INTENSET_ENDEPOUT1_Enabled (1UL)
- #define USBD_INTENSET_ENDEPOUT1_Set (1UL)
- #define USBD_INTENSET_ENDEPOUT0_Pos (12UL)
- #define USBD_INTENSET_ENDEPOUT0_Msk (0x1UL << USBD_INTENSET_ENDEPOUT0_Pos)
- #define USBD_INTENSET_ENDEPOUT0_Disabled (0UL)
- #define USBD_INTENSET_ENDEPOUT0_Enabled (1UL)
- #define USBD_INTENSET_ENDEPOUT0_Set (1UL)
- #define USBD_INTENSET_ENDISOIN_Pos (11UL)
- #define USBD_INTENSET_ENDISOIN_Msk (0x1UL << USBD_INTENSET_ENDISOIN_Pos)
- #define USBD_INTENSET_ENDISOIN_Disabled (0UL)
- #define USBD_INTENSET_ENDISOIN_Enabled (1UL)
- #define USBD_INTENSET_ENDISOIN_Set (1UL)
- #define USBD_INTENSET_EP0DATADONE_Pos (10UL)
- #define USBD_INTENSET_EP0DATADONE_Msk (0x1UL << USBD_INTENSET_EP0DATADONE_Pos)
- #define USBD_INTENSET_EP0DATADONE_Disabled (0UL)
- #define USBD_INTENSET_EP0DATADONE_Enabled (1UL)
- #define USBD_INTENSET_EP0DATADONE_Set (1UL)
- #define USBD_INTENSET_ENDEPIN7_Pos (9UL)
- #define USBD_INTENSET_ENDEPIN7_Msk (0x1UL << USBD_INTENSET_ENDEPIN7_Pos)
- #define USBD_INTENSET_ENDEPIN7_Disabled (0UL)
- #define USBD_INTENSET_ENDEPIN7_Enabled (1UL)
- #define USBD_INTENSET_ENDEPIN7_Set (1UL)
- #define USBD_INTENSET_ENDEPIN6_Pos (8UL)
- #define USBD_INTENSET_ENDEPIN6_Msk (0x1UL << USBD_INTENSET_ENDEPIN6_Pos)
- #define USBD_INTENSET_ENDEPIN6_Disabled (0UL)
- #define USBD_INTENSET_ENDEPIN6_Enabled (1UL)
- #define USBD_INTENSET_ENDEPIN6_Set (1UL)
- #define USBD_INTENSET_ENDEPIN5_Pos (7UL)
- #define USBD_INTENSET_ENDEPIN5_Msk (0x1UL << USBD_INTENSET_ENDEPIN5_Pos)
- #define USBD_INTENSET_ENDEPIN5_Disabled (0UL)
- #define USBD_INTENSET_ENDEPIN5_Enabled (1UL)
- #define USBD_INTENSET_ENDEPIN5_Set (1UL)
- #define USBD_INTENSET_ENDEPIN4_Pos (6UL)
- #define USBD_INTENSET_ENDEPIN4_Msk (0x1UL << USBD_INTENSET_ENDEPIN4_Pos)
- #define USBD_INTENSET_ENDEPIN4_Disabled (0UL)
- #define USBD_INTENSET_ENDEPIN4_Enabled (1UL)
- #define USBD_INTENSET_ENDEPIN4_Set (1UL)
- #define USBD_INTENSET_ENDEPIN3_Pos (5UL)
- #define USBD_INTENSET_ENDEPIN3_Msk (0x1UL << USBD_INTENSET_ENDEPIN3_Pos)
- #define USBD_INTENSET_ENDEPIN3_Disabled (0UL)
- #define USBD_INTENSET_ENDEPIN3_Enabled (1UL)
- #define USBD_INTENSET_ENDEPIN3_Set (1UL)
- #define USBD_INTENSET_ENDEPIN2_Pos (4UL)
- #define USBD_INTENSET_ENDEPIN2_Msk (0x1UL << USBD_INTENSET_ENDEPIN2_Pos)
- #define USBD_INTENSET_ENDEPIN2_Disabled (0UL)
- #define USBD_INTENSET_ENDEPIN2_Enabled (1UL)
- #define USBD_INTENSET_ENDEPIN2_Set (1UL)
- #define USBD_INTENSET_ENDEPIN1_Pos (3UL)
- #define USBD_INTENSET_ENDEPIN1_Msk (0x1UL << USBD_INTENSET_ENDEPIN1_Pos)
- #define USBD_INTENSET_ENDEPIN1_Disabled (0UL)
- #define USBD_INTENSET_ENDEPIN1_Enabled (1UL)
- #define USBD_INTENSET_ENDEPIN1_Set (1UL)
- #define USBD_INTENSET_ENDEPIN0_Pos (2UL)
- #define USBD_INTENSET_ENDEPIN0_Msk (0x1UL << USBD_INTENSET_ENDEPIN0_Pos)
- #define USBD_INTENSET_ENDEPIN0_Disabled (0UL)
- #define USBD_INTENSET_ENDEPIN0_Enabled (1UL)
- #define USBD_INTENSET_ENDEPIN0_Set (1UL)
- #define USBD_INTENSET_STARTED_Pos (1UL)
- #define USBD_INTENSET_STARTED_Msk (0x1UL << USBD_INTENSET_STARTED_Pos)
- #define USBD_INTENSET_STARTED_Disabled (0UL)
- #define USBD_INTENSET_STARTED_Enabled (1UL)
- #define USBD_INTENSET_STARTED_Set (1UL)
- #define USBD_INTENSET_USBRESET_Pos (0UL)
- #define USBD_INTENSET_USBRESET_Msk (0x1UL << USBD_INTENSET_USBRESET_Pos)
- #define USBD_INTENSET_USBRESET_Disabled (0UL)
- #define USBD_INTENSET_USBRESET_Enabled (1UL)
- #define USBD_INTENSET_USBRESET_Set (1UL)
- #define USBD_INTENCLR_EPDATA_Pos (24UL)
- #define USBD_INTENCLR_EPDATA_Msk (0x1UL << USBD_INTENCLR_EPDATA_Pos)
- #define USBD_INTENCLR_EPDATA_Disabled (0UL)
- #define USBD_INTENCLR_EPDATA_Enabled (1UL)
- #define USBD_INTENCLR_EPDATA_Clear (1UL)
- #define USBD_INTENCLR_EP0SETUP_Pos (23UL)
- #define USBD_INTENCLR_EP0SETUP_Msk (0x1UL << USBD_INTENCLR_EP0SETUP_Pos)
- #define USBD_INTENCLR_EP0SETUP_Disabled (0UL)
- #define USBD_INTENCLR_EP0SETUP_Enabled (1UL)
- #define USBD_INTENCLR_EP0SETUP_Clear (1UL)
- #define USBD_INTENCLR_USBEVENT_Pos (22UL)
- #define USBD_INTENCLR_USBEVENT_Msk (0x1UL << USBD_INTENCLR_USBEVENT_Pos)
- #define USBD_INTENCLR_USBEVENT_Disabled (0UL)
- #define USBD_INTENCLR_USBEVENT_Enabled (1UL)
- #define USBD_INTENCLR_USBEVENT_Clear (1UL)
- #define USBD_INTENCLR_SOF_Pos (21UL)
- #define USBD_INTENCLR_SOF_Msk (0x1UL << USBD_INTENCLR_SOF_Pos)
- #define USBD_INTENCLR_SOF_Disabled (0UL)
- #define USBD_INTENCLR_SOF_Enabled (1UL)
- #define USBD_INTENCLR_SOF_Clear (1UL)
- #define USBD_INTENCLR_ENDISOOUT_Pos (20UL)
- #define USBD_INTENCLR_ENDISOOUT_Msk (0x1UL << USBD_INTENCLR_ENDISOOUT_Pos)
- #define USBD_INTENCLR_ENDISOOUT_Disabled (0UL)
- #define USBD_INTENCLR_ENDISOOUT_Enabled (1UL)
- #define USBD_INTENCLR_ENDISOOUT_Clear (1UL)
- #define USBD_INTENCLR_ENDEPOUT7_Pos (19UL)
- #define USBD_INTENCLR_ENDEPOUT7_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT7_Pos)
- #define USBD_INTENCLR_ENDEPOUT7_Disabled (0UL)
- #define USBD_INTENCLR_ENDEPOUT7_Enabled (1UL)
- #define USBD_INTENCLR_ENDEPOUT7_Clear (1UL)
- #define USBD_INTENCLR_ENDEPOUT6_Pos (18UL)
- #define USBD_INTENCLR_ENDEPOUT6_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT6_Pos)
- #define USBD_INTENCLR_ENDEPOUT6_Disabled (0UL)
- #define USBD_INTENCLR_ENDEPOUT6_Enabled (1UL)
- #define USBD_INTENCLR_ENDEPOUT6_Clear (1UL)
- #define USBD_INTENCLR_ENDEPOUT5_Pos (17UL)
- #define USBD_INTENCLR_ENDEPOUT5_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT5_Pos)
- #define USBD_INTENCLR_ENDEPOUT5_Disabled (0UL)
- #define USBD_INTENCLR_ENDEPOUT5_Enabled (1UL)
- #define USBD_INTENCLR_ENDEPOUT5_Clear (1UL)
- #define USBD_INTENCLR_ENDEPOUT4_Pos (16UL)
- #define USBD_INTENCLR_ENDEPOUT4_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT4_Pos)
- #define USBD_INTENCLR_ENDEPOUT4_Disabled (0UL)
- #define USBD_INTENCLR_ENDEPOUT4_Enabled (1UL)
- #define USBD_INTENCLR_ENDEPOUT4_Clear (1UL)
- #define USBD_INTENCLR_ENDEPOUT3_Pos (15UL)
- #define USBD_INTENCLR_ENDEPOUT3_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT3_Pos)
- #define USBD_INTENCLR_ENDEPOUT3_Disabled (0UL)
- #define USBD_INTENCLR_ENDEPOUT3_Enabled (1UL)
- #define USBD_INTENCLR_ENDEPOUT3_Clear (1UL)
- #define USBD_INTENCLR_ENDEPOUT2_Pos (14UL)
- #define USBD_INTENCLR_ENDEPOUT2_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT2_Pos)
- #define USBD_INTENCLR_ENDEPOUT2_Disabled (0UL)
- #define USBD_INTENCLR_ENDEPOUT2_Enabled (1UL)
- #define USBD_INTENCLR_ENDEPOUT2_Clear (1UL)
- #define USBD_INTENCLR_ENDEPOUT1_Pos (13UL)
- #define USBD_INTENCLR_ENDEPOUT1_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT1_Pos)
- #define USBD_INTENCLR_ENDEPOUT1_Disabled (0UL)
- #define USBD_INTENCLR_ENDEPOUT1_Enabled (1UL)
- #define USBD_INTENCLR_ENDEPOUT1_Clear (1UL)
- #define USBD_INTENCLR_ENDEPOUT0_Pos (12UL)
- #define USBD_INTENCLR_ENDEPOUT0_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT0_Pos)
- #define USBD_INTENCLR_ENDEPOUT0_Disabled (0UL)
- #define USBD_INTENCLR_ENDEPOUT0_Enabled (1UL)
- #define USBD_INTENCLR_ENDEPOUT0_Clear (1UL)
- #define USBD_INTENCLR_ENDISOIN_Pos (11UL)
- #define USBD_INTENCLR_ENDISOIN_Msk (0x1UL << USBD_INTENCLR_ENDISOIN_Pos)
- #define USBD_INTENCLR_ENDISOIN_Disabled (0UL)
- #define USBD_INTENCLR_ENDISOIN_Enabled (1UL)
- #define USBD_INTENCLR_ENDISOIN_Clear (1UL)
- #define USBD_INTENCLR_EP0DATADONE_Pos (10UL)
- #define USBD_INTENCLR_EP0DATADONE_Msk (0x1UL << USBD_INTENCLR_EP0DATADONE_Pos)
- #define USBD_INTENCLR_EP0DATADONE_Disabled (0UL)
- #define USBD_INTENCLR_EP0DATADONE_Enabled (1UL)
- #define USBD_INTENCLR_EP0DATADONE_Clear (1UL)
- #define USBD_INTENCLR_ENDEPIN7_Pos (9UL)
- #define USBD_INTENCLR_ENDEPIN7_Msk (0x1UL << USBD_INTENCLR_ENDEPIN7_Pos)
- #define USBD_INTENCLR_ENDEPIN7_Disabled (0UL)
- #define USBD_INTENCLR_ENDEPIN7_Enabled (1UL)
- #define USBD_INTENCLR_ENDEPIN7_Clear (1UL)
- #define USBD_INTENCLR_ENDEPIN6_Pos (8UL)
- #define USBD_INTENCLR_ENDEPIN6_Msk (0x1UL << USBD_INTENCLR_ENDEPIN6_Pos)
- #define USBD_INTENCLR_ENDEPIN6_Disabled (0UL)
- #define USBD_INTENCLR_ENDEPIN6_Enabled (1UL)
- #define USBD_INTENCLR_ENDEPIN6_Clear (1UL)
- #define USBD_INTENCLR_ENDEPIN5_Pos (7UL)
- #define USBD_INTENCLR_ENDEPIN5_Msk (0x1UL << USBD_INTENCLR_ENDEPIN5_Pos)
- #define USBD_INTENCLR_ENDEPIN5_Disabled (0UL)
- #define USBD_INTENCLR_ENDEPIN5_Enabled (1UL)
- #define USBD_INTENCLR_ENDEPIN5_Clear (1UL)
- #define USBD_INTENCLR_ENDEPIN4_Pos (6UL)
- #define USBD_INTENCLR_ENDEPIN4_Msk (0x1UL << USBD_INTENCLR_ENDEPIN4_Pos)
- #define USBD_INTENCLR_ENDEPIN4_Disabled (0UL)
- #define USBD_INTENCLR_ENDEPIN4_Enabled (1UL)
- #define USBD_INTENCLR_ENDEPIN4_Clear (1UL)
- #define USBD_INTENCLR_ENDEPIN3_Pos (5UL)
- #define USBD_INTENCLR_ENDEPIN3_Msk (0x1UL << USBD_INTENCLR_ENDEPIN3_Pos)
- #define USBD_INTENCLR_ENDEPIN3_Disabled (0UL)
- #define USBD_INTENCLR_ENDEPIN3_Enabled (1UL)
- #define USBD_INTENCLR_ENDEPIN3_Clear (1UL)
- #define USBD_INTENCLR_ENDEPIN2_Pos (4UL)
- #define USBD_INTENCLR_ENDEPIN2_Msk (0x1UL << USBD_INTENCLR_ENDEPIN2_Pos)
- #define USBD_INTENCLR_ENDEPIN2_Disabled (0UL)
- #define USBD_INTENCLR_ENDEPIN2_Enabled (1UL)
- #define USBD_INTENCLR_ENDEPIN2_Clear (1UL)
- #define USBD_INTENCLR_ENDEPIN1_Pos (3UL)
- #define USBD_INTENCLR_ENDEPIN1_Msk (0x1UL << USBD_INTENCLR_ENDEPIN1_Pos)
- #define USBD_INTENCLR_ENDEPIN1_Disabled (0UL)
- #define USBD_INTENCLR_ENDEPIN1_Enabled (1UL)
- #define USBD_INTENCLR_ENDEPIN1_Clear (1UL)
- #define USBD_INTENCLR_ENDEPIN0_Pos (2UL)
- #define USBD_INTENCLR_ENDEPIN0_Msk (0x1UL << USBD_INTENCLR_ENDEPIN0_Pos)
- #define USBD_INTENCLR_ENDEPIN0_Disabled (0UL)
- #define USBD_INTENCLR_ENDEPIN0_Enabled (1UL)
- #define USBD_INTENCLR_ENDEPIN0_Clear (1UL)
- #define USBD_INTENCLR_STARTED_Pos (1UL)
- #define USBD_INTENCLR_STARTED_Msk (0x1UL << USBD_INTENCLR_STARTED_Pos)
- #define USBD_INTENCLR_STARTED_Disabled (0UL)
- #define USBD_INTENCLR_STARTED_Enabled (1UL)
- #define USBD_INTENCLR_STARTED_Clear (1UL)
- #define USBD_INTENCLR_USBRESET_Pos (0UL)
- #define USBD_INTENCLR_USBRESET_Msk (0x1UL << USBD_INTENCLR_USBRESET_Pos)
- #define USBD_INTENCLR_USBRESET_Disabled (0UL)
- #define USBD_INTENCLR_USBRESET_Enabled (1UL)
- #define USBD_INTENCLR_USBRESET_Clear (1UL)
- #define USBD_EVENTCAUSE_READY_Pos (11UL)
- #define USBD_EVENTCAUSE_READY_Msk (0x1UL << USBD_EVENTCAUSE_READY_Pos)
- #define USBD_EVENTCAUSE_READY_NotDetected (0UL)
- #define USBD_EVENTCAUSE_READY_Ready (1UL)
- #define USBD_EVENTCAUSE_USBWUALLOWED_Pos (10UL)
- #define USBD_EVENTCAUSE_USBWUALLOWED_Msk (0x1UL << USBD_EVENTCAUSE_USBWUALLOWED_Pos)
- #define USBD_EVENTCAUSE_USBWUALLOWED_NotAllowed (0UL)
- #define USBD_EVENTCAUSE_USBWUALLOWED_Allowed (1UL)
- #define USBD_EVENTCAUSE_RESUME_Pos (9UL)
- #define USBD_EVENTCAUSE_RESUME_Msk (0x1UL << USBD_EVENTCAUSE_RESUME_Pos)
- #define USBD_EVENTCAUSE_RESUME_NotDetected (0UL)
- #define USBD_EVENTCAUSE_RESUME_Detected (1UL)
- #define USBD_EVENTCAUSE_SUSPEND_Pos (8UL)
- #define USBD_EVENTCAUSE_SUSPEND_Msk (0x1UL << USBD_EVENTCAUSE_SUSPEND_Pos)
- #define USBD_EVENTCAUSE_SUSPEND_NotDetected (0UL)
- #define USBD_EVENTCAUSE_SUSPEND_Detected (1UL)
- #define USBD_EVENTCAUSE_ISOOUTCRC_Pos (0UL)
- #define USBD_EVENTCAUSE_ISOOUTCRC_Msk (0x1UL << USBD_EVENTCAUSE_ISOOUTCRC_Pos)
- #define USBD_EVENTCAUSE_ISOOUTCRC_NotDetected (0UL)
- #define USBD_EVENTCAUSE_ISOOUTCRC_Detected (1UL)
- #define USBD_HALTED_EPIN_GETSTATUS_Pos (0UL)
- #define USBD_HALTED_EPIN_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPIN_GETSTATUS_Pos)
- #define USBD_HALTED_EPIN_GETSTATUS_NotHalted (0UL)
- #define USBD_HALTED_EPIN_GETSTATUS_Halted (1UL)
- #define USBD_HALTED_EPOUT_GETSTATUS_Pos (0UL)
- #define USBD_HALTED_EPOUT_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPOUT_GETSTATUS_Pos)
- #define USBD_HALTED_EPOUT_GETSTATUS_NotHalted (0UL)
- #define USBD_HALTED_EPOUT_GETSTATUS_Halted (1UL)
- #define USBD_EPSTATUS_EPOUT8_Pos (24UL)
- #define USBD_EPSTATUS_EPOUT8_Msk (0x1UL << USBD_EPSTATUS_EPOUT8_Pos)
- #define USBD_EPSTATUS_EPOUT8_NoData (0UL)
- #define USBD_EPSTATUS_EPOUT8_DataDone (1UL)
- #define USBD_EPSTATUS_EPOUT7_Pos (23UL)
- #define USBD_EPSTATUS_EPOUT7_Msk (0x1UL << USBD_EPSTATUS_EPOUT7_Pos)
- #define USBD_EPSTATUS_EPOUT7_NoData (0UL)
- #define USBD_EPSTATUS_EPOUT7_DataDone (1UL)
- #define USBD_EPSTATUS_EPOUT6_Pos (22UL)
- #define USBD_EPSTATUS_EPOUT6_Msk (0x1UL << USBD_EPSTATUS_EPOUT6_Pos)
- #define USBD_EPSTATUS_EPOUT6_NoData (0UL)
- #define USBD_EPSTATUS_EPOUT6_DataDone (1UL)
- #define USBD_EPSTATUS_EPOUT5_Pos (21UL)
- #define USBD_EPSTATUS_EPOUT5_Msk (0x1UL << USBD_EPSTATUS_EPOUT5_Pos)
- #define USBD_EPSTATUS_EPOUT5_NoData (0UL)
- #define USBD_EPSTATUS_EPOUT5_DataDone (1UL)
- #define USBD_EPSTATUS_EPOUT4_Pos (20UL)
- #define USBD_EPSTATUS_EPOUT4_Msk (0x1UL << USBD_EPSTATUS_EPOUT4_Pos)
- #define USBD_EPSTATUS_EPOUT4_NoData (0UL)
- #define USBD_EPSTATUS_EPOUT4_DataDone (1UL)
- #define USBD_EPSTATUS_EPOUT3_Pos (19UL)
- #define USBD_EPSTATUS_EPOUT3_Msk (0x1UL << USBD_EPSTATUS_EPOUT3_Pos)
- #define USBD_EPSTATUS_EPOUT3_NoData (0UL)
- #define USBD_EPSTATUS_EPOUT3_DataDone (1UL)
- #define USBD_EPSTATUS_EPOUT2_Pos (18UL)
- #define USBD_EPSTATUS_EPOUT2_Msk (0x1UL << USBD_EPSTATUS_EPOUT2_Pos)
- #define USBD_EPSTATUS_EPOUT2_NoData (0UL)
- #define USBD_EPSTATUS_EPOUT2_DataDone (1UL)
- #define USBD_EPSTATUS_EPOUT1_Pos (17UL)
- #define USBD_EPSTATUS_EPOUT1_Msk (0x1UL << USBD_EPSTATUS_EPOUT1_Pos)
- #define USBD_EPSTATUS_EPOUT1_NoData (0UL)
- #define USBD_EPSTATUS_EPOUT1_DataDone (1UL)
- #define USBD_EPSTATUS_EPOUT0_Pos (16UL)
- #define USBD_EPSTATUS_EPOUT0_Msk (0x1UL << USBD_EPSTATUS_EPOUT0_Pos)
- #define USBD_EPSTATUS_EPOUT0_NoData (0UL)
- #define USBD_EPSTATUS_EPOUT0_DataDone (1UL)
- #define USBD_EPSTATUS_EPIN8_Pos (8UL)
- #define USBD_EPSTATUS_EPIN8_Msk (0x1UL << USBD_EPSTATUS_EPIN8_Pos)
- #define USBD_EPSTATUS_EPIN8_NoData (0UL)
- #define USBD_EPSTATUS_EPIN8_DataDone (1UL)
- #define USBD_EPSTATUS_EPIN7_Pos (7UL)
- #define USBD_EPSTATUS_EPIN7_Msk (0x1UL << USBD_EPSTATUS_EPIN7_Pos)
- #define USBD_EPSTATUS_EPIN7_NoData (0UL)
- #define USBD_EPSTATUS_EPIN7_DataDone (1UL)
- #define USBD_EPSTATUS_EPIN6_Pos (6UL)
- #define USBD_EPSTATUS_EPIN6_Msk (0x1UL << USBD_EPSTATUS_EPIN6_Pos)
- #define USBD_EPSTATUS_EPIN6_NoData (0UL)
- #define USBD_EPSTATUS_EPIN6_DataDone (1UL)
- #define USBD_EPSTATUS_EPIN5_Pos (5UL)
- #define USBD_EPSTATUS_EPIN5_Msk (0x1UL << USBD_EPSTATUS_EPIN5_Pos)
- #define USBD_EPSTATUS_EPIN5_NoData (0UL)
- #define USBD_EPSTATUS_EPIN5_DataDone (1UL)
- #define USBD_EPSTATUS_EPIN4_Pos (4UL)
- #define USBD_EPSTATUS_EPIN4_Msk (0x1UL << USBD_EPSTATUS_EPIN4_Pos)
- #define USBD_EPSTATUS_EPIN4_NoData (0UL)
- #define USBD_EPSTATUS_EPIN4_DataDone (1UL)
- #define USBD_EPSTATUS_EPIN3_Pos (3UL)
- #define USBD_EPSTATUS_EPIN3_Msk (0x1UL << USBD_EPSTATUS_EPIN3_Pos)
- #define USBD_EPSTATUS_EPIN3_NoData (0UL)
- #define USBD_EPSTATUS_EPIN3_DataDone (1UL)
- #define USBD_EPSTATUS_EPIN2_Pos (2UL)
- #define USBD_EPSTATUS_EPIN2_Msk (0x1UL << USBD_EPSTATUS_EPIN2_Pos)
- #define USBD_EPSTATUS_EPIN2_NoData (0UL)
- #define USBD_EPSTATUS_EPIN2_DataDone (1UL)
- #define USBD_EPSTATUS_EPIN1_Pos (1UL)
- #define USBD_EPSTATUS_EPIN1_Msk (0x1UL << USBD_EPSTATUS_EPIN1_Pos)
- #define USBD_EPSTATUS_EPIN1_NoData (0UL)
- #define USBD_EPSTATUS_EPIN1_DataDone (1UL)
- #define USBD_EPSTATUS_EPIN0_Pos (0UL)
- #define USBD_EPSTATUS_EPIN0_Msk (0x1UL << USBD_EPSTATUS_EPIN0_Pos)
- #define USBD_EPSTATUS_EPIN0_NoData (0UL)
- #define USBD_EPSTATUS_EPIN0_DataDone (1UL)
- #define USBD_EPDATASTATUS_EPOUT7_Pos (23UL)
- #define USBD_EPDATASTATUS_EPOUT7_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT7_Pos)
- #define USBD_EPDATASTATUS_EPOUT7_NotStarted (0UL)
- #define USBD_EPDATASTATUS_EPOUT7_Started (1UL)
- #define USBD_EPDATASTATUS_EPOUT6_Pos (22UL)
- #define USBD_EPDATASTATUS_EPOUT6_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT6_Pos)
- #define USBD_EPDATASTATUS_EPOUT6_NotStarted (0UL)
- #define USBD_EPDATASTATUS_EPOUT6_Started (1UL)
- #define USBD_EPDATASTATUS_EPOUT5_Pos (21UL)
- #define USBD_EPDATASTATUS_EPOUT5_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT5_Pos)
- #define USBD_EPDATASTATUS_EPOUT5_NotStarted (0UL)
- #define USBD_EPDATASTATUS_EPOUT5_Started (1UL)
- #define USBD_EPDATASTATUS_EPOUT4_Pos (20UL)
- #define USBD_EPDATASTATUS_EPOUT4_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT4_Pos)
- #define USBD_EPDATASTATUS_EPOUT4_NotStarted (0UL)
- #define USBD_EPDATASTATUS_EPOUT4_Started (1UL)
- #define USBD_EPDATASTATUS_EPOUT3_Pos (19UL)
- #define USBD_EPDATASTATUS_EPOUT3_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT3_Pos)
- #define USBD_EPDATASTATUS_EPOUT3_NotStarted (0UL)
- #define USBD_EPDATASTATUS_EPOUT3_Started (1UL)
- #define USBD_EPDATASTATUS_EPOUT2_Pos (18UL)
- #define USBD_EPDATASTATUS_EPOUT2_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT2_Pos)
- #define USBD_EPDATASTATUS_EPOUT2_NotStarted (0UL)
- #define USBD_EPDATASTATUS_EPOUT2_Started (1UL)
- #define USBD_EPDATASTATUS_EPOUT1_Pos (17UL)
- #define USBD_EPDATASTATUS_EPOUT1_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT1_Pos)
- #define USBD_EPDATASTATUS_EPOUT1_NotStarted (0UL)
- #define USBD_EPDATASTATUS_EPOUT1_Started (1UL)
- #define USBD_EPDATASTATUS_EPIN7_Pos (7UL)
- #define USBD_EPDATASTATUS_EPIN7_Msk (0x1UL << USBD_EPDATASTATUS_EPIN7_Pos)
- #define USBD_EPDATASTATUS_EPIN7_NotDone (0UL)
- #define USBD_EPDATASTATUS_EPIN7_DataDone (1UL)
- #define USBD_EPDATASTATUS_EPIN6_Pos (6UL)
- #define USBD_EPDATASTATUS_EPIN6_Msk (0x1UL << USBD_EPDATASTATUS_EPIN6_Pos)
- #define USBD_EPDATASTATUS_EPIN6_NotDone (0UL)
- #define USBD_EPDATASTATUS_EPIN6_DataDone (1UL)
- #define USBD_EPDATASTATUS_EPIN5_Pos (5UL)
- #define USBD_EPDATASTATUS_EPIN5_Msk (0x1UL << USBD_EPDATASTATUS_EPIN5_Pos)
- #define USBD_EPDATASTATUS_EPIN5_NotDone (0UL)
- #define USBD_EPDATASTATUS_EPIN5_DataDone (1UL)
- #define USBD_EPDATASTATUS_EPIN4_Pos (4UL)
- #define USBD_EPDATASTATUS_EPIN4_Msk (0x1UL << USBD_EPDATASTATUS_EPIN4_Pos)
- #define USBD_EPDATASTATUS_EPIN4_NotDone (0UL)
- #define USBD_EPDATASTATUS_EPIN4_DataDone (1UL)
- #define USBD_EPDATASTATUS_EPIN3_Pos (3UL)
- #define USBD_EPDATASTATUS_EPIN3_Msk (0x1UL << USBD_EPDATASTATUS_EPIN3_Pos)
- #define USBD_EPDATASTATUS_EPIN3_NotDone (0UL)
- #define USBD_EPDATASTATUS_EPIN3_DataDone (1UL)
- #define USBD_EPDATASTATUS_EPIN2_Pos (2UL)
- #define USBD_EPDATASTATUS_EPIN2_Msk (0x1UL << USBD_EPDATASTATUS_EPIN2_Pos)
- #define USBD_EPDATASTATUS_EPIN2_NotDone (0UL)
- #define USBD_EPDATASTATUS_EPIN2_DataDone (1UL)
- #define USBD_EPDATASTATUS_EPIN1_Pos (1UL)
- #define USBD_EPDATASTATUS_EPIN1_Msk (0x1UL << USBD_EPDATASTATUS_EPIN1_Pos)
- #define USBD_EPDATASTATUS_EPIN1_NotDone (0UL)
- #define USBD_EPDATASTATUS_EPIN1_DataDone (1UL)
- #define USBD_USBADDR_ADDR_Pos (0UL)
- #define USBD_USBADDR_ADDR_Msk (0x7FUL << USBD_USBADDR_ADDR_Pos)
- #define USBD_BMREQUESTTYPE_DIRECTION_Pos (7UL)
- #define USBD_BMREQUESTTYPE_DIRECTION_Msk (0x1UL << USBD_BMREQUESTTYPE_DIRECTION_Pos)
- #define USBD_BMREQUESTTYPE_DIRECTION_HostToDevice (0UL)
- #define USBD_BMREQUESTTYPE_DIRECTION_DeviceToHost (1UL)
- #define USBD_BMREQUESTTYPE_TYPE_Pos (5UL)
- #define USBD_BMREQUESTTYPE_TYPE_Msk (0x3UL << USBD_BMREQUESTTYPE_TYPE_Pos)
- #define USBD_BMREQUESTTYPE_TYPE_Standard (0UL)
- #define USBD_BMREQUESTTYPE_TYPE_Class (1UL)
- #define USBD_BMREQUESTTYPE_TYPE_Vendor (2UL)
- #define USBD_BMREQUESTTYPE_RECIPIENT_Pos (0UL)
- #define USBD_BMREQUESTTYPE_RECIPIENT_Msk (0x1FUL << USBD_BMREQUESTTYPE_RECIPIENT_Pos)
- #define USBD_BMREQUESTTYPE_RECIPIENT_Device (0UL)
- #define USBD_BMREQUESTTYPE_RECIPIENT_Interface (1UL)
- #define USBD_BMREQUESTTYPE_RECIPIENT_Endpoint (2UL)
- #define USBD_BMREQUESTTYPE_RECIPIENT_Other (3UL)
- #define USBD_BREQUEST_BREQUEST_Pos (0UL)
- #define USBD_BREQUEST_BREQUEST_Msk (0xFFUL << USBD_BREQUEST_BREQUEST_Pos)
- #define USBD_BREQUEST_BREQUEST_STD_GET_STATUS (0UL)
- #define USBD_BREQUEST_BREQUEST_STD_CLEAR_FEATURE (1UL)
- #define USBD_BREQUEST_BREQUEST_STD_SET_FEATURE (3UL)
- #define USBD_BREQUEST_BREQUEST_STD_SET_ADDRESS (5UL)
- #define USBD_BREQUEST_BREQUEST_STD_GET_DESCRIPTOR (6UL)
- #define USBD_BREQUEST_BREQUEST_STD_SET_DESCRIPTOR (7UL)
- #define USBD_BREQUEST_BREQUEST_STD_GET_CONFIGURATION (8UL)
- #define USBD_BREQUEST_BREQUEST_STD_SET_CONFIGURATION (9UL)
- #define USBD_BREQUEST_BREQUEST_STD_GET_INTERFACE (10UL)
- #define USBD_BREQUEST_BREQUEST_STD_SET_INTERFACE (11UL)
- #define USBD_BREQUEST_BREQUEST_STD_SYNCH_FRAME (12UL)
- #define USBD_WVALUEL_WVALUEL_Pos (0UL)
- #define USBD_WVALUEL_WVALUEL_Msk (0xFFUL << USBD_WVALUEL_WVALUEL_Pos)
- #define USBD_WVALUEH_WVALUEH_Pos (0UL)
- #define USBD_WVALUEH_WVALUEH_Msk (0xFFUL << USBD_WVALUEH_WVALUEH_Pos)
- #define USBD_WINDEXL_WINDEXL_Pos (0UL)
- #define USBD_WINDEXL_WINDEXL_Msk (0xFFUL << USBD_WINDEXL_WINDEXL_Pos)
- #define USBD_WINDEXH_WINDEXH_Pos (0UL)
- #define USBD_WINDEXH_WINDEXH_Msk (0xFFUL << USBD_WINDEXH_WINDEXH_Pos)
- #define USBD_WLENGTHL_WLENGTHL_Pos (0UL)
- #define USBD_WLENGTHL_WLENGTHL_Msk (0xFFUL << USBD_WLENGTHL_WLENGTHL_Pos)
- #define USBD_WLENGTHH_WLENGTHH_Pos (0UL)
- #define USBD_WLENGTHH_WLENGTHH_Msk (0xFFUL << USBD_WLENGTHH_WLENGTHH_Pos)
- #define USBD_SIZE_EPOUT_SIZE_Pos (0UL)
- #define USBD_SIZE_EPOUT_SIZE_Msk (0x7FUL << USBD_SIZE_EPOUT_SIZE_Pos)
- #define USBD_SIZE_ISOOUT_ZERO_Pos (16UL)
- #define USBD_SIZE_ISOOUT_ZERO_Msk (0x1UL << USBD_SIZE_ISOOUT_ZERO_Pos)
- #define USBD_SIZE_ISOOUT_ZERO_Normal (0UL)
- #define USBD_SIZE_ISOOUT_ZERO_ZeroData (1UL)
- #define USBD_SIZE_ISOOUT_SIZE_Pos (0UL)
- #define USBD_SIZE_ISOOUT_SIZE_Msk (0x3FFUL << USBD_SIZE_ISOOUT_SIZE_Pos)
- #define USBD_ENABLE_ENABLE_Pos (0UL)
- #define USBD_ENABLE_ENABLE_Msk (0x1UL << USBD_ENABLE_ENABLE_Pos)
- #define USBD_ENABLE_ENABLE_Disabled (0UL)
- #define USBD_ENABLE_ENABLE_Enabled (1UL)
- #define USBD_USBPULLUP_CONNECT_Pos (0UL)
- #define USBD_USBPULLUP_CONNECT_Msk (0x1UL << USBD_USBPULLUP_CONNECT_Pos)
- #define USBD_USBPULLUP_CONNECT_Disabled (0UL)
- #define USBD_USBPULLUP_CONNECT_Enabled (1UL)
- #define USBD_DPDMVALUE_STATE_Pos (0UL)
- #define USBD_DPDMVALUE_STATE_Msk (0x1FUL << USBD_DPDMVALUE_STATE_Pos)
- #define USBD_DPDMVALUE_STATE_Resume (1UL)
- #define USBD_DPDMVALUE_STATE_J (2UL)
- #define USBD_DPDMVALUE_STATE_K (4UL)
- #define USBD_DTOGGLE_VALUE_Pos (8UL)
- #define USBD_DTOGGLE_VALUE_Msk (0x3UL << USBD_DTOGGLE_VALUE_Pos)
- #define USBD_DTOGGLE_VALUE_Nop (0UL)
- #define USBD_DTOGGLE_VALUE_Data0 (1UL)
- #define USBD_DTOGGLE_VALUE_Data1 (2UL)
- #define USBD_DTOGGLE_IO_Pos (7UL)
- #define USBD_DTOGGLE_IO_Msk (0x1UL << USBD_DTOGGLE_IO_Pos)
- #define USBD_DTOGGLE_IO_Out (0UL)
- #define USBD_DTOGGLE_IO_In (1UL)
- #define USBD_DTOGGLE_EP_Pos (0UL)
- #define USBD_DTOGGLE_EP_Msk (0x7UL << USBD_DTOGGLE_EP_Pos)
- #define USBD_EPINEN_ISOIN_Pos (8UL)
- #define USBD_EPINEN_ISOIN_Msk (0x1UL << USBD_EPINEN_ISOIN_Pos)
- #define USBD_EPINEN_ISOIN_Disable (0UL)
- #define USBD_EPINEN_ISOIN_Enable (1UL)
- #define USBD_EPINEN_IN7_Pos (7UL)
- #define USBD_EPINEN_IN7_Msk (0x1UL << USBD_EPINEN_IN7_Pos)
- #define USBD_EPINEN_IN7_Disable (0UL)
- #define USBD_EPINEN_IN7_Enable (1UL)
- #define USBD_EPINEN_IN6_Pos (6UL)
- #define USBD_EPINEN_IN6_Msk (0x1UL << USBD_EPINEN_IN6_Pos)
- #define USBD_EPINEN_IN6_Disable (0UL)
- #define USBD_EPINEN_IN6_Enable (1UL)
- #define USBD_EPINEN_IN5_Pos (5UL)
- #define USBD_EPINEN_IN5_Msk (0x1UL << USBD_EPINEN_IN5_Pos)
- #define USBD_EPINEN_IN5_Disable (0UL)
- #define USBD_EPINEN_IN5_Enable (1UL)
- #define USBD_EPINEN_IN4_Pos (4UL)
- #define USBD_EPINEN_IN4_Msk (0x1UL << USBD_EPINEN_IN4_Pos)
- #define USBD_EPINEN_IN4_Disable (0UL)
- #define USBD_EPINEN_IN4_Enable (1UL)
- #define USBD_EPINEN_IN3_Pos (3UL)
- #define USBD_EPINEN_IN3_Msk (0x1UL << USBD_EPINEN_IN3_Pos)
- #define USBD_EPINEN_IN3_Disable (0UL)
- #define USBD_EPINEN_IN3_Enable (1UL)
- #define USBD_EPINEN_IN2_Pos (2UL)
- #define USBD_EPINEN_IN2_Msk (0x1UL << USBD_EPINEN_IN2_Pos)
- #define USBD_EPINEN_IN2_Disable (0UL)
- #define USBD_EPINEN_IN2_Enable (1UL)
- #define USBD_EPINEN_IN1_Pos (1UL)
- #define USBD_EPINEN_IN1_Msk (0x1UL << USBD_EPINEN_IN1_Pos)
- #define USBD_EPINEN_IN1_Disable (0UL)
- #define USBD_EPINEN_IN1_Enable (1UL)
- #define USBD_EPINEN_IN0_Pos (0UL)
- #define USBD_EPINEN_IN0_Msk (0x1UL << USBD_EPINEN_IN0_Pos)
- #define USBD_EPINEN_IN0_Disable (0UL)
- #define USBD_EPINEN_IN0_Enable (1UL)
- #define USBD_EPOUTEN_ISOOUT_Pos (8UL)
- #define USBD_EPOUTEN_ISOOUT_Msk (0x1UL << USBD_EPOUTEN_ISOOUT_Pos)
- #define USBD_EPOUTEN_ISOOUT_Disable (0UL)
- #define USBD_EPOUTEN_ISOOUT_Enable (1UL)
- #define USBD_EPOUTEN_OUT7_Pos (7UL)
- #define USBD_EPOUTEN_OUT7_Msk (0x1UL << USBD_EPOUTEN_OUT7_Pos)
- #define USBD_EPOUTEN_OUT7_Disable (0UL)
- #define USBD_EPOUTEN_OUT7_Enable (1UL)
- #define USBD_EPOUTEN_OUT6_Pos (6UL)
- #define USBD_EPOUTEN_OUT6_Msk (0x1UL << USBD_EPOUTEN_OUT6_Pos)
- #define USBD_EPOUTEN_OUT6_Disable (0UL)
- #define USBD_EPOUTEN_OUT6_Enable (1UL)
- #define USBD_EPOUTEN_OUT5_Pos (5UL)
- #define USBD_EPOUTEN_OUT5_Msk (0x1UL << USBD_EPOUTEN_OUT5_Pos)
- #define USBD_EPOUTEN_OUT5_Disable (0UL)
- #define USBD_EPOUTEN_OUT5_Enable (1UL)
- #define USBD_EPOUTEN_OUT4_Pos (4UL)
- #define USBD_EPOUTEN_OUT4_Msk (0x1UL << USBD_EPOUTEN_OUT4_Pos)
- #define USBD_EPOUTEN_OUT4_Disable (0UL)
- #define USBD_EPOUTEN_OUT4_Enable (1UL)
- #define USBD_EPOUTEN_OUT3_Pos (3UL)
- #define USBD_EPOUTEN_OUT3_Msk (0x1UL << USBD_EPOUTEN_OUT3_Pos)
- #define USBD_EPOUTEN_OUT3_Disable (0UL)
- #define USBD_EPOUTEN_OUT3_Enable (1UL)
- #define USBD_EPOUTEN_OUT2_Pos (2UL)
- #define USBD_EPOUTEN_OUT2_Msk (0x1UL << USBD_EPOUTEN_OUT2_Pos)
- #define USBD_EPOUTEN_OUT2_Disable (0UL)
- #define USBD_EPOUTEN_OUT2_Enable (1UL)
- #define USBD_EPOUTEN_OUT1_Pos (1UL)
- #define USBD_EPOUTEN_OUT1_Msk (0x1UL << USBD_EPOUTEN_OUT1_Pos)
- #define USBD_EPOUTEN_OUT1_Disable (0UL)
- #define USBD_EPOUTEN_OUT1_Enable (1UL)
- #define USBD_EPOUTEN_OUT0_Pos (0UL)
- #define USBD_EPOUTEN_OUT0_Msk (0x1UL << USBD_EPOUTEN_OUT0_Pos)
- #define USBD_EPOUTEN_OUT0_Disable (0UL)
- #define USBD_EPOUTEN_OUT0_Enable (1UL)
- #define USBD_EPSTALL_STALL_Pos (8UL)
- #define USBD_EPSTALL_STALL_Msk (0x1UL << USBD_EPSTALL_STALL_Pos)
- #define USBD_EPSTALL_STALL_UnStall (0UL)
- #define USBD_EPSTALL_STALL_Stall (1UL)
- #define USBD_EPSTALL_IO_Pos (7UL)
- #define USBD_EPSTALL_IO_Msk (0x1UL << USBD_EPSTALL_IO_Pos)
- #define USBD_EPSTALL_IO_Out (0UL)
- #define USBD_EPSTALL_IO_In (1UL)
- #define USBD_EPSTALL_EP_Pos (0UL)
- #define USBD_EPSTALL_EP_Msk (0x7UL << USBD_EPSTALL_EP_Pos)
- #define USBD_ISOSPLIT_SPLIT_Pos (0UL)
- #define USBD_ISOSPLIT_SPLIT_Msk (0xFFFFUL << USBD_ISOSPLIT_SPLIT_Pos)
- #define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL)
- #define USBD_ISOSPLIT_SPLIT_HalfIN (0x0080UL)
- #define USBD_FRAMECNTR_FRAMECNTR_Pos (0UL)
- #define USBD_FRAMECNTR_FRAMECNTR_Msk (0x7FFUL << USBD_FRAMECNTR_FRAMECNTR_Pos)
- #define USBD_LOWPOWER_LOWPOWER_Pos (0UL)
- #define USBD_LOWPOWER_LOWPOWER_Msk (0x1UL << USBD_LOWPOWER_LOWPOWER_Pos)
- #define USBD_LOWPOWER_LOWPOWER_ForceNormal (0UL)
- #define USBD_LOWPOWER_LOWPOWER_LowPower (1UL)
- #define USBD_ISOINCONFIG_RESPONSE_Pos (0UL)
- #define USBD_ISOINCONFIG_RESPONSE_Msk (0x1UL << USBD_ISOINCONFIG_RESPONSE_Pos)
- #define USBD_ISOINCONFIG_RESPONSE_NoResp (0UL)
- #define USBD_ISOINCONFIG_RESPONSE_ZeroData (1UL)
- #define USBD_EPIN_PTR_PTR_Pos (0UL)
- #define USBD_EPIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPIN_PTR_PTR_Pos)
- #define USBD_EPIN_MAXCNT_MAXCNT_Pos (0UL)
- #define USBD_EPIN_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPIN_MAXCNT_MAXCNT_Pos)
- #define USBD_EPIN_AMOUNT_AMOUNT_Pos (0UL)
- #define USBD_EPIN_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPIN_AMOUNT_AMOUNT_Pos)
- #define USBD_ISOIN_PTR_PTR_Pos (0UL)
- #define USBD_ISOIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOIN_PTR_PTR_Pos)
- #define USBD_ISOIN_MAXCNT_MAXCNT_Pos (0UL)
- #define USBD_ISOIN_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOIN_MAXCNT_MAXCNT_Pos)
- #define USBD_ISOIN_AMOUNT_AMOUNT_Pos (0UL)
- #define USBD_ISOIN_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOIN_AMOUNT_AMOUNT_Pos)
- #define USBD_EPOUT_PTR_PTR_Pos (0UL)
- #define USBD_EPOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPOUT_PTR_PTR_Pos)
- #define USBD_EPOUT_MAXCNT_MAXCNT_Pos (0UL)
- #define USBD_EPOUT_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPOUT_MAXCNT_MAXCNT_Pos)
- #define USBD_EPOUT_AMOUNT_AMOUNT_Pos (0UL)
- #define USBD_EPOUT_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPOUT_AMOUNT_AMOUNT_Pos)
- #define USBD_ISOOUT_PTR_PTR_Pos (0UL)
- #define USBD_ISOOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOOUT_PTR_PTR_Pos)
- #define USBD_ISOOUT_MAXCNT_MAXCNT_Pos (0UL)
- #define USBD_ISOOUT_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOOUT_MAXCNT_MAXCNT_Pos)
- #define USBD_ISOOUT_AMOUNT_AMOUNT_Pos (0UL)
- #define USBD_ISOOUT_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOOUT_AMOUNT_AMOUNT_Pos)
- #define USBREG_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos (0UL)
- #define USBREG_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Msk (0x1UL << USBREG_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos)
- #define USBREG_EVENTS_USBDETECTED_EVENTS_USBDETECTED_NotGenerated (0UL)
- #define USBREG_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Generated (1UL)
- #define USBREG_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos (0UL)
- #define USBREG_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Msk (0x1UL << USBREG_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos)
- #define USBREG_EVENTS_USBREMOVED_EVENTS_USBREMOVED_NotGenerated (0UL)
- #define USBREG_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Generated (1UL)
- #define USBREG_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos (0UL)
- #define USBREG_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Msk (0x1UL << USBREG_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos)
- #define USBREG_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_NotGenerated (0UL)
- #define USBREG_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Generated (1UL)
- #define USBREG_PUBLISH_USBDETECTED_EN_Pos (31UL)
- #define USBREG_PUBLISH_USBDETECTED_EN_Msk (0x1UL << USBREG_PUBLISH_USBDETECTED_EN_Pos)
- #define USBREG_PUBLISH_USBDETECTED_EN_Disabled (0UL)
- #define USBREG_PUBLISH_USBDETECTED_EN_Enabled (1UL)
- #define USBREG_PUBLISH_USBDETECTED_CHIDX_Pos (0UL)
- #define USBREG_PUBLISH_USBDETECTED_CHIDX_Msk (0xFFUL << USBREG_PUBLISH_USBDETECTED_CHIDX_Pos)
- #define USBREG_PUBLISH_USBREMOVED_EN_Pos (31UL)
- #define USBREG_PUBLISH_USBREMOVED_EN_Msk (0x1UL << USBREG_PUBLISH_USBREMOVED_EN_Pos)
- #define USBREG_PUBLISH_USBREMOVED_EN_Disabled (0UL)
- #define USBREG_PUBLISH_USBREMOVED_EN_Enabled (1UL)
- #define USBREG_PUBLISH_USBREMOVED_CHIDX_Pos (0UL)
- #define USBREG_PUBLISH_USBREMOVED_CHIDX_Msk (0xFFUL << USBREG_PUBLISH_USBREMOVED_CHIDX_Pos)
- #define USBREG_PUBLISH_USBPWRRDY_EN_Pos (31UL)
- #define USBREG_PUBLISH_USBPWRRDY_EN_Msk (0x1UL << USBREG_PUBLISH_USBPWRRDY_EN_Pos)
- #define USBREG_PUBLISH_USBPWRRDY_EN_Disabled (0UL)
- #define USBREG_PUBLISH_USBPWRRDY_EN_Enabled (1UL)
- #define USBREG_PUBLISH_USBPWRRDY_CHIDX_Pos (0UL)
- #define USBREG_PUBLISH_USBPWRRDY_CHIDX_Msk (0xFFUL << USBREG_PUBLISH_USBPWRRDY_CHIDX_Pos)
- #define USBREG_INTEN_USBPWRRDY_Pos (2UL)
- #define USBREG_INTEN_USBPWRRDY_Msk (0x1UL << USBREG_INTEN_USBPWRRDY_Pos)
- #define USBREG_INTEN_USBPWRRDY_Disabled (0UL)
- #define USBREG_INTEN_USBPWRRDY_Enabled (1UL)
- #define USBREG_INTEN_USBREMOVED_Pos (1UL)
- #define USBREG_INTEN_USBREMOVED_Msk (0x1UL << USBREG_INTEN_USBREMOVED_Pos)
- #define USBREG_INTEN_USBREMOVED_Disabled (0UL)
- #define USBREG_INTEN_USBREMOVED_Enabled (1UL)
- #define USBREG_INTEN_USBDETECTED_Pos (0UL)
- #define USBREG_INTEN_USBDETECTED_Msk (0x1UL << USBREG_INTEN_USBDETECTED_Pos)
- #define USBREG_INTEN_USBDETECTED_Disabled (0UL)
- #define USBREG_INTEN_USBDETECTED_Enabled (1UL)
- #define USBREG_INTENSET_USBPWRRDY_Pos (2UL)
- #define USBREG_INTENSET_USBPWRRDY_Msk (0x1UL << USBREG_INTENSET_USBPWRRDY_Pos)
- #define USBREG_INTENSET_USBPWRRDY_Disabled (0UL)
- #define USBREG_INTENSET_USBPWRRDY_Enabled (1UL)
- #define USBREG_INTENSET_USBPWRRDY_Set (1UL)
- #define USBREG_INTENSET_USBREMOVED_Pos (1UL)
- #define USBREG_INTENSET_USBREMOVED_Msk (0x1UL << USBREG_INTENSET_USBREMOVED_Pos)
- #define USBREG_INTENSET_USBREMOVED_Disabled (0UL)
- #define USBREG_INTENSET_USBREMOVED_Enabled (1UL)
- #define USBREG_INTENSET_USBREMOVED_Set (1UL)
- #define USBREG_INTENSET_USBDETECTED_Pos (0UL)
- #define USBREG_INTENSET_USBDETECTED_Msk (0x1UL << USBREG_INTENSET_USBDETECTED_Pos)
- #define USBREG_INTENSET_USBDETECTED_Disabled (0UL)
- #define USBREG_INTENSET_USBDETECTED_Enabled (1UL)
- #define USBREG_INTENSET_USBDETECTED_Set (1UL)
- #define USBREG_INTENCLR_USBPWRRDY_Pos (2UL)
- #define USBREG_INTENCLR_USBPWRRDY_Msk (0x1UL << USBREG_INTENCLR_USBPWRRDY_Pos)
- #define USBREG_INTENCLR_USBPWRRDY_Disabled (0UL)
- #define USBREG_INTENCLR_USBPWRRDY_Enabled (1UL)
- #define USBREG_INTENCLR_USBPWRRDY_Clear (1UL)
- #define USBREG_INTENCLR_USBREMOVED_Pos (1UL)
- #define USBREG_INTENCLR_USBREMOVED_Msk (0x1UL << USBREG_INTENCLR_USBREMOVED_Pos)
- #define USBREG_INTENCLR_USBREMOVED_Disabled (0UL)
- #define USBREG_INTENCLR_USBREMOVED_Enabled (1UL)
- #define USBREG_INTENCLR_USBREMOVED_Clear (1UL)
- #define USBREG_INTENCLR_USBDETECTED_Pos (0UL)
- #define USBREG_INTENCLR_USBDETECTED_Msk (0x1UL << USBREG_INTENCLR_USBDETECTED_Pos)
- #define USBREG_INTENCLR_USBDETECTED_Disabled (0UL)
- #define USBREG_INTENCLR_USBDETECTED_Enabled (1UL)
- #define USBREG_INTENCLR_USBDETECTED_Clear (1UL)
- #define USBREG_USBREGSTATUS_OUTPUTRDY_Pos (1UL)
- #define USBREG_USBREGSTATUS_OUTPUTRDY_Msk (0x1UL << USBREG_USBREGSTATUS_OUTPUTRDY_Pos)
- #define USBREG_USBREGSTATUS_OUTPUTRDY_NotReady (0UL)
- #define USBREG_USBREGSTATUS_OUTPUTRDY_Ready (1UL)
- #define USBREG_USBREGSTATUS_VBUSDETECT_Pos (0UL)
- #define USBREG_USBREGSTATUS_VBUSDETECT_Msk (0x1UL << USBREG_USBREGSTATUS_VBUSDETECT_Pos)
- #define USBREG_USBREGSTATUS_VBUSDETECT_NoVbus (0UL)
- #define USBREG_USBREGSTATUS_VBUSDETECT_VbusPresent (1UL)
- #define VMC_RAM_POWER_S15RETENTION_Pos (31UL)
- #define VMC_RAM_POWER_S15RETENTION_Msk (0x1UL << VMC_RAM_POWER_S15RETENTION_Pos)
- #define VMC_RAM_POWER_S15RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S15RETENTION_On (1UL)
- #define VMC_RAM_POWER_S14RETENTION_Pos (30UL)
- #define VMC_RAM_POWER_S14RETENTION_Msk (0x1UL << VMC_RAM_POWER_S14RETENTION_Pos)
- #define VMC_RAM_POWER_S14RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S14RETENTION_On (1UL)
- #define VMC_RAM_POWER_S13RETENTION_Pos (29UL)
- #define VMC_RAM_POWER_S13RETENTION_Msk (0x1UL << VMC_RAM_POWER_S13RETENTION_Pos)
- #define VMC_RAM_POWER_S13RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S13RETENTION_On (1UL)
- #define VMC_RAM_POWER_S12RETENTION_Pos (28UL)
- #define VMC_RAM_POWER_S12RETENTION_Msk (0x1UL << VMC_RAM_POWER_S12RETENTION_Pos)
- #define VMC_RAM_POWER_S12RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S12RETENTION_On (1UL)
- #define VMC_RAM_POWER_S11RETENTION_Pos (27UL)
- #define VMC_RAM_POWER_S11RETENTION_Msk (0x1UL << VMC_RAM_POWER_S11RETENTION_Pos)
- #define VMC_RAM_POWER_S11RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S11RETENTION_On (1UL)
- #define VMC_RAM_POWER_S10RETENTION_Pos (26UL)
- #define VMC_RAM_POWER_S10RETENTION_Msk (0x1UL << VMC_RAM_POWER_S10RETENTION_Pos)
- #define VMC_RAM_POWER_S10RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S10RETENTION_On (1UL)
- #define VMC_RAM_POWER_S9RETENTION_Pos (25UL)
- #define VMC_RAM_POWER_S9RETENTION_Msk (0x1UL << VMC_RAM_POWER_S9RETENTION_Pos)
- #define VMC_RAM_POWER_S9RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S9RETENTION_On (1UL)
- #define VMC_RAM_POWER_S8RETENTION_Pos (24UL)
- #define VMC_RAM_POWER_S8RETENTION_Msk (0x1UL << VMC_RAM_POWER_S8RETENTION_Pos)
- #define VMC_RAM_POWER_S8RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S8RETENTION_On (1UL)
- #define VMC_RAM_POWER_S7RETENTION_Pos (23UL)
- #define VMC_RAM_POWER_S7RETENTION_Msk (0x1UL << VMC_RAM_POWER_S7RETENTION_Pos)
- #define VMC_RAM_POWER_S7RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S7RETENTION_On (1UL)
- #define VMC_RAM_POWER_S6RETENTION_Pos (22UL)
- #define VMC_RAM_POWER_S6RETENTION_Msk (0x1UL << VMC_RAM_POWER_S6RETENTION_Pos)
- #define VMC_RAM_POWER_S6RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S6RETENTION_On (1UL)
- #define VMC_RAM_POWER_S5RETENTION_Pos (21UL)
- #define VMC_RAM_POWER_S5RETENTION_Msk (0x1UL << VMC_RAM_POWER_S5RETENTION_Pos)
- #define VMC_RAM_POWER_S5RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S5RETENTION_On (1UL)
- #define VMC_RAM_POWER_S4RETENTION_Pos (20UL)
- #define VMC_RAM_POWER_S4RETENTION_Msk (0x1UL << VMC_RAM_POWER_S4RETENTION_Pos)
- #define VMC_RAM_POWER_S4RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S4RETENTION_On (1UL)
- #define VMC_RAM_POWER_S3RETENTION_Pos (19UL)
- #define VMC_RAM_POWER_S3RETENTION_Msk (0x1UL << VMC_RAM_POWER_S3RETENTION_Pos)
- #define VMC_RAM_POWER_S3RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S3RETENTION_On (1UL)
- #define VMC_RAM_POWER_S2RETENTION_Pos (18UL)
- #define VMC_RAM_POWER_S2RETENTION_Msk (0x1UL << VMC_RAM_POWER_S2RETENTION_Pos)
- #define VMC_RAM_POWER_S2RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S2RETENTION_On (1UL)
- #define VMC_RAM_POWER_S1RETENTION_Pos (17UL)
- #define VMC_RAM_POWER_S1RETENTION_Msk (0x1UL << VMC_RAM_POWER_S1RETENTION_Pos)
- #define VMC_RAM_POWER_S1RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S1RETENTION_On (1UL)
- #define VMC_RAM_POWER_S0RETENTION_Pos (16UL)
- #define VMC_RAM_POWER_S0RETENTION_Msk (0x1UL << VMC_RAM_POWER_S0RETENTION_Pos)
- #define VMC_RAM_POWER_S0RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S0RETENTION_On (1UL)
- #define VMC_RAM_POWER_S15POWER_Pos (15UL)
- #define VMC_RAM_POWER_S15POWER_Msk (0x1UL << VMC_RAM_POWER_S15POWER_Pos)
- #define VMC_RAM_POWER_S15POWER_Off (0UL)
- #define VMC_RAM_POWER_S15POWER_On (1UL)
- #define VMC_RAM_POWER_S14POWER_Pos (14UL)
- #define VMC_RAM_POWER_S14POWER_Msk (0x1UL << VMC_RAM_POWER_S14POWER_Pos)
- #define VMC_RAM_POWER_S14POWER_Off (0UL)
- #define VMC_RAM_POWER_S14POWER_On (1UL)
- #define VMC_RAM_POWER_S13POWER_Pos (13UL)
- #define VMC_RAM_POWER_S13POWER_Msk (0x1UL << VMC_RAM_POWER_S13POWER_Pos)
- #define VMC_RAM_POWER_S13POWER_Off (0UL)
- #define VMC_RAM_POWER_S13POWER_On (1UL)
- #define VMC_RAM_POWER_S12POWER_Pos (12UL)
- #define VMC_RAM_POWER_S12POWER_Msk (0x1UL << VMC_RAM_POWER_S12POWER_Pos)
- #define VMC_RAM_POWER_S12POWER_Off (0UL)
- #define VMC_RAM_POWER_S12POWER_On (1UL)
- #define VMC_RAM_POWER_S11POWER_Pos (11UL)
- #define VMC_RAM_POWER_S11POWER_Msk (0x1UL << VMC_RAM_POWER_S11POWER_Pos)
- #define VMC_RAM_POWER_S11POWER_Off (0UL)
- #define VMC_RAM_POWER_S11POWER_On (1UL)
- #define VMC_RAM_POWER_S10POWER_Pos (10UL)
- #define VMC_RAM_POWER_S10POWER_Msk (0x1UL << VMC_RAM_POWER_S10POWER_Pos)
- #define VMC_RAM_POWER_S10POWER_Off (0UL)
- #define VMC_RAM_POWER_S10POWER_On (1UL)
- #define VMC_RAM_POWER_S9POWER_Pos (9UL)
- #define VMC_RAM_POWER_S9POWER_Msk (0x1UL << VMC_RAM_POWER_S9POWER_Pos)
- #define VMC_RAM_POWER_S9POWER_Off (0UL)
- #define VMC_RAM_POWER_S9POWER_On (1UL)
- #define VMC_RAM_POWER_S8POWER_Pos (8UL)
- #define VMC_RAM_POWER_S8POWER_Msk (0x1UL << VMC_RAM_POWER_S8POWER_Pos)
- #define VMC_RAM_POWER_S8POWER_Off (0UL)
- #define VMC_RAM_POWER_S8POWER_On (1UL)
- #define VMC_RAM_POWER_S7POWER_Pos (7UL)
- #define VMC_RAM_POWER_S7POWER_Msk (0x1UL << VMC_RAM_POWER_S7POWER_Pos)
- #define VMC_RAM_POWER_S7POWER_Off (0UL)
- #define VMC_RAM_POWER_S7POWER_On (1UL)
- #define VMC_RAM_POWER_S6POWER_Pos (6UL)
- #define VMC_RAM_POWER_S6POWER_Msk (0x1UL << VMC_RAM_POWER_S6POWER_Pos)
- #define VMC_RAM_POWER_S6POWER_Off (0UL)
- #define VMC_RAM_POWER_S6POWER_On (1UL)
- #define VMC_RAM_POWER_S5POWER_Pos (5UL)
- #define VMC_RAM_POWER_S5POWER_Msk (0x1UL << VMC_RAM_POWER_S5POWER_Pos)
- #define VMC_RAM_POWER_S5POWER_Off (0UL)
- #define VMC_RAM_POWER_S5POWER_On (1UL)
- #define VMC_RAM_POWER_S4POWER_Pos (4UL)
- #define VMC_RAM_POWER_S4POWER_Msk (0x1UL << VMC_RAM_POWER_S4POWER_Pos)
- #define VMC_RAM_POWER_S4POWER_Off (0UL)
- #define VMC_RAM_POWER_S4POWER_On (1UL)
- #define VMC_RAM_POWER_S3POWER_Pos (3UL)
- #define VMC_RAM_POWER_S3POWER_Msk (0x1UL << VMC_RAM_POWER_S3POWER_Pos)
- #define VMC_RAM_POWER_S3POWER_Off (0UL)
- #define VMC_RAM_POWER_S3POWER_On (1UL)
- #define VMC_RAM_POWER_S2POWER_Pos (2UL)
- #define VMC_RAM_POWER_S2POWER_Msk (0x1UL << VMC_RAM_POWER_S2POWER_Pos)
- #define VMC_RAM_POWER_S2POWER_Off (0UL)
- #define VMC_RAM_POWER_S2POWER_On (1UL)
- #define VMC_RAM_POWER_S1POWER_Pos (1UL)
- #define VMC_RAM_POWER_S1POWER_Msk (0x1UL << VMC_RAM_POWER_S1POWER_Pos)
- #define VMC_RAM_POWER_S1POWER_Off (0UL)
- #define VMC_RAM_POWER_S1POWER_On (1UL)
- #define VMC_RAM_POWER_S0POWER_Pos (0UL)
- #define VMC_RAM_POWER_S0POWER_Msk (0x1UL << VMC_RAM_POWER_S0POWER_Pos)
- #define VMC_RAM_POWER_S0POWER_Off (0UL)
- #define VMC_RAM_POWER_S0POWER_On (1UL)
- #define VMC_RAM_POWERSET_S15RETENTION_Pos (31UL)
- #define VMC_RAM_POWERSET_S15RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S15RETENTION_Pos)
- #define VMC_RAM_POWERSET_S15RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S14RETENTION_Pos (30UL)
- #define VMC_RAM_POWERSET_S14RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S14RETENTION_Pos)
- #define VMC_RAM_POWERSET_S14RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S13RETENTION_Pos (29UL)
- #define VMC_RAM_POWERSET_S13RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S13RETENTION_Pos)
- #define VMC_RAM_POWERSET_S13RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S12RETENTION_Pos (28UL)
- #define VMC_RAM_POWERSET_S12RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S12RETENTION_Pos)
- #define VMC_RAM_POWERSET_S12RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S11RETENTION_Pos (27UL)
- #define VMC_RAM_POWERSET_S11RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S11RETENTION_Pos)
- #define VMC_RAM_POWERSET_S11RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S10RETENTION_Pos (26UL)
- #define VMC_RAM_POWERSET_S10RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S10RETENTION_Pos)
- #define VMC_RAM_POWERSET_S10RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S9RETENTION_Pos (25UL)
- #define VMC_RAM_POWERSET_S9RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S9RETENTION_Pos)
- #define VMC_RAM_POWERSET_S9RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S8RETENTION_Pos (24UL)
- #define VMC_RAM_POWERSET_S8RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S8RETENTION_Pos)
- #define VMC_RAM_POWERSET_S8RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S7RETENTION_Pos (23UL)
- #define VMC_RAM_POWERSET_S7RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S7RETENTION_Pos)
- #define VMC_RAM_POWERSET_S7RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S6RETENTION_Pos (22UL)
- #define VMC_RAM_POWERSET_S6RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S6RETENTION_Pos)
- #define VMC_RAM_POWERSET_S6RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S5RETENTION_Pos (21UL)
- #define VMC_RAM_POWERSET_S5RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S5RETENTION_Pos)
- #define VMC_RAM_POWERSET_S5RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S4RETENTION_Pos (20UL)
- #define VMC_RAM_POWERSET_S4RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S4RETENTION_Pos)
- #define VMC_RAM_POWERSET_S4RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S3RETENTION_Pos (19UL)
- #define VMC_RAM_POWERSET_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S3RETENTION_Pos)
- #define VMC_RAM_POWERSET_S3RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S2RETENTION_Pos (18UL)
- #define VMC_RAM_POWERSET_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S2RETENTION_Pos)
- #define VMC_RAM_POWERSET_S2RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S1RETENTION_Pos (17UL)
- #define VMC_RAM_POWERSET_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S1RETENTION_Pos)
- #define VMC_RAM_POWERSET_S1RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S0RETENTION_Pos (16UL)
- #define VMC_RAM_POWERSET_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S0RETENTION_Pos)
- #define VMC_RAM_POWERSET_S0RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S15POWER_Pos (15UL)
- #define VMC_RAM_POWERSET_S15POWER_Msk (0x1UL << VMC_RAM_POWERSET_S15POWER_Pos)
- #define VMC_RAM_POWERSET_S15POWER_On (1UL)
- #define VMC_RAM_POWERSET_S14POWER_Pos (14UL)
- #define VMC_RAM_POWERSET_S14POWER_Msk (0x1UL << VMC_RAM_POWERSET_S14POWER_Pos)
- #define VMC_RAM_POWERSET_S14POWER_On (1UL)
- #define VMC_RAM_POWERSET_S13POWER_Pos (13UL)
- #define VMC_RAM_POWERSET_S13POWER_Msk (0x1UL << VMC_RAM_POWERSET_S13POWER_Pos)
- #define VMC_RAM_POWERSET_S13POWER_On (1UL)
- #define VMC_RAM_POWERSET_S12POWER_Pos (12UL)
- #define VMC_RAM_POWERSET_S12POWER_Msk (0x1UL << VMC_RAM_POWERSET_S12POWER_Pos)
- #define VMC_RAM_POWERSET_S12POWER_On (1UL)
- #define VMC_RAM_POWERSET_S11POWER_Pos (11UL)
- #define VMC_RAM_POWERSET_S11POWER_Msk (0x1UL << VMC_RAM_POWERSET_S11POWER_Pos)
- #define VMC_RAM_POWERSET_S11POWER_On (1UL)
- #define VMC_RAM_POWERSET_S10POWER_Pos (10UL)
- #define VMC_RAM_POWERSET_S10POWER_Msk (0x1UL << VMC_RAM_POWERSET_S10POWER_Pos)
- #define VMC_RAM_POWERSET_S10POWER_On (1UL)
- #define VMC_RAM_POWERSET_S9POWER_Pos (9UL)
- #define VMC_RAM_POWERSET_S9POWER_Msk (0x1UL << VMC_RAM_POWERSET_S9POWER_Pos)
- #define VMC_RAM_POWERSET_S9POWER_On (1UL)
- #define VMC_RAM_POWERSET_S8POWER_Pos (8UL)
- #define VMC_RAM_POWERSET_S8POWER_Msk (0x1UL << VMC_RAM_POWERSET_S8POWER_Pos)
- #define VMC_RAM_POWERSET_S8POWER_On (1UL)
- #define VMC_RAM_POWERSET_S7POWER_Pos (7UL)
- #define VMC_RAM_POWERSET_S7POWER_Msk (0x1UL << VMC_RAM_POWERSET_S7POWER_Pos)
- #define VMC_RAM_POWERSET_S7POWER_On (1UL)
- #define VMC_RAM_POWERSET_S6POWER_Pos (6UL)
- #define VMC_RAM_POWERSET_S6POWER_Msk (0x1UL << VMC_RAM_POWERSET_S6POWER_Pos)
- #define VMC_RAM_POWERSET_S6POWER_On (1UL)
- #define VMC_RAM_POWERSET_S5POWER_Pos (5UL)
- #define VMC_RAM_POWERSET_S5POWER_Msk (0x1UL << VMC_RAM_POWERSET_S5POWER_Pos)
- #define VMC_RAM_POWERSET_S5POWER_On (1UL)
- #define VMC_RAM_POWERSET_S4POWER_Pos (4UL)
- #define VMC_RAM_POWERSET_S4POWER_Msk (0x1UL << VMC_RAM_POWERSET_S4POWER_Pos)
- #define VMC_RAM_POWERSET_S4POWER_On (1UL)
- #define VMC_RAM_POWERSET_S3POWER_Pos (3UL)
- #define VMC_RAM_POWERSET_S3POWER_Msk (0x1UL << VMC_RAM_POWERSET_S3POWER_Pos)
- #define VMC_RAM_POWERSET_S3POWER_On (1UL)
- #define VMC_RAM_POWERSET_S2POWER_Pos (2UL)
- #define VMC_RAM_POWERSET_S2POWER_Msk (0x1UL << VMC_RAM_POWERSET_S2POWER_Pos)
- #define VMC_RAM_POWERSET_S2POWER_On (1UL)
- #define VMC_RAM_POWERSET_S1POWER_Pos (1UL)
- #define VMC_RAM_POWERSET_S1POWER_Msk (0x1UL << VMC_RAM_POWERSET_S1POWER_Pos)
- #define VMC_RAM_POWERSET_S1POWER_On (1UL)
- #define VMC_RAM_POWERSET_S0POWER_Pos (0UL)
- #define VMC_RAM_POWERSET_S0POWER_Msk (0x1UL << VMC_RAM_POWERSET_S0POWER_Pos)
- #define VMC_RAM_POWERSET_S0POWER_On (1UL)
- #define VMC_RAM_POWERCLR_S15RETENTION_Pos (31UL)
- #define VMC_RAM_POWERCLR_S15RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S15RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S15RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S14RETENTION_Pos (30UL)
- #define VMC_RAM_POWERCLR_S14RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S14RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S14RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S13RETENTION_Pos (29UL)
- #define VMC_RAM_POWERCLR_S13RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S13RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S13RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S12RETENTION_Pos (28UL)
- #define VMC_RAM_POWERCLR_S12RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S12RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S12RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S11RETENTION_Pos (27UL)
- #define VMC_RAM_POWERCLR_S11RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S11RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S11RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S10RETENTION_Pos (26UL)
- #define VMC_RAM_POWERCLR_S10RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S10RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S10RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S9RETENTION_Pos (25UL)
- #define VMC_RAM_POWERCLR_S9RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S9RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S9RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S8RETENTION_Pos (24UL)
- #define VMC_RAM_POWERCLR_S8RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S8RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S8RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S7RETENTION_Pos (23UL)
- #define VMC_RAM_POWERCLR_S7RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S7RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S7RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S6RETENTION_Pos (22UL)
- #define VMC_RAM_POWERCLR_S6RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S6RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S6RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S5RETENTION_Pos (21UL)
- #define VMC_RAM_POWERCLR_S5RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S5RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S5RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S4RETENTION_Pos (20UL)
- #define VMC_RAM_POWERCLR_S4RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S4RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S4RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S3RETENTION_Pos (19UL)
- #define VMC_RAM_POWERCLR_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S3RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S3RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S2RETENTION_Pos (18UL)
- #define VMC_RAM_POWERCLR_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S2RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S2RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S1RETENTION_Pos (17UL)
- #define VMC_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S1RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S1RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S0RETENTION_Pos (16UL)
- #define VMC_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S0RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S0RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S15POWER_Pos (15UL)
- #define VMC_RAM_POWERCLR_S15POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S15POWER_Pos)
- #define VMC_RAM_POWERCLR_S15POWER_Off (1UL)
- #define VMC_RAM_POWERCLR_S14POWER_Pos (14UL)
- #define VMC_RAM_POWERCLR_S14POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S14POWER_Pos)
- #define VMC_RAM_POWERCLR_S14POWER_Off (1UL)
- #define VMC_RAM_POWERCLR_S13POWER_Pos (13UL)
- #define VMC_RAM_POWERCLR_S13POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S13POWER_Pos)
- #define VMC_RAM_POWERCLR_S13POWER_Off (1UL)
- #define VMC_RAM_POWERCLR_S12POWER_Pos (12UL)
- #define VMC_RAM_POWERCLR_S12POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S12POWER_Pos)
- #define VMC_RAM_POWERCLR_S12POWER_Off (1UL)
- #define VMC_RAM_POWERCLR_S11POWER_Pos (11UL)
- #define VMC_RAM_POWERCLR_S11POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S11POWER_Pos)
- #define VMC_RAM_POWERCLR_S11POWER_Off (1UL)
- #define VMC_RAM_POWERCLR_S10POWER_Pos (10UL)
- #define VMC_RAM_POWERCLR_S10POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S10POWER_Pos)
- #define VMC_RAM_POWERCLR_S10POWER_Off (1UL)
- #define VMC_RAM_POWERCLR_S9POWER_Pos (9UL)
- #define VMC_RAM_POWERCLR_S9POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S9POWER_Pos)
- #define VMC_RAM_POWERCLR_S9POWER_Off (1UL)
- #define VMC_RAM_POWERCLR_S8POWER_Pos (8UL)
- #define VMC_RAM_POWERCLR_S8POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S8POWER_Pos)
- #define VMC_RAM_POWERCLR_S8POWER_Off (1UL)
- #define VMC_RAM_POWERCLR_S7POWER_Pos (7UL)
- #define VMC_RAM_POWERCLR_S7POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S7POWER_Pos)
- #define VMC_RAM_POWERCLR_S7POWER_Off (1UL)
- #define VMC_RAM_POWERCLR_S6POWER_Pos (6UL)
- #define VMC_RAM_POWERCLR_S6POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S6POWER_Pos)
- #define VMC_RAM_POWERCLR_S6POWER_Off (1UL)
- #define VMC_RAM_POWERCLR_S5POWER_Pos (5UL)
- #define VMC_RAM_POWERCLR_S5POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S5POWER_Pos)
- #define VMC_RAM_POWERCLR_S5POWER_Off (1UL)
- #define VMC_RAM_POWERCLR_S4POWER_Pos (4UL)
- #define VMC_RAM_POWERCLR_S4POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S4POWER_Pos)
- #define VMC_RAM_POWERCLR_S4POWER_Off (1UL)
- #define VMC_RAM_POWERCLR_S3POWER_Pos (3UL)
- #define VMC_RAM_POWERCLR_S3POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S3POWER_Pos)
- #define VMC_RAM_POWERCLR_S3POWER_Off (1UL)
- #define VMC_RAM_POWERCLR_S2POWER_Pos (2UL)
- #define VMC_RAM_POWERCLR_S2POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S2POWER_Pos)
- #define VMC_RAM_POWERCLR_S2POWER_Off (1UL)
- #define VMC_RAM_POWERCLR_S1POWER_Pos (1UL)
- #define VMC_RAM_POWERCLR_S1POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S1POWER_Pos)
- #define VMC_RAM_POWERCLR_S1POWER_Off (1UL)
- #define VMC_RAM_POWERCLR_S0POWER_Pos (0UL)
- #define VMC_RAM_POWERCLR_S0POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S0POWER_Pos)
- #define VMC_RAM_POWERCLR_S0POWER_Off (1UL)
- #define WDT_TASKS_START_TASKS_START_Pos (0UL)
- #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos)
- #define WDT_TASKS_START_TASKS_START_Trigger (1UL)
- #define WDT_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define WDT_TASKS_STOP_TASKS_STOP_Msk (0x1UL << WDT_TASKS_STOP_TASKS_STOP_Pos)
- #define WDT_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define WDT_SUBSCRIBE_START_EN_Pos (31UL)
- #define WDT_SUBSCRIBE_START_EN_Msk (0x1UL << WDT_SUBSCRIBE_START_EN_Pos)
- #define WDT_SUBSCRIBE_START_EN_Disabled (0UL)
- #define WDT_SUBSCRIBE_START_EN_Enabled (1UL)
- #define WDT_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define WDT_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_START_CHIDX_Pos)
- #define WDT_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define WDT_SUBSCRIBE_STOP_EN_Msk (0x1UL << WDT_SUBSCRIBE_STOP_EN_Pos)
- #define WDT_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define WDT_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define WDT_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define WDT_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_STOP_CHIDX_Pos)
- #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL)
- #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos)
- #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL)
- #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL)
- #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL)
- #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << WDT_EVENTS_STOPPED_EVENTS_STOPPED_Pos)
- #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL)
- #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL)
- #define WDT_PUBLISH_TIMEOUT_EN_Pos (31UL)
- #define WDT_PUBLISH_TIMEOUT_EN_Msk (0x1UL << WDT_PUBLISH_TIMEOUT_EN_Pos)
- #define WDT_PUBLISH_TIMEOUT_EN_Disabled (0UL)
- #define WDT_PUBLISH_TIMEOUT_EN_Enabled (1UL)
- #define WDT_PUBLISH_TIMEOUT_CHIDX_Pos (0UL)
- #define WDT_PUBLISH_TIMEOUT_CHIDX_Msk (0xFFUL << WDT_PUBLISH_TIMEOUT_CHIDX_Pos)
- #define WDT_PUBLISH_STOPPED_EN_Pos (31UL)
- #define WDT_PUBLISH_STOPPED_EN_Msk (0x1UL << WDT_PUBLISH_STOPPED_EN_Pos)
- #define WDT_PUBLISH_STOPPED_EN_Disabled (0UL)
- #define WDT_PUBLISH_STOPPED_EN_Enabled (1UL)
- #define WDT_PUBLISH_STOPPED_CHIDX_Pos (0UL)
- #define WDT_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << WDT_PUBLISH_STOPPED_CHIDX_Pos)
- #define WDT_INTENSET_STOPPED_Pos (1UL)
- #define WDT_INTENSET_STOPPED_Msk (0x1UL << WDT_INTENSET_STOPPED_Pos)
- #define WDT_INTENSET_STOPPED_Disabled (0UL)
- #define WDT_INTENSET_STOPPED_Enabled (1UL)
- #define WDT_INTENSET_STOPPED_Set (1UL)
- #define WDT_INTENSET_TIMEOUT_Pos (0UL)
- #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos)
- #define WDT_INTENSET_TIMEOUT_Disabled (0UL)
- #define WDT_INTENSET_TIMEOUT_Enabled (1UL)
- #define WDT_INTENSET_TIMEOUT_Set (1UL)
- #define WDT_INTENCLR_STOPPED_Pos (1UL)
- #define WDT_INTENCLR_STOPPED_Msk (0x1UL << WDT_INTENCLR_STOPPED_Pos)
- #define WDT_INTENCLR_STOPPED_Disabled (0UL)
- #define WDT_INTENCLR_STOPPED_Enabled (1UL)
- #define WDT_INTENCLR_STOPPED_Clear (1UL)
- #define WDT_INTENCLR_TIMEOUT_Pos (0UL)
- #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos)
- #define WDT_INTENCLR_TIMEOUT_Disabled (0UL)
- #define WDT_INTENCLR_TIMEOUT_Enabled (1UL)
- #define WDT_INTENCLR_TIMEOUT_Clear (1UL)
- #define WDT_NMIENSET_STOPPED_Pos (1UL)
- #define WDT_NMIENSET_STOPPED_Msk (0x1UL << WDT_NMIENSET_STOPPED_Pos)
- #define WDT_NMIENSET_STOPPED_Disabled (0UL)
- #define WDT_NMIENSET_STOPPED_Enabled (1UL)
- #define WDT_NMIENSET_STOPPED_Set (1UL)
- #define WDT_NMIENSET_TIMEOUT_Pos (0UL)
- #define WDT_NMIENSET_TIMEOUT_Msk (0x1UL << WDT_NMIENSET_TIMEOUT_Pos)
- #define WDT_NMIENSET_TIMEOUT_Disabled (0UL)
- #define WDT_NMIENSET_TIMEOUT_Enabled (1UL)
- #define WDT_NMIENSET_TIMEOUT_Set (1UL)
- #define WDT_NMIENCLR_STOPPED_Pos (1UL)
- #define WDT_NMIENCLR_STOPPED_Msk (0x1UL << WDT_NMIENCLR_STOPPED_Pos)
- #define WDT_NMIENCLR_STOPPED_Disabled (0UL)
- #define WDT_NMIENCLR_STOPPED_Enabled (1UL)
- #define WDT_NMIENCLR_STOPPED_Clear (1UL)
- #define WDT_NMIENCLR_TIMEOUT_Pos (0UL)
- #define WDT_NMIENCLR_TIMEOUT_Msk (0x1UL << WDT_NMIENCLR_TIMEOUT_Pos)
- #define WDT_NMIENCLR_TIMEOUT_Disabled (0UL)
- #define WDT_NMIENCLR_TIMEOUT_Enabled (1UL)
- #define WDT_NMIENCLR_TIMEOUT_Clear (1UL)
- #define WDT_RUNSTATUS_RUNSTATUSWDT_Pos (0UL)
- #define WDT_RUNSTATUS_RUNSTATUSWDT_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUSWDT_Pos)
- #define WDT_RUNSTATUS_RUNSTATUSWDT_NotRunning (0UL)
- #define WDT_RUNSTATUS_RUNSTATUSWDT_Running (1UL)
- #define WDT_REQSTATUS_RR7_Pos (7UL)
- #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos)
- #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL)
- #define WDT_REQSTATUS_RR6_Pos (6UL)
- #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos)
- #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL)
- #define WDT_REQSTATUS_RR5_Pos (5UL)
- #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos)
- #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL)
- #define WDT_REQSTATUS_RR4_Pos (4UL)
- #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos)
- #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL)
- #define WDT_REQSTATUS_RR3_Pos (3UL)
- #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos)
- #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL)
- #define WDT_REQSTATUS_RR2_Pos (2UL)
- #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos)
- #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL)
- #define WDT_REQSTATUS_RR1_Pos (1UL)
- #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos)
- #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL)
- #define WDT_REQSTATUS_RR0_Pos (0UL)
- #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos)
- #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL)
- #define WDT_CRV_CRV_Pos (0UL)
- #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos)
- #define WDT_RREN_RR7_Pos (7UL)
- #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos)
- #define WDT_RREN_RR7_Disabled (0UL)
- #define WDT_RREN_RR7_Enabled (1UL)
- #define WDT_RREN_RR6_Pos (6UL)
- #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos)
- #define WDT_RREN_RR6_Disabled (0UL)
- #define WDT_RREN_RR6_Enabled (1UL)
- #define WDT_RREN_RR5_Pos (5UL)
- #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos)
- #define WDT_RREN_RR5_Disabled (0UL)
- #define WDT_RREN_RR5_Enabled (1UL)
- #define WDT_RREN_RR4_Pos (4UL)
- #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos)
- #define WDT_RREN_RR4_Disabled (0UL)
- #define WDT_RREN_RR4_Enabled (1UL)
- #define WDT_RREN_RR3_Pos (3UL)
- #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos)
- #define WDT_RREN_RR3_Disabled (0UL)
- #define WDT_RREN_RR3_Enabled (1UL)
- #define WDT_RREN_RR2_Pos (2UL)
- #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos)
- #define WDT_RREN_RR2_Disabled (0UL)
- #define WDT_RREN_RR2_Enabled (1UL)
- #define WDT_RREN_RR1_Pos (1UL)
- #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos)
- #define WDT_RREN_RR1_Disabled (0UL)
- #define WDT_RREN_RR1_Enabled (1UL)
- #define WDT_RREN_RR0_Pos (0UL)
- #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos)
- #define WDT_RREN_RR0_Disabled (0UL)
- #define WDT_RREN_RR0_Enabled (1UL)
- #define WDT_CONFIG_STOPEN_Pos (6UL)
- #define WDT_CONFIG_STOPEN_Msk (0x1UL << WDT_CONFIG_STOPEN_Pos)
- #define WDT_CONFIG_STOPEN_Disable (0UL)
- #define WDT_CONFIG_STOPEN_Enable (1UL)
- #define WDT_CONFIG_HALT_Pos (3UL)
- #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos)
- #define WDT_CONFIG_HALT_Pause (0UL)
- #define WDT_CONFIG_HALT_Run (1UL)
- #define WDT_CONFIG_SLEEP_Pos (0UL)
- #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos)
- #define WDT_CONFIG_SLEEP_Pause (0UL)
- #define WDT_CONFIG_SLEEP_Run (1UL)
- #define WDT_TSEN_TSEN_Pos (0UL)
- #define WDT_TSEN_TSEN_Msk (0xFFFFFFFFUL << WDT_TSEN_TSEN_Pos)
- #define WDT_TSEN_TSEN_Enable (0x6E524635UL)
- #define WDT_RR_RR_Pos (0UL)
- #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos)
- #define WDT_RR_RR_Reload (0x6E524635UL)
- #endif
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