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- #ifndef NRF52833_H
- #define NRF52833_H
- #ifdef __cplusplus
- extern "C" {
- #endif
- typedef enum {
- Reset_IRQn = -15,
- NonMaskableInt_IRQn = -14,
- HardFault_IRQn = -13,
- MemoryManagement_IRQn = -12,
- BusFault_IRQn = -11,
- UsageFault_IRQn = -10,
- SVCall_IRQn = -5,
- DebugMonitor_IRQn = -4,
- PendSV_IRQn = -2,
- SysTick_IRQn = -1,
- POWER_CLOCK_IRQn = 0,
- RADIO_IRQn = 1,
- UARTE0_UART0_IRQn = 2,
- SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3,
- SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4,
- NFCT_IRQn = 5,
- GPIOTE_IRQn = 6,
- SAADC_IRQn = 7,
- TIMER0_IRQn = 8,
- TIMER1_IRQn = 9,
- TIMER2_IRQn = 10,
- RTC0_IRQn = 11,
- TEMP_IRQn = 12,
- RNG_IRQn = 13,
- ECB_IRQn = 14,
- CCM_AAR_IRQn = 15,
- WDT_IRQn = 16,
- RTC1_IRQn = 17,
- QDEC_IRQn = 18,
- COMP_LPCOMP_IRQn = 19,
- SWI0_EGU0_IRQn = 20,
- SWI1_EGU1_IRQn = 21,
- SWI2_EGU2_IRQn = 22,
- SWI3_EGU3_IRQn = 23,
- SWI4_EGU4_IRQn = 24,
- SWI5_EGU5_IRQn = 25,
- TIMER3_IRQn = 26,
- TIMER4_IRQn = 27,
- PWM0_IRQn = 28,
- PDM_IRQn = 29,
- MWU_IRQn = 32,
- PWM1_IRQn = 33,
- PWM2_IRQn = 34,
- SPIM2_SPIS2_SPI2_IRQn = 35,
- RTC2_IRQn = 36,
- I2S_IRQn = 37,
- FPU_IRQn = 38,
- USBD_IRQn = 39,
- UARTE1_IRQn = 40,
- PWM3_IRQn = 45,
- SPIM3_IRQn = 47
- } IRQn_Type;
- #define __CM4_REV 0x0001U
- #define __DSP_PRESENT 1
- #define __VTOR_PRESENT 1
- #define __NVIC_PRIO_BITS 3
- #define __Vendor_SysTickConfig 0
- #define __MPU_PRESENT 1
- #define __FPU_PRESENT 1
-
- #include "core_cm4.h"
- #include "system_nrf52833.h"
- #ifndef __IM
- #define __IM __I
- #endif
- #ifndef __OM
- #define __OM __O
- #endif
- #ifndef __IOM
- #define __IOM __IO
- #endif
- #if defined (__CC_ARM)
- #pragma push
- #pragma anon_unions
- #elif defined (__ICCARM__)
- #pragma language=extended
- #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang diagnostic push
- #pragma clang diagnostic ignored "-Wc11-extensions"
- #pragma clang diagnostic ignored "-Wreserved-id-macro"
- #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
- #pragma clang diagnostic ignored "-Wnested-anon-types"
- #elif defined (__GNUC__)
-
- #elif defined (__TMS470__)
-
- #elif defined (__TASKING__)
- #pragma warning 586
- #elif defined (__CSMC__)
-
- #else
- #warning Not supported compiler type
- #endif
- typedef struct {
- __IM uint32_t PART;
- __IM uint32_t VARIANT;
- __IM uint32_t PACKAGE;
- __IM uint32_t RAM;
- __IM uint32_t FLASH;
- } FICR_INFO_Type;
- typedef struct {
- __IM uint32_t A0;
- __IM uint32_t A1;
- __IM uint32_t A2;
- __IM uint32_t A3;
- __IM uint32_t A4;
- __IM uint32_t A5;
- __IM uint32_t B0;
- __IM uint32_t B1;
- __IM uint32_t B2;
- __IM uint32_t B3;
- __IM uint32_t B4;
- __IM uint32_t B5;
- __IM uint32_t T0;
- __IM uint32_t T1;
- __IM uint32_t T2;
- __IM uint32_t T3;
- __IM uint32_t T4;
- } FICR_TEMP_Type;
- typedef struct {
- __IM uint32_t TAGHEADER0;
- __IM uint32_t TAGHEADER1;
- __IM uint32_t TAGHEADER2;
- __IM uint32_t TAGHEADER3;
- } FICR_NFC_Type;
- typedef struct {
- __IOM uint32_t POWER;
- __OM uint32_t POWERSET;
- __OM uint32_t POWERCLR;
- __IM uint32_t RESERVED;
- } POWER_RAM_Type;
- typedef struct {
- __IOM uint32_t DFEGPIO[8];
- } RADIO_PSEL_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- } RADIO_DFEPACKET_Type;
- typedef struct {
- __IOM uint32_t RTS;
- __IOM uint32_t TXD;
- __IOM uint32_t CTS;
- __IOM uint32_t RXD;
- } UART_PSEL_Type;
- typedef struct {
- __IOM uint32_t RTS;
- __IOM uint32_t TXD;
- __IOM uint32_t CTS;
- __IOM uint32_t RXD;
- } UARTE_PSEL_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- } UARTE_RXD_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- } UARTE_TXD_Type;
- typedef struct {
- __IOM uint32_t SCK;
- __IOM uint32_t MOSI;
- __IOM uint32_t MISO;
- } SPI_PSEL_Type;
- typedef struct {
- __IOM uint32_t SCK;
- __IOM uint32_t MOSI;
- __IOM uint32_t MISO;
- __IOM uint32_t CSN;
- } SPIM_PSEL_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- __IOM uint32_t LIST;
- } SPIM_RXD_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- __IOM uint32_t LIST;
- } SPIM_TXD_Type;
- typedef struct {
- __IOM uint32_t RXDELAY;
- __IOM uint32_t CSNDUR;
- } SPIM_IFTIMING_Type;
- typedef struct {
- __IOM uint32_t SCK;
- __IOM uint32_t MISO;
- __IOM uint32_t MOSI;
- __IOM uint32_t CSN;
- } SPIS_PSEL_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- __IOM uint32_t LIST;
- } SPIS_RXD_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- __IOM uint32_t LIST;
- } SPIS_TXD_Type;
- typedef struct {
- __IOM uint32_t SCL;
- __IOM uint32_t SDA;
- } TWI_PSEL_Type;
- typedef struct {
- __IOM uint32_t SCL;
- __IOM uint32_t SDA;
- } TWIM_PSEL_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- __IOM uint32_t LIST;
- } TWIM_RXD_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- __IOM uint32_t LIST;
- } TWIM_TXD_Type;
- typedef struct {
- __IOM uint32_t SCL;
- __IOM uint32_t SDA;
- } TWIS_PSEL_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- __IOM uint32_t LIST;
- } TWIS_RXD_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- __IOM uint32_t LIST;
- } TWIS_TXD_Type;
- typedef struct {
- __IOM uint32_t RX;
- } NFCT_FRAMESTATUS_Type;
- typedef struct {
- __IOM uint32_t FRAMECONFIG;
- __IOM uint32_t AMOUNT;
- } NFCT_TXD_Type;
- typedef struct {
- __IOM uint32_t FRAMECONFIG;
- __IM uint32_t AMOUNT;
- } NFCT_RXD_Type;
- typedef struct {
- __IOM uint32_t LIMITH;
- __IOM uint32_t LIMITL;
- } SAADC_EVENTS_CH_Type;
- typedef struct {
- __IOM uint32_t PSELP;
- __IOM uint32_t PSELN;
- __IOM uint32_t CONFIG;
- __IOM uint32_t LIMIT;
- } SAADC_CH_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- } SAADC_RESULT_Type;
- typedef struct {
- __IOM uint32_t LED;
- __IOM uint32_t A;
- __IOM uint32_t B;
- } QDEC_PSEL_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t CNT;
- __IOM uint32_t REFRESH;
- __IOM uint32_t ENDDELAY;
- __IM uint32_t RESERVED[4];
- } PWM_SEQ_Type;
- typedef struct {
- __IOM uint32_t OUT[4];
- } PWM_PSEL_Type;
- typedef struct {
- __IOM uint32_t CLK;
- __IOM uint32_t DIN;
- } PDM_PSEL_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- } PDM_SAMPLE_Type;
- typedef struct {
- __IOM uint32_t ADDR;
- __IOM uint32_t SIZE;
- __IOM uint32_t PERM;
- __IM uint32_t RESERVED;
- } ACL_ACL_Type;
- typedef struct {
- __OM uint32_t EN;
- __OM uint32_t DIS;
- } PPI_TASKS_CHG_Type;
- typedef struct {
- __IOM uint32_t EEP;
- __IOM uint32_t TEP;
- } PPI_CH_Type;
- typedef struct {
- __IOM uint32_t TEP;
- } PPI_FORK_Type;
- typedef struct {
- __IOM uint32_t WA;
- __IOM uint32_t RA;
- } MWU_EVENTS_REGION_Type;
- typedef struct {
- __IOM uint32_t WA;
- __IOM uint32_t RA;
- } MWU_EVENTS_PREGION_Type;
- typedef struct {
- __IOM uint32_t SUBSTATWA;
- __IOM uint32_t SUBSTATRA;
- } MWU_PERREGION_Type;
- typedef struct {
- __IOM uint32_t START;
- __IOM uint32_t END;
- __IM uint32_t RESERVED[2];
- } MWU_REGION_Type;
- typedef struct {
- __IM uint32_t START;
- __IM uint32_t END;
- __IOM uint32_t SUBS;
- __IM uint32_t RESERVED;
- } MWU_PREGION_Type;
- typedef struct {
- __IOM uint32_t MODE;
- __IOM uint32_t RXEN;
- __IOM uint32_t TXEN;
- __IOM uint32_t MCKEN;
- __IOM uint32_t MCKFREQ;
- __IOM uint32_t RATIO;
- __IOM uint32_t SWIDTH;
- __IOM uint32_t ALIGN;
- __IOM uint32_t FORMAT;
- __IOM uint32_t CHANNELS;
- } I2S_CONFIG_Type;
- typedef struct {
- __IOM uint32_t PTR;
- } I2S_RXD_Type;
- typedef struct {
- __IOM uint32_t PTR;
- } I2S_TXD_Type;
- typedef struct {
- __IOM uint32_t MAXCNT;
- } I2S_RXTXD_Type;
- typedef struct {
- __IOM uint32_t MCK;
- __IOM uint32_t SCK;
- __IOM uint32_t LRCK;
- __IOM uint32_t SDIN;
- __IOM uint32_t SDOUT;
- } I2S_PSEL_Type;
- typedef struct {
- __IM uint32_t EPIN[8];
- __IM uint32_t RESERVED;
- __IM uint32_t EPOUT[8];
- } USBD_HALTED_Type;
- typedef struct {
- __IOM uint32_t EPOUT[8];
- __IM uint32_t ISOOUT;
- } USBD_SIZE_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- __IM uint32_t RESERVED[2];
- } USBD_EPIN_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- } USBD_ISOIN_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- __IM uint32_t RESERVED[2];
- } USBD_EPOUT_Type;
- typedef struct {
- __IOM uint32_t PTR;
- __IOM uint32_t MAXCNT;
- __IM uint32_t AMOUNT;
- } USBD_ISOOUT_Type;
-
- typedef struct {
- __IM uint32_t RESERVED[4];
- __IM uint32_t CODEPAGESIZE;
- __IM uint32_t CODESIZE;
- __IM uint32_t RESERVED1[18];
- __IM uint32_t DEVICEID[2];
- __IM uint32_t RESERVED2[6];
- __IM uint32_t ER[4];
- __IM uint32_t IR[4];
- __IM uint32_t DEVICEADDRTYPE;
- __IM uint32_t DEVICEADDR[2];
- __IM uint32_t RESERVED3[21];
- __IM FICR_INFO_Type INFO;
- __IM uint32_t RESERVED4[143];
- __IM uint32_t PRODTEST[3];
- __IM uint32_t RESERVED5[42];
- __IM FICR_TEMP_Type TEMP;
- __IM uint32_t RESERVED6[2];
- __IOM FICR_NFC_Type NFC;
- } NRF_FICR_Type;
- typedef struct {
- __IM uint32_t RESERVED[5];
- __IOM uint32_t NRFFW[13];
- __IM uint32_t RESERVED1[2];
- __IOM uint32_t NRFHW[12];
- __IOM uint32_t CUSTOMER[32];
- __IM uint32_t RESERVED2[64];
- __IOM uint32_t PSELRESET[2];
- __IOM uint32_t APPROTECT;
- __IOM uint32_t NFCPINS;
- __IOM uint32_t DEBUGCTRL;
- __IM uint32_t RESERVED3[60];
- __IOM uint32_t REGOUT0;
- } NRF_UICR_Type;
- typedef struct {
- __OM uint32_t TASKS_HFCLKSTART;
- __OM uint32_t TASKS_HFCLKSTOP;
- __OM uint32_t TASKS_LFCLKSTART;
- __OM uint32_t TASKS_LFCLKSTOP;
- __OM uint32_t TASKS_CAL;
- __OM uint32_t TASKS_CTSTART;
- __OM uint32_t TASKS_CTSTOP;
- __IM uint32_t RESERVED[57];
- __IOM uint32_t EVENTS_HFCLKSTARTED;
- __IOM uint32_t EVENTS_LFCLKSTARTED;
- __IM uint32_t RESERVED1;
- __IOM uint32_t EVENTS_DONE;
- __IOM uint32_t EVENTS_CTTO;
- __IM uint32_t RESERVED2[5];
- __IOM uint32_t EVENTS_CTSTARTED;
- __IOM uint32_t EVENTS_CTSTOPPED;
- __IM uint32_t RESERVED3[117];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED4[63];
- __IM uint32_t HFCLKRUN;
- __IM uint32_t HFCLKSTAT;
- __IM uint32_t RESERVED5;
- __IM uint32_t LFCLKRUN;
- __IM uint32_t LFCLKSTAT;
- __IM uint32_t LFCLKSRCCOPY;
- __IM uint32_t RESERVED6[62];
- __IOM uint32_t LFCLKSRC;
- __IM uint32_t RESERVED7[3];
- __IOM uint32_t HFXODEBOUNCE;
- __IOM uint32_t LFXODEBOUNCE;
- __IM uint32_t RESERVED8[2];
- __IOM uint32_t CTIV;
- __IM uint32_t RESERVED9[8];
- __IOM uint32_t TRACECONFIG;
- } NRF_CLOCK_Type;
- typedef struct {
- __IM uint32_t RESERVED[30];
- __OM uint32_t TASKS_CONSTLAT;
- __OM uint32_t TASKS_LOWPWR;
- __IM uint32_t RESERVED1[34];
- __IOM uint32_t EVENTS_POFWARN;
- __IM uint32_t RESERVED2[2];
- __IOM uint32_t EVENTS_SLEEPENTER;
- __IOM uint32_t EVENTS_SLEEPEXIT;
- __IOM uint32_t EVENTS_USBDETECTED;
- __IOM uint32_t EVENTS_USBREMOVED;
- __IOM uint32_t EVENTS_USBPWRRDY;
- __IM uint32_t RESERVED3[119];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED4[61];
- __IOM uint32_t RESETREAS;
- __IM uint32_t RESERVED5[9];
- __IM uint32_t RAMSTATUS;
- __IM uint32_t RESERVED6[3];
- __IM uint32_t USBREGSTATUS;
- __IM uint32_t RESERVED7[49];
- __OM uint32_t SYSTEMOFF;
- __IM uint32_t RESERVED8[3];
- __IOM uint32_t POFCON;
- __IM uint32_t RESERVED9[2];
- __IOM uint32_t GPREGRET;
- __IOM uint32_t GPREGRET2;
- __IM uint32_t RESERVED10[21];
- __IOM uint32_t DCDCEN;
- __IM uint32_t RESERVED11[49];
- __IM uint32_t MAINREGSTATUS;
- __IM uint32_t RESERVED12[175];
- __IOM POWER_RAM_Type RAM[9];
- } NRF_POWER_Type;
- typedef struct {
- __IM uint32_t RESERVED[321];
- __IOM uint32_t OUT;
- __IOM uint32_t OUTSET;
- __IOM uint32_t OUTCLR;
- __IM uint32_t IN;
- __IOM uint32_t DIR;
- __IOM uint32_t DIRSET;
- __IOM uint32_t DIRCLR;
- __IOM uint32_t LATCH;
- __IOM uint32_t DETECTMODE;
- __IM uint32_t RESERVED1[118];
- __IOM uint32_t PIN_CNF[32];
- } NRF_GPIO_Type;
- typedef struct {
- __OM uint32_t TASKS_TXEN;
- __OM uint32_t TASKS_RXEN;
- __OM uint32_t TASKS_START;
- __OM uint32_t TASKS_STOP;
- __OM uint32_t TASKS_DISABLE;
- __OM uint32_t TASKS_RSSISTART;
- __OM uint32_t TASKS_RSSISTOP;
- __OM uint32_t TASKS_BCSTART;
- __OM uint32_t TASKS_BCSTOP;
- __OM uint32_t TASKS_EDSTART;
- __OM uint32_t TASKS_EDSTOP;
- __OM uint32_t TASKS_CCASTART;
- __OM uint32_t TASKS_CCASTOP;
- __IM uint32_t RESERVED[51];
- __IOM uint32_t EVENTS_READY;
- __IOM uint32_t EVENTS_ADDRESS;
- __IOM uint32_t EVENTS_PAYLOAD;
- __IOM uint32_t EVENTS_END;
- __IOM uint32_t EVENTS_DISABLED;
- __IOM uint32_t EVENTS_DEVMATCH;
- __IOM uint32_t EVENTS_DEVMISS;
- __IOM uint32_t EVENTS_RSSIEND;
- __IM uint32_t RESERVED1[2];
- __IOM uint32_t EVENTS_BCMATCH;
- __IM uint32_t RESERVED2;
- __IOM uint32_t EVENTS_CRCOK;
- __IOM uint32_t EVENTS_CRCERROR;
- __IOM uint32_t EVENTS_FRAMESTART;
- __IOM uint32_t EVENTS_EDEND;
- __IOM uint32_t EVENTS_EDSTOPPED;
- __IOM uint32_t EVENTS_CCAIDLE;
- __IOM uint32_t EVENTS_CCABUSY;
- __IOM uint32_t EVENTS_CCASTOPPED;
- __IOM uint32_t EVENTS_RATEBOOST;
- __IOM uint32_t EVENTS_TXREADY;
- __IOM uint32_t EVENTS_RXREADY;
- __IOM uint32_t EVENTS_MHRMATCH;
- __IM uint32_t RESERVED3[2];
- __IOM uint32_t EVENTS_SYNC;
- __IOM uint32_t EVENTS_PHYEND;
- __IOM uint32_t EVENTS_CTEPRESENT;
- __IM uint32_t RESERVED4[35];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED5[64];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED6[61];
- __IM uint32_t CRCSTATUS;
- __IM uint32_t RESERVED7;
- __IM uint32_t RXMATCH;
- __IM uint32_t RXCRC;
- __IM uint32_t DAI;
- __IM uint32_t PDUSTAT;
- __IM uint32_t RESERVED8[13];
- __IM uint32_t CTESTATUS;
- __IM uint32_t RESERVED9[2];
- __IM uint32_t DFESTATUS;
- __IM uint32_t RESERVED10[42];
- __IOM uint32_t PACKETPTR;
- __IOM uint32_t FREQUENCY;
- __IOM uint32_t TXPOWER;
- __IOM uint32_t MODE;
- __IOM uint32_t PCNF0;
- __IOM uint32_t PCNF1;
- __IOM uint32_t BASE0;
- __IOM uint32_t BASE1;
- __IOM uint32_t PREFIX0;
- __IOM uint32_t PREFIX1;
- __IOM uint32_t TXADDRESS;
- __IOM uint32_t RXADDRESSES;
- __IOM uint32_t CRCCNF;
- __IOM uint32_t CRCPOLY;
- __IOM uint32_t CRCINIT;
- __IM uint32_t RESERVED11;
- __IOM uint32_t TIFS;
- __IM uint32_t RSSISAMPLE;
- __IM uint32_t RESERVED12;
- __IM uint32_t STATE;
- __IOM uint32_t DATAWHITEIV;
- __IM uint32_t RESERVED13[2];
- __IOM uint32_t BCC;
- __IM uint32_t RESERVED14[39];
- __IOM uint32_t DAB[8];
- __IOM uint32_t DAP[8];
- __IOM uint32_t DACNF;
- __IOM uint32_t MHRMATCHCONF;
- __IOM uint32_t MHRMATCHMAS;
- __IM uint32_t RESERVED15;
- __IOM uint32_t MODECNF0;
- __IM uint32_t RESERVED16[3];
- __IOM uint32_t SFD;
- __IOM uint32_t EDCNT;
- __IM uint32_t EDSAMPLE;
- __IOM uint32_t CCACTRL;
- __IM uint32_t RESERVED17[164];
- __IOM uint32_t DFEMODE;
- __IOM uint32_t CTEINLINECONF;
- __IM uint32_t RESERVED18[2];
- __IOM uint32_t DFECTRL1;
- __IOM uint32_t DFECTRL2;
- __IM uint32_t RESERVED19[4];
- __IOM uint32_t SWITCHPATTERN;
- __IOM uint32_t CLEARPATTERN;
- __IOM RADIO_PSEL_Type PSEL;
- __IOM RADIO_DFEPACKET_Type DFEPACKET;
- __IM uint32_t RESERVED20[424];
- __IOM uint32_t POWER;
- } NRF_RADIO_Type;
- typedef struct {
- __OM uint32_t TASKS_STARTRX;
- __OM uint32_t TASKS_STOPRX;
- __OM uint32_t TASKS_STARTTX;
- __OM uint32_t TASKS_STOPTX;
- __IM uint32_t RESERVED[3];
- __OM uint32_t TASKS_SUSPEND;
- __IM uint32_t RESERVED1[56];
- __IOM uint32_t EVENTS_CTS;
- __IOM uint32_t EVENTS_NCTS;
- __IOM uint32_t EVENTS_RXDRDY;
- __IM uint32_t RESERVED2[4];
- __IOM uint32_t EVENTS_TXDRDY;
- __IM uint32_t RESERVED3;
- __IOM uint32_t EVENTS_ERROR;
- __IM uint32_t RESERVED4[7];
- __IOM uint32_t EVENTS_RXTO;
- __IM uint32_t RESERVED5[46];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED6[64];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED7[93];
- __IOM uint32_t ERRORSRC;
- __IM uint32_t RESERVED8[31];
- __IOM uint32_t ENABLE;
- __IM uint32_t RESERVED9;
- __IOM UART_PSEL_Type PSEL;
- __IM uint32_t RXD;
- __OM uint32_t TXD;
- __IM uint32_t RESERVED10;
- __IOM uint32_t BAUDRATE;
- __IM uint32_t RESERVED11[17];
- __IOM uint32_t CONFIG;
- } NRF_UART_Type;
- typedef struct {
- __OM uint32_t TASKS_STARTRX;
- __OM uint32_t TASKS_STOPRX;
- __OM uint32_t TASKS_STARTTX;
- __OM uint32_t TASKS_STOPTX;
- __IM uint32_t RESERVED[7];
- __OM uint32_t TASKS_FLUSHRX;
- __IM uint32_t RESERVED1[52];
- __IOM uint32_t EVENTS_CTS;
- __IOM uint32_t EVENTS_NCTS;
- __IOM uint32_t EVENTS_RXDRDY;
- __IM uint32_t RESERVED2;
- __IOM uint32_t EVENTS_ENDRX;
- __IM uint32_t RESERVED3[2];
- __IOM uint32_t EVENTS_TXDRDY;
- __IOM uint32_t EVENTS_ENDTX;
- __IOM uint32_t EVENTS_ERROR;
- __IM uint32_t RESERVED4[7];
- __IOM uint32_t EVENTS_RXTO;
- __IM uint32_t RESERVED5;
- __IOM uint32_t EVENTS_RXSTARTED;
- __IOM uint32_t EVENTS_TXSTARTED;
- __IM uint32_t RESERVED6;
- __IOM uint32_t EVENTS_TXSTOPPED;
- __IM uint32_t RESERVED7[41];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED8[63];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED9[93];
- __IOM uint32_t ERRORSRC;
- __IM uint32_t RESERVED10[31];
- __IOM uint32_t ENABLE;
- __IM uint32_t RESERVED11;
- __IOM UARTE_PSEL_Type PSEL;
- __IM uint32_t RESERVED12[3];
- __IOM uint32_t BAUDRATE;
- __IM uint32_t RESERVED13[3];
- __IOM UARTE_RXD_Type RXD;
- __IM uint32_t RESERVED14;
- __IOM UARTE_TXD_Type TXD;
- __IM uint32_t RESERVED15[7];
- __IOM uint32_t CONFIG;
- } NRF_UARTE_Type;
- typedef struct {
- __IM uint32_t RESERVED[66];
- __IOM uint32_t EVENTS_READY;
- __IM uint32_t RESERVED1[126];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED2[125];
- __IOM uint32_t ENABLE;
- __IM uint32_t RESERVED3;
- __IOM SPI_PSEL_Type PSEL;
- __IM uint32_t RESERVED4;
- __IM uint32_t RXD;
- __IOM uint32_t TXD;
- __IM uint32_t RESERVED5;
- __IOM uint32_t FREQUENCY;
- __IM uint32_t RESERVED6[11];
- __IOM uint32_t CONFIG;
- } NRF_SPI_Type;
- typedef struct {
- __IM uint32_t RESERVED[4];
- __OM uint32_t TASKS_START;
- __OM uint32_t TASKS_STOP;
- __IM uint32_t RESERVED1;
- __OM uint32_t TASKS_SUSPEND;
- __OM uint32_t TASKS_RESUME;
- __IM uint32_t RESERVED2[56];
- __IOM uint32_t EVENTS_STOPPED;
- __IM uint32_t RESERVED3[2];
- __IOM uint32_t EVENTS_ENDRX;
- __IM uint32_t RESERVED4;
- __IOM uint32_t EVENTS_END;
- __IM uint32_t RESERVED5;
- __IOM uint32_t EVENTS_ENDTX;
- __IM uint32_t RESERVED6[10];
- __IOM uint32_t EVENTS_STARTED;
- __IM uint32_t RESERVED7[44];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED8[64];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED9[61];
- __IOM uint32_t STALLSTAT;
- __IM uint32_t RESERVED10[63];
- __IOM uint32_t ENABLE;
- __IM uint32_t RESERVED11;
- __IOM SPIM_PSEL_Type PSEL;
- __IM uint32_t RESERVED12[3];
- __IOM uint32_t FREQUENCY;
- __IM uint32_t RESERVED13[3];
- __IOM SPIM_RXD_Type RXD;
- __IOM SPIM_TXD_Type TXD;
- __IOM uint32_t CONFIG;
- __IM uint32_t RESERVED14[2];
- __IOM SPIM_IFTIMING_Type IFTIMING;
- __IOM uint32_t CSNPOL;
- __IOM uint32_t PSELDCX;
- __IOM uint32_t DCXCNT;
- __IM uint32_t RESERVED15[19];
- __IOM uint32_t ORC;
- } NRF_SPIM_Type;
- typedef struct {
- __IM uint32_t RESERVED[9];
- __OM uint32_t TASKS_ACQUIRE;
- __OM uint32_t TASKS_RELEASE;
- __IM uint32_t RESERVED1[54];
- __IOM uint32_t EVENTS_END;
- __IM uint32_t RESERVED2[2];
- __IOM uint32_t EVENTS_ENDRX;
- __IM uint32_t RESERVED3[5];
- __IOM uint32_t EVENTS_ACQUIRED;
- __IM uint32_t RESERVED4[53];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED5[64];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED6[61];
- __IM uint32_t SEMSTAT;
- __IM uint32_t RESERVED7[15];
- __IOM uint32_t STATUS;
- __IM uint32_t RESERVED8[47];
- __IOM uint32_t ENABLE;
- __IM uint32_t RESERVED9;
- __IOM SPIS_PSEL_Type PSEL;
- __IM uint32_t RESERVED10[7];
- __IOM SPIS_RXD_Type RXD;
- __IOM SPIS_TXD_Type TXD;
- __IOM uint32_t CONFIG;
- __IM uint32_t RESERVED11;
- __IOM uint32_t DEF;
- __IM uint32_t RESERVED12[24];
- __IOM uint32_t ORC;
- } NRF_SPIS_Type;
- typedef struct {
- __OM uint32_t TASKS_STARTRX;
- __IM uint32_t RESERVED;
- __OM uint32_t TASKS_STARTTX;
- __IM uint32_t RESERVED1[2];
- __OM uint32_t TASKS_STOP;
- __IM uint32_t RESERVED2;
- __OM uint32_t TASKS_SUSPEND;
- __OM uint32_t TASKS_RESUME;
- __IM uint32_t RESERVED3[56];
- __IOM uint32_t EVENTS_STOPPED;
- __IOM uint32_t EVENTS_RXDREADY;
- __IM uint32_t RESERVED4[4];
- __IOM uint32_t EVENTS_TXDSENT;
- __IM uint32_t RESERVED5;
- __IOM uint32_t EVENTS_ERROR;
- __IM uint32_t RESERVED6[4];
- __IOM uint32_t EVENTS_BB;
- __IM uint32_t RESERVED7[3];
- __IOM uint32_t EVENTS_SUSPENDED;
- __IM uint32_t RESERVED8[45];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED9[64];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED10[110];
- __IOM uint32_t ERRORSRC;
- __IM uint32_t RESERVED11[14];
- __IOM uint32_t ENABLE;
- __IM uint32_t RESERVED12;
- __IOM TWI_PSEL_Type PSEL;
- __IM uint32_t RESERVED13[2];
- __IM uint32_t RXD;
- __IOM uint32_t TXD;
- __IM uint32_t RESERVED14;
- __IOM uint32_t FREQUENCY;
- __IM uint32_t RESERVED15[24];
- __IOM uint32_t ADDRESS;
- } NRF_TWI_Type;
- typedef struct {
- __OM uint32_t TASKS_STARTRX;
- __IM uint32_t RESERVED;
- __OM uint32_t TASKS_STARTTX;
- __IM uint32_t RESERVED1[2];
- __OM uint32_t TASKS_STOP;
- __IM uint32_t RESERVED2;
- __OM uint32_t TASKS_SUSPEND;
- __OM uint32_t TASKS_RESUME;
- __IM uint32_t RESERVED3[56];
- __IOM uint32_t EVENTS_STOPPED;
- __IM uint32_t RESERVED4[7];
- __IOM uint32_t EVENTS_ERROR;
- __IM uint32_t RESERVED5[8];
- __IOM uint32_t EVENTS_SUSPENDED;
- __IOM uint32_t EVENTS_RXSTARTED;
- __IOM uint32_t EVENTS_TXSTARTED;
- __IM uint32_t RESERVED6[2];
- __IOM uint32_t EVENTS_LASTRX;
- __IOM uint32_t EVENTS_LASTTX;
- __IM uint32_t RESERVED7[39];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED8[63];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED9[110];
- __IOM uint32_t ERRORSRC;
- __IM uint32_t RESERVED10[14];
- __IOM uint32_t ENABLE;
- __IM uint32_t RESERVED11;
- __IOM TWIM_PSEL_Type PSEL;
- __IM uint32_t RESERVED12[5];
- __IOM uint32_t FREQUENCY;
- __IM uint32_t RESERVED13[3];
- __IOM TWIM_RXD_Type RXD;
- __IOM TWIM_TXD_Type TXD;
- __IM uint32_t RESERVED14[13];
- __IOM uint32_t ADDRESS;
- } NRF_TWIM_Type;
- typedef struct {
- __IM uint32_t RESERVED[5];
- __OM uint32_t TASKS_STOP;
- __IM uint32_t RESERVED1;
- __OM uint32_t TASKS_SUSPEND;
- __OM uint32_t TASKS_RESUME;
- __IM uint32_t RESERVED2[3];
- __OM uint32_t TASKS_PREPARERX;
- __OM uint32_t TASKS_PREPARETX;
- __IM uint32_t RESERVED3[51];
- __IOM uint32_t EVENTS_STOPPED;
- __IM uint32_t RESERVED4[7];
- __IOM uint32_t EVENTS_ERROR;
- __IM uint32_t RESERVED5[9];
- __IOM uint32_t EVENTS_RXSTARTED;
- __IOM uint32_t EVENTS_TXSTARTED;
- __IM uint32_t RESERVED6[4];
- __IOM uint32_t EVENTS_WRITE;
- __IOM uint32_t EVENTS_READ;
- __IM uint32_t RESERVED7[37];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED8[63];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED9[113];
- __IOM uint32_t ERRORSRC;
- __IM uint32_t MATCH;
- __IM uint32_t RESERVED10[10];
- __IOM uint32_t ENABLE;
- __IM uint32_t RESERVED11;
- __IOM TWIS_PSEL_Type PSEL;
- __IM uint32_t RESERVED12[9];
- __IOM TWIS_RXD_Type RXD;
- __IOM TWIS_TXD_Type TXD;
- __IM uint32_t RESERVED13[13];
- __IOM uint32_t ADDRESS[2];
- __IM uint32_t RESERVED14;
- __IOM uint32_t CONFIG;
- __IM uint32_t RESERVED15[10];
- __IOM uint32_t ORC;
- } NRF_TWIS_Type;
- typedef struct {
- __OM uint32_t TASKS_ACTIVATE;
- __OM uint32_t TASKS_DISABLE;
- __OM uint32_t TASKS_SENSE;
- __OM uint32_t TASKS_STARTTX;
- __IM uint32_t RESERVED[3];
- __OM uint32_t TASKS_ENABLERXDATA;
- __IM uint32_t RESERVED1;
- __OM uint32_t TASKS_GOIDLE;
- __OM uint32_t TASKS_GOSLEEP;
- __IM uint32_t RESERVED2[53];
- __IOM uint32_t EVENTS_READY;
- __IOM uint32_t EVENTS_FIELDDETECTED;
- __IOM uint32_t EVENTS_FIELDLOST;
- __IOM uint32_t EVENTS_TXFRAMESTART;
- __IOM uint32_t EVENTS_TXFRAMEEND;
- __IOM uint32_t EVENTS_RXFRAMESTART;
- __IOM uint32_t EVENTS_RXFRAMEEND;
- __IOM uint32_t EVENTS_ERROR;
- __IM uint32_t RESERVED3[2];
- __IOM uint32_t EVENTS_RXERROR;
- __IOM uint32_t EVENTS_ENDRX;
- __IOM uint32_t EVENTS_ENDTX;
- __IM uint32_t RESERVED4;
- __IOM uint32_t EVENTS_AUTOCOLRESSTARTED;
- __IM uint32_t RESERVED5[3];
- __IOM uint32_t EVENTS_COLLISION;
- __IOM uint32_t EVENTS_SELECTED;
- __IOM uint32_t EVENTS_STARTED;
- __IM uint32_t RESERVED6[43];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED7[63];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED8[62];
- __IOM uint32_t ERRORSTATUS;
- __IM uint32_t RESERVED9;
- __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS;
- __IM uint32_t NFCTAGSTATE;
- __IM uint32_t RESERVED10[3];
- __IM uint32_t SLEEPSTATE;
- __IM uint32_t RESERVED11[6];
- __IM uint32_t FIELDPRESENT;
- __IM uint32_t RESERVED12[49];
- __IOM uint32_t FRAMEDELAYMIN;
- __IOM uint32_t FRAMEDELAYMAX;
- __IOM uint32_t FRAMEDELAYMODE;
- __IOM uint32_t PACKETPTR;
- __IOM uint32_t MAXLEN;
- __IOM NFCT_TXD_Type TXD;
- __IOM NFCT_RXD_Type RXD;
- __IM uint32_t RESERVED13;
- __IOM uint32_t MODULATIONCTRL;
- __IM uint32_t RESERVED14[2];
- __IOM uint32_t MODULATIONPSEL;
- __IM uint32_t RESERVED15[21];
- __IOM uint32_t NFCID1_LAST;
- __IOM uint32_t NFCID1_2ND_LAST;
- __IOM uint32_t NFCID1_3RD_LAST;
- __IOM uint32_t AUTOCOLRESCONFIG;
- __IOM uint32_t SENSRES;
- __IOM uint32_t SELRES;
- } NRF_NFCT_Type;
- typedef struct {
- __OM uint32_t TASKS_OUT[8];
- __IM uint32_t RESERVED[4];
- __OM uint32_t TASKS_SET[8];
- __IM uint32_t RESERVED1[4];
- __OM uint32_t TASKS_CLR[8];
- __IM uint32_t RESERVED2[32];
- __IOM uint32_t EVENTS_IN[8];
- __IM uint32_t RESERVED3[23];
- __IOM uint32_t EVENTS_PORT;
- __IM uint32_t RESERVED4[97];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED5[129];
- __IOM uint32_t CONFIG[8];
- } NRF_GPIOTE_Type;
- typedef struct {
- __OM uint32_t TASKS_START;
- __OM uint32_t TASKS_SAMPLE;
- __OM uint32_t TASKS_STOP;
- __OM uint32_t TASKS_CALIBRATEOFFSET;
- __IM uint32_t RESERVED[60];
- __IOM uint32_t EVENTS_STARTED;
- __IOM uint32_t EVENTS_END;
- __IOM uint32_t EVENTS_DONE;
- __IOM uint32_t EVENTS_RESULTDONE;
- __IOM uint32_t EVENTS_CALIBRATEDONE;
- __IOM uint32_t EVENTS_STOPPED;
- __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8];
- __IM uint32_t RESERVED1[106];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED2[61];
- __IM uint32_t STATUS;
- __IM uint32_t RESERVED3[63];
- __IOM uint32_t ENABLE;
- __IM uint32_t RESERVED4[3];
- __IOM SAADC_CH_Type CH[8];
- __IM uint32_t RESERVED5[24];
- __IOM uint32_t RESOLUTION;
- __IOM uint32_t OVERSAMPLE;
- __IOM uint32_t SAMPLERATE;
- __IM uint32_t RESERVED6[12];
- __IOM SAADC_RESULT_Type RESULT;
- } NRF_SAADC_Type;
- typedef struct {
- __OM uint32_t TASKS_START;
- __OM uint32_t TASKS_STOP;
- __OM uint32_t TASKS_COUNT;
- __OM uint32_t TASKS_CLEAR;
- __OM uint32_t TASKS_SHUTDOWN;
- __IM uint32_t RESERVED[11];
- __OM uint32_t TASKS_CAPTURE[6];
- __IM uint32_t RESERVED1[58];
- __IOM uint32_t EVENTS_COMPARE[6];
- __IM uint32_t RESERVED2[42];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED3[64];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED4[126];
- __IOM uint32_t MODE;
- __IOM uint32_t BITMODE;
- __IM uint32_t RESERVED5;
- __IOM uint32_t PRESCALER;
- __IM uint32_t RESERVED6[11];
- __IOM uint32_t CC[6];
- } NRF_TIMER_Type;
- typedef struct {
- __OM uint32_t TASKS_START;
- __OM uint32_t TASKS_STOP;
- __OM uint32_t TASKS_CLEAR;
- __OM uint32_t TASKS_TRIGOVRFLW;
- __IM uint32_t RESERVED[60];
- __IOM uint32_t EVENTS_TICK;
- __IOM uint32_t EVENTS_OVRFLW;
- __IM uint32_t RESERVED1[14];
- __IOM uint32_t EVENTS_COMPARE[4];
- __IM uint32_t RESERVED2[109];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED3[13];
- __IOM uint32_t EVTEN;
- __IOM uint32_t EVTENSET;
- __IOM uint32_t EVTENCLR;
- __IM uint32_t RESERVED4[110];
- __IM uint32_t COUNTER;
- __IOM uint32_t PRESCALER;
- __IM uint32_t RESERVED5[13];
- __IOM uint32_t CC[4];
- } NRF_RTC_Type;
- typedef struct {
- __OM uint32_t TASKS_START;
- __OM uint32_t TASKS_STOP;
- __IM uint32_t RESERVED[62];
- __IOM uint32_t EVENTS_DATARDY;
- __IM uint32_t RESERVED1[128];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED2[127];
- __IM int32_t TEMP;
- __IM uint32_t RESERVED3[5];
- __IOM uint32_t A0;
- __IOM uint32_t A1;
- __IOM uint32_t A2;
- __IOM uint32_t A3;
- __IOM uint32_t A4;
- __IOM uint32_t A5;
- __IM uint32_t RESERVED4[2];
- __IOM uint32_t B0;
- __IOM uint32_t B1;
- __IOM uint32_t B2;
- __IOM uint32_t B3;
- __IOM uint32_t B4;
- __IOM uint32_t B5;
- __IM uint32_t RESERVED5[2];
- __IOM uint32_t T0;
- __IOM uint32_t T1;
- __IOM uint32_t T2;
- __IOM uint32_t T3;
- __IOM uint32_t T4;
- } NRF_TEMP_Type;
- typedef struct {
- __OM uint32_t TASKS_START;
- __OM uint32_t TASKS_STOP;
- __IM uint32_t RESERVED[62];
- __IOM uint32_t EVENTS_VALRDY;
- __IM uint32_t RESERVED1[63];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED2[64];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED3[126];
- __IOM uint32_t CONFIG;
- __IM uint32_t VALUE;
- } NRF_RNG_Type;
- typedef struct {
- __OM uint32_t TASKS_STARTECB;
- __OM uint32_t TASKS_STOPECB;
- __IM uint32_t RESERVED[62];
- __IOM uint32_t EVENTS_ENDECB;
- __IOM uint32_t EVENTS_ERRORECB;
- __IM uint32_t RESERVED1[127];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED2[126];
- __IOM uint32_t ECBDATAPTR;
- } NRF_ECB_Type;
- typedef struct {
- __OM uint32_t TASKS_START;
- __IM uint32_t RESERVED;
- __OM uint32_t TASKS_STOP;
- __IM uint32_t RESERVED1[61];
- __IOM uint32_t EVENTS_END;
- __IOM uint32_t EVENTS_RESOLVED;
- __IOM uint32_t EVENTS_NOTRESOLVED;
- __IM uint32_t RESERVED2[126];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED3[61];
- __IM uint32_t STATUS;
- __IM uint32_t RESERVED4[63];
- __IOM uint32_t ENABLE;
- __IOM uint32_t NIRK;
- __IOM uint32_t IRKPTR;
- __IM uint32_t RESERVED5;
- __IOM uint32_t ADDRPTR;
- __IOM uint32_t SCRATCHPTR;
- } NRF_AAR_Type;
- typedef struct {
- __OM uint32_t TASKS_KSGEN;
- __OM uint32_t TASKS_CRYPT;
- __OM uint32_t TASKS_STOP;
- __OM uint32_t TASKS_RATEOVERRIDE;
- __IM uint32_t RESERVED[60];
- __IOM uint32_t EVENTS_ENDKSGEN;
- __IOM uint32_t EVENTS_ENDCRYPT;
- __IOM uint32_t EVENTS_ERROR;
- __IM uint32_t RESERVED1[61];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED2[64];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED3[61];
- __IM uint32_t MICSTATUS;
- __IM uint32_t RESERVED4[63];
- __IOM uint32_t ENABLE;
- __IOM uint32_t MODE;
- __IOM uint32_t CNFPTR;
- __IOM uint32_t INPTR;
- __IOM uint32_t OUTPTR;
- __IOM uint32_t SCRATCHPTR;
- __IOM uint32_t MAXPACKETSIZE;
- __IOM uint32_t RATEOVERRIDE;
- } NRF_CCM_Type;
- typedef struct {
- __OM uint32_t TASKS_START;
- __IM uint32_t RESERVED[63];
- __IOM uint32_t EVENTS_TIMEOUT;
- __IM uint32_t RESERVED1[128];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED2[61];
- __IM uint32_t RUNSTATUS;
- __IM uint32_t REQSTATUS;
- __IM uint32_t RESERVED3[63];
- __IOM uint32_t CRV;
- __IOM uint32_t RREN;
- __IOM uint32_t CONFIG;
- __IM uint32_t RESERVED4[60];
- __OM uint32_t RR[8];
- } NRF_WDT_Type;
- typedef struct {
- __OM uint32_t TASKS_START;
- __OM uint32_t TASKS_STOP;
- __OM uint32_t TASKS_READCLRACC;
- __OM uint32_t TASKS_RDCLRACC;
- __OM uint32_t TASKS_RDCLRDBL;
- __IM uint32_t RESERVED[59];
- __IOM uint32_t EVENTS_SAMPLERDY;
- __IOM uint32_t EVENTS_REPORTRDY;
- __IOM uint32_t EVENTS_ACCOF;
- __IOM uint32_t EVENTS_DBLRDY;
- __IOM uint32_t EVENTS_STOPPED;
- __IM uint32_t RESERVED1[59];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED2[64];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED3[125];
- __IOM uint32_t ENABLE;
- __IOM uint32_t LEDPOL;
- __IOM uint32_t SAMPLEPER;
- __IM int32_t SAMPLE;
- __IOM uint32_t REPORTPER;
- __IM int32_t ACC;
- __IM int32_t ACCREAD;
- __IOM QDEC_PSEL_Type PSEL;
- __IOM uint32_t DBFEN;
- __IM uint32_t RESERVED4[5];
- __IOM uint32_t LEDPRE;
- __IM uint32_t ACCDBL;
- __IM uint32_t ACCDBLREAD;
- } NRF_QDEC_Type;
- typedef struct {
- __OM uint32_t TASKS_START;
- __OM uint32_t TASKS_STOP;
- __OM uint32_t TASKS_SAMPLE;
- __IM uint32_t RESERVED[61];
- __IOM uint32_t EVENTS_READY;
- __IOM uint32_t EVENTS_DOWN;
- __IOM uint32_t EVENTS_UP;
- __IOM uint32_t EVENTS_CROSS;
- __IM uint32_t RESERVED1[60];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED2[63];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED3[61];
- __IM uint32_t RESULT;
- __IM uint32_t RESERVED4[63];
- __IOM uint32_t ENABLE;
- __IOM uint32_t PSEL;
- __IOM uint32_t REFSEL;
- __IOM uint32_t EXTREFSEL;
- __IM uint32_t RESERVED5[8];
- __IOM uint32_t TH;
- __IOM uint32_t MODE;
- __IOM uint32_t HYST;
- } NRF_COMP_Type;
- typedef struct {
- __OM uint32_t TASKS_START;
- __OM uint32_t TASKS_STOP;
- __OM uint32_t TASKS_SAMPLE;
- __IM uint32_t RESERVED[61];
- __IOM uint32_t EVENTS_READY;
- __IOM uint32_t EVENTS_DOWN;
- __IOM uint32_t EVENTS_UP;
- __IOM uint32_t EVENTS_CROSS;
- __IM uint32_t RESERVED1[60];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED2[64];
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED3[61];
- __IM uint32_t RESULT;
- __IM uint32_t RESERVED4[63];
- __IOM uint32_t ENABLE;
- __IOM uint32_t PSEL;
- __IOM uint32_t REFSEL;
- __IOM uint32_t EXTREFSEL;
- __IM uint32_t RESERVED5[4];
- __IOM uint32_t ANADETECT;
- __IM uint32_t RESERVED6[5];
- __IOM uint32_t HYST;
- } NRF_LPCOMP_Type;
- typedef struct {
- __OM uint32_t TASKS_TRIGGER[16];
- __IM uint32_t RESERVED[48];
- __IOM uint32_t EVENTS_TRIGGERED[16];
- __IM uint32_t RESERVED1[112];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- } NRF_EGU_Type;
- typedef struct {
- __IM uint32_t UNUSED;
- } NRF_SWI_Type;
- typedef struct {
- __IM uint32_t RESERVED;
- __OM uint32_t TASKS_STOP;
- __OM uint32_t TASKS_SEQSTART[2];
- __OM uint32_t TASKS_NEXTSTEP;
- __IM uint32_t RESERVED1[60];
- __IOM uint32_t EVENTS_STOPPED;
- __IOM uint32_t EVENTS_SEQSTARTED[2];
- __IOM uint32_t EVENTS_SEQEND[2];
- __IOM uint32_t EVENTS_PWMPERIODEND;
- __IOM uint32_t EVENTS_LOOPSDONE;
- __IM uint32_t RESERVED2[56];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED3[63];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED4[125];
- __IOM uint32_t ENABLE;
- __IOM uint32_t MODE;
- __IOM uint32_t COUNTERTOP;
- __IOM uint32_t PRESCALER;
- __IOM uint32_t DECODER;
- __IOM uint32_t LOOP;
- __IM uint32_t RESERVED5[2];
- __IOM PWM_SEQ_Type SEQ[2];
- __IOM PWM_PSEL_Type PSEL;
- } NRF_PWM_Type;
- typedef struct {
- __OM uint32_t TASKS_START;
- __OM uint32_t TASKS_STOP;
- __IM uint32_t RESERVED[62];
- __IOM uint32_t EVENTS_STARTED;
- __IOM uint32_t EVENTS_STOPPED;
- __IOM uint32_t EVENTS_END;
- __IM uint32_t RESERVED1[125];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED2[125];
- __IOM uint32_t ENABLE;
- __IOM uint32_t PDMCLKCTRL;
- __IOM uint32_t MODE;
- __IM uint32_t RESERVED3[3];
- __IOM uint32_t GAINL;
- __IOM uint32_t GAINR;
- __IOM uint32_t RATIO;
- __IM uint32_t RESERVED4[7];
- __IOM PDM_PSEL_Type PSEL;
- __IM uint32_t RESERVED5[6];
- __IOM PDM_SAMPLE_Type SAMPLE;
- } NRF_PDM_Type;
- typedef struct {
- __IM uint32_t RESERVED[512];
- __IOM ACL_ACL_Type ACL[8];
- } NRF_ACL_Type;
- typedef struct {
- __IM uint32_t RESERVED[256];
- __IM uint32_t READY;
- __IM uint32_t RESERVED1;
- __IM uint32_t READYNEXT;
- __IM uint32_t RESERVED2[62];
- __IOM uint32_t CONFIG;
-
- union {
- __OM uint32_t ERASEPAGE;
- __OM uint32_t ERASEPCR1;
- };
- __OM uint32_t ERASEALL;
- __OM uint32_t ERASEPCR0;
- __OM uint32_t ERASEUICR;
- __OM uint32_t ERASEPAGEPARTIAL;
- __IOM uint32_t ERASEPAGEPARTIALCFG;
- __IM uint32_t RESERVED3[8];
- __IOM uint32_t ICACHECNF;
- __IM uint32_t RESERVED4;
- __IOM uint32_t IHIT;
- __IOM uint32_t IMISS;
- } NRF_NVMC_Type;
- typedef struct {
- __OM PPI_TASKS_CHG_Type TASKS_CHG[6];
- __IM uint32_t RESERVED[308];
- __IOM uint32_t CHEN;
- __IOM uint32_t CHENSET;
- __IOM uint32_t CHENCLR;
- __IM uint32_t RESERVED1;
- __IOM PPI_CH_Type CH[20];
- __IM uint32_t RESERVED2[148];
- __IOM uint32_t CHG[6];
- __IM uint32_t RESERVED3[62];
- __IOM PPI_FORK_Type FORK[32];
- } NRF_PPI_Type;
- typedef struct {
- __IM uint32_t RESERVED[64];
- __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];
- __IM uint32_t RESERVED1[16];
- __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];
- __IM uint32_t RESERVED2[100];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED3[5];
- __IOM uint32_t NMIEN;
- __IOM uint32_t NMIENSET;
- __IOM uint32_t NMIENCLR;
- __IM uint32_t RESERVED4[53];
- __IOM MWU_PERREGION_Type PERREGION[2];
- __IM uint32_t RESERVED5[64];
- __IOM uint32_t REGIONEN;
- __IOM uint32_t REGIONENSET;
- __IOM uint32_t REGIONENCLR;
- __IM uint32_t RESERVED6[57];
- __IOM MWU_REGION_Type REGION[4];
- __IM uint32_t RESERVED7[32];
- __IOM MWU_PREGION_Type PREGION[2];
- } NRF_MWU_Type;
- typedef struct {
- __OM uint32_t TASKS_START;
- __OM uint32_t TASKS_STOP;
- __IM uint32_t RESERVED[63];
- __IOM uint32_t EVENTS_RXPTRUPD;
- __IOM uint32_t EVENTS_STOPPED;
- __IM uint32_t RESERVED1[2];
- __IOM uint32_t EVENTS_TXPTRUPD;
- __IM uint32_t RESERVED2[122];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED3[125];
- __IOM uint32_t ENABLE;
- __IOM I2S_CONFIG_Type CONFIG;
- __IM uint32_t RESERVED4[3];
- __IOM I2S_RXD_Type RXD;
- __IM uint32_t RESERVED5;
- __IOM I2S_TXD_Type TXD;
- __IM uint32_t RESERVED6[3];
- __IOM I2S_RXTXD_Type RXTXD;
- __IM uint32_t RESERVED7[3];
- __IOM I2S_PSEL_Type PSEL;
- } NRF_I2S_Type;
- typedef struct {
- __IM uint32_t UNUSED;
- } NRF_FPU_Type;
- typedef struct {
- __IM uint32_t RESERVED;
- __OM uint32_t TASKS_STARTEPIN[8];
- __OM uint32_t TASKS_STARTISOIN;
- __OM uint32_t TASKS_STARTEPOUT[8];
- __OM uint32_t TASKS_STARTISOOUT;
- __OM uint32_t TASKS_EP0RCVOUT;
- __OM uint32_t TASKS_EP0STATUS;
- __OM uint32_t TASKS_EP0STALL;
- __OM uint32_t TASKS_DPDMDRIVE;
- __OM uint32_t TASKS_DPDMNODRIVE;
- __IM uint32_t RESERVED1[40];
- __IOM uint32_t EVENTS_USBRESET;
- __IOM uint32_t EVENTS_STARTED;
- __IOM uint32_t EVENTS_ENDEPIN[8];
- __IOM uint32_t EVENTS_EP0DATADONE;
- __IOM uint32_t EVENTS_ENDISOIN;
- __IOM uint32_t EVENTS_ENDEPOUT[8];
- __IOM uint32_t EVENTS_ENDISOOUT;
- __IOM uint32_t EVENTS_SOF;
- __IOM uint32_t EVENTS_USBEVENT;
- __IOM uint32_t EVENTS_EP0SETUP;
- __IOM uint32_t EVENTS_EPDATA;
- __IM uint32_t RESERVED2[39];
- __IOM uint32_t SHORTS;
- __IM uint32_t RESERVED3[63];
- __IOM uint32_t INTEN;
- __IOM uint32_t INTENSET;
- __IOM uint32_t INTENCLR;
- __IM uint32_t RESERVED4[61];
- __IOM uint32_t EVENTCAUSE;
- __IM uint32_t RESERVED5[7];
- __IOM USBD_HALTED_Type HALTED;
- __IM uint32_t RESERVED6;
- __IOM uint32_t EPSTATUS;
- __IOM uint32_t EPDATASTATUS;
- __IM uint32_t USBADDR;
- __IM uint32_t RESERVED7[3];
- __IM uint32_t BMREQUESTTYPE;
- __IM uint32_t BREQUEST;
- __IM uint32_t WVALUEL;
- __IM uint32_t WVALUEH;
- __IM uint32_t WINDEXL;
- __IM uint32_t WINDEXH;
- __IM uint32_t WLENGTHL;
- __IM uint32_t WLENGTHH;
- __IOM USBD_SIZE_Type SIZE;
- __IM uint32_t RESERVED8[15];
- __IOM uint32_t ENABLE;
- __IOM uint32_t USBPULLUP;
- __IOM uint32_t DPDMVALUE;
- __IOM uint32_t DTOGGLE;
- __IOM uint32_t EPINEN;
- __IOM uint32_t EPOUTEN;
- __OM uint32_t EPSTALL;
- __IOM uint32_t ISOSPLIT;
- __IM uint32_t FRAMECNTR;
- __IM uint32_t RESERVED9[2];
- __IOM uint32_t LOWPOWER;
- __IOM uint32_t ISOINCONFIG;
- __IM uint32_t RESERVED10[51];
- __IOM USBD_EPIN_Type EPIN[8];
- __IOM USBD_ISOIN_Type ISOIN;
- __IM uint32_t RESERVED11[21];
- __IOM USBD_EPOUT_Type EPOUT[8];
- __IOM USBD_ISOOUT_Type ISOOUT;
- } NRF_USBD_Type;
-
- #define NRF_FICR_BASE 0x10000000UL
- #define NRF_UICR_BASE 0x10001000UL
- #define NRF_CLOCK_BASE 0x40000000UL
- #define NRF_POWER_BASE 0x40000000UL
- #define NRF_P0_BASE 0x50000000UL
- #define NRF_P1_BASE 0x50000300UL
- #define NRF_RADIO_BASE 0x40001000UL
- #define NRF_UART0_BASE 0x40002000UL
- #define NRF_UARTE0_BASE 0x40002000UL
- #define NRF_SPI0_BASE 0x40003000UL
- #define NRF_SPIM0_BASE 0x40003000UL
- #define NRF_SPIS0_BASE 0x40003000UL
- #define NRF_TWI0_BASE 0x40003000UL
- #define NRF_TWIM0_BASE 0x40003000UL
- #define NRF_TWIS0_BASE 0x40003000UL
- #define NRF_SPI1_BASE 0x40004000UL
- #define NRF_SPIM1_BASE 0x40004000UL
- #define NRF_SPIS1_BASE 0x40004000UL
- #define NRF_TWI1_BASE 0x40004000UL
- #define NRF_TWIM1_BASE 0x40004000UL
- #define NRF_TWIS1_BASE 0x40004000UL
- #define NRF_NFCT_BASE 0x40005000UL
- #define NRF_GPIOTE_BASE 0x40006000UL
- #define NRF_SAADC_BASE 0x40007000UL
- #define NRF_TIMER0_BASE 0x40008000UL
- #define NRF_TIMER1_BASE 0x40009000UL
- #define NRF_TIMER2_BASE 0x4000A000UL
- #define NRF_RTC0_BASE 0x4000B000UL
- #define NRF_TEMP_BASE 0x4000C000UL
- #define NRF_RNG_BASE 0x4000D000UL
- #define NRF_ECB_BASE 0x4000E000UL
- #define NRF_AAR_BASE 0x4000F000UL
- #define NRF_CCM_BASE 0x4000F000UL
- #define NRF_WDT_BASE 0x40010000UL
- #define NRF_RTC1_BASE 0x40011000UL
- #define NRF_QDEC_BASE 0x40012000UL
- #define NRF_COMP_BASE 0x40013000UL
- #define NRF_LPCOMP_BASE 0x40013000UL
- #define NRF_EGU0_BASE 0x40014000UL
- #define NRF_SWI0_BASE 0x40014000UL
- #define NRF_EGU1_BASE 0x40015000UL
- #define NRF_SWI1_BASE 0x40015000UL
- #define NRF_EGU2_BASE 0x40016000UL
- #define NRF_SWI2_BASE 0x40016000UL
- #define NRF_EGU3_BASE 0x40017000UL
- #define NRF_SWI3_BASE 0x40017000UL
- #define NRF_EGU4_BASE 0x40018000UL
- #define NRF_SWI4_BASE 0x40018000UL
- #define NRF_EGU5_BASE 0x40019000UL
- #define NRF_SWI5_BASE 0x40019000UL
- #define NRF_TIMER3_BASE 0x4001A000UL
- #define NRF_TIMER4_BASE 0x4001B000UL
- #define NRF_PWM0_BASE 0x4001C000UL
- #define NRF_PDM_BASE 0x4001D000UL
- #define NRF_ACL_BASE 0x4001E000UL
- #define NRF_NVMC_BASE 0x4001E000UL
- #define NRF_PPI_BASE 0x4001F000UL
- #define NRF_MWU_BASE 0x40020000UL
- #define NRF_PWM1_BASE 0x40021000UL
- #define NRF_PWM2_BASE 0x40022000UL
- #define NRF_SPI2_BASE 0x40023000UL
- #define NRF_SPIM2_BASE 0x40023000UL
- #define NRF_SPIS2_BASE 0x40023000UL
- #define NRF_RTC2_BASE 0x40024000UL
- #define NRF_I2S_BASE 0x40025000UL
- #define NRF_FPU_BASE 0x40026000UL
- #define NRF_USBD_BASE 0x40027000UL
- #define NRF_UARTE1_BASE 0x40028000UL
- #define NRF_PWM3_BASE 0x4002D000UL
- #define NRF_SPIM3_BASE 0x4002F000UL
-
- #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE)
- #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE)
- #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE)
- #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE)
- #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE)
- #define NRF_P1 ((NRF_GPIO_Type*) NRF_P1_BASE)
- #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE)
- #define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE)
- #define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE)
- #define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE)
- #define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE)
- #define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE)
- #define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE)
- #define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE)
- #define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE)
- #define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE)
- #define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE)
- #define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE)
- #define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE)
- #define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE)
- #define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE)
- #define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE)
- #define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE)
- #define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE)
- #define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE)
- #define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE)
- #define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE)
- #define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE)
- #define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE)
- #define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE)
- #define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE)
- #define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE)
- #define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE)
- #define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE)
- #define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE)
- #define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE)
- #define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE)
- #define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE)
- #define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE)
- #define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE)
- #define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE)
- #define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE)
- #define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE)
- #define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE)
- #define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE)
- #define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE)
- #define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE)
- #define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE)
- #define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE)
- #define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE)
- #define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE)
- #define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE)
- #define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE)
- #define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE)
- #define NRF_ACL ((NRF_ACL_Type*) NRF_ACL_BASE)
- #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE)
- #define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE)
- #define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE)
- #define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE)
- #define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE)
- #define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE)
- #define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE)
- #define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE)
- #define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE)
- #define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE)
- #define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE)
- #define NRF_USBD ((NRF_USBD_Type*) NRF_USBD_BASE)
- #define NRF_UARTE1 ((NRF_UARTE_Type*) NRF_UARTE1_BASE)
- #define NRF_PWM3 ((NRF_PWM_Type*) NRF_PWM3_BASE)
- #define NRF_SPIM3 ((NRF_SPIM_Type*) NRF_SPIM3_BASE)
-
- #if defined (__CC_ARM)
- #pragma pop
- #elif defined (__ICCARM__)
-
- #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang diagnostic pop
- #elif defined (__GNUC__)
-
- #elif defined (__TMS470__)
-
- #elif defined (__TASKING__)
- #pragma warning restore
- #elif defined (__CSMC__)
-
- #endif
- #ifdef __cplusplus
- }
- #endif
- #endif
-
-
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