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- #ifndef NRF_SPIM_H__
- #define NRF_SPIM_H__
- #include <nrfx.h>
- #ifdef __cplusplus
- extern "C" {
- #endif
- #define NRF_SPIM_PIN_NOT_CONNECTED 0xFFFFFFFF
- #if defined(SPIM_DCXCNT_DCXCNT_Msk) || defined(__NRFX_DOXYGEN__)
- #define NRF_SPIM_DCX_CNT_ALL_CMD 0xF
- #endif
- #define NRF_SPIM_HW_CSN_PRESENT \
- (NRFX_CHECK(SPIM0_FEATURE_HARDWARE_CSN_PRESENT) || \
- NRFX_CHECK(SPIM1_FEATURE_HARDWARE_CSN_PRESENT) || \
- NRFX_CHECK(SPIM2_FEATURE_HARDWARE_CSN_PRESENT) || \
- NRFX_CHECK(SPIM3_FEATURE_HARDWARE_CSN_PRESENT))
- typedef enum
- {
- NRF_SPIM_TASK_START = offsetof(NRF_SPIM_Type, TASKS_START),
- NRF_SPIM_TASK_STOP = offsetof(NRF_SPIM_Type, TASKS_STOP),
- NRF_SPIM_TASK_SUSPEND = offsetof(NRF_SPIM_Type, TASKS_SUSPEND),
- NRF_SPIM_TASK_RESUME = offsetof(NRF_SPIM_Type, TASKS_RESUME)
- } nrf_spim_task_t;
- typedef enum
- {
- NRF_SPIM_EVENT_STOPPED = offsetof(NRF_SPIM_Type, EVENTS_STOPPED),
- NRF_SPIM_EVENT_ENDRX = offsetof(NRF_SPIM_Type, EVENTS_ENDRX),
- NRF_SPIM_EVENT_END = offsetof(NRF_SPIM_Type, EVENTS_END),
- NRF_SPIM_EVENT_ENDTX = offsetof(NRF_SPIM_Type, EVENTS_ENDTX),
- NRF_SPIM_EVENT_STARTED = offsetof(NRF_SPIM_Type, EVENTS_STARTED)
- } nrf_spim_event_t;
- typedef enum
- {
- NRF_SPIM_SHORT_END_START_MASK = SPIM_SHORTS_END_START_Msk,
- NRF_SPIM_ALL_SHORTS_MASK = SPIM_SHORTS_END_START_Msk
- } nrf_spim_short_mask_t;
- typedef enum
- {
- NRF_SPIM_INT_STOPPED_MASK = SPIM_INTENSET_STOPPED_Msk,
- NRF_SPIM_INT_ENDRX_MASK = SPIM_INTENSET_ENDRX_Msk,
- NRF_SPIM_INT_END_MASK = SPIM_INTENSET_END_Msk,
- NRF_SPIM_INT_ENDTX_MASK = SPIM_INTENSET_ENDTX_Msk,
- NRF_SPIM_INT_STARTED_MASK = SPIM_INTENSET_STARTED_Msk,
- NRF_SPIM_ALL_INTS_MASK = SPIM_INTENSET_STOPPED_Msk |
- SPIM_INTENSET_ENDRX_Msk |
- SPIM_INTENSET_END_Msk |
- SPIM_INTENSET_ENDTX_Msk |
- SPIM_INTENSET_STARTED_Msk
- } nrf_spim_int_mask_t;
- typedef enum
- {
- NRF_SPIM_FREQ_125K = SPIM_FREQUENCY_FREQUENCY_K125,
- NRF_SPIM_FREQ_250K = SPIM_FREQUENCY_FREQUENCY_K250,
- NRF_SPIM_FREQ_500K = SPIM_FREQUENCY_FREQUENCY_K500,
- NRF_SPIM_FREQ_1M = SPIM_FREQUENCY_FREQUENCY_M1,
- NRF_SPIM_FREQ_2M = SPIM_FREQUENCY_FREQUENCY_M2,
- NRF_SPIM_FREQ_4M = SPIM_FREQUENCY_FREQUENCY_M4,
-
-
- NRF_SPIM_FREQ_8M = (int)SPIM_FREQUENCY_FREQUENCY_M8,
- #if defined(SPIM_FREQUENCY_FREQUENCY_M16) || defined(__NRFX_DOXYGEN__)
- NRF_SPIM_FREQ_16M = SPIM_FREQUENCY_FREQUENCY_M16,
- #endif
- #if defined(SPIM_FREQUENCY_FREQUENCY_M32) || defined(__NRFX_DOXYGEN__)
- NRF_SPIM_FREQ_32M = SPIM_FREQUENCY_FREQUENCY_M32
- #endif
- } nrf_spim_frequency_t;
- typedef enum
- {
- NRF_SPIM_MODE_0,
- NRF_SPIM_MODE_1,
- NRF_SPIM_MODE_2,
- NRF_SPIM_MODE_3
- } nrf_spim_mode_t;
- typedef enum
- {
- NRF_SPIM_BIT_ORDER_MSB_FIRST = SPIM_CONFIG_ORDER_MsbFirst,
- NRF_SPIM_BIT_ORDER_LSB_FIRST = SPIM_CONFIG_ORDER_LsbFirst
- } nrf_spim_bit_order_t;
- #if (NRF_SPIM_HW_CSN_PRESENT) || defined(__NRFX_DOXYGEN__)
- typedef enum
- {
- NRF_SPIM_CSN_POL_LOW = SPIM_CSNPOL_CSNPOL_LOW,
- NRF_SPIM_CSN_POL_HIGH = SPIM_CSNPOL_CSNPOL_HIGH
- } nrf_spim_csn_pol_t;
- #endif
- __STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_reg,
- nrf_spim_task_t task);
- __STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type * p_reg,
- nrf_spim_task_t task);
- __STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg,
- nrf_spim_event_t event);
- __STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_reg,
- nrf_spim_event_t event);
- __STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type * p_reg,
- nrf_spim_event_t event);
- __STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg,
- uint32_t mask);
- __STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg,
- uint32_t mask);
- __STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type * p_reg);
- __STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_reg,
- uint32_t mask);
- __STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_reg,
- uint32_t mask);
- __STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_reg,
- nrf_spim_int_mask_t spim_int);
- #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
- __STATIC_INLINE void nrf_spim_subscribe_set(NRF_SPIM_Type * p_reg,
- nrf_spim_task_t task,
- uint8_t channel);
- __STATIC_INLINE void nrf_spim_subscribe_clear(NRF_SPIM_Type * p_reg,
- nrf_spim_task_t task);
- __STATIC_INLINE void nrf_spim_publish_set(NRF_SPIM_Type * p_reg,
- nrf_spim_event_t event,
- uint8_t channel);
- __STATIC_INLINE void nrf_spim_publish_clear(NRF_SPIM_Type * p_reg,
- nrf_spim_event_t event);
- #endif
- __STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_reg);
- __STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg);
- __STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
- uint32_t sck_pin,
- uint32_t mosi_pin,
- uint32_t miso_pin);
- #if (NRF_SPIM_HW_CSN_PRESENT) || defined(__NRFX_DOXYGEN__)
- __STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type * p_reg,
- uint32_t pin,
- nrf_spim_csn_pol_t polarity,
- uint32_t duration);
- #endif
- #if defined(SPIM_PSELDCX_CONNECT_Msk) || defined(__NRFX_DOXYGEN__)
- __STATIC_INLINE void nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg,
- uint32_t dcx_pin);
- __STATIC_INLINE void nrf_spim_dcx_cnt_set(NRF_SPIM_Type * p_reg,
- uint32_t count);
- #endif
- #if defined(SPIM_IFTIMING_RXDELAY_RXDELAY_Msk) || defined(__NRFX_DOXYGEN__)
- __STATIC_INLINE void nrf_spim_iftiming_set(NRF_SPIM_Type * p_reg,
- uint32_t rxdelay);
- #endif
- #if defined(SPIM_STALLSTAT_RX_Msk) || defined(__NRFX_DOXYGEN__)
- __STATIC_INLINE void nrf_spim_stallstat_rx_clear(NRF_SPIM_Type * p_reg);
- __STATIC_INLINE bool nrf_spim_stallstat_rx_get(NRF_SPIM_Type * p_reg);
- #endif
- #if defined(SPIM_STALLSTAT_TX_Msk) || defined(__NRFX_DOXYGEN__)
- __STATIC_INLINE void nrf_spim_stallstat_tx_clear(NRF_SPIM_Type * p_reg);
- __STATIC_INLINE bool nrf_spim_stallstat_tx_get(NRF_SPIM_Type * p_reg);
- #endif
- __STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,
- nrf_spim_frequency_t frequency);
- __STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,
- uint8_t const * p_buffer,
- size_t length);
- __STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg,
- uint8_t * p_buffer,
- size_t length);
- __STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg,
- nrf_spim_mode_t spi_mode,
- nrf_spim_bit_order_t spi_bit_order);
- __STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg,
- uint8_t orc);
- __STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg);
- __STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg);
- __STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg);
- __STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg);
- #ifndef SUPPRESS_INLINE_IMPLEMENTATION
- __STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_reg,
- nrf_spim_task_t task)
- {
- *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
- }
- __STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type * p_reg,
- nrf_spim_task_t task)
- {
- return (uint32_t)((uint8_t *)p_reg + (uint32_t)task);
- }
- __STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg,
- nrf_spim_event_t event)
- {
- *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
- #if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
- #endif
- }
- __STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_reg,
- nrf_spim_event_t event)
- {
- return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
- }
- __STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type * p_reg,
- nrf_spim_event_t event)
- {
- return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
- }
- __STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg,
- uint32_t mask)
- {
- p_reg->SHORTS |= mask;
- }
- __STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg,
- uint32_t mask)
- {
- p_reg->SHORTS &= ~(mask);
- }
- __STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type * p_reg)
- {
- return p_reg->SHORTS;
- }
- __STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_reg,
- uint32_t mask)
- {
- p_reg->INTENSET = mask;
- }
- __STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_reg,
- uint32_t mask)
- {
- p_reg->INTENCLR = mask;
- }
- __STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_reg,
- nrf_spim_int_mask_t spim_int)
- {
- return (bool)(p_reg->INTENSET & spim_int);
- }
- #if defined(DPPI_PRESENT)
- __STATIC_INLINE void nrf_spim_subscribe_set(NRF_SPIM_Type * p_reg,
- nrf_spim_task_t task,
- uint8_t channel)
- {
- *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
- ((uint32_t)channel | SPIM_SUBSCRIBE_START_EN_Msk);
- }
- __STATIC_INLINE void nrf_spim_subscribe_clear(NRF_SPIM_Type * p_reg,
- nrf_spim_task_t task)
- {
- *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
- }
- __STATIC_INLINE void nrf_spim_publish_set(NRF_SPIM_Type * p_reg,
- nrf_spim_event_t event,
- uint8_t channel)
- {
- *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
- ((uint32_t)channel | SPIM_PUBLISH_STARTED_EN_Msk);
- }
- __STATIC_INLINE void nrf_spim_publish_clear(NRF_SPIM_Type * p_reg,
- nrf_spim_event_t event)
- {
- *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
- }
- #endif
- __STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_reg)
- {
- p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);
- }
- __STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg)
- {
- p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos);
- }
- __STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
- uint32_t sck_pin,
- uint32_t mosi_pin,
- uint32_t miso_pin)
- {
- p_reg->PSEL.SCK = sck_pin;
- p_reg->PSEL.MOSI = mosi_pin;
- p_reg->PSEL.MISO = miso_pin;
- }
- #if (NRF_SPIM_HW_CSN_PRESENT)
- __STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type * p_reg,
- uint32_t pin,
- nrf_spim_csn_pol_t polarity,
- uint32_t duration)
- {
- p_reg->PSEL.CSN = pin;
- p_reg->CSNPOL = polarity;
- p_reg->IFTIMING.CSNDUR = duration;
- }
- #endif
- #if defined(SPIM_PSELDCX_CONNECT_Msk)
- __STATIC_INLINE void nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg,
- uint32_t dcx_pin)
- {
- p_reg->PSELDCX = dcx_pin;
- }
- __STATIC_INLINE void nrf_spim_dcx_cnt_set(NRF_SPIM_Type * p_reg,
- uint32_t dcx_cnt)
- {
- p_reg->DCXCNT = dcx_cnt;
- }
- #endif
- #if defined(SPIM_IFTIMING_RXDELAY_RXDELAY_Msk)
- __STATIC_INLINE void nrf_spim_iftiming_set(NRF_SPIM_Type * p_reg,
- uint32_t rxdelay)
- {
- p_reg->IFTIMING.RXDELAY = rxdelay;
- }
- #endif
- #if defined(SPIM_STALLSTAT_RX_Msk)
- __STATIC_INLINE void nrf_spim_stallstat_rx_clear(NRF_SPIM_Type * p_reg)
- {
- p_reg->STALLSTAT &= ~(SPIM_STALLSTAT_RX_Msk);
- }
- __STATIC_INLINE bool nrf_spim_stallstat_rx_get(NRF_SPIM_Type * p_reg)
- {
- return (p_reg->STALLSTAT & SPIM_STALLSTAT_RX_Msk) != 0;
- }
- #endif
- #if defined(SPIM_STALLSTAT_TX_Msk)
- __STATIC_INLINE void nrf_spim_stallstat_tx_clear(NRF_SPIM_Type * p_reg)
- {
- p_reg->STALLSTAT &= ~(SPIM_STALLSTAT_TX_Msk);
- }
- __STATIC_INLINE bool nrf_spim_stallstat_tx_get(NRF_SPIM_Type * p_reg)
- {
- return (p_reg->STALLSTAT & SPIM_STALLSTAT_TX_Msk) != 0;
- }
- #endif
- __STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,
- nrf_spim_frequency_t frequency)
- {
- p_reg->FREQUENCY = (uint32_t)frequency;
- }
- __STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,
- uint8_t const * p_buffer,
- size_t length)
- {
- p_reg->TXD.PTR = (uint32_t)p_buffer;
- p_reg->TXD.MAXCNT = length;
- }
- __STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg,
- uint8_t * p_buffer,
- size_t length)
- {
- p_reg->RXD.PTR = (uint32_t)p_buffer;
- p_reg->RXD.MAXCNT = length;
- }
- __STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg,
- nrf_spim_mode_t spi_mode,
- nrf_spim_bit_order_t spi_bit_order)
- {
- uint32_t config = (spi_bit_order == NRF_SPIM_BIT_ORDER_MSB_FIRST ?
- SPIM_CONFIG_ORDER_MsbFirst : SPIM_CONFIG_ORDER_LsbFirst);
- switch (spi_mode)
- {
- default:
- case NRF_SPIM_MODE_0:
- config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
- (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
- break;
- case NRF_SPIM_MODE_1:
- config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
- (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
- break;
- case NRF_SPIM_MODE_2:
- config |= (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
- (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
- break;
- case NRF_SPIM_MODE_3:
- config |= (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
- (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
- break;
- }
- p_reg->CONFIG = config;
- }
- __STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg,
- uint8_t orc)
- {
- p_reg->ORC = orc;
- }
- __STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg)
- {
- p_reg->TXD.LIST = 1;
- }
- __STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg)
- {
- p_reg->TXD.LIST = 0;
- }
- __STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg)
- {
- p_reg->RXD.LIST = 1;
- }
- __STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg)
- {
- p_reg->RXD.LIST = 0;
- }
- #endif
- #ifdef __cplusplus
- }
- #endif
- #endif
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