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- #ifndef NRF_QSPI_H__
- #define NRF_QSPI_H__
- #include <nrfx.h>
- #ifdef __cplusplus
- extern "C" {
- #endif
- #define NRF_QSPI_PIN_NOT_CONNECTED 0xFF
- #define NRF_QSPI_PIN_VAL(pin) (pin) == NRF_QSPI_PIN_NOT_CONNECTED ? 0xFFFFFFFF : (pin)
- typedef enum
- {
- NRF_QSPI_TASK_ACTIVATE = offsetof(NRF_QSPI_Type, TASKS_ACTIVATE),
- NRF_QSPI_TASK_READSTART = offsetof(NRF_QSPI_Type, TASKS_READSTART),
- NRF_QSPI_TASK_WRITESTART = offsetof(NRF_QSPI_Type, TASKS_WRITESTART),
- NRF_QSPI_TASK_ERASESTART = offsetof(NRF_QSPI_Type, TASKS_ERASESTART),
- NRF_QSPI_TASK_DEACTIVATE = offsetof(NRF_QSPI_Type, TASKS_DEACTIVATE),
- } nrf_qspi_task_t;
- typedef enum
- {
- NRF_QSPI_EVENT_READY = offsetof(NRF_QSPI_Type, EVENTS_READY)
- } nrf_qspi_event_t;
- typedef enum
- {
- NRF_QSPI_INT_READY_MASK = QSPI_INTENSET_READY_Msk
- } nrf_qspi_int_mask_t;
- typedef enum
- {
- NRF_QSPI_FREQ_32MDIV1,
- NRF_QSPI_FREQ_32MDIV2,
- NRF_QSPI_FREQ_32MDIV3,
- NRF_QSPI_FREQ_32MDIV4,
- NRF_QSPI_FREQ_32MDIV5,
- NRF_QSPI_FREQ_32MDIV6,
- NRF_QSPI_FREQ_32MDIV7,
- NRF_QSPI_FREQ_32MDIV8,
- NRF_QSPI_FREQ_32MDIV9,
- NRF_QSPI_FREQ_32MDIV10,
- NRF_QSPI_FREQ_32MDIV11,
- NRF_QSPI_FREQ_32MDIV12,
- NRF_QSPI_FREQ_32MDIV13,
- NRF_QSPI_FREQ_32MDIV14,
- NRF_QSPI_FREQ_32MDIV15,
- NRF_QSPI_FREQ_32MDIV16,
- } nrf_qspi_frequency_t;
- typedef enum
- {
- NRF_QSPI_READOC_FASTREAD = QSPI_IFCONFIG0_READOC_FASTREAD,
- NRF_QSPI_READOC_READ2O = QSPI_IFCONFIG0_READOC_READ2O,
- NRF_QSPI_READOC_READ2IO = QSPI_IFCONFIG0_READOC_READ2IO,
- NRF_QSPI_READOC_READ4O = QSPI_IFCONFIG0_READOC_READ4O,
- NRF_QSPI_READOC_READ4IO = QSPI_IFCONFIG0_READOC_READ4IO
- } nrf_qspi_readoc_t;
- typedef enum
- {
- NRF_QSPI_WRITEOC_PP = QSPI_IFCONFIG0_WRITEOC_PP,
- NRF_QSPI_WRITEOC_PP2O = QSPI_IFCONFIG0_WRITEOC_PP2O,
- NRF_QSPI_WRITEOC_PP4O = QSPI_IFCONFIG0_WRITEOC_PP4O,
- NRF_QSPI_WRITEOC_PP4IO = QSPI_IFCONFIG0_WRITEOC_PP4IO,
- } nrf_qspi_writeoc_t;
- typedef enum
- {
- NRF_QSPI_ADDRMODE_24BIT = QSPI_IFCONFIG0_ADDRMODE_24BIT,
- NRF_QSPI_ADDRMODE_32BIT = QSPI_IFCONFIG0_ADDRMODE_32BIT
- } nrf_qspi_addrmode_t;
- typedef enum
- {
- NRF_QSPI_MODE_0 = QSPI_IFCONFIG1_SPIMODE_MODE0,
- NRF_QSPI_MODE_1 = QSPI_IFCONFIG1_SPIMODE_MODE3
- } nrf_qspi_spi_mode_t;
- typedef enum
- {
- NRF_QSPI_ADDRCONF_MODE_NOINSTR = QSPI_ADDRCONF_MODE_NoInstr,
- NRF_QSPI_ADDRCONF_MODE_OPCODE = QSPI_ADDRCONF_MODE_Opcode,
- NRF_QSPI_ADDRCONF_MODE_OPBYTE0 = QSPI_ADDRCONF_MODE_OpByte0,
- NRF_QSPI_ADDRCONF_MODE_ALL = QSPI_ADDRCONF_MODE_All
- } nrf_qspi_addrconfig_mode_t;
- typedef enum
- {
- NRF_QSPI_ERASE_LEN_4KB = QSPI_ERASE_LEN_LEN_4KB,
- NRF_QSPI_ERASE_LEN_64KB = QSPI_ERASE_LEN_LEN_64KB,
- NRF_QSPI_ERASE_LEN_ALL = QSPI_ERASE_LEN_LEN_All
- } nrf_qspi_erase_len_t;
- typedef enum
- {
- NRF_QSPI_CINSTR_LEN_1B = QSPI_CINSTRCONF_LENGTH_1B,
- NRF_QSPI_CINSTR_LEN_2B = QSPI_CINSTRCONF_LENGTH_2B,
- NRF_QSPI_CINSTR_LEN_3B = QSPI_CINSTRCONF_LENGTH_3B,
- NRF_QSPI_CINSTR_LEN_4B = QSPI_CINSTRCONF_LENGTH_4B,
- NRF_QSPI_CINSTR_LEN_5B = QSPI_CINSTRCONF_LENGTH_5B,
- NRF_QSPI_CINSTR_LEN_6B = QSPI_CINSTRCONF_LENGTH_6B,
- NRF_QSPI_CINSTR_LEN_7B = QSPI_CINSTRCONF_LENGTH_7B,
- NRF_QSPI_CINSTR_LEN_8B = QSPI_CINSTRCONF_LENGTH_8B,
- NRF_QSPI_CINSTR_LEN_9B = QSPI_CINSTRCONF_LENGTH_9B
- } nrf_qspi_cinstr_len_t;
- typedef struct
- {
- uint8_t sck_pin;
- uint8_t csn_pin;
- uint8_t io0_pin;
- uint8_t io1_pin;
- uint8_t io2_pin;
- uint8_t io3_pin;
- } nrf_qspi_pins_t;
- typedef struct
- {
- uint8_t opcode;
- nrf_qspi_cinstr_len_t length;
- bool io2_level;
- bool io3_level;
- bool wipwait;
- bool wren;
- } nrf_qspi_cinstr_conf_t;
- typedef struct
- {
- uint8_t opcode;
- uint8_t byte0;
- uint8_t byte1;
- nrf_qspi_addrconfig_mode_t mode;
- bool wipwait;
- bool wren;
- } nrf_qspi_addrconfig_conf_t;
- typedef struct
- {
- nrf_qspi_readoc_t readoc;
- nrf_qspi_writeoc_t writeoc;
- nrf_qspi_addrmode_t addrmode;
- bool dpmconfig;
- } nrf_qspi_prot_conf_t;
- typedef struct
- {
- uint8_t sck_delay;
- bool dpmen;
- nrf_qspi_spi_mode_t spi_mode;
- nrf_qspi_frequency_t sck_freq;
- } nrf_qspi_phy_conf_t;
- __STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task);
- __STATIC_INLINE uint32_t nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg,
- nrf_qspi_task_t task);
- __STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t event);
- __STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t event);
- __STATIC_INLINE uint32_t * nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg,
- nrf_qspi_event_t event);
- __STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t mask);
- __STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t mask);
- __STATIC_INLINE bool nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg,
- nrf_qspi_int_mask_t qspi_int);
- __STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type * p_reg);
- __STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg);
- __STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg,
- const nrf_qspi_pins_t * p_pins);
- __STATIC_INLINE void nrf_qspi_xip_offset_set(NRF_QSPI_Type * p_reg,
- uint32_t xip_offset);
- __STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg,
- const nrf_qspi_prot_conf_t * p_config);
- __STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg,
- const nrf_qspi_phy_conf_t * p_config);
- __STATIC_INLINE void nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg,
- const nrf_qspi_addrconfig_conf_t * p_config);
- __STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg,
- void const * p_buffer,
- uint32_t length,
- uint32_t dest_addr);
- __STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg,
- void * p_buffer,
- uint32_t length,
- uint32_t src_addr);
- __STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg,
- uint32_t erase_addr,
- nrf_qspi_erase_len_t len);
- __STATIC_INLINE uint32_t nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg);
- __STATIC_INLINE uint8_t nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg);
- __STATIC_INLINE bool nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg);
- __STATIC_INLINE void nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg,
- nrf_qspi_cinstr_len_t length,
- void const * p_tx_data);
- __STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg,
- nrf_qspi_cinstr_len_t length,
- void * p_rx_data);
- __STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg,
- const nrf_qspi_cinstr_conf_t * p_config);
- __STATIC_INLINE void nrf_qspi_cinstr_long_transfer_start(NRF_QSPI_Type * p_reg,
- const nrf_qspi_cinstr_conf_t * p_config);
- __STATIC_INLINE bool nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI_Type const * p_reg);
- __STATIC_INLINE void nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI_Type * p_reg,
- nrf_qspi_cinstr_len_t length,
- bool finalize);
- #ifndef SUPPRESS_INLINE_IMPLEMENTATION
- __STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task)
- {
- *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
- }
- __STATIC_INLINE uint32_t nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg,
- nrf_qspi_task_t task)
- {
- return ((uint32_t)p_reg + (uint32_t)task);
- }
- __STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t event)
- {
- *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
- }
- __STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t event)
- {
- return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
- }
- __STATIC_INLINE uint32_t * nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg,
- nrf_qspi_event_t event)
- {
- return (uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
- }
- __STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t mask)
- {
- p_reg->INTENSET = mask;
- }
- __STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t mask)
- {
- p_reg->INTENCLR = mask;
- }
- __STATIC_INLINE bool nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg,
- nrf_qspi_int_mask_t qspi_int)
- {
- return (bool)(p_reg->INTENSET & qspi_int);
- }
- __STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type * p_reg)
- {
- p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Enabled << QSPI_ENABLE_ENABLE_Pos);
- }
- __STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg)
- {
-
- *(volatile uint32_t *)0x40029054ul = 1ul;
- p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Disabled << QSPI_ENABLE_ENABLE_Pos);
- }
- __STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg, const nrf_qspi_pins_t * p_pins)
- {
- p_reg->PSEL.SCK = NRF_QSPI_PIN_VAL(p_pins->sck_pin);
- p_reg->PSEL.CSN = NRF_QSPI_PIN_VAL(p_pins->csn_pin);
- p_reg->PSEL.IO0 = NRF_QSPI_PIN_VAL(p_pins->io0_pin);
- p_reg->PSEL.IO1 = NRF_QSPI_PIN_VAL(p_pins->io1_pin);
- p_reg->PSEL.IO2 = NRF_QSPI_PIN_VAL(p_pins->io2_pin);
- p_reg->PSEL.IO3 = NRF_QSPI_PIN_VAL(p_pins->io3_pin);
- }
- __STATIC_INLINE void nrf_qspi_xip_offset_set(NRF_QSPI_Type * p_reg,
- uint32_t xip_offset)
- {
- p_reg->XIPOFFSET = xip_offset;
- }
- __STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg,
- const nrf_qspi_prot_conf_t * p_config)
- {
- uint32_t config = p_config->readoc;
- config |= ((uint32_t)p_config->writeoc) << QSPI_IFCONFIG0_WRITEOC_Pos;
- config |= ((uint32_t)p_config->addrmode) << QSPI_IFCONFIG0_ADDRMODE_Pos;
- config |= (p_config->dpmconfig ? 1U : 0U ) << QSPI_IFCONFIG0_DPMENABLE_Pos;
- p_reg->IFCONFIG0 = config;
- }
- __STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg,
- const nrf_qspi_phy_conf_t * p_config)
- {
-
- uint32_t config = p_reg->IFCONFIG1 & 0x00FFFF00;
- config |= p_config->sck_delay;
- config |= (p_config->dpmen ? 1U : 0U) << QSPI_IFCONFIG1_DPMEN_Pos;
- config |= ((uint32_t)(p_config->spi_mode)) << QSPI_IFCONFIG1_SPIMODE_Pos;
- config |= ((uint32_t)(p_config->sck_freq)) << QSPI_IFCONFIG1_SCKFREQ_Pos;
- p_reg->IFCONFIG1 = config;
- }
- __STATIC_INLINE void nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg,
- const nrf_qspi_addrconfig_conf_t * p_config)
- {
- uint32_t config = p_config->opcode;
- config |= ((uint32_t)p_config->byte0) << QSPI_ADDRCONF_BYTE0_Pos;
- config |= ((uint32_t)p_config->byte1) << QSPI_ADDRCONF_BYTE1_Pos;
- config |= ((uint32_t)(p_config->mode)) << QSPI_ADDRCONF_MODE_Pos;
- config |= (p_config->wipwait ? 1U : 0U) << QSPI_ADDRCONF_WIPWAIT_Pos;
- config |= (p_config->wren ? 1U : 0U) << QSPI_ADDRCONF_WREN_Pos;
- p_reg->ADDRCONF = config;
- }
- __STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg,
- void const * p_buffer,
- uint32_t length,
- uint32_t dest_addr)
- {
- p_reg->WRITE.DST = dest_addr;
- p_reg->WRITE.SRC = (uint32_t) p_buffer;
- p_reg->WRITE.CNT = length;
- }
- __STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg,
- void * p_buffer,
- uint32_t length,
- uint32_t src_addr)
- {
- p_reg->READ.SRC = src_addr;
- p_reg->READ.DST = (uint32_t) p_buffer;
- p_reg->READ.CNT = length;
- }
- __STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg,
- uint32_t erase_addr,
- nrf_qspi_erase_len_t len)
- {
- p_reg->ERASE.PTR = erase_addr;
- p_reg->ERASE.LEN = len;
- }
- __STATIC_INLINE uint32_t nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg)
- {
- return p_reg->STATUS;
- }
- __STATIC_INLINE uint8_t nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg)
- {
- return (uint8_t)(p_reg->STATUS & QSPI_STATUS_SREG_Msk) >> QSPI_STATUS_SREG_Pos;
- }
- __STATIC_INLINE bool nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg)
- {
- return ((p_reg->STATUS & QSPI_STATUS_READY_Msk) >>
- QSPI_STATUS_READY_Pos) == QSPI_STATUS_READY_BUSY;
- }
- __STATIC_INLINE void nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg,
- nrf_qspi_cinstr_len_t length,
- void const * p_tx_data)
- {
- uint32_t reg = 0;
- uint8_t const *p_tx_data_8 = (uint8_t const *) p_tx_data;
-
- switch (length)
- {
- case NRF_QSPI_CINSTR_LEN_9B:
- reg |= ((uint32_t)p_tx_data_8[7]) << QSPI_CINSTRDAT1_BYTE7_Pos;
-
- case NRF_QSPI_CINSTR_LEN_8B:
- reg |= ((uint32_t)p_tx_data_8[6]) << QSPI_CINSTRDAT1_BYTE6_Pos;
-
- case NRF_QSPI_CINSTR_LEN_7B:
- reg |= ((uint32_t)p_tx_data_8[5]) << QSPI_CINSTRDAT1_BYTE5_Pos;
-
- case NRF_QSPI_CINSTR_LEN_6B:
- reg |= ((uint32_t)p_tx_data_8[4]);
- p_reg->CINSTRDAT1 = reg;
- reg = 0;
-
- case NRF_QSPI_CINSTR_LEN_5B:
- reg |= ((uint32_t)p_tx_data_8[3]) << QSPI_CINSTRDAT0_BYTE3_Pos;
-
- case NRF_QSPI_CINSTR_LEN_4B:
- reg |= ((uint32_t)p_tx_data_8[2]) << QSPI_CINSTRDAT0_BYTE2_Pos;
-
- case NRF_QSPI_CINSTR_LEN_3B:
- reg |= ((uint32_t)p_tx_data_8[1]) << QSPI_CINSTRDAT0_BYTE1_Pos;
-
- case NRF_QSPI_CINSTR_LEN_2B:
- reg |= ((uint32_t)p_tx_data_8[0]);
- p_reg->CINSTRDAT0 = reg;
-
- case NRF_QSPI_CINSTR_LEN_1B:
-
- break;
- default:
- break;
- }
- }
- __STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg,
- nrf_qspi_cinstr_len_t length,
- void * p_rx_data)
- {
- uint8_t *p_rx_data_8 = (uint8_t *) p_rx_data;
- uint32_t reg1 = p_reg->CINSTRDAT1;
- uint32_t reg0 = p_reg->CINSTRDAT0;
- switch (length)
- {
- case NRF_QSPI_CINSTR_LEN_9B:
- p_rx_data_8[7] = (uint8_t)(reg1 >> QSPI_CINSTRDAT1_BYTE7_Pos);
-
- case NRF_QSPI_CINSTR_LEN_8B:
- p_rx_data_8[6] = (uint8_t)(reg1 >> QSPI_CINSTRDAT1_BYTE6_Pos);
-
- case NRF_QSPI_CINSTR_LEN_7B:
- p_rx_data_8[5] = (uint8_t)(reg1 >> QSPI_CINSTRDAT1_BYTE5_Pos);
-
- case NRF_QSPI_CINSTR_LEN_6B:
- p_rx_data_8[4] = (uint8_t)(reg1);
-
- case NRF_QSPI_CINSTR_LEN_5B:
- p_rx_data_8[3] = (uint8_t)(reg0 >> QSPI_CINSTRDAT0_BYTE3_Pos);
-
- case NRF_QSPI_CINSTR_LEN_4B:
- p_rx_data_8[2] = (uint8_t)(reg0 >> QSPI_CINSTRDAT0_BYTE2_Pos);
-
- case NRF_QSPI_CINSTR_LEN_3B:
- p_rx_data_8[1] = (uint8_t)(reg0 >> QSPI_CINSTRDAT0_BYTE1_Pos);
-
- case NRF_QSPI_CINSTR_LEN_2B:
- p_rx_data_8[0] = (uint8_t)(reg0);
-
- case NRF_QSPI_CINSTR_LEN_1B:
-
- break;
- default:
- break;
- }
- }
- __STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg,
- const nrf_qspi_cinstr_conf_t * p_config)
- {
- p_reg->CINSTRCONF = (((uint32_t)p_config->opcode << QSPI_CINSTRCONF_OPCODE_Pos) |
- ((uint32_t)p_config->length << QSPI_CINSTRCONF_LENGTH_Pos) |
- ((uint32_t)p_config->io2_level << QSPI_CINSTRCONF_LIO2_Pos) |
- ((uint32_t)p_config->io3_level << QSPI_CINSTRCONF_LIO3_Pos) |
- ((uint32_t)p_config->wipwait << QSPI_CINSTRCONF_WIPWAIT_Pos) |
- ((uint32_t)p_config->wren << QSPI_CINSTRCONF_WREN_Pos));
- }
- __STATIC_INLINE void nrf_qspi_cinstr_long_transfer_start(NRF_QSPI_Type * p_reg,
- const nrf_qspi_cinstr_conf_t * p_config)
- {
- p_reg->CINSTRCONF = (((uint32_t)p_config->opcode << QSPI_CINSTRCONF_OPCODE_Pos) |
- ((uint32_t)p_config->length << QSPI_CINSTRCONF_LENGTH_Pos) |
- ((uint32_t)p_config->io2_level << QSPI_CINSTRCONF_LIO2_Pos) |
- ((uint32_t)p_config->io3_level << QSPI_CINSTRCONF_LIO3_Pos) |
- ((uint32_t)p_config->wipwait << QSPI_CINSTRCONF_WIPWAIT_Pos) |
- ((uint32_t)p_config->wren << QSPI_CINSTRCONF_WREN_Pos) |
- (QSPI_CINSTRCONF_LFEN_Msk));
- }
- __STATIC_INLINE bool nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI_Type const * p_reg)
- {
- return (bool)((p_reg->CINSTRCONF & (QSPI_CINSTRCONF_LFEN_Msk | QSPI_CINSTRCONF_LFSTOP_Msk))
- == QSPI_CINSTRCONF_LFEN_Msk);
- }
- __STATIC_INLINE void nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI_Type * p_reg,
- nrf_qspi_cinstr_len_t length,
- bool finalize)
- {
- uint32_t mask = (((uint32_t)length << QSPI_CINSTRCONF_LENGTH_Pos) | (QSPI_CINSTRCONF_LFEN_Msk));
- mask |= (finalize ? QSPI_CINSTRCONF_LFSTOP_Msk : 0);
- p_reg->CINSTRCONF = mask;
- }
- #endif
- #ifdef __cplusplus
- }
- #endif
- #endif
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