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- #ifndef __NRF9160_BITS_H
- #define __NRF9160_BITS_H
- #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos (0UL)
- #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Msk (0x3UL << CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos)
- #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_DR (0UL)
- #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_PRTL (1UL)
- #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Session (2UL)
- #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos (0UL)
- #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos)
- #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Disabled (0UL)
- #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Enabled (1UL)
- #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos (0UL)
- #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos)
- #define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos (0UL)
- #define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos)
- #define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos (0UL)
- #define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos)
- #define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos (0UL)
- #define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos)
- #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos (8UL)
- #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos)
- #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Invalid (0UL)
- #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Valid (1UL)
- #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos (0UL)
- #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Msk (0x7UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos)
- #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Debug (0UL)
- #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Secure (2UL)
- #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL)
- #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos)
- #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL)
- #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL)
- #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos)
- #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL)
- #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL)
- #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos)
- #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL)
- #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL)
- #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos)
- #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos (31UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos)
- #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Disabled (0UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Enabled (1UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos (0UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Msk (0xFUL << CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos)
- #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos (31UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos)
- #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Disabled (0UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Enabled (1UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos (0UL)
- #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Msk (0xFUL << CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos)
- #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos (31UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos)
- #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (1UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos (0UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Msk (0xFUL << CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos)
- #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos (31UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos)
- #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (1UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos (0UL)
- #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Msk (0xFUL << CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos)
- #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL)
- #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos)
- #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL)
- #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL)
- #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL)
- #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos)
- #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL)
- #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL)
- #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos (31UL)
- #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos)
- #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Disabled (0UL)
- #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Enabled (1UL)
- #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos (0UL)
- #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Msk (0xFUL << CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos)
- #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos (31UL)
- #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos)
- #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Disabled (0UL)
- #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (1UL)
- #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos (0UL)
- #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Msk (0xFUL << CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos)
- #define CLOCK_INTEN_LFCLKSTARTED_Pos (1UL)
- #define CLOCK_INTEN_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_LFCLKSTARTED_Pos)
- #define CLOCK_INTEN_LFCLKSTARTED_Disabled (0UL)
- #define CLOCK_INTEN_LFCLKSTARTED_Enabled (1UL)
- #define CLOCK_INTEN_HFCLKSTARTED_Pos (0UL)
- #define CLOCK_INTEN_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKSTARTED_Pos)
- #define CLOCK_INTEN_HFCLKSTARTED_Disabled (0UL)
- #define CLOCK_INTEN_HFCLKSTARTED_Enabled (1UL)
- #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL)
- #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos)
- #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL)
- #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL)
- #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL)
- #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL)
- #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos)
- #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL)
- #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL)
- #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL)
- #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL)
- #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos)
- #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL)
- #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL)
- #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL)
- #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL)
- #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos)
- #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL)
- #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL)
- #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL)
- #define CLOCK_INTPEND_LFCLKSTARTED_Pos (1UL)
- #define CLOCK_INTPEND_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_LFCLKSTARTED_Pos)
- #define CLOCK_INTPEND_LFCLKSTARTED_NotPending (0UL)
- #define CLOCK_INTPEND_LFCLKSTARTED_Pending (1UL)
- #define CLOCK_INTPEND_HFCLKSTARTED_Pos (0UL)
- #define CLOCK_INTPEND_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKSTARTED_Pos)
- #define CLOCK_INTPEND_HFCLKSTARTED_NotPending (0UL)
- #define CLOCK_INTPEND_HFCLKSTARTED_Pending (1UL)
- #define CLOCK_HFCLKRUN_STATUS_Pos (0UL)
- #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos)
- #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL)
- #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL)
- #define CLOCK_HFCLKSTAT_STATE_Pos (16UL)
- #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos)
- #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL)
- #define CLOCK_HFCLKSTAT_STATE_Running (1UL)
- #define CLOCK_HFCLKSTAT_SRC_Pos (0UL)
- #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos)
- #define CLOCK_HFCLKSTAT_SRC_HFXO (1UL)
- #define CLOCK_LFCLKRUN_STATUS_Pos (0UL)
- #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos)
- #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL)
- #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL)
- #define CLOCK_LFCLKSTAT_STATE_Pos (16UL)
- #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos)
- #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL)
- #define CLOCK_LFCLKSTAT_STATE_Running (1UL)
- #define CLOCK_LFCLKSTAT_SRC_Pos (0UL)
- #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos)
- #define CLOCK_LFCLKSTAT_SRC_RFU (0UL)
- #define CLOCK_LFCLKSTAT_SRC_LFRC (1UL)
- #define CLOCK_LFCLKSTAT_SRC_LFXO (2UL)
- #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL)
- #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos)
- #define CLOCK_LFCLKSRCCOPY_SRC_RFU (0UL)
- #define CLOCK_LFCLKSRCCOPY_SRC_LFRC (1UL)
- #define CLOCK_LFCLKSRCCOPY_SRC_LFXO (2UL)
- #define CLOCK_LFCLKSRC_SRC_Pos (0UL)
- #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos)
- #define CLOCK_LFCLKSRC_SRC_RFU (0UL)
- #define CLOCK_LFCLKSRC_SRC_LFRC (1UL)
- #define CLOCK_LFCLKSRC_SRC_LFXO (2UL)
- #define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL)
- #define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos)
- #define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL)
- #define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL)
- #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos (0UL)
- #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos)
- #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos (0UL)
- #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos)
- #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_NoDataPending (0UL)
- #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (1UL)
- #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos (0UL)
- #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos)
- #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos (0UL)
- #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos)
- #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_NoDataPending (0UL)
- #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (1UL)
- #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos (0UL)
- #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos)
- #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked (0UL)
- #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked (1UL)
- #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos (0UL)
- #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos)
- #define DPPIC_TASKS_CHG_EN_EN_Pos (0UL)
- #define DPPIC_TASKS_CHG_EN_EN_Msk (0x1UL << DPPIC_TASKS_CHG_EN_EN_Pos)
- #define DPPIC_TASKS_CHG_EN_EN_Trigger (1UL)
- #define DPPIC_TASKS_CHG_DIS_DIS_Pos (0UL)
- #define DPPIC_TASKS_CHG_DIS_DIS_Msk (0x1UL << DPPIC_TASKS_CHG_DIS_DIS_Pos)
- #define DPPIC_TASKS_CHG_DIS_DIS_Trigger (1UL)
- #define DPPIC_SUBSCRIBE_CHG_EN_EN_Pos (31UL)
- #define DPPIC_SUBSCRIBE_CHG_EN_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_EN_EN_Pos)
- #define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0UL)
- #define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (1UL)
- #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL)
- #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos)
- #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos (31UL)
- #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos)
- #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0UL)
- #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (1UL)
- #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL)
- #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos)
- #define DPPIC_CHEN_CH15_Pos (15UL)
- #define DPPIC_CHEN_CH15_Msk (0x1UL << DPPIC_CHEN_CH15_Pos)
- #define DPPIC_CHEN_CH15_Disabled (0UL)
- #define DPPIC_CHEN_CH15_Enabled (1UL)
- #define DPPIC_CHEN_CH14_Pos (14UL)
- #define DPPIC_CHEN_CH14_Msk (0x1UL << DPPIC_CHEN_CH14_Pos)
- #define DPPIC_CHEN_CH14_Disabled (0UL)
- #define DPPIC_CHEN_CH14_Enabled (1UL)
- #define DPPIC_CHEN_CH13_Pos (13UL)
- #define DPPIC_CHEN_CH13_Msk (0x1UL << DPPIC_CHEN_CH13_Pos)
- #define DPPIC_CHEN_CH13_Disabled (0UL)
- #define DPPIC_CHEN_CH13_Enabled (1UL)
- #define DPPIC_CHEN_CH12_Pos (12UL)
- #define DPPIC_CHEN_CH12_Msk (0x1UL << DPPIC_CHEN_CH12_Pos)
- #define DPPIC_CHEN_CH12_Disabled (0UL)
- #define DPPIC_CHEN_CH12_Enabled (1UL)
- #define DPPIC_CHEN_CH11_Pos (11UL)
- #define DPPIC_CHEN_CH11_Msk (0x1UL << DPPIC_CHEN_CH11_Pos)
- #define DPPIC_CHEN_CH11_Disabled (0UL)
- #define DPPIC_CHEN_CH11_Enabled (1UL)
- #define DPPIC_CHEN_CH10_Pos (10UL)
- #define DPPIC_CHEN_CH10_Msk (0x1UL << DPPIC_CHEN_CH10_Pos)
- #define DPPIC_CHEN_CH10_Disabled (0UL)
- #define DPPIC_CHEN_CH10_Enabled (1UL)
- #define DPPIC_CHEN_CH9_Pos (9UL)
- #define DPPIC_CHEN_CH9_Msk (0x1UL << DPPIC_CHEN_CH9_Pos)
- #define DPPIC_CHEN_CH9_Disabled (0UL)
- #define DPPIC_CHEN_CH9_Enabled (1UL)
- #define DPPIC_CHEN_CH8_Pos (8UL)
- #define DPPIC_CHEN_CH8_Msk (0x1UL << DPPIC_CHEN_CH8_Pos)
- #define DPPIC_CHEN_CH8_Disabled (0UL)
- #define DPPIC_CHEN_CH8_Enabled (1UL)
- #define DPPIC_CHEN_CH7_Pos (7UL)
- #define DPPIC_CHEN_CH7_Msk (0x1UL << DPPIC_CHEN_CH7_Pos)
- #define DPPIC_CHEN_CH7_Disabled (0UL)
- #define DPPIC_CHEN_CH7_Enabled (1UL)
- #define DPPIC_CHEN_CH6_Pos (6UL)
- #define DPPIC_CHEN_CH6_Msk (0x1UL << DPPIC_CHEN_CH6_Pos)
- #define DPPIC_CHEN_CH6_Disabled (0UL)
- #define DPPIC_CHEN_CH6_Enabled (1UL)
- #define DPPIC_CHEN_CH5_Pos (5UL)
- #define DPPIC_CHEN_CH5_Msk (0x1UL << DPPIC_CHEN_CH5_Pos)
- #define DPPIC_CHEN_CH5_Disabled (0UL)
- #define DPPIC_CHEN_CH5_Enabled (1UL)
- #define DPPIC_CHEN_CH4_Pos (4UL)
- #define DPPIC_CHEN_CH4_Msk (0x1UL << DPPIC_CHEN_CH4_Pos)
- #define DPPIC_CHEN_CH4_Disabled (0UL)
- #define DPPIC_CHEN_CH4_Enabled (1UL)
- #define DPPIC_CHEN_CH3_Pos (3UL)
- #define DPPIC_CHEN_CH3_Msk (0x1UL << DPPIC_CHEN_CH3_Pos)
- #define DPPIC_CHEN_CH3_Disabled (0UL)
- #define DPPIC_CHEN_CH3_Enabled (1UL)
- #define DPPIC_CHEN_CH2_Pos (2UL)
- #define DPPIC_CHEN_CH2_Msk (0x1UL << DPPIC_CHEN_CH2_Pos)
- #define DPPIC_CHEN_CH2_Disabled (0UL)
- #define DPPIC_CHEN_CH2_Enabled (1UL)
- #define DPPIC_CHEN_CH1_Pos (1UL)
- #define DPPIC_CHEN_CH1_Msk (0x1UL << DPPIC_CHEN_CH1_Pos)
- #define DPPIC_CHEN_CH1_Disabled (0UL)
- #define DPPIC_CHEN_CH1_Enabled (1UL)
- #define DPPIC_CHEN_CH0_Pos (0UL)
- #define DPPIC_CHEN_CH0_Msk (0x1UL << DPPIC_CHEN_CH0_Pos)
- #define DPPIC_CHEN_CH0_Disabled (0UL)
- #define DPPIC_CHEN_CH0_Enabled (1UL)
- #define DPPIC_CHENSET_CH15_Pos (15UL)
- #define DPPIC_CHENSET_CH15_Msk (0x1UL << DPPIC_CHENSET_CH15_Pos)
- #define DPPIC_CHENSET_CH15_Disabled (0UL)
- #define DPPIC_CHENSET_CH15_Enabled (1UL)
- #define DPPIC_CHENSET_CH15_Set (1UL)
- #define DPPIC_CHENSET_CH14_Pos (14UL)
- #define DPPIC_CHENSET_CH14_Msk (0x1UL << DPPIC_CHENSET_CH14_Pos)
- #define DPPIC_CHENSET_CH14_Disabled (0UL)
- #define DPPIC_CHENSET_CH14_Enabled (1UL)
- #define DPPIC_CHENSET_CH14_Set (1UL)
- #define DPPIC_CHENSET_CH13_Pos (13UL)
- #define DPPIC_CHENSET_CH13_Msk (0x1UL << DPPIC_CHENSET_CH13_Pos)
- #define DPPIC_CHENSET_CH13_Disabled (0UL)
- #define DPPIC_CHENSET_CH13_Enabled (1UL)
- #define DPPIC_CHENSET_CH13_Set (1UL)
- #define DPPIC_CHENSET_CH12_Pos (12UL)
- #define DPPIC_CHENSET_CH12_Msk (0x1UL << DPPIC_CHENSET_CH12_Pos)
- #define DPPIC_CHENSET_CH12_Disabled (0UL)
- #define DPPIC_CHENSET_CH12_Enabled (1UL)
- #define DPPIC_CHENSET_CH12_Set (1UL)
- #define DPPIC_CHENSET_CH11_Pos (11UL)
- #define DPPIC_CHENSET_CH11_Msk (0x1UL << DPPIC_CHENSET_CH11_Pos)
- #define DPPIC_CHENSET_CH11_Disabled (0UL)
- #define DPPIC_CHENSET_CH11_Enabled (1UL)
- #define DPPIC_CHENSET_CH11_Set (1UL)
- #define DPPIC_CHENSET_CH10_Pos (10UL)
- #define DPPIC_CHENSET_CH10_Msk (0x1UL << DPPIC_CHENSET_CH10_Pos)
- #define DPPIC_CHENSET_CH10_Disabled (0UL)
- #define DPPIC_CHENSET_CH10_Enabled (1UL)
- #define DPPIC_CHENSET_CH10_Set (1UL)
- #define DPPIC_CHENSET_CH9_Pos (9UL)
- #define DPPIC_CHENSET_CH9_Msk (0x1UL << DPPIC_CHENSET_CH9_Pos)
- #define DPPIC_CHENSET_CH9_Disabled (0UL)
- #define DPPIC_CHENSET_CH9_Enabled (1UL)
- #define DPPIC_CHENSET_CH9_Set (1UL)
- #define DPPIC_CHENSET_CH8_Pos (8UL)
- #define DPPIC_CHENSET_CH8_Msk (0x1UL << DPPIC_CHENSET_CH8_Pos)
- #define DPPIC_CHENSET_CH8_Disabled (0UL)
- #define DPPIC_CHENSET_CH8_Enabled (1UL)
- #define DPPIC_CHENSET_CH8_Set (1UL)
- #define DPPIC_CHENSET_CH7_Pos (7UL)
- #define DPPIC_CHENSET_CH7_Msk (0x1UL << DPPIC_CHENSET_CH7_Pos)
- #define DPPIC_CHENSET_CH7_Disabled (0UL)
- #define DPPIC_CHENSET_CH7_Enabled (1UL)
- #define DPPIC_CHENSET_CH7_Set (1UL)
- #define DPPIC_CHENSET_CH6_Pos (6UL)
- #define DPPIC_CHENSET_CH6_Msk (0x1UL << DPPIC_CHENSET_CH6_Pos)
- #define DPPIC_CHENSET_CH6_Disabled (0UL)
- #define DPPIC_CHENSET_CH6_Enabled (1UL)
- #define DPPIC_CHENSET_CH6_Set (1UL)
- #define DPPIC_CHENSET_CH5_Pos (5UL)
- #define DPPIC_CHENSET_CH5_Msk (0x1UL << DPPIC_CHENSET_CH5_Pos)
- #define DPPIC_CHENSET_CH5_Disabled (0UL)
- #define DPPIC_CHENSET_CH5_Enabled (1UL)
- #define DPPIC_CHENSET_CH5_Set (1UL)
- #define DPPIC_CHENSET_CH4_Pos (4UL)
- #define DPPIC_CHENSET_CH4_Msk (0x1UL << DPPIC_CHENSET_CH4_Pos)
- #define DPPIC_CHENSET_CH4_Disabled (0UL)
- #define DPPIC_CHENSET_CH4_Enabled (1UL)
- #define DPPIC_CHENSET_CH4_Set (1UL)
- #define DPPIC_CHENSET_CH3_Pos (3UL)
- #define DPPIC_CHENSET_CH3_Msk (0x1UL << DPPIC_CHENSET_CH3_Pos)
- #define DPPIC_CHENSET_CH3_Disabled (0UL)
- #define DPPIC_CHENSET_CH3_Enabled (1UL)
- #define DPPIC_CHENSET_CH3_Set (1UL)
- #define DPPIC_CHENSET_CH2_Pos (2UL)
- #define DPPIC_CHENSET_CH2_Msk (0x1UL << DPPIC_CHENSET_CH2_Pos)
- #define DPPIC_CHENSET_CH2_Disabled (0UL)
- #define DPPIC_CHENSET_CH2_Enabled (1UL)
- #define DPPIC_CHENSET_CH2_Set (1UL)
- #define DPPIC_CHENSET_CH1_Pos (1UL)
- #define DPPIC_CHENSET_CH1_Msk (0x1UL << DPPIC_CHENSET_CH1_Pos)
- #define DPPIC_CHENSET_CH1_Disabled (0UL)
- #define DPPIC_CHENSET_CH1_Enabled (1UL)
- #define DPPIC_CHENSET_CH1_Set (1UL)
- #define DPPIC_CHENSET_CH0_Pos (0UL)
- #define DPPIC_CHENSET_CH0_Msk (0x1UL << DPPIC_CHENSET_CH0_Pos)
- #define DPPIC_CHENSET_CH0_Disabled (0UL)
- #define DPPIC_CHENSET_CH0_Enabled (1UL)
- #define DPPIC_CHENSET_CH0_Set (1UL)
- #define DPPIC_CHENCLR_CH15_Pos (15UL)
- #define DPPIC_CHENCLR_CH15_Msk (0x1UL << DPPIC_CHENCLR_CH15_Pos)
- #define DPPIC_CHENCLR_CH15_Disabled (0UL)
- #define DPPIC_CHENCLR_CH15_Enabled (1UL)
- #define DPPIC_CHENCLR_CH15_Clear (1UL)
- #define DPPIC_CHENCLR_CH14_Pos (14UL)
- #define DPPIC_CHENCLR_CH14_Msk (0x1UL << DPPIC_CHENCLR_CH14_Pos)
- #define DPPIC_CHENCLR_CH14_Disabled (0UL)
- #define DPPIC_CHENCLR_CH14_Enabled (1UL)
- #define DPPIC_CHENCLR_CH14_Clear (1UL)
- #define DPPIC_CHENCLR_CH13_Pos (13UL)
- #define DPPIC_CHENCLR_CH13_Msk (0x1UL << DPPIC_CHENCLR_CH13_Pos)
- #define DPPIC_CHENCLR_CH13_Disabled (0UL)
- #define DPPIC_CHENCLR_CH13_Enabled (1UL)
- #define DPPIC_CHENCLR_CH13_Clear (1UL)
- #define DPPIC_CHENCLR_CH12_Pos (12UL)
- #define DPPIC_CHENCLR_CH12_Msk (0x1UL << DPPIC_CHENCLR_CH12_Pos)
- #define DPPIC_CHENCLR_CH12_Disabled (0UL)
- #define DPPIC_CHENCLR_CH12_Enabled (1UL)
- #define DPPIC_CHENCLR_CH12_Clear (1UL)
- #define DPPIC_CHENCLR_CH11_Pos (11UL)
- #define DPPIC_CHENCLR_CH11_Msk (0x1UL << DPPIC_CHENCLR_CH11_Pos)
- #define DPPIC_CHENCLR_CH11_Disabled (0UL)
- #define DPPIC_CHENCLR_CH11_Enabled (1UL)
- #define DPPIC_CHENCLR_CH11_Clear (1UL)
- #define DPPIC_CHENCLR_CH10_Pos (10UL)
- #define DPPIC_CHENCLR_CH10_Msk (0x1UL << DPPIC_CHENCLR_CH10_Pos)
- #define DPPIC_CHENCLR_CH10_Disabled (0UL)
- #define DPPIC_CHENCLR_CH10_Enabled (1UL)
- #define DPPIC_CHENCLR_CH10_Clear (1UL)
- #define DPPIC_CHENCLR_CH9_Pos (9UL)
- #define DPPIC_CHENCLR_CH9_Msk (0x1UL << DPPIC_CHENCLR_CH9_Pos)
- #define DPPIC_CHENCLR_CH9_Disabled (0UL)
- #define DPPIC_CHENCLR_CH9_Enabled (1UL)
- #define DPPIC_CHENCLR_CH9_Clear (1UL)
- #define DPPIC_CHENCLR_CH8_Pos (8UL)
- #define DPPIC_CHENCLR_CH8_Msk (0x1UL << DPPIC_CHENCLR_CH8_Pos)
- #define DPPIC_CHENCLR_CH8_Disabled (0UL)
- #define DPPIC_CHENCLR_CH8_Enabled (1UL)
- #define DPPIC_CHENCLR_CH8_Clear (1UL)
- #define DPPIC_CHENCLR_CH7_Pos (7UL)
- #define DPPIC_CHENCLR_CH7_Msk (0x1UL << DPPIC_CHENCLR_CH7_Pos)
- #define DPPIC_CHENCLR_CH7_Disabled (0UL)
- #define DPPIC_CHENCLR_CH7_Enabled (1UL)
- #define DPPIC_CHENCLR_CH7_Clear (1UL)
- #define DPPIC_CHENCLR_CH6_Pos (6UL)
- #define DPPIC_CHENCLR_CH6_Msk (0x1UL << DPPIC_CHENCLR_CH6_Pos)
- #define DPPIC_CHENCLR_CH6_Disabled (0UL)
- #define DPPIC_CHENCLR_CH6_Enabled (1UL)
- #define DPPIC_CHENCLR_CH6_Clear (1UL)
- #define DPPIC_CHENCLR_CH5_Pos (5UL)
- #define DPPIC_CHENCLR_CH5_Msk (0x1UL << DPPIC_CHENCLR_CH5_Pos)
- #define DPPIC_CHENCLR_CH5_Disabled (0UL)
- #define DPPIC_CHENCLR_CH5_Enabled (1UL)
- #define DPPIC_CHENCLR_CH5_Clear (1UL)
- #define DPPIC_CHENCLR_CH4_Pos (4UL)
- #define DPPIC_CHENCLR_CH4_Msk (0x1UL << DPPIC_CHENCLR_CH4_Pos)
- #define DPPIC_CHENCLR_CH4_Disabled (0UL)
- #define DPPIC_CHENCLR_CH4_Enabled (1UL)
- #define DPPIC_CHENCLR_CH4_Clear (1UL)
- #define DPPIC_CHENCLR_CH3_Pos (3UL)
- #define DPPIC_CHENCLR_CH3_Msk (0x1UL << DPPIC_CHENCLR_CH3_Pos)
- #define DPPIC_CHENCLR_CH3_Disabled (0UL)
- #define DPPIC_CHENCLR_CH3_Enabled (1UL)
- #define DPPIC_CHENCLR_CH3_Clear (1UL)
- #define DPPIC_CHENCLR_CH2_Pos (2UL)
- #define DPPIC_CHENCLR_CH2_Msk (0x1UL << DPPIC_CHENCLR_CH2_Pos)
- #define DPPIC_CHENCLR_CH2_Disabled (0UL)
- #define DPPIC_CHENCLR_CH2_Enabled (1UL)
- #define DPPIC_CHENCLR_CH2_Clear (1UL)
- #define DPPIC_CHENCLR_CH1_Pos (1UL)
- #define DPPIC_CHENCLR_CH1_Msk (0x1UL << DPPIC_CHENCLR_CH1_Pos)
- #define DPPIC_CHENCLR_CH1_Disabled (0UL)
- #define DPPIC_CHENCLR_CH1_Enabled (1UL)
- #define DPPIC_CHENCLR_CH1_Clear (1UL)
- #define DPPIC_CHENCLR_CH0_Pos (0UL)
- #define DPPIC_CHENCLR_CH0_Msk (0x1UL << DPPIC_CHENCLR_CH0_Pos)
- #define DPPIC_CHENCLR_CH0_Disabled (0UL)
- #define DPPIC_CHENCLR_CH0_Enabled (1UL)
- #define DPPIC_CHENCLR_CH0_Clear (1UL)
- #define DPPIC_CHG_CH15_Pos (15UL)
- #define DPPIC_CHG_CH15_Msk (0x1UL << DPPIC_CHG_CH15_Pos)
- #define DPPIC_CHG_CH15_Excluded (0UL)
- #define DPPIC_CHG_CH15_Included (1UL)
- #define DPPIC_CHG_CH14_Pos (14UL)
- #define DPPIC_CHG_CH14_Msk (0x1UL << DPPIC_CHG_CH14_Pos)
- #define DPPIC_CHG_CH14_Excluded (0UL)
- #define DPPIC_CHG_CH14_Included (1UL)
- #define DPPIC_CHG_CH13_Pos (13UL)
- #define DPPIC_CHG_CH13_Msk (0x1UL << DPPIC_CHG_CH13_Pos)
- #define DPPIC_CHG_CH13_Excluded (0UL)
- #define DPPIC_CHG_CH13_Included (1UL)
- #define DPPIC_CHG_CH12_Pos (12UL)
- #define DPPIC_CHG_CH12_Msk (0x1UL << DPPIC_CHG_CH12_Pos)
- #define DPPIC_CHG_CH12_Excluded (0UL)
- #define DPPIC_CHG_CH12_Included (1UL)
- #define DPPIC_CHG_CH11_Pos (11UL)
- #define DPPIC_CHG_CH11_Msk (0x1UL << DPPIC_CHG_CH11_Pos)
- #define DPPIC_CHG_CH11_Excluded (0UL)
- #define DPPIC_CHG_CH11_Included (1UL)
- #define DPPIC_CHG_CH10_Pos (10UL)
- #define DPPIC_CHG_CH10_Msk (0x1UL << DPPIC_CHG_CH10_Pos)
- #define DPPIC_CHG_CH10_Excluded (0UL)
- #define DPPIC_CHG_CH10_Included (1UL)
- #define DPPIC_CHG_CH9_Pos (9UL)
- #define DPPIC_CHG_CH9_Msk (0x1UL << DPPIC_CHG_CH9_Pos)
- #define DPPIC_CHG_CH9_Excluded (0UL)
- #define DPPIC_CHG_CH9_Included (1UL)
- #define DPPIC_CHG_CH8_Pos (8UL)
- #define DPPIC_CHG_CH8_Msk (0x1UL << DPPIC_CHG_CH8_Pos)
- #define DPPIC_CHG_CH8_Excluded (0UL)
- #define DPPIC_CHG_CH8_Included (1UL)
- #define DPPIC_CHG_CH7_Pos (7UL)
- #define DPPIC_CHG_CH7_Msk (0x1UL << DPPIC_CHG_CH7_Pos)
- #define DPPIC_CHG_CH7_Excluded (0UL)
- #define DPPIC_CHG_CH7_Included (1UL)
- #define DPPIC_CHG_CH6_Pos (6UL)
- #define DPPIC_CHG_CH6_Msk (0x1UL << DPPIC_CHG_CH6_Pos)
- #define DPPIC_CHG_CH6_Excluded (0UL)
- #define DPPIC_CHG_CH6_Included (1UL)
- #define DPPIC_CHG_CH5_Pos (5UL)
- #define DPPIC_CHG_CH5_Msk (0x1UL << DPPIC_CHG_CH5_Pos)
- #define DPPIC_CHG_CH5_Excluded (0UL)
- #define DPPIC_CHG_CH5_Included (1UL)
- #define DPPIC_CHG_CH4_Pos (4UL)
- #define DPPIC_CHG_CH4_Msk (0x1UL << DPPIC_CHG_CH4_Pos)
- #define DPPIC_CHG_CH4_Excluded (0UL)
- #define DPPIC_CHG_CH4_Included (1UL)
- #define DPPIC_CHG_CH3_Pos (3UL)
- #define DPPIC_CHG_CH3_Msk (0x1UL << DPPIC_CHG_CH3_Pos)
- #define DPPIC_CHG_CH3_Excluded (0UL)
- #define DPPIC_CHG_CH3_Included (1UL)
- #define DPPIC_CHG_CH2_Pos (2UL)
- #define DPPIC_CHG_CH2_Msk (0x1UL << DPPIC_CHG_CH2_Pos)
- #define DPPIC_CHG_CH2_Excluded (0UL)
- #define DPPIC_CHG_CH2_Included (1UL)
- #define DPPIC_CHG_CH1_Pos (1UL)
- #define DPPIC_CHG_CH1_Msk (0x1UL << DPPIC_CHG_CH1_Pos)
- #define DPPIC_CHG_CH1_Excluded (0UL)
- #define DPPIC_CHG_CH1_Included (1UL)
- #define DPPIC_CHG_CH0_Pos (0UL)
- #define DPPIC_CHG_CH0_Msk (0x1UL << DPPIC_CHG_CH0_Pos)
- #define DPPIC_CHG_CH0_Excluded (0UL)
- #define DPPIC_CHG_CH0_Included (1UL)
- #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL)
- #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos)
- #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL)
- #define EGU_SUBSCRIBE_TRIGGER_EN_Pos (31UL)
- #define EGU_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << EGU_SUBSCRIBE_TRIGGER_EN_Pos)
- #define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0UL)
- #define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (1UL)
- #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL)
- #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos)
- #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL)
- #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos)
- #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL)
- #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL)
- #define EGU_PUBLISH_TRIGGERED_EN_Pos (31UL)
- #define EGU_PUBLISH_TRIGGERED_EN_Msk (0x1UL << EGU_PUBLISH_TRIGGERED_EN_Pos)
- #define EGU_PUBLISH_TRIGGERED_EN_Disabled (0UL)
- #define EGU_PUBLISH_TRIGGERED_EN_Enabled (1UL)
- #define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL)
- #define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos)
- #define EGU_INTEN_TRIGGERED15_Pos (15UL)
- #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos)
- #define EGU_INTEN_TRIGGERED15_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED15_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED14_Pos (14UL)
- #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos)
- #define EGU_INTEN_TRIGGERED14_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED14_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED13_Pos (13UL)
- #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos)
- #define EGU_INTEN_TRIGGERED13_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED13_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED12_Pos (12UL)
- #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos)
- #define EGU_INTEN_TRIGGERED12_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED12_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED11_Pos (11UL)
- #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos)
- #define EGU_INTEN_TRIGGERED11_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED11_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED10_Pos (10UL)
- #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos)
- #define EGU_INTEN_TRIGGERED10_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED10_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED9_Pos (9UL)
- #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos)
- #define EGU_INTEN_TRIGGERED9_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED9_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED8_Pos (8UL)
- #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos)
- #define EGU_INTEN_TRIGGERED8_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED8_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED7_Pos (7UL)
- #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos)
- #define EGU_INTEN_TRIGGERED7_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED7_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED6_Pos (6UL)
- #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos)
- #define EGU_INTEN_TRIGGERED6_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED6_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED5_Pos (5UL)
- #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos)
- #define EGU_INTEN_TRIGGERED5_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED5_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED4_Pos (4UL)
- #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos)
- #define EGU_INTEN_TRIGGERED4_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED4_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED3_Pos (3UL)
- #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos)
- #define EGU_INTEN_TRIGGERED3_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED3_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED2_Pos (2UL)
- #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos)
- #define EGU_INTEN_TRIGGERED2_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED2_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED1_Pos (1UL)
- #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos)
- #define EGU_INTEN_TRIGGERED1_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED1_Enabled (1UL)
- #define EGU_INTEN_TRIGGERED0_Pos (0UL)
- #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos)
- #define EGU_INTEN_TRIGGERED0_Disabled (0UL)
- #define EGU_INTEN_TRIGGERED0_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED15_Pos (15UL)
- #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos)
- #define EGU_INTENSET_TRIGGERED15_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED15_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED15_Set (1UL)
- #define EGU_INTENSET_TRIGGERED14_Pos (14UL)
- #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos)
- #define EGU_INTENSET_TRIGGERED14_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED14_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED14_Set (1UL)
- #define EGU_INTENSET_TRIGGERED13_Pos (13UL)
- #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos)
- #define EGU_INTENSET_TRIGGERED13_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED13_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED13_Set (1UL)
- #define EGU_INTENSET_TRIGGERED12_Pos (12UL)
- #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos)
- #define EGU_INTENSET_TRIGGERED12_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED12_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED12_Set (1UL)
- #define EGU_INTENSET_TRIGGERED11_Pos (11UL)
- #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos)
- #define EGU_INTENSET_TRIGGERED11_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED11_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED11_Set (1UL)
- #define EGU_INTENSET_TRIGGERED10_Pos (10UL)
- #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos)
- #define EGU_INTENSET_TRIGGERED10_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED10_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED10_Set (1UL)
- #define EGU_INTENSET_TRIGGERED9_Pos (9UL)
- #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos)
- #define EGU_INTENSET_TRIGGERED9_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED9_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED9_Set (1UL)
- #define EGU_INTENSET_TRIGGERED8_Pos (8UL)
- #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos)
- #define EGU_INTENSET_TRIGGERED8_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED8_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED8_Set (1UL)
- #define EGU_INTENSET_TRIGGERED7_Pos (7UL)
- #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos)
- #define EGU_INTENSET_TRIGGERED7_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED7_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED7_Set (1UL)
- #define EGU_INTENSET_TRIGGERED6_Pos (6UL)
- #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos)
- #define EGU_INTENSET_TRIGGERED6_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED6_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED6_Set (1UL)
- #define EGU_INTENSET_TRIGGERED5_Pos (5UL)
- #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos)
- #define EGU_INTENSET_TRIGGERED5_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED5_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED5_Set (1UL)
- #define EGU_INTENSET_TRIGGERED4_Pos (4UL)
- #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos)
- #define EGU_INTENSET_TRIGGERED4_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED4_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED4_Set (1UL)
- #define EGU_INTENSET_TRIGGERED3_Pos (3UL)
- #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos)
- #define EGU_INTENSET_TRIGGERED3_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED3_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED3_Set (1UL)
- #define EGU_INTENSET_TRIGGERED2_Pos (2UL)
- #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos)
- #define EGU_INTENSET_TRIGGERED2_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED2_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED2_Set (1UL)
- #define EGU_INTENSET_TRIGGERED1_Pos (1UL)
- #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos)
- #define EGU_INTENSET_TRIGGERED1_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED1_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED1_Set (1UL)
- #define EGU_INTENSET_TRIGGERED0_Pos (0UL)
- #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos)
- #define EGU_INTENSET_TRIGGERED0_Disabled (0UL)
- #define EGU_INTENSET_TRIGGERED0_Enabled (1UL)
- #define EGU_INTENSET_TRIGGERED0_Set (1UL)
- #define EGU_INTENCLR_TRIGGERED15_Pos (15UL)
- #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos)
- #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED15_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED14_Pos (14UL)
- #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos)
- #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED14_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED13_Pos (13UL)
- #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos)
- #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED13_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED12_Pos (12UL)
- #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos)
- #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED12_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED11_Pos (11UL)
- #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos)
- #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED11_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED10_Pos (10UL)
- #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos)
- #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED10_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED9_Pos (9UL)
- #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos)
- #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED9_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED8_Pos (8UL)
- #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos)
- #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED8_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED7_Pos (7UL)
- #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos)
- #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED7_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED6_Pos (6UL)
- #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos)
- #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED6_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED5_Pos (5UL)
- #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos)
- #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED5_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED4_Pos (4UL)
- #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos)
- #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED4_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED3_Pos (3UL)
- #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos)
- #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED3_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED2_Pos (2UL)
- #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos)
- #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED2_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED1_Pos (1UL)
- #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos)
- #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED1_Clear (1UL)
- #define EGU_INTENCLR_TRIGGERED0_Pos (0UL)
- #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos)
- #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL)
- #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL)
- #define EGU_INTENCLR_TRIGGERED0_Clear (1UL)
- #define FICR_INFO_DEVICEID_DEVICEID_Pos (0UL)
- #define FICR_INFO_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICEID_DEVICEID_Pos)
- #define FICR_INFO_PART_PART_Pos (0UL)
- #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos)
- #define FICR_INFO_PART_PART_N9160 (0x9160UL)
- #define FICR_INFO_VARIANT_VARIANT_Pos (0UL)
- #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos)
- #define FICR_INFO_VARIANT_VARIANT_AAA0 (0x41414130UL)
- #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL)
- #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL)
- #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos)
- #define FICR_INFO_PACKAGE_PACKAGE_CC (0x2000UL)
- #define FICR_INFO_RAM_RAM_Pos (0UL)
- #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos)
- #define FICR_INFO_RAM_RAM_K256 (0x100UL)
- #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL)
- #define FICR_INFO_FLASH_FLASH_Pos (0UL)
- #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos)
- #define FICR_INFO_FLASH_FLASH_K1024 (0x400UL)
- #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL)
- #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos)
- #define FICR_INFO_CODESIZE_CODESIZE_Pos (0UL)
- #define FICR_INFO_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODESIZE_CODESIZE_Pos)
- #define FICR_INFO_DEVICETYPE_DEVICETYPE_Pos (0UL)
- #define FICR_INFO_DEVICETYPE_DEVICETYPE_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICETYPE_DEVICETYPE_Pos)
- #define FICR_INFO_DEVICETYPE_DEVICETYPE_Die (0x0000000UL)
- #define FICR_INFO_DEVICETYPE_DEVICETYPE_FPGA (0xFFFFFFFFUL)
- #define FICR_TRIMCNF_ADDR_Address_Pos (0UL)
- #define FICR_TRIMCNF_ADDR_Address_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_ADDR_Address_Pos)
- #define FICR_TRIMCNF_DATA_Data_Pos (0UL)
- #define FICR_TRIMCNF_DATA_Data_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_DATA_Data_Pos)
- #define FICR_TRNG90B_BYTES_BYTES_Pos (0UL)
- #define FICR_TRNG90B_BYTES_BYTES_Msk (0xFFFFFFFFUL << FICR_TRNG90B_BYTES_BYTES_Pos)
- #define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos (0UL)
- #define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos)
- #define FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos (0UL)
- #define FICR_TRNG90B_APCUTOFF_APCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos)
- #define FICR_TRNG90B_STARTUP_STARTUP_Pos (0UL)
- #define FICR_TRNG90B_STARTUP_STARTUP_Msk (0xFFFFFFFFUL << FICR_TRNG90B_STARTUP_STARTUP_Pos)
- #define FICR_TRNG90B_ROSC1_ROSC1_Pos (0UL)
- #define FICR_TRNG90B_ROSC1_ROSC1_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC1_ROSC1_Pos)
- #define FICR_TRNG90B_ROSC2_ROSC2_Pos (0UL)
- #define FICR_TRNG90B_ROSC2_ROSC2_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC2_ROSC2_Pos)
- #define FICR_TRNG90B_ROSC3_ROSC3_Pos (0UL)
- #define FICR_TRNG90B_ROSC3_ROSC3_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC3_ROSC3_Pos)
- #define FICR_TRNG90B_ROSC4_ROSC4_Pos (0UL)
- #define FICR_TRNG90B_ROSC4_ROSC4_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC4_ROSC4_Pos)
- #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL)
- #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos)
- #define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL)
- #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL)
- #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos)
- #define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL)
- #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL)
- #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos)
- #define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL)
- #define GPIOTE_SUBSCRIBE_OUT_EN_Pos (31UL)
- #define GPIOTE_SUBSCRIBE_OUT_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_OUT_EN_Pos)
- #define GPIOTE_SUBSCRIBE_OUT_EN_Disabled (0UL)
- #define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (1UL)
- #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos (0UL)
- #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Msk (0xFUL << GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos)
- #define GPIOTE_SUBSCRIBE_SET_EN_Pos (31UL)
- #define GPIOTE_SUBSCRIBE_SET_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_SET_EN_Pos)
- #define GPIOTE_SUBSCRIBE_SET_EN_Disabled (0UL)
- #define GPIOTE_SUBSCRIBE_SET_EN_Enabled (1UL)
- #define GPIOTE_SUBSCRIBE_SET_CHIDX_Pos (0UL)
- #define GPIOTE_SUBSCRIBE_SET_CHIDX_Msk (0xFUL << GPIOTE_SUBSCRIBE_SET_CHIDX_Pos)
- #define GPIOTE_SUBSCRIBE_CLR_EN_Pos (31UL)
- #define GPIOTE_SUBSCRIBE_CLR_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_CLR_EN_Pos)
- #define GPIOTE_SUBSCRIBE_CLR_EN_Disabled (0UL)
- #define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (1UL)
- #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos (0UL)
- #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Msk (0xFUL << GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos)
- #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL)
- #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos)
- #define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL)
- #define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL)
- #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL)
- #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos)
- #define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL)
- #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL)
- #define GPIOTE_PUBLISH_IN_EN_Pos (31UL)
- #define GPIOTE_PUBLISH_IN_EN_Msk (0x1UL << GPIOTE_PUBLISH_IN_EN_Pos)
- #define GPIOTE_PUBLISH_IN_EN_Disabled (0UL)
- #define GPIOTE_PUBLISH_IN_EN_Enabled (1UL)
- #define GPIOTE_PUBLISH_IN_CHIDX_Pos (0UL)
- #define GPIOTE_PUBLISH_IN_CHIDX_Msk (0xFUL << GPIOTE_PUBLISH_IN_CHIDX_Pos)
- #define GPIOTE_PUBLISH_PORT_EN_Pos (31UL)
- #define GPIOTE_PUBLISH_PORT_EN_Msk (0x1UL << GPIOTE_PUBLISH_PORT_EN_Pos)
- #define GPIOTE_PUBLISH_PORT_EN_Disabled (0UL)
- #define GPIOTE_PUBLISH_PORT_EN_Enabled (1UL)
- #define GPIOTE_PUBLISH_PORT_CHIDX_Pos (0UL)
- #define GPIOTE_PUBLISH_PORT_CHIDX_Msk (0xFUL << GPIOTE_PUBLISH_PORT_CHIDX_Pos)
- #define GPIOTE_INTENSET_PORT_Pos (31UL)
- #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos)
- #define GPIOTE_INTENSET_PORT_Disabled (0UL)
- #define GPIOTE_INTENSET_PORT_Enabled (1UL)
- #define GPIOTE_INTENSET_PORT_Set (1UL)
- #define GPIOTE_INTENSET_IN7_Pos (7UL)
- #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos)
- #define GPIOTE_INTENSET_IN7_Disabled (0UL)
- #define GPIOTE_INTENSET_IN7_Enabled (1UL)
- #define GPIOTE_INTENSET_IN7_Set (1UL)
- #define GPIOTE_INTENSET_IN6_Pos (6UL)
- #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos)
- #define GPIOTE_INTENSET_IN6_Disabled (0UL)
- #define GPIOTE_INTENSET_IN6_Enabled (1UL)
- #define GPIOTE_INTENSET_IN6_Set (1UL)
- #define GPIOTE_INTENSET_IN5_Pos (5UL)
- #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos)
- #define GPIOTE_INTENSET_IN5_Disabled (0UL)
- #define GPIOTE_INTENSET_IN5_Enabled (1UL)
- #define GPIOTE_INTENSET_IN5_Set (1UL)
- #define GPIOTE_INTENSET_IN4_Pos (4UL)
- #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos)
- #define GPIOTE_INTENSET_IN4_Disabled (0UL)
- #define GPIOTE_INTENSET_IN4_Enabled (1UL)
- #define GPIOTE_INTENSET_IN4_Set (1UL)
- #define GPIOTE_INTENSET_IN3_Pos (3UL)
- #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos)
- #define GPIOTE_INTENSET_IN3_Disabled (0UL)
- #define GPIOTE_INTENSET_IN3_Enabled (1UL)
- #define GPIOTE_INTENSET_IN3_Set (1UL)
- #define GPIOTE_INTENSET_IN2_Pos (2UL)
- #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos)
- #define GPIOTE_INTENSET_IN2_Disabled (0UL)
- #define GPIOTE_INTENSET_IN2_Enabled (1UL)
- #define GPIOTE_INTENSET_IN2_Set (1UL)
- #define GPIOTE_INTENSET_IN1_Pos (1UL)
- #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos)
- #define GPIOTE_INTENSET_IN1_Disabled (0UL)
- #define GPIOTE_INTENSET_IN1_Enabled (1UL)
- #define GPIOTE_INTENSET_IN1_Set (1UL)
- #define GPIOTE_INTENSET_IN0_Pos (0UL)
- #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos)
- #define GPIOTE_INTENSET_IN0_Disabled (0UL)
- #define GPIOTE_INTENSET_IN0_Enabled (1UL)
- #define GPIOTE_INTENSET_IN0_Set (1UL)
- #define GPIOTE_INTENCLR_PORT_Pos (31UL)
- #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos)
- #define GPIOTE_INTENCLR_PORT_Disabled (0UL)
- #define GPIOTE_INTENCLR_PORT_Enabled (1UL)
- #define GPIOTE_INTENCLR_PORT_Clear (1UL)
- #define GPIOTE_INTENCLR_IN7_Pos (7UL)
- #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos)
- #define GPIOTE_INTENCLR_IN7_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN7_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN7_Clear (1UL)
- #define GPIOTE_INTENCLR_IN6_Pos (6UL)
- #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos)
- #define GPIOTE_INTENCLR_IN6_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN6_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN6_Clear (1UL)
- #define GPIOTE_INTENCLR_IN5_Pos (5UL)
- #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos)
- #define GPIOTE_INTENCLR_IN5_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN5_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN5_Clear (1UL)
- #define GPIOTE_INTENCLR_IN4_Pos (4UL)
- #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos)
- #define GPIOTE_INTENCLR_IN4_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN4_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN4_Clear (1UL)
- #define GPIOTE_INTENCLR_IN3_Pos (3UL)
- #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos)
- #define GPIOTE_INTENCLR_IN3_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN3_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN3_Clear (1UL)
- #define GPIOTE_INTENCLR_IN2_Pos (2UL)
- #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos)
- #define GPIOTE_INTENCLR_IN2_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN2_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN2_Clear (1UL)
- #define GPIOTE_INTENCLR_IN1_Pos (1UL)
- #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos)
- #define GPIOTE_INTENCLR_IN1_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN1_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN1_Clear (1UL)
- #define GPIOTE_INTENCLR_IN0_Pos (0UL)
- #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos)
- #define GPIOTE_INTENCLR_IN0_Disabled (0UL)
- #define GPIOTE_INTENCLR_IN0_Enabled (1UL)
- #define GPIOTE_INTENCLR_IN0_Clear (1UL)
- #define GPIOTE_CONFIG_OUTINIT_Pos (20UL)
- #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos)
- #define GPIOTE_CONFIG_OUTINIT_Low (0UL)
- #define GPIOTE_CONFIG_OUTINIT_High (1UL)
- #define GPIOTE_CONFIG_POLARITY_Pos (16UL)
- #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos)
- #define GPIOTE_CONFIG_POLARITY_None (0UL)
- #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL)
- #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL)
- #define GPIOTE_CONFIG_POLARITY_Toggle (3UL)
- #define GPIOTE_CONFIG_PSEL_Pos (8UL)
- #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos)
- #define GPIOTE_CONFIG_MODE_Pos (0UL)
- #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos)
- #define GPIOTE_CONFIG_MODE_Disabled (0UL)
- #define GPIOTE_CONFIG_MODE_Event (1UL)
- #define GPIOTE_CONFIG_MODE_Task (3UL)
- #define I2S_TASKS_START_TASKS_START_Pos (0UL)
- #define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos)
- #define I2S_TASKS_START_TASKS_START_Trigger (1UL)
- #define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos)
- #define I2S_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define I2S_SUBSCRIBE_START_EN_Pos (31UL)
- #define I2S_SUBSCRIBE_START_EN_Msk (0x1UL << I2S_SUBSCRIBE_START_EN_Pos)
- #define I2S_SUBSCRIBE_START_EN_Disabled (0UL)
- #define I2S_SUBSCRIBE_START_EN_Enabled (1UL)
- #define I2S_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define I2S_SUBSCRIBE_START_CHIDX_Msk (0xFUL << I2S_SUBSCRIBE_START_CHIDX_Pos)
- #define I2S_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define I2S_SUBSCRIBE_STOP_EN_Msk (0x1UL << I2S_SUBSCRIBE_STOP_EN_Pos)
- #define I2S_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define I2S_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define I2S_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define I2S_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << I2S_SUBSCRIBE_STOP_CHIDX_Pos)
- #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL)
- #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos)
- #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0UL)
- #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (1UL)
- #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL)
- #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos)
- #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL)
- #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL)
- #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL)
- #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos)
- #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0UL)
- #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (1UL)
- #define I2S_PUBLISH_RXPTRUPD_EN_Pos (31UL)
- #define I2S_PUBLISH_RXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_RXPTRUPD_EN_Pos)
- #define I2S_PUBLISH_RXPTRUPD_EN_Disabled (0UL)
- #define I2S_PUBLISH_RXPTRUPD_EN_Enabled (1UL)
- #define I2S_PUBLISH_RXPTRUPD_CHIDX_Pos (0UL)
- #define I2S_PUBLISH_RXPTRUPD_CHIDX_Msk (0xFUL << I2S_PUBLISH_RXPTRUPD_CHIDX_Pos)
- #define I2S_PUBLISH_STOPPED_EN_Pos (31UL)
- #define I2S_PUBLISH_STOPPED_EN_Msk (0x1UL << I2S_PUBLISH_STOPPED_EN_Pos)
- #define I2S_PUBLISH_STOPPED_EN_Disabled (0UL)
- #define I2S_PUBLISH_STOPPED_EN_Enabled (1UL)
- #define I2S_PUBLISH_STOPPED_CHIDX_Pos (0UL)
- #define I2S_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << I2S_PUBLISH_STOPPED_CHIDX_Pos)
- #define I2S_PUBLISH_TXPTRUPD_EN_Pos (31UL)
- #define I2S_PUBLISH_TXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_TXPTRUPD_EN_Pos)
- #define I2S_PUBLISH_TXPTRUPD_EN_Disabled (0UL)
- #define I2S_PUBLISH_TXPTRUPD_EN_Enabled (1UL)
- #define I2S_PUBLISH_TXPTRUPD_CHIDX_Pos (0UL)
- #define I2S_PUBLISH_TXPTRUPD_CHIDX_Msk (0xFUL << I2S_PUBLISH_TXPTRUPD_CHIDX_Pos)
- #define I2S_INTEN_TXPTRUPD_Pos (5UL)
- #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos)
- #define I2S_INTEN_TXPTRUPD_Disabled (0UL)
- #define I2S_INTEN_TXPTRUPD_Enabled (1UL)
- #define I2S_INTEN_STOPPED_Pos (2UL)
- #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos)
- #define I2S_INTEN_STOPPED_Disabled (0UL)
- #define I2S_INTEN_STOPPED_Enabled (1UL)
- #define I2S_INTEN_RXPTRUPD_Pos (1UL)
- #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos)
- #define I2S_INTEN_RXPTRUPD_Disabled (0UL)
- #define I2S_INTEN_RXPTRUPD_Enabled (1UL)
- #define I2S_INTENSET_TXPTRUPD_Pos (5UL)
- #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos)
- #define I2S_INTENSET_TXPTRUPD_Disabled (0UL)
- #define I2S_INTENSET_TXPTRUPD_Enabled (1UL)
- #define I2S_INTENSET_TXPTRUPD_Set (1UL)
- #define I2S_INTENSET_STOPPED_Pos (2UL)
- #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos)
- #define I2S_INTENSET_STOPPED_Disabled (0UL)
- #define I2S_INTENSET_STOPPED_Enabled (1UL)
- #define I2S_INTENSET_STOPPED_Set (1UL)
- #define I2S_INTENSET_RXPTRUPD_Pos (1UL)
- #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos)
- #define I2S_INTENSET_RXPTRUPD_Disabled (0UL)
- #define I2S_INTENSET_RXPTRUPD_Enabled (1UL)
- #define I2S_INTENSET_RXPTRUPD_Set (1UL)
- #define I2S_INTENCLR_TXPTRUPD_Pos (5UL)
- #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos)
- #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL)
- #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL)
- #define I2S_INTENCLR_TXPTRUPD_Clear (1UL)
- #define I2S_INTENCLR_STOPPED_Pos (2UL)
- #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos)
- #define I2S_INTENCLR_STOPPED_Disabled (0UL)
- #define I2S_INTENCLR_STOPPED_Enabled (1UL)
- #define I2S_INTENCLR_STOPPED_Clear (1UL)
- #define I2S_INTENCLR_RXPTRUPD_Pos (1UL)
- #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos)
- #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL)
- #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL)
- #define I2S_INTENCLR_RXPTRUPD_Clear (1UL)
- #define I2S_ENABLE_ENABLE_Pos (0UL)
- #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos)
- #define I2S_ENABLE_ENABLE_Disabled (0UL)
- #define I2S_ENABLE_ENABLE_Enabled (1UL)
- #define I2S_CONFIG_MODE_MODE_Pos (0UL)
- #define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos)
- #define I2S_CONFIG_MODE_MODE_Master (0UL)
- #define I2S_CONFIG_MODE_MODE_Slave (1UL)
- #define I2S_CONFIG_RXEN_RXEN_Pos (0UL)
- #define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos)
- #define I2S_CONFIG_RXEN_RXEN_Disabled (0UL)
- #define I2S_CONFIG_RXEN_RXEN_Enabled (1UL)
- #define I2S_CONFIG_TXEN_TXEN_Pos (0UL)
- #define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos)
- #define I2S_CONFIG_TXEN_TXEN_Disabled (0UL)
- #define I2S_CONFIG_TXEN_TXEN_Enabled (1UL)
- #define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL)
- #define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos)
- #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL)
- #define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL)
- #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL)
- #define I2S_CONFIG_RATIO_RATIO_Pos (0UL)
- #define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos)
- #define I2S_CONFIG_RATIO_RATIO_32X (0UL)
- #define I2S_CONFIG_RATIO_RATIO_48X (1UL)
- #define I2S_CONFIG_RATIO_RATIO_64X (2UL)
- #define I2S_CONFIG_RATIO_RATIO_96X (3UL)
- #define I2S_CONFIG_RATIO_RATIO_128X (4UL)
- #define I2S_CONFIG_RATIO_RATIO_192X (5UL)
- #define I2S_CONFIG_RATIO_RATIO_256X (6UL)
- #define I2S_CONFIG_RATIO_RATIO_384X (7UL)
- #define I2S_CONFIG_RATIO_RATIO_512X (8UL)
- #define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL)
- #define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos)
- #define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL)
- #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL)
- #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL)
- #define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL)
- #define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos)
- #define I2S_CONFIG_ALIGN_ALIGN_Left (0UL)
- #define I2S_CONFIG_ALIGN_ALIGN_Right (1UL)
- #define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL)
- #define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos)
- #define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL)
- #define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL)
- #define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL)
- #define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos)
- #define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL)
- #define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL)
- #define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL)
- #define I2S_RXD_PTR_PTR_Pos (0UL)
- #define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos)
- #define I2S_TXD_PTR_PTR_Pos (0UL)
- #define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos)
- #define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL)
- #define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos)
- #define I2S_PSEL_MCK_CONNECT_Pos (31UL)
- #define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos)
- #define I2S_PSEL_MCK_CONNECT_Connected (0UL)
- #define I2S_PSEL_MCK_CONNECT_Disconnected (1UL)
- #define I2S_PSEL_MCK_PIN_Pos (0UL)
- #define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos)
- #define I2S_PSEL_SCK_CONNECT_Pos (31UL)
- #define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos)
- #define I2S_PSEL_SCK_CONNECT_Connected (0UL)
- #define I2S_PSEL_SCK_CONNECT_Disconnected (1UL)
- #define I2S_PSEL_SCK_PIN_Pos (0UL)
- #define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos)
- #define I2S_PSEL_LRCK_CONNECT_Pos (31UL)
- #define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos)
- #define I2S_PSEL_LRCK_CONNECT_Connected (0UL)
- #define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL)
- #define I2S_PSEL_LRCK_PIN_Pos (0UL)
- #define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos)
- #define I2S_PSEL_SDIN_CONNECT_Pos (31UL)
- #define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos)
- #define I2S_PSEL_SDIN_CONNECT_Connected (0UL)
- #define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL)
- #define I2S_PSEL_SDIN_PIN_Pos (0UL)
- #define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos)
- #define I2S_PSEL_SDOUT_CONNECT_Pos (31UL)
- #define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos)
- #define I2S_PSEL_SDOUT_CONNECT_Connected (0UL)
- #define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL)
- #define I2S_PSEL_SDOUT_PIN_Pos (0UL)
- #define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos)
- #define IPC_TASKS_SEND_TASKS_SEND_Pos (0UL)
- #define IPC_TASKS_SEND_TASKS_SEND_Msk (0x1UL << IPC_TASKS_SEND_TASKS_SEND_Pos)
- #define IPC_TASKS_SEND_TASKS_SEND_Trigger (1UL)
- #define IPC_SUBSCRIBE_SEND_EN_Pos (31UL)
- #define IPC_SUBSCRIBE_SEND_EN_Msk (0x1UL << IPC_SUBSCRIBE_SEND_EN_Pos)
- #define IPC_SUBSCRIBE_SEND_EN_Disabled (0UL)
- #define IPC_SUBSCRIBE_SEND_EN_Enabled (1UL)
- #define IPC_SUBSCRIBE_SEND_CHIDX_Pos (0UL)
- #define IPC_SUBSCRIBE_SEND_CHIDX_Msk (0xFUL << IPC_SUBSCRIBE_SEND_CHIDX_Pos)
- #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos (0UL)
- #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Msk (0x1UL << IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos)
- #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_NotGenerated (0UL)
- #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Generated (1UL)
- #define IPC_PUBLISH_RECEIVE_EN_Pos (31UL)
- #define IPC_PUBLISH_RECEIVE_EN_Msk (0x1UL << IPC_PUBLISH_RECEIVE_EN_Pos)
- #define IPC_PUBLISH_RECEIVE_EN_Disabled (0UL)
- #define IPC_PUBLISH_RECEIVE_EN_Enabled (1UL)
- #define IPC_PUBLISH_RECEIVE_CHIDX_Pos (0UL)
- #define IPC_PUBLISH_RECEIVE_CHIDX_Msk (0xFUL << IPC_PUBLISH_RECEIVE_CHIDX_Pos)
- #define IPC_INTEN_RECEIVE7_Pos (7UL)
- #define IPC_INTEN_RECEIVE7_Msk (0x1UL << IPC_INTEN_RECEIVE7_Pos)
- #define IPC_INTEN_RECEIVE7_Disabled (0UL)
- #define IPC_INTEN_RECEIVE7_Enabled (1UL)
- #define IPC_INTEN_RECEIVE6_Pos (6UL)
- #define IPC_INTEN_RECEIVE6_Msk (0x1UL << IPC_INTEN_RECEIVE6_Pos)
- #define IPC_INTEN_RECEIVE6_Disabled (0UL)
- #define IPC_INTEN_RECEIVE6_Enabled (1UL)
- #define IPC_INTEN_RECEIVE5_Pos (5UL)
- #define IPC_INTEN_RECEIVE5_Msk (0x1UL << IPC_INTEN_RECEIVE5_Pos)
- #define IPC_INTEN_RECEIVE5_Disabled (0UL)
- #define IPC_INTEN_RECEIVE5_Enabled (1UL)
- #define IPC_INTEN_RECEIVE4_Pos (4UL)
- #define IPC_INTEN_RECEIVE4_Msk (0x1UL << IPC_INTEN_RECEIVE4_Pos)
- #define IPC_INTEN_RECEIVE4_Disabled (0UL)
- #define IPC_INTEN_RECEIVE4_Enabled (1UL)
- #define IPC_INTEN_RECEIVE3_Pos (3UL)
- #define IPC_INTEN_RECEIVE3_Msk (0x1UL << IPC_INTEN_RECEIVE3_Pos)
- #define IPC_INTEN_RECEIVE3_Disabled (0UL)
- #define IPC_INTEN_RECEIVE3_Enabled (1UL)
- #define IPC_INTEN_RECEIVE2_Pos (2UL)
- #define IPC_INTEN_RECEIVE2_Msk (0x1UL << IPC_INTEN_RECEIVE2_Pos)
- #define IPC_INTEN_RECEIVE2_Disabled (0UL)
- #define IPC_INTEN_RECEIVE2_Enabled (1UL)
- #define IPC_INTEN_RECEIVE1_Pos (1UL)
- #define IPC_INTEN_RECEIVE1_Msk (0x1UL << IPC_INTEN_RECEIVE1_Pos)
- #define IPC_INTEN_RECEIVE1_Disabled (0UL)
- #define IPC_INTEN_RECEIVE1_Enabled (1UL)
- #define IPC_INTEN_RECEIVE0_Pos (0UL)
- #define IPC_INTEN_RECEIVE0_Msk (0x1UL << IPC_INTEN_RECEIVE0_Pos)
- #define IPC_INTEN_RECEIVE0_Disabled (0UL)
- #define IPC_INTEN_RECEIVE0_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE7_Pos (7UL)
- #define IPC_INTENSET_RECEIVE7_Msk (0x1UL << IPC_INTENSET_RECEIVE7_Pos)
- #define IPC_INTENSET_RECEIVE7_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE7_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE7_Set (1UL)
- #define IPC_INTENSET_RECEIVE6_Pos (6UL)
- #define IPC_INTENSET_RECEIVE6_Msk (0x1UL << IPC_INTENSET_RECEIVE6_Pos)
- #define IPC_INTENSET_RECEIVE6_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE6_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE6_Set (1UL)
- #define IPC_INTENSET_RECEIVE5_Pos (5UL)
- #define IPC_INTENSET_RECEIVE5_Msk (0x1UL << IPC_INTENSET_RECEIVE5_Pos)
- #define IPC_INTENSET_RECEIVE5_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE5_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE5_Set (1UL)
- #define IPC_INTENSET_RECEIVE4_Pos (4UL)
- #define IPC_INTENSET_RECEIVE4_Msk (0x1UL << IPC_INTENSET_RECEIVE4_Pos)
- #define IPC_INTENSET_RECEIVE4_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE4_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE4_Set (1UL)
- #define IPC_INTENSET_RECEIVE3_Pos (3UL)
- #define IPC_INTENSET_RECEIVE3_Msk (0x1UL << IPC_INTENSET_RECEIVE3_Pos)
- #define IPC_INTENSET_RECEIVE3_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE3_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE3_Set (1UL)
- #define IPC_INTENSET_RECEIVE2_Pos (2UL)
- #define IPC_INTENSET_RECEIVE2_Msk (0x1UL << IPC_INTENSET_RECEIVE2_Pos)
- #define IPC_INTENSET_RECEIVE2_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE2_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE2_Set (1UL)
- #define IPC_INTENSET_RECEIVE1_Pos (1UL)
- #define IPC_INTENSET_RECEIVE1_Msk (0x1UL << IPC_INTENSET_RECEIVE1_Pos)
- #define IPC_INTENSET_RECEIVE1_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE1_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE1_Set (1UL)
- #define IPC_INTENSET_RECEIVE0_Pos (0UL)
- #define IPC_INTENSET_RECEIVE0_Msk (0x1UL << IPC_INTENSET_RECEIVE0_Pos)
- #define IPC_INTENSET_RECEIVE0_Disabled (0UL)
- #define IPC_INTENSET_RECEIVE0_Enabled (1UL)
- #define IPC_INTENSET_RECEIVE0_Set (1UL)
- #define IPC_INTENCLR_RECEIVE7_Pos (7UL)
- #define IPC_INTENCLR_RECEIVE7_Msk (0x1UL << IPC_INTENCLR_RECEIVE7_Pos)
- #define IPC_INTENCLR_RECEIVE7_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE7_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE7_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE6_Pos (6UL)
- #define IPC_INTENCLR_RECEIVE6_Msk (0x1UL << IPC_INTENCLR_RECEIVE6_Pos)
- #define IPC_INTENCLR_RECEIVE6_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE6_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE6_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE5_Pos (5UL)
- #define IPC_INTENCLR_RECEIVE5_Msk (0x1UL << IPC_INTENCLR_RECEIVE5_Pos)
- #define IPC_INTENCLR_RECEIVE5_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE5_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE5_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE4_Pos (4UL)
- #define IPC_INTENCLR_RECEIVE4_Msk (0x1UL << IPC_INTENCLR_RECEIVE4_Pos)
- #define IPC_INTENCLR_RECEIVE4_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE4_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE4_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE3_Pos (3UL)
- #define IPC_INTENCLR_RECEIVE3_Msk (0x1UL << IPC_INTENCLR_RECEIVE3_Pos)
- #define IPC_INTENCLR_RECEIVE3_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE3_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE3_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE2_Pos (2UL)
- #define IPC_INTENCLR_RECEIVE2_Msk (0x1UL << IPC_INTENCLR_RECEIVE2_Pos)
- #define IPC_INTENCLR_RECEIVE2_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE2_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE2_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE1_Pos (1UL)
- #define IPC_INTENCLR_RECEIVE1_Msk (0x1UL << IPC_INTENCLR_RECEIVE1_Pos)
- #define IPC_INTENCLR_RECEIVE1_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE1_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE1_Clear (1UL)
- #define IPC_INTENCLR_RECEIVE0_Pos (0UL)
- #define IPC_INTENCLR_RECEIVE0_Msk (0x1UL << IPC_INTENCLR_RECEIVE0_Pos)
- #define IPC_INTENCLR_RECEIVE0_Disabled (0UL)
- #define IPC_INTENCLR_RECEIVE0_Enabled (1UL)
- #define IPC_INTENCLR_RECEIVE0_Clear (1UL)
- #define IPC_INTPEND_RECEIVE7_Pos (7UL)
- #define IPC_INTPEND_RECEIVE7_Msk (0x1UL << IPC_INTPEND_RECEIVE7_Pos)
- #define IPC_INTPEND_RECEIVE7_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE7_Pending (1UL)
- #define IPC_INTPEND_RECEIVE6_Pos (6UL)
- #define IPC_INTPEND_RECEIVE6_Msk (0x1UL << IPC_INTPEND_RECEIVE6_Pos)
- #define IPC_INTPEND_RECEIVE6_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE6_Pending (1UL)
- #define IPC_INTPEND_RECEIVE5_Pos (5UL)
- #define IPC_INTPEND_RECEIVE5_Msk (0x1UL << IPC_INTPEND_RECEIVE5_Pos)
- #define IPC_INTPEND_RECEIVE5_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE5_Pending (1UL)
- #define IPC_INTPEND_RECEIVE4_Pos (4UL)
- #define IPC_INTPEND_RECEIVE4_Msk (0x1UL << IPC_INTPEND_RECEIVE4_Pos)
- #define IPC_INTPEND_RECEIVE4_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE4_Pending (1UL)
- #define IPC_INTPEND_RECEIVE3_Pos (3UL)
- #define IPC_INTPEND_RECEIVE3_Msk (0x1UL << IPC_INTPEND_RECEIVE3_Pos)
- #define IPC_INTPEND_RECEIVE3_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE3_Pending (1UL)
- #define IPC_INTPEND_RECEIVE2_Pos (2UL)
- #define IPC_INTPEND_RECEIVE2_Msk (0x1UL << IPC_INTPEND_RECEIVE2_Pos)
- #define IPC_INTPEND_RECEIVE2_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE2_Pending (1UL)
- #define IPC_INTPEND_RECEIVE1_Pos (1UL)
- #define IPC_INTPEND_RECEIVE1_Msk (0x1UL << IPC_INTPEND_RECEIVE1_Pos)
- #define IPC_INTPEND_RECEIVE1_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE1_Pending (1UL)
- #define IPC_INTPEND_RECEIVE0_Pos (0UL)
- #define IPC_INTPEND_RECEIVE0_Msk (0x1UL << IPC_INTPEND_RECEIVE0_Pos)
- #define IPC_INTPEND_RECEIVE0_NotPending (0UL)
- #define IPC_INTPEND_RECEIVE0_Pending (1UL)
- #define IPC_SEND_CNF_CHEN7_Pos (7UL)
- #define IPC_SEND_CNF_CHEN7_Msk (0x1UL << IPC_SEND_CNF_CHEN7_Pos)
- #define IPC_SEND_CNF_CHEN7_Disable (0UL)
- #define IPC_SEND_CNF_CHEN7_Enable (1UL)
- #define IPC_SEND_CNF_CHEN6_Pos (6UL)
- #define IPC_SEND_CNF_CHEN6_Msk (0x1UL << IPC_SEND_CNF_CHEN6_Pos)
- #define IPC_SEND_CNF_CHEN6_Disable (0UL)
- #define IPC_SEND_CNF_CHEN6_Enable (1UL)
- #define IPC_SEND_CNF_CHEN5_Pos (5UL)
- #define IPC_SEND_CNF_CHEN5_Msk (0x1UL << IPC_SEND_CNF_CHEN5_Pos)
- #define IPC_SEND_CNF_CHEN5_Disable (0UL)
- #define IPC_SEND_CNF_CHEN5_Enable (1UL)
- #define IPC_SEND_CNF_CHEN4_Pos (4UL)
- #define IPC_SEND_CNF_CHEN4_Msk (0x1UL << IPC_SEND_CNF_CHEN4_Pos)
- #define IPC_SEND_CNF_CHEN4_Disable (0UL)
- #define IPC_SEND_CNF_CHEN4_Enable (1UL)
- #define IPC_SEND_CNF_CHEN3_Pos (3UL)
- #define IPC_SEND_CNF_CHEN3_Msk (0x1UL << IPC_SEND_CNF_CHEN3_Pos)
- #define IPC_SEND_CNF_CHEN3_Disable (0UL)
- #define IPC_SEND_CNF_CHEN3_Enable (1UL)
- #define IPC_SEND_CNF_CHEN2_Pos (2UL)
- #define IPC_SEND_CNF_CHEN2_Msk (0x1UL << IPC_SEND_CNF_CHEN2_Pos)
- #define IPC_SEND_CNF_CHEN2_Disable (0UL)
- #define IPC_SEND_CNF_CHEN2_Enable (1UL)
- #define IPC_SEND_CNF_CHEN1_Pos (1UL)
- #define IPC_SEND_CNF_CHEN1_Msk (0x1UL << IPC_SEND_CNF_CHEN1_Pos)
- #define IPC_SEND_CNF_CHEN1_Disable (0UL)
- #define IPC_SEND_CNF_CHEN1_Enable (1UL)
- #define IPC_SEND_CNF_CHEN0_Pos (0UL)
- #define IPC_SEND_CNF_CHEN0_Msk (0x1UL << IPC_SEND_CNF_CHEN0_Pos)
- #define IPC_SEND_CNF_CHEN0_Disable (0UL)
- #define IPC_SEND_CNF_CHEN0_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN7_Pos (7UL)
- #define IPC_RECEIVE_CNF_CHEN7_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN7_Pos)
- #define IPC_RECEIVE_CNF_CHEN7_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN7_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN6_Pos (6UL)
- #define IPC_RECEIVE_CNF_CHEN6_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN6_Pos)
- #define IPC_RECEIVE_CNF_CHEN6_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN6_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN5_Pos (5UL)
- #define IPC_RECEIVE_CNF_CHEN5_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN5_Pos)
- #define IPC_RECEIVE_CNF_CHEN5_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN5_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN4_Pos (4UL)
- #define IPC_RECEIVE_CNF_CHEN4_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN4_Pos)
- #define IPC_RECEIVE_CNF_CHEN4_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN4_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN3_Pos (3UL)
- #define IPC_RECEIVE_CNF_CHEN3_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN3_Pos)
- #define IPC_RECEIVE_CNF_CHEN3_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN3_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN2_Pos (2UL)
- #define IPC_RECEIVE_CNF_CHEN2_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN2_Pos)
- #define IPC_RECEIVE_CNF_CHEN2_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN2_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN1_Pos (1UL)
- #define IPC_RECEIVE_CNF_CHEN1_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN1_Pos)
- #define IPC_RECEIVE_CNF_CHEN1_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN1_Enable (1UL)
- #define IPC_RECEIVE_CNF_CHEN0_Pos (0UL)
- #define IPC_RECEIVE_CNF_CHEN0_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN0_Pos)
- #define IPC_RECEIVE_CNF_CHEN0_Disable (0UL)
- #define IPC_RECEIVE_CNF_CHEN0_Enable (1UL)
- #define IPC_GPMEM_GPMEM_Pos (0UL)
- #define IPC_GPMEM_GPMEM_Msk (0xFFFFFFFFUL << IPC_GPMEM_GPMEM_Pos)
- #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos (0UL)
- #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Msk (0x1UL << KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos)
- #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Trigger (1UL)
- #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos (0UL)
- #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos)
- #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_NotGenerated (0UL)
- #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Generated (1UL)
- #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos (0UL)
- #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos)
- #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_NotGenerated (0UL)
- #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Generated (1UL)
- #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos (0UL)
- #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Msk (0x1UL << KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos)
- #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_NotGenerated (0UL)
- #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Generated (1UL)
- #define KMU_INTEN_KEYSLOT_ERROR_Pos (2UL)
- #define KMU_INTEN_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTEN_KEYSLOT_ERROR_Pos)
- #define KMU_INTEN_KEYSLOT_ERROR_Disabled (0UL)
- #define KMU_INTEN_KEYSLOT_ERROR_Enabled (1UL)
- #define KMU_INTEN_KEYSLOT_REVOKED_Pos (1UL)
- #define KMU_INTEN_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTEN_KEYSLOT_REVOKED_Pos)
- #define KMU_INTEN_KEYSLOT_REVOKED_Disabled (0UL)
- #define KMU_INTEN_KEYSLOT_REVOKED_Enabled (1UL)
- #define KMU_INTEN_KEYSLOT_PUSHED_Pos (0UL)
- #define KMU_INTEN_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTEN_KEYSLOT_PUSHED_Pos)
- #define KMU_INTEN_KEYSLOT_PUSHED_Disabled (0UL)
- #define KMU_INTEN_KEYSLOT_PUSHED_Enabled (1UL)
- #define KMU_INTENSET_KEYSLOT_ERROR_Pos (2UL)
- #define KMU_INTENSET_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENSET_KEYSLOT_ERROR_Pos)
- #define KMU_INTENSET_KEYSLOT_ERROR_Disabled (0UL)
- #define KMU_INTENSET_KEYSLOT_ERROR_Enabled (1UL)
- #define KMU_INTENSET_KEYSLOT_ERROR_Set (1UL)
- #define KMU_INTENSET_KEYSLOT_REVOKED_Pos (1UL)
- #define KMU_INTENSET_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_REVOKED_Pos)
- #define KMU_INTENSET_KEYSLOT_REVOKED_Disabled (0UL)
- #define KMU_INTENSET_KEYSLOT_REVOKED_Enabled (1UL)
- #define KMU_INTENSET_KEYSLOT_REVOKED_Set (1UL)
- #define KMU_INTENSET_KEYSLOT_PUSHED_Pos (0UL)
- #define KMU_INTENSET_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_PUSHED_Pos)
- #define KMU_INTENSET_KEYSLOT_PUSHED_Disabled (0UL)
- #define KMU_INTENSET_KEYSLOT_PUSHED_Enabled (1UL)
- #define KMU_INTENSET_KEYSLOT_PUSHED_Set (1UL)
- #define KMU_INTENCLR_KEYSLOT_ERROR_Pos (2UL)
- #define KMU_INTENCLR_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_ERROR_Pos)
- #define KMU_INTENCLR_KEYSLOT_ERROR_Disabled (0UL)
- #define KMU_INTENCLR_KEYSLOT_ERROR_Enabled (1UL)
- #define KMU_INTENCLR_KEYSLOT_ERROR_Clear (1UL)
- #define KMU_INTENCLR_KEYSLOT_REVOKED_Pos (1UL)
- #define KMU_INTENCLR_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_REVOKED_Pos)
- #define KMU_INTENCLR_KEYSLOT_REVOKED_Disabled (0UL)
- #define KMU_INTENCLR_KEYSLOT_REVOKED_Enabled (1UL)
- #define KMU_INTENCLR_KEYSLOT_REVOKED_Clear (1UL)
- #define KMU_INTENCLR_KEYSLOT_PUSHED_Pos (0UL)
- #define KMU_INTENCLR_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_PUSHED_Pos)
- #define KMU_INTENCLR_KEYSLOT_PUSHED_Disabled (0UL)
- #define KMU_INTENCLR_KEYSLOT_PUSHED_Enabled (1UL)
- #define KMU_INTENCLR_KEYSLOT_PUSHED_Clear (1UL)
- #define KMU_INTPEND_KEYSLOT_ERROR_Pos (2UL)
- #define KMU_INTPEND_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTPEND_KEYSLOT_ERROR_Pos)
- #define KMU_INTPEND_KEYSLOT_ERROR_NotPending (0UL)
- #define KMU_INTPEND_KEYSLOT_ERROR_Pending (1UL)
- #define KMU_INTPEND_KEYSLOT_REVOKED_Pos (1UL)
- #define KMU_INTPEND_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_REVOKED_Pos)
- #define KMU_INTPEND_KEYSLOT_REVOKED_NotPending (0UL)
- #define KMU_INTPEND_KEYSLOT_REVOKED_Pending (1UL)
- #define KMU_INTPEND_KEYSLOT_PUSHED_Pos (0UL)
- #define KMU_INTPEND_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_PUSHED_Pos)
- #define KMU_INTPEND_KEYSLOT_PUSHED_NotPending (0UL)
- #define KMU_INTPEND_KEYSLOT_PUSHED_Pending (1UL)
- #define KMU_STATUS_BLOCKED_Pos (1UL)
- #define KMU_STATUS_BLOCKED_Msk (0x1UL << KMU_STATUS_BLOCKED_Pos)
- #define KMU_STATUS_BLOCKED_Disabled (0UL)
- #define KMU_STATUS_BLOCKED_Enabled (1UL)
- #define KMU_STATUS_SELECTED_Pos (0UL)
- #define KMU_STATUS_SELECTED_Msk (0x1UL << KMU_STATUS_SELECTED_Pos)
- #define KMU_STATUS_SELECTED_Disabled (0UL)
- #define KMU_STATUS_SELECTED_Enabled (1UL)
- #define KMU_SELECTKEYSLOT_ID_Pos (0UL)
- #define KMU_SELECTKEYSLOT_ID_Msk (0xFFUL << KMU_SELECTKEYSLOT_ID_Pos)
- #define NVMC_READY_READY_Pos (0UL)
- #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos)
- #define NVMC_READY_READY_Busy (0UL)
- #define NVMC_READY_READY_Ready (1UL)
- #define NVMC_READYNEXT_READYNEXT_Pos (0UL)
- #define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos)
- #define NVMC_READYNEXT_READYNEXT_Busy (0UL)
- #define NVMC_READYNEXT_READYNEXT_Ready (1UL)
- #define NVMC_CONFIG_WEN_Pos (0UL)
- #define NVMC_CONFIG_WEN_Msk (0x7UL << NVMC_CONFIG_WEN_Pos)
- #define NVMC_CONFIG_WEN_Ren (0UL)
- #define NVMC_CONFIG_WEN_Wen (1UL)
- #define NVMC_CONFIG_WEN_Een (2UL)
- #define NVMC_CONFIG_WEN_PEen (4UL)
- #define NVMC_ERASEALL_ERASEALL_Pos (0UL)
- #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos)
- #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL)
- #define NVMC_ERASEALL_ERASEALL_Erase (1UL)
- #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL)
- #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos)
- #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL)
- #define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos)
- #define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL)
- #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL)
- #define NVMC_ICACHECNF_CACHEEN_Pos (0UL)
- #define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos)
- #define NVMC_ICACHECNF_CACHEEN_Disabled (0UL)
- #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL)
- #define NVMC_IHIT_HITS_Pos (0UL)
- #define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos)
- #define NVMC_IMISS_MISSES_Pos (0UL)
- #define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos)
- #define NVMC_CONFIGNS_WEN_Pos (0UL)
- #define NVMC_CONFIGNS_WEN_Msk (0x3UL << NVMC_CONFIGNS_WEN_Pos)
- #define NVMC_CONFIGNS_WEN_Ren (0UL)
- #define NVMC_CONFIGNS_WEN_Wen (1UL)
- #define NVMC_CONFIGNS_WEN_Een (2UL)
- #define NVMC_WRITEUICRNS_KEY_Pos (4UL)
- #define NVMC_WRITEUICRNS_KEY_Msk (0xFFFFFFFUL << NVMC_WRITEUICRNS_KEY_Pos)
- #define NVMC_WRITEUICRNS_KEY_Keyvalid (0xAFBE5A7UL)
- #define NVMC_WRITEUICRNS_SET_Pos (0UL)
- #define NVMC_WRITEUICRNS_SET_Msk (0x1UL << NVMC_WRITEUICRNS_SET_Pos)
- #define NVMC_WRITEUICRNS_SET_Set (1UL)
- #define GPIO_OUT_PIN31_Pos (31UL)
- #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos)
- #define GPIO_OUT_PIN31_Low (0UL)
- #define GPIO_OUT_PIN31_High (1UL)
- #define GPIO_OUT_PIN30_Pos (30UL)
- #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos)
- #define GPIO_OUT_PIN30_Low (0UL)
- #define GPIO_OUT_PIN30_High (1UL)
- #define GPIO_OUT_PIN29_Pos (29UL)
- #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos)
- #define GPIO_OUT_PIN29_Low (0UL)
- #define GPIO_OUT_PIN29_High (1UL)
- #define GPIO_OUT_PIN28_Pos (28UL)
- #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos)
- #define GPIO_OUT_PIN28_Low (0UL)
- #define GPIO_OUT_PIN28_High (1UL)
- #define GPIO_OUT_PIN27_Pos (27UL)
- #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos)
- #define GPIO_OUT_PIN27_Low (0UL)
- #define GPIO_OUT_PIN27_High (1UL)
- #define GPIO_OUT_PIN26_Pos (26UL)
- #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos)
- #define GPIO_OUT_PIN26_Low (0UL)
- #define GPIO_OUT_PIN26_High (1UL)
- #define GPIO_OUT_PIN25_Pos (25UL)
- #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos)
- #define GPIO_OUT_PIN25_Low (0UL)
- #define GPIO_OUT_PIN25_High (1UL)
- #define GPIO_OUT_PIN24_Pos (24UL)
- #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos)
- #define GPIO_OUT_PIN24_Low (0UL)
- #define GPIO_OUT_PIN24_High (1UL)
- #define GPIO_OUT_PIN23_Pos (23UL)
- #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos)
- #define GPIO_OUT_PIN23_Low (0UL)
- #define GPIO_OUT_PIN23_High (1UL)
- #define GPIO_OUT_PIN22_Pos (22UL)
- #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos)
- #define GPIO_OUT_PIN22_Low (0UL)
- #define GPIO_OUT_PIN22_High (1UL)
- #define GPIO_OUT_PIN21_Pos (21UL)
- #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos)
- #define GPIO_OUT_PIN21_Low (0UL)
- #define GPIO_OUT_PIN21_High (1UL)
- #define GPIO_OUT_PIN20_Pos (20UL)
- #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos)
- #define GPIO_OUT_PIN20_Low (0UL)
- #define GPIO_OUT_PIN20_High (1UL)
- #define GPIO_OUT_PIN19_Pos (19UL)
- #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos)
- #define GPIO_OUT_PIN19_Low (0UL)
- #define GPIO_OUT_PIN19_High (1UL)
- #define GPIO_OUT_PIN18_Pos (18UL)
- #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos)
- #define GPIO_OUT_PIN18_Low (0UL)
- #define GPIO_OUT_PIN18_High (1UL)
- #define GPIO_OUT_PIN17_Pos (17UL)
- #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos)
- #define GPIO_OUT_PIN17_Low (0UL)
- #define GPIO_OUT_PIN17_High (1UL)
- #define GPIO_OUT_PIN16_Pos (16UL)
- #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos)
- #define GPIO_OUT_PIN16_Low (0UL)
- #define GPIO_OUT_PIN16_High (1UL)
- #define GPIO_OUT_PIN15_Pos (15UL)
- #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos)
- #define GPIO_OUT_PIN15_Low (0UL)
- #define GPIO_OUT_PIN15_High (1UL)
- #define GPIO_OUT_PIN14_Pos (14UL)
- #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos)
- #define GPIO_OUT_PIN14_Low (0UL)
- #define GPIO_OUT_PIN14_High (1UL)
- #define GPIO_OUT_PIN13_Pos (13UL)
- #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos)
- #define GPIO_OUT_PIN13_Low (0UL)
- #define GPIO_OUT_PIN13_High (1UL)
- #define GPIO_OUT_PIN12_Pos (12UL)
- #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos)
- #define GPIO_OUT_PIN12_Low (0UL)
- #define GPIO_OUT_PIN12_High (1UL)
- #define GPIO_OUT_PIN11_Pos (11UL)
- #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos)
- #define GPIO_OUT_PIN11_Low (0UL)
- #define GPIO_OUT_PIN11_High (1UL)
- #define GPIO_OUT_PIN10_Pos (10UL)
- #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos)
- #define GPIO_OUT_PIN10_Low (0UL)
- #define GPIO_OUT_PIN10_High (1UL)
- #define GPIO_OUT_PIN9_Pos (9UL)
- #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos)
- #define GPIO_OUT_PIN9_Low (0UL)
- #define GPIO_OUT_PIN9_High (1UL)
- #define GPIO_OUT_PIN8_Pos (8UL)
- #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos)
- #define GPIO_OUT_PIN8_Low (0UL)
- #define GPIO_OUT_PIN8_High (1UL)
- #define GPIO_OUT_PIN7_Pos (7UL)
- #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos)
- #define GPIO_OUT_PIN7_Low (0UL)
- #define GPIO_OUT_PIN7_High (1UL)
- #define GPIO_OUT_PIN6_Pos (6UL)
- #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos)
- #define GPIO_OUT_PIN6_Low (0UL)
- #define GPIO_OUT_PIN6_High (1UL)
- #define GPIO_OUT_PIN5_Pos (5UL)
- #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos)
- #define GPIO_OUT_PIN5_Low (0UL)
- #define GPIO_OUT_PIN5_High (1UL)
- #define GPIO_OUT_PIN4_Pos (4UL)
- #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos)
- #define GPIO_OUT_PIN4_Low (0UL)
- #define GPIO_OUT_PIN4_High (1UL)
- #define GPIO_OUT_PIN3_Pos (3UL)
- #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos)
- #define GPIO_OUT_PIN3_Low (0UL)
- #define GPIO_OUT_PIN3_High (1UL)
- #define GPIO_OUT_PIN2_Pos (2UL)
- #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos)
- #define GPIO_OUT_PIN2_Low (0UL)
- #define GPIO_OUT_PIN2_High (1UL)
- #define GPIO_OUT_PIN1_Pos (1UL)
- #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos)
- #define GPIO_OUT_PIN1_Low (0UL)
- #define GPIO_OUT_PIN1_High (1UL)
- #define GPIO_OUT_PIN0_Pos (0UL)
- #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos)
- #define GPIO_OUT_PIN0_Low (0UL)
- #define GPIO_OUT_PIN0_High (1UL)
- #define GPIO_OUTSET_PIN31_Pos (31UL)
- #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos)
- #define GPIO_OUTSET_PIN31_Low (0UL)
- #define GPIO_OUTSET_PIN31_High (1UL)
- #define GPIO_OUTSET_PIN31_Set (1UL)
- #define GPIO_OUTSET_PIN30_Pos (30UL)
- #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos)
- #define GPIO_OUTSET_PIN30_Low (0UL)
- #define GPIO_OUTSET_PIN30_High (1UL)
- #define GPIO_OUTSET_PIN30_Set (1UL)
- #define GPIO_OUTSET_PIN29_Pos (29UL)
- #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos)
- #define GPIO_OUTSET_PIN29_Low (0UL)
- #define GPIO_OUTSET_PIN29_High (1UL)
- #define GPIO_OUTSET_PIN29_Set (1UL)
- #define GPIO_OUTSET_PIN28_Pos (28UL)
- #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos)
- #define GPIO_OUTSET_PIN28_Low (0UL)
- #define GPIO_OUTSET_PIN28_High (1UL)
- #define GPIO_OUTSET_PIN28_Set (1UL)
- #define GPIO_OUTSET_PIN27_Pos (27UL)
- #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos)
- #define GPIO_OUTSET_PIN27_Low (0UL)
- #define GPIO_OUTSET_PIN27_High (1UL)
- #define GPIO_OUTSET_PIN27_Set (1UL)
- #define GPIO_OUTSET_PIN26_Pos (26UL)
- #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos)
- #define GPIO_OUTSET_PIN26_Low (0UL)
- #define GPIO_OUTSET_PIN26_High (1UL)
- #define GPIO_OUTSET_PIN26_Set (1UL)
- #define GPIO_OUTSET_PIN25_Pos (25UL)
- #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos)
- #define GPIO_OUTSET_PIN25_Low (0UL)
- #define GPIO_OUTSET_PIN25_High (1UL)
- #define GPIO_OUTSET_PIN25_Set (1UL)
- #define GPIO_OUTSET_PIN24_Pos (24UL)
- #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos)
- #define GPIO_OUTSET_PIN24_Low (0UL)
- #define GPIO_OUTSET_PIN24_High (1UL)
- #define GPIO_OUTSET_PIN24_Set (1UL)
- #define GPIO_OUTSET_PIN23_Pos (23UL)
- #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos)
- #define GPIO_OUTSET_PIN23_Low (0UL)
- #define GPIO_OUTSET_PIN23_High (1UL)
- #define GPIO_OUTSET_PIN23_Set (1UL)
- #define GPIO_OUTSET_PIN22_Pos (22UL)
- #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos)
- #define GPIO_OUTSET_PIN22_Low (0UL)
- #define GPIO_OUTSET_PIN22_High (1UL)
- #define GPIO_OUTSET_PIN22_Set (1UL)
- #define GPIO_OUTSET_PIN21_Pos (21UL)
- #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos)
- #define GPIO_OUTSET_PIN21_Low (0UL)
- #define GPIO_OUTSET_PIN21_High (1UL)
- #define GPIO_OUTSET_PIN21_Set (1UL)
- #define GPIO_OUTSET_PIN20_Pos (20UL)
- #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos)
- #define GPIO_OUTSET_PIN20_Low (0UL)
- #define GPIO_OUTSET_PIN20_High (1UL)
- #define GPIO_OUTSET_PIN20_Set (1UL)
- #define GPIO_OUTSET_PIN19_Pos (19UL)
- #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos)
- #define GPIO_OUTSET_PIN19_Low (0UL)
- #define GPIO_OUTSET_PIN19_High (1UL)
- #define GPIO_OUTSET_PIN19_Set (1UL)
- #define GPIO_OUTSET_PIN18_Pos (18UL)
- #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos)
- #define GPIO_OUTSET_PIN18_Low (0UL)
- #define GPIO_OUTSET_PIN18_High (1UL)
- #define GPIO_OUTSET_PIN18_Set (1UL)
- #define GPIO_OUTSET_PIN17_Pos (17UL)
- #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos)
- #define GPIO_OUTSET_PIN17_Low (0UL)
- #define GPIO_OUTSET_PIN17_High (1UL)
- #define GPIO_OUTSET_PIN17_Set (1UL)
- #define GPIO_OUTSET_PIN16_Pos (16UL)
- #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos)
- #define GPIO_OUTSET_PIN16_Low (0UL)
- #define GPIO_OUTSET_PIN16_High (1UL)
- #define GPIO_OUTSET_PIN16_Set (1UL)
- #define GPIO_OUTSET_PIN15_Pos (15UL)
- #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos)
- #define GPIO_OUTSET_PIN15_Low (0UL)
- #define GPIO_OUTSET_PIN15_High (1UL)
- #define GPIO_OUTSET_PIN15_Set (1UL)
- #define GPIO_OUTSET_PIN14_Pos (14UL)
- #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos)
- #define GPIO_OUTSET_PIN14_Low (0UL)
- #define GPIO_OUTSET_PIN14_High (1UL)
- #define GPIO_OUTSET_PIN14_Set (1UL)
- #define GPIO_OUTSET_PIN13_Pos (13UL)
- #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos)
- #define GPIO_OUTSET_PIN13_Low (0UL)
- #define GPIO_OUTSET_PIN13_High (1UL)
- #define GPIO_OUTSET_PIN13_Set (1UL)
- #define GPIO_OUTSET_PIN12_Pos (12UL)
- #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos)
- #define GPIO_OUTSET_PIN12_Low (0UL)
- #define GPIO_OUTSET_PIN12_High (1UL)
- #define GPIO_OUTSET_PIN12_Set (1UL)
- #define GPIO_OUTSET_PIN11_Pos (11UL)
- #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos)
- #define GPIO_OUTSET_PIN11_Low (0UL)
- #define GPIO_OUTSET_PIN11_High (1UL)
- #define GPIO_OUTSET_PIN11_Set (1UL)
- #define GPIO_OUTSET_PIN10_Pos (10UL)
- #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos)
- #define GPIO_OUTSET_PIN10_Low (0UL)
- #define GPIO_OUTSET_PIN10_High (1UL)
- #define GPIO_OUTSET_PIN10_Set (1UL)
- #define GPIO_OUTSET_PIN9_Pos (9UL)
- #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos)
- #define GPIO_OUTSET_PIN9_Low (0UL)
- #define GPIO_OUTSET_PIN9_High (1UL)
- #define GPIO_OUTSET_PIN9_Set (1UL)
- #define GPIO_OUTSET_PIN8_Pos (8UL)
- #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos)
- #define GPIO_OUTSET_PIN8_Low (0UL)
- #define GPIO_OUTSET_PIN8_High (1UL)
- #define GPIO_OUTSET_PIN8_Set (1UL)
- #define GPIO_OUTSET_PIN7_Pos (7UL)
- #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos)
- #define GPIO_OUTSET_PIN7_Low (0UL)
- #define GPIO_OUTSET_PIN7_High (1UL)
- #define GPIO_OUTSET_PIN7_Set (1UL)
- #define GPIO_OUTSET_PIN6_Pos (6UL)
- #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos)
- #define GPIO_OUTSET_PIN6_Low (0UL)
- #define GPIO_OUTSET_PIN6_High (1UL)
- #define GPIO_OUTSET_PIN6_Set (1UL)
- #define GPIO_OUTSET_PIN5_Pos (5UL)
- #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos)
- #define GPIO_OUTSET_PIN5_Low (0UL)
- #define GPIO_OUTSET_PIN5_High (1UL)
- #define GPIO_OUTSET_PIN5_Set (1UL)
- #define GPIO_OUTSET_PIN4_Pos (4UL)
- #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos)
- #define GPIO_OUTSET_PIN4_Low (0UL)
- #define GPIO_OUTSET_PIN4_High (1UL)
- #define GPIO_OUTSET_PIN4_Set (1UL)
- #define GPIO_OUTSET_PIN3_Pos (3UL)
- #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos)
- #define GPIO_OUTSET_PIN3_Low (0UL)
- #define GPIO_OUTSET_PIN3_High (1UL)
- #define GPIO_OUTSET_PIN3_Set (1UL)
- #define GPIO_OUTSET_PIN2_Pos (2UL)
- #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos)
- #define GPIO_OUTSET_PIN2_Low (0UL)
- #define GPIO_OUTSET_PIN2_High (1UL)
- #define GPIO_OUTSET_PIN2_Set (1UL)
- #define GPIO_OUTSET_PIN1_Pos (1UL)
- #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos)
- #define GPIO_OUTSET_PIN1_Low (0UL)
- #define GPIO_OUTSET_PIN1_High (1UL)
- #define GPIO_OUTSET_PIN1_Set (1UL)
- #define GPIO_OUTSET_PIN0_Pos (0UL)
- #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos)
- #define GPIO_OUTSET_PIN0_Low (0UL)
- #define GPIO_OUTSET_PIN0_High (1UL)
- #define GPIO_OUTSET_PIN0_Set (1UL)
- #define GPIO_OUTCLR_PIN31_Pos (31UL)
- #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos)
- #define GPIO_OUTCLR_PIN31_Low (0UL)
- #define GPIO_OUTCLR_PIN31_High (1UL)
- #define GPIO_OUTCLR_PIN31_Clear (1UL)
- #define GPIO_OUTCLR_PIN30_Pos (30UL)
- #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos)
- #define GPIO_OUTCLR_PIN30_Low (0UL)
- #define GPIO_OUTCLR_PIN30_High (1UL)
- #define GPIO_OUTCLR_PIN30_Clear (1UL)
- #define GPIO_OUTCLR_PIN29_Pos (29UL)
- #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos)
- #define GPIO_OUTCLR_PIN29_Low (0UL)
- #define GPIO_OUTCLR_PIN29_High (1UL)
- #define GPIO_OUTCLR_PIN29_Clear (1UL)
- #define GPIO_OUTCLR_PIN28_Pos (28UL)
- #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos)
- #define GPIO_OUTCLR_PIN28_Low (0UL)
- #define GPIO_OUTCLR_PIN28_High (1UL)
- #define GPIO_OUTCLR_PIN28_Clear (1UL)
- #define GPIO_OUTCLR_PIN27_Pos (27UL)
- #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos)
- #define GPIO_OUTCLR_PIN27_Low (0UL)
- #define GPIO_OUTCLR_PIN27_High (1UL)
- #define GPIO_OUTCLR_PIN27_Clear (1UL)
- #define GPIO_OUTCLR_PIN26_Pos (26UL)
- #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos)
- #define GPIO_OUTCLR_PIN26_Low (0UL)
- #define GPIO_OUTCLR_PIN26_High (1UL)
- #define GPIO_OUTCLR_PIN26_Clear (1UL)
- #define GPIO_OUTCLR_PIN25_Pos (25UL)
- #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos)
- #define GPIO_OUTCLR_PIN25_Low (0UL)
- #define GPIO_OUTCLR_PIN25_High (1UL)
- #define GPIO_OUTCLR_PIN25_Clear (1UL)
- #define GPIO_OUTCLR_PIN24_Pos (24UL)
- #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos)
- #define GPIO_OUTCLR_PIN24_Low (0UL)
- #define GPIO_OUTCLR_PIN24_High (1UL)
- #define GPIO_OUTCLR_PIN24_Clear (1UL)
- #define GPIO_OUTCLR_PIN23_Pos (23UL)
- #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos)
- #define GPIO_OUTCLR_PIN23_Low (0UL)
- #define GPIO_OUTCLR_PIN23_High (1UL)
- #define GPIO_OUTCLR_PIN23_Clear (1UL)
- #define GPIO_OUTCLR_PIN22_Pos (22UL)
- #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos)
- #define GPIO_OUTCLR_PIN22_Low (0UL)
- #define GPIO_OUTCLR_PIN22_High (1UL)
- #define GPIO_OUTCLR_PIN22_Clear (1UL)
- #define GPIO_OUTCLR_PIN21_Pos (21UL)
- #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos)
- #define GPIO_OUTCLR_PIN21_Low (0UL)
- #define GPIO_OUTCLR_PIN21_High (1UL)
- #define GPIO_OUTCLR_PIN21_Clear (1UL)
- #define GPIO_OUTCLR_PIN20_Pos (20UL)
- #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos)
- #define GPIO_OUTCLR_PIN20_Low (0UL)
- #define GPIO_OUTCLR_PIN20_High (1UL)
- #define GPIO_OUTCLR_PIN20_Clear (1UL)
- #define GPIO_OUTCLR_PIN19_Pos (19UL)
- #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos)
- #define GPIO_OUTCLR_PIN19_Low (0UL)
- #define GPIO_OUTCLR_PIN19_High (1UL)
- #define GPIO_OUTCLR_PIN19_Clear (1UL)
- #define GPIO_OUTCLR_PIN18_Pos (18UL)
- #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos)
- #define GPIO_OUTCLR_PIN18_Low (0UL)
- #define GPIO_OUTCLR_PIN18_High (1UL)
- #define GPIO_OUTCLR_PIN18_Clear (1UL)
- #define GPIO_OUTCLR_PIN17_Pos (17UL)
- #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos)
- #define GPIO_OUTCLR_PIN17_Low (0UL)
- #define GPIO_OUTCLR_PIN17_High (1UL)
- #define GPIO_OUTCLR_PIN17_Clear (1UL)
- #define GPIO_OUTCLR_PIN16_Pos (16UL)
- #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos)
- #define GPIO_OUTCLR_PIN16_Low (0UL)
- #define GPIO_OUTCLR_PIN16_High (1UL)
- #define GPIO_OUTCLR_PIN16_Clear (1UL)
- #define GPIO_OUTCLR_PIN15_Pos (15UL)
- #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos)
- #define GPIO_OUTCLR_PIN15_Low (0UL)
- #define GPIO_OUTCLR_PIN15_High (1UL)
- #define GPIO_OUTCLR_PIN15_Clear (1UL)
- #define GPIO_OUTCLR_PIN14_Pos (14UL)
- #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos)
- #define GPIO_OUTCLR_PIN14_Low (0UL)
- #define GPIO_OUTCLR_PIN14_High (1UL)
- #define GPIO_OUTCLR_PIN14_Clear (1UL)
- #define GPIO_OUTCLR_PIN13_Pos (13UL)
- #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos)
- #define GPIO_OUTCLR_PIN13_Low (0UL)
- #define GPIO_OUTCLR_PIN13_High (1UL)
- #define GPIO_OUTCLR_PIN13_Clear (1UL)
- #define GPIO_OUTCLR_PIN12_Pos (12UL)
- #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos)
- #define GPIO_OUTCLR_PIN12_Low (0UL)
- #define GPIO_OUTCLR_PIN12_High (1UL)
- #define GPIO_OUTCLR_PIN12_Clear (1UL)
- #define GPIO_OUTCLR_PIN11_Pos (11UL)
- #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos)
- #define GPIO_OUTCLR_PIN11_Low (0UL)
- #define GPIO_OUTCLR_PIN11_High (1UL)
- #define GPIO_OUTCLR_PIN11_Clear (1UL)
- #define GPIO_OUTCLR_PIN10_Pos (10UL)
- #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos)
- #define GPIO_OUTCLR_PIN10_Low (0UL)
- #define GPIO_OUTCLR_PIN10_High (1UL)
- #define GPIO_OUTCLR_PIN10_Clear (1UL)
- #define GPIO_OUTCLR_PIN9_Pos (9UL)
- #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos)
- #define GPIO_OUTCLR_PIN9_Low (0UL)
- #define GPIO_OUTCLR_PIN9_High (1UL)
- #define GPIO_OUTCLR_PIN9_Clear (1UL)
- #define GPIO_OUTCLR_PIN8_Pos (8UL)
- #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos)
- #define GPIO_OUTCLR_PIN8_Low (0UL)
- #define GPIO_OUTCLR_PIN8_High (1UL)
- #define GPIO_OUTCLR_PIN8_Clear (1UL)
- #define GPIO_OUTCLR_PIN7_Pos (7UL)
- #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos)
- #define GPIO_OUTCLR_PIN7_Low (0UL)
- #define GPIO_OUTCLR_PIN7_High (1UL)
- #define GPIO_OUTCLR_PIN7_Clear (1UL)
- #define GPIO_OUTCLR_PIN6_Pos (6UL)
- #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos)
- #define GPIO_OUTCLR_PIN6_Low (0UL)
- #define GPIO_OUTCLR_PIN6_High (1UL)
- #define GPIO_OUTCLR_PIN6_Clear (1UL)
- #define GPIO_OUTCLR_PIN5_Pos (5UL)
- #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos)
- #define GPIO_OUTCLR_PIN5_Low (0UL)
- #define GPIO_OUTCLR_PIN5_High (1UL)
- #define GPIO_OUTCLR_PIN5_Clear (1UL)
- #define GPIO_OUTCLR_PIN4_Pos (4UL)
- #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos)
- #define GPIO_OUTCLR_PIN4_Low (0UL)
- #define GPIO_OUTCLR_PIN4_High (1UL)
- #define GPIO_OUTCLR_PIN4_Clear (1UL)
- #define GPIO_OUTCLR_PIN3_Pos (3UL)
- #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos)
- #define GPIO_OUTCLR_PIN3_Low (0UL)
- #define GPIO_OUTCLR_PIN3_High (1UL)
- #define GPIO_OUTCLR_PIN3_Clear (1UL)
- #define GPIO_OUTCLR_PIN2_Pos (2UL)
- #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos)
- #define GPIO_OUTCLR_PIN2_Low (0UL)
- #define GPIO_OUTCLR_PIN2_High (1UL)
- #define GPIO_OUTCLR_PIN2_Clear (1UL)
- #define GPIO_OUTCLR_PIN1_Pos (1UL)
- #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos)
- #define GPIO_OUTCLR_PIN1_Low (0UL)
- #define GPIO_OUTCLR_PIN1_High (1UL)
- #define GPIO_OUTCLR_PIN1_Clear (1UL)
- #define GPIO_OUTCLR_PIN0_Pos (0UL)
- #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos)
- #define GPIO_OUTCLR_PIN0_Low (0UL)
- #define GPIO_OUTCLR_PIN0_High (1UL)
- #define GPIO_OUTCLR_PIN0_Clear (1UL)
- #define GPIO_IN_PIN31_Pos (31UL)
- #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos)
- #define GPIO_IN_PIN31_Low (0UL)
- #define GPIO_IN_PIN31_High (1UL)
- #define GPIO_IN_PIN30_Pos (30UL)
- #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos)
- #define GPIO_IN_PIN30_Low (0UL)
- #define GPIO_IN_PIN30_High (1UL)
- #define GPIO_IN_PIN29_Pos (29UL)
- #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos)
- #define GPIO_IN_PIN29_Low (0UL)
- #define GPIO_IN_PIN29_High (1UL)
- #define GPIO_IN_PIN28_Pos (28UL)
- #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos)
- #define GPIO_IN_PIN28_Low (0UL)
- #define GPIO_IN_PIN28_High (1UL)
- #define GPIO_IN_PIN27_Pos (27UL)
- #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos)
- #define GPIO_IN_PIN27_Low (0UL)
- #define GPIO_IN_PIN27_High (1UL)
- #define GPIO_IN_PIN26_Pos (26UL)
- #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos)
- #define GPIO_IN_PIN26_Low (0UL)
- #define GPIO_IN_PIN26_High (1UL)
- #define GPIO_IN_PIN25_Pos (25UL)
- #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos)
- #define GPIO_IN_PIN25_Low (0UL)
- #define GPIO_IN_PIN25_High (1UL)
- #define GPIO_IN_PIN24_Pos (24UL)
- #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos)
- #define GPIO_IN_PIN24_Low (0UL)
- #define GPIO_IN_PIN24_High (1UL)
- #define GPIO_IN_PIN23_Pos (23UL)
- #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos)
- #define GPIO_IN_PIN23_Low (0UL)
- #define GPIO_IN_PIN23_High (1UL)
- #define GPIO_IN_PIN22_Pos (22UL)
- #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos)
- #define GPIO_IN_PIN22_Low (0UL)
- #define GPIO_IN_PIN22_High (1UL)
- #define GPIO_IN_PIN21_Pos (21UL)
- #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos)
- #define GPIO_IN_PIN21_Low (0UL)
- #define GPIO_IN_PIN21_High (1UL)
- #define GPIO_IN_PIN20_Pos (20UL)
- #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos)
- #define GPIO_IN_PIN20_Low (0UL)
- #define GPIO_IN_PIN20_High (1UL)
- #define GPIO_IN_PIN19_Pos (19UL)
- #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos)
- #define GPIO_IN_PIN19_Low (0UL)
- #define GPIO_IN_PIN19_High (1UL)
- #define GPIO_IN_PIN18_Pos (18UL)
- #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos)
- #define GPIO_IN_PIN18_Low (0UL)
- #define GPIO_IN_PIN18_High (1UL)
- #define GPIO_IN_PIN17_Pos (17UL)
- #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos)
- #define GPIO_IN_PIN17_Low (0UL)
- #define GPIO_IN_PIN17_High (1UL)
- #define GPIO_IN_PIN16_Pos (16UL)
- #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos)
- #define GPIO_IN_PIN16_Low (0UL)
- #define GPIO_IN_PIN16_High (1UL)
- #define GPIO_IN_PIN15_Pos (15UL)
- #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos)
- #define GPIO_IN_PIN15_Low (0UL)
- #define GPIO_IN_PIN15_High (1UL)
- #define GPIO_IN_PIN14_Pos (14UL)
- #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos)
- #define GPIO_IN_PIN14_Low (0UL)
- #define GPIO_IN_PIN14_High (1UL)
- #define GPIO_IN_PIN13_Pos (13UL)
- #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos)
- #define GPIO_IN_PIN13_Low (0UL)
- #define GPIO_IN_PIN13_High (1UL)
- #define GPIO_IN_PIN12_Pos (12UL)
- #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos)
- #define GPIO_IN_PIN12_Low (0UL)
- #define GPIO_IN_PIN12_High (1UL)
- #define GPIO_IN_PIN11_Pos (11UL)
- #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos)
- #define GPIO_IN_PIN11_Low (0UL)
- #define GPIO_IN_PIN11_High (1UL)
- #define GPIO_IN_PIN10_Pos (10UL)
- #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos)
- #define GPIO_IN_PIN10_Low (0UL)
- #define GPIO_IN_PIN10_High (1UL)
- #define GPIO_IN_PIN9_Pos (9UL)
- #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos)
- #define GPIO_IN_PIN9_Low (0UL)
- #define GPIO_IN_PIN9_High (1UL)
- #define GPIO_IN_PIN8_Pos (8UL)
- #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos)
- #define GPIO_IN_PIN8_Low (0UL)
- #define GPIO_IN_PIN8_High (1UL)
- #define GPIO_IN_PIN7_Pos (7UL)
- #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos)
- #define GPIO_IN_PIN7_Low (0UL)
- #define GPIO_IN_PIN7_High (1UL)
- #define GPIO_IN_PIN6_Pos (6UL)
- #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos)
- #define GPIO_IN_PIN6_Low (0UL)
- #define GPIO_IN_PIN6_High (1UL)
- #define GPIO_IN_PIN5_Pos (5UL)
- #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos)
- #define GPIO_IN_PIN5_Low (0UL)
- #define GPIO_IN_PIN5_High (1UL)
- #define GPIO_IN_PIN4_Pos (4UL)
- #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos)
- #define GPIO_IN_PIN4_Low (0UL)
- #define GPIO_IN_PIN4_High (1UL)
- #define GPIO_IN_PIN3_Pos (3UL)
- #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos)
- #define GPIO_IN_PIN3_Low (0UL)
- #define GPIO_IN_PIN3_High (1UL)
- #define GPIO_IN_PIN2_Pos (2UL)
- #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos)
- #define GPIO_IN_PIN2_Low (0UL)
- #define GPIO_IN_PIN2_High (1UL)
- #define GPIO_IN_PIN1_Pos (1UL)
- #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos)
- #define GPIO_IN_PIN1_Low (0UL)
- #define GPIO_IN_PIN1_High (1UL)
- #define GPIO_IN_PIN0_Pos (0UL)
- #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos)
- #define GPIO_IN_PIN0_Low (0UL)
- #define GPIO_IN_PIN0_High (1UL)
- #define GPIO_DIR_PIN31_Pos (31UL)
- #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos)
- #define GPIO_DIR_PIN31_Input (0UL)
- #define GPIO_DIR_PIN31_Output (1UL)
- #define GPIO_DIR_PIN30_Pos (30UL)
- #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos)
- #define GPIO_DIR_PIN30_Input (0UL)
- #define GPIO_DIR_PIN30_Output (1UL)
- #define GPIO_DIR_PIN29_Pos (29UL)
- #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos)
- #define GPIO_DIR_PIN29_Input (0UL)
- #define GPIO_DIR_PIN29_Output (1UL)
- #define GPIO_DIR_PIN28_Pos (28UL)
- #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos)
- #define GPIO_DIR_PIN28_Input (0UL)
- #define GPIO_DIR_PIN28_Output (1UL)
- #define GPIO_DIR_PIN27_Pos (27UL)
- #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos)
- #define GPIO_DIR_PIN27_Input (0UL)
- #define GPIO_DIR_PIN27_Output (1UL)
- #define GPIO_DIR_PIN26_Pos (26UL)
- #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos)
- #define GPIO_DIR_PIN26_Input (0UL)
- #define GPIO_DIR_PIN26_Output (1UL)
- #define GPIO_DIR_PIN25_Pos (25UL)
- #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos)
- #define GPIO_DIR_PIN25_Input (0UL)
- #define GPIO_DIR_PIN25_Output (1UL)
- #define GPIO_DIR_PIN24_Pos (24UL)
- #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos)
- #define GPIO_DIR_PIN24_Input (0UL)
- #define GPIO_DIR_PIN24_Output (1UL)
- #define GPIO_DIR_PIN23_Pos (23UL)
- #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos)
- #define GPIO_DIR_PIN23_Input (0UL)
- #define GPIO_DIR_PIN23_Output (1UL)
- #define GPIO_DIR_PIN22_Pos (22UL)
- #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos)
- #define GPIO_DIR_PIN22_Input (0UL)
- #define GPIO_DIR_PIN22_Output (1UL)
- #define GPIO_DIR_PIN21_Pos (21UL)
- #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos)
- #define GPIO_DIR_PIN21_Input (0UL)
- #define GPIO_DIR_PIN21_Output (1UL)
- #define GPIO_DIR_PIN20_Pos (20UL)
- #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos)
- #define GPIO_DIR_PIN20_Input (0UL)
- #define GPIO_DIR_PIN20_Output (1UL)
- #define GPIO_DIR_PIN19_Pos (19UL)
- #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos)
- #define GPIO_DIR_PIN19_Input (0UL)
- #define GPIO_DIR_PIN19_Output (1UL)
- #define GPIO_DIR_PIN18_Pos (18UL)
- #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos)
- #define GPIO_DIR_PIN18_Input (0UL)
- #define GPIO_DIR_PIN18_Output (1UL)
- #define GPIO_DIR_PIN17_Pos (17UL)
- #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos)
- #define GPIO_DIR_PIN17_Input (0UL)
- #define GPIO_DIR_PIN17_Output (1UL)
- #define GPIO_DIR_PIN16_Pos (16UL)
- #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos)
- #define GPIO_DIR_PIN16_Input (0UL)
- #define GPIO_DIR_PIN16_Output (1UL)
- #define GPIO_DIR_PIN15_Pos (15UL)
- #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos)
- #define GPIO_DIR_PIN15_Input (0UL)
- #define GPIO_DIR_PIN15_Output (1UL)
- #define GPIO_DIR_PIN14_Pos (14UL)
- #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos)
- #define GPIO_DIR_PIN14_Input (0UL)
- #define GPIO_DIR_PIN14_Output (1UL)
- #define GPIO_DIR_PIN13_Pos (13UL)
- #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos)
- #define GPIO_DIR_PIN13_Input (0UL)
- #define GPIO_DIR_PIN13_Output (1UL)
- #define GPIO_DIR_PIN12_Pos (12UL)
- #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos)
- #define GPIO_DIR_PIN12_Input (0UL)
- #define GPIO_DIR_PIN12_Output (1UL)
- #define GPIO_DIR_PIN11_Pos (11UL)
- #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos)
- #define GPIO_DIR_PIN11_Input (0UL)
- #define GPIO_DIR_PIN11_Output (1UL)
- #define GPIO_DIR_PIN10_Pos (10UL)
- #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos)
- #define GPIO_DIR_PIN10_Input (0UL)
- #define GPIO_DIR_PIN10_Output (1UL)
- #define GPIO_DIR_PIN9_Pos (9UL)
- #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos)
- #define GPIO_DIR_PIN9_Input (0UL)
- #define GPIO_DIR_PIN9_Output (1UL)
- #define GPIO_DIR_PIN8_Pos (8UL)
- #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos)
- #define GPIO_DIR_PIN8_Input (0UL)
- #define GPIO_DIR_PIN8_Output (1UL)
- #define GPIO_DIR_PIN7_Pos (7UL)
- #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos)
- #define GPIO_DIR_PIN7_Input (0UL)
- #define GPIO_DIR_PIN7_Output (1UL)
- #define GPIO_DIR_PIN6_Pos (6UL)
- #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos)
- #define GPIO_DIR_PIN6_Input (0UL)
- #define GPIO_DIR_PIN6_Output (1UL)
- #define GPIO_DIR_PIN5_Pos (5UL)
- #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos)
- #define GPIO_DIR_PIN5_Input (0UL)
- #define GPIO_DIR_PIN5_Output (1UL)
- #define GPIO_DIR_PIN4_Pos (4UL)
- #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos)
- #define GPIO_DIR_PIN4_Input (0UL)
- #define GPIO_DIR_PIN4_Output (1UL)
- #define GPIO_DIR_PIN3_Pos (3UL)
- #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos)
- #define GPIO_DIR_PIN3_Input (0UL)
- #define GPIO_DIR_PIN3_Output (1UL)
- #define GPIO_DIR_PIN2_Pos (2UL)
- #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos)
- #define GPIO_DIR_PIN2_Input (0UL)
- #define GPIO_DIR_PIN2_Output (1UL)
- #define GPIO_DIR_PIN1_Pos (1UL)
- #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos)
- #define GPIO_DIR_PIN1_Input (0UL)
- #define GPIO_DIR_PIN1_Output (1UL)
- #define GPIO_DIR_PIN0_Pos (0UL)
- #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos)
- #define GPIO_DIR_PIN0_Input (0UL)
- #define GPIO_DIR_PIN0_Output (1UL)
- #define GPIO_DIRSET_PIN31_Pos (31UL)
- #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos)
- #define GPIO_DIRSET_PIN31_Input (0UL)
- #define GPIO_DIRSET_PIN31_Output (1UL)
- #define GPIO_DIRSET_PIN31_Set (1UL)
- #define GPIO_DIRSET_PIN30_Pos (30UL)
- #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos)
- #define GPIO_DIRSET_PIN30_Input (0UL)
- #define GPIO_DIRSET_PIN30_Output (1UL)
- #define GPIO_DIRSET_PIN30_Set (1UL)
- #define GPIO_DIRSET_PIN29_Pos (29UL)
- #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos)
- #define GPIO_DIRSET_PIN29_Input (0UL)
- #define GPIO_DIRSET_PIN29_Output (1UL)
- #define GPIO_DIRSET_PIN29_Set (1UL)
- #define GPIO_DIRSET_PIN28_Pos (28UL)
- #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos)
- #define GPIO_DIRSET_PIN28_Input (0UL)
- #define GPIO_DIRSET_PIN28_Output (1UL)
- #define GPIO_DIRSET_PIN28_Set (1UL)
- #define GPIO_DIRSET_PIN27_Pos (27UL)
- #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos)
- #define GPIO_DIRSET_PIN27_Input (0UL)
- #define GPIO_DIRSET_PIN27_Output (1UL)
- #define GPIO_DIRSET_PIN27_Set (1UL)
- #define GPIO_DIRSET_PIN26_Pos (26UL)
- #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos)
- #define GPIO_DIRSET_PIN26_Input (0UL)
- #define GPIO_DIRSET_PIN26_Output (1UL)
- #define GPIO_DIRSET_PIN26_Set (1UL)
- #define GPIO_DIRSET_PIN25_Pos (25UL)
- #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos)
- #define GPIO_DIRSET_PIN25_Input (0UL)
- #define GPIO_DIRSET_PIN25_Output (1UL)
- #define GPIO_DIRSET_PIN25_Set (1UL)
- #define GPIO_DIRSET_PIN24_Pos (24UL)
- #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos)
- #define GPIO_DIRSET_PIN24_Input (0UL)
- #define GPIO_DIRSET_PIN24_Output (1UL)
- #define GPIO_DIRSET_PIN24_Set (1UL)
- #define GPIO_DIRSET_PIN23_Pos (23UL)
- #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos)
- #define GPIO_DIRSET_PIN23_Input (0UL)
- #define GPIO_DIRSET_PIN23_Output (1UL)
- #define GPIO_DIRSET_PIN23_Set (1UL)
- #define GPIO_DIRSET_PIN22_Pos (22UL)
- #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos)
- #define GPIO_DIRSET_PIN22_Input (0UL)
- #define GPIO_DIRSET_PIN22_Output (1UL)
- #define GPIO_DIRSET_PIN22_Set (1UL)
- #define GPIO_DIRSET_PIN21_Pos (21UL)
- #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos)
- #define GPIO_DIRSET_PIN21_Input (0UL)
- #define GPIO_DIRSET_PIN21_Output (1UL)
- #define GPIO_DIRSET_PIN21_Set (1UL)
- #define GPIO_DIRSET_PIN20_Pos (20UL)
- #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos)
- #define GPIO_DIRSET_PIN20_Input (0UL)
- #define GPIO_DIRSET_PIN20_Output (1UL)
- #define GPIO_DIRSET_PIN20_Set (1UL)
- #define GPIO_DIRSET_PIN19_Pos (19UL)
- #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos)
- #define GPIO_DIRSET_PIN19_Input (0UL)
- #define GPIO_DIRSET_PIN19_Output (1UL)
- #define GPIO_DIRSET_PIN19_Set (1UL)
- #define GPIO_DIRSET_PIN18_Pos (18UL)
- #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos)
- #define GPIO_DIRSET_PIN18_Input (0UL)
- #define GPIO_DIRSET_PIN18_Output (1UL)
- #define GPIO_DIRSET_PIN18_Set (1UL)
- #define GPIO_DIRSET_PIN17_Pos (17UL)
- #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos)
- #define GPIO_DIRSET_PIN17_Input (0UL)
- #define GPIO_DIRSET_PIN17_Output (1UL)
- #define GPIO_DIRSET_PIN17_Set (1UL)
- #define GPIO_DIRSET_PIN16_Pos (16UL)
- #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos)
- #define GPIO_DIRSET_PIN16_Input (0UL)
- #define GPIO_DIRSET_PIN16_Output (1UL)
- #define GPIO_DIRSET_PIN16_Set (1UL)
- #define GPIO_DIRSET_PIN15_Pos (15UL)
- #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos)
- #define GPIO_DIRSET_PIN15_Input (0UL)
- #define GPIO_DIRSET_PIN15_Output (1UL)
- #define GPIO_DIRSET_PIN15_Set (1UL)
- #define GPIO_DIRSET_PIN14_Pos (14UL)
- #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos)
- #define GPIO_DIRSET_PIN14_Input (0UL)
- #define GPIO_DIRSET_PIN14_Output (1UL)
- #define GPIO_DIRSET_PIN14_Set (1UL)
- #define GPIO_DIRSET_PIN13_Pos (13UL)
- #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos)
- #define GPIO_DIRSET_PIN13_Input (0UL)
- #define GPIO_DIRSET_PIN13_Output (1UL)
- #define GPIO_DIRSET_PIN13_Set (1UL)
- #define GPIO_DIRSET_PIN12_Pos (12UL)
- #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos)
- #define GPIO_DIRSET_PIN12_Input (0UL)
- #define GPIO_DIRSET_PIN12_Output (1UL)
- #define GPIO_DIRSET_PIN12_Set (1UL)
- #define GPIO_DIRSET_PIN11_Pos (11UL)
- #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos)
- #define GPIO_DIRSET_PIN11_Input (0UL)
- #define GPIO_DIRSET_PIN11_Output (1UL)
- #define GPIO_DIRSET_PIN11_Set (1UL)
- #define GPIO_DIRSET_PIN10_Pos (10UL)
- #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos)
- #define GPIO_DIRSET_PIN10_Input (0UL)
- #define GPIO_DIRSET_PIN10_Output (1UL)
- #define GPIO_DIRSET_PIN10_Set (1UL)
- #define GPIO_DIRSET_PIN9_Pos (9UL)
- #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos)
- #define GPIO_DIRSET_PIN9_Input (0UL)
- #define GPIO_DIRSET_PIN9_Output (1UL)
- #define GPIO_DIRSET_PIN9_Set (1UL)
- #define GPIO_DIRSET_PIN8_Pos (8UL)
- #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos)
- #define GPIO_DIRSET_PIN8_Input (0UL)
- #define GPIO_DIRSET_PIN8_Output (1UL)
- #define GPIO_DIRSET_PIN8_Set (1UL)
- #define GPIO_DIRSET_PIN7_Pos (7UL)
- #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos)
- #define GPIO_DIRSET_PIN7_Input (0UL)
- #define GPIO_DIRSET_PIN7_Output (1UL)
- #define GPIO_DIRSET_PIN7_Set (1UL)
- #define GPIO_DIRSET_PIN6_Pos (6UL)
- #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos)
- #define GPIO_DIRSET_PIN6_Input (0UL)
- #define GPIO_DIRSET_PIN6_Output (1UL)
- #define GPIO_DIRSET_PIN6_Set (1UL)
- #define GPIO_DIRSET_PIN5_Pos (5UL)
- #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos)
- #define GPIO_DIRSET_PIN5_Input (0UL)
- #define GPIO_DIRSET_PIN5_Output (1UL)
- #define GPIO_DIRSET_PIN5_Set (1UL)
- #define GPIO_DIRSET_PIN4_Pos (4UL)
- #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos)
- #define GPIO_DIRSET_PIN4_Input (0UL)
- #define GPIO_DIRSET_PIN4_Output (1UL)
- #define GPIO_DIRSET_PIN4_Set (1UL)
- #define GPIO_DIRSET_PIN3_Pos (3UL)
- #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos)
- #define GPIO_DIRSET_PIN3_Input (0UL)
- #define GPIO_DIRSET_PIN3_Output (1UL)
- #define GPIO_DIRSET_PIN3_Set (1UL)
- #define GPIO_DIRSET_PIN2_Pos (2UL)
- #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos)
- #define GPIO_DIRSET_PIN2_Input (0UL)
- #define GPIO_DIRSET_PIN2_Output (1UL)
- #define GPIO_DIRSET_PIN2_Set (1UL)
- #define GPIO_DIRSET_PIN1_Pos (1UL)
- #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos)
- #define GPIO_DIRSET_PIN1_Input (0UL)
- #define GPIO_DIRSET_PIN1_Output (1UL)
- #define GPIO_DIRSET_PIN1_Set (1UL)
- #define GPIO_DIRSET_PIN0_Pos (0UL)
- #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos)
- #define GPIO_DIRSET_PIN0_Input (0UL)
- #define GPIO_DIRSET_PIN0_Output (1UL)
- #define GPIO_DIRSET_PIN0_Set (1UL)
- #define GPIO_DIRCLR_PIN31_Pos (31UL)
- #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos)
- #define GPIO_DIRCLR_PIN31_Input (0UL)
- #define GPIO_DIRCLR_PIN31_Output (1UL)
- #define GPIO_DIRCLR_PIN31_Clear (1UL)
- #define GPIO_DIRCLR_PIN30_Pos (30UL)
- #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos)
- #define GPIO_DIRCLR_PIN30_Input (0UL)
- #define GPIO_DIRCLR_PIN30_Output (1UL)
- #define GPIO_DIRCLR_PIN30_Clear (1UL)
- #define GPIO_DIRCLR_PIN29_Pos (29UL)
- #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos)
- #define GPIO_DIRCLR_PIN29_Input (0UL)
- #define GPIO_DIRCLR_PIN29_Output (1UL)
- #define GPIO_DIRCLR_PIN29_Clear (1UL)
- #define GPIO_DIRCLR_PIN28_Pos (28UL)
- #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos)
- #define GPIO_DIRCLR_PIN28_Input (0UL)
- #define GPIO_DIRCLR_PIN28_Output (1UL)
- #define GPIO_DIRCLR_PIN28_Clear (1UL)
- #define GPIO_DIRCLR_PIN27_Pos (27UL)
- #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos)
- #define GPIO_DIRCLR_PIN27_Input (0UL)
- #define GPIO_DIRCLR_PIN27_Output (1UL)
- #define GPIO_DIRCLR_PIN27_Clear (1UL)
- #define GPIO_DIRCLR_PIN26_Pos (26UL)
- #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos)
- #define GPIO_DIRCLR_PIN26_Input (0UL)
- #define GPIO_DIRCLR_PIN26_Output (1UL)
- #define GPIO_DIRCLR_PIN26_Clear (1UL)
- #define GPIO_DIRCLR_PIN25_Pos (25UL)
- #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos)
- #define GPIO_DIRCLR_PIN25_Input (0UL)
- #define GPIO_DIRCLR_PIN25_Output (1UL)
- #define GPIO_DIRCLR_PIN25_Clear (1UL)
- #define GPIO_DIRCLR_PIN24_Pos (24UL)
- #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos)
- #define GPIO_DIRCLR_PIN24_Input (0UL)
- #define GPIO_DIRCLR_PIN24_Output (1UL)
- #define GPIO_DIRCLR_PIN24_Clear (1UL)
- #define GPIO_DIRCLR_PIN23_Pos (23UL)
- #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos)
- #define GPIO_DIRCLR_PIN23_Input (0UL)
- #define GPIO_DIRCLR_PIN23_Output (1UL)
- #define GPIO_DIRCLR_PIN23_Clear (1UL)
- #define GPIO_DIRCLR_PIN22_Pos (22UL)
- #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos)
- #define GPIO_DIRCLR_PIN22_Input (0UL)
- #define GPIO_DIRCLR_PIN22_Output (1UL)
- #define GPIO_DIRCLR_PIN22_Clear (1UL)
- #define GPIO_DIRCLR_PIN21_Pos (21UL)
- #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos)
- #define GPIO_DIRCLR_PIN21_Input (0UL)
- #define GPIO_DIRCLR_PIN21_Output (1UL)
- #define GPIO_DIRCLR_PIN21_Clear (1UL)
- #define GPIO_DIRCLR_PIN20_Pos (20UL)
- #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos)
- #define GPIO_DIRCLR_PIN20_Input (0UL)
- #define GPIO_DIRCLR_PIN20_Output (1UL)
- #define GPIO_DIRCLR_PIN20_Clear (1UL)
- #define GPIO_DIRCLR_PIN19_Pos (19UL)
- #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos)
- #define GPIO_DIRCLR_PIN19_Input (0UL)
- #define GPIO_DIRCLR_PIN19_Output (1UL)
- #define GPIO_DIRCLR_PIN19_Clear (1UL)
- #define GPIO_DIRCLR_PIN18_Pos (18UL)
- #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos)
- #define GPIO_DIRCLR_PIN18_Input (0UL)
- #define GPIO_DIRCLR_PIN18_Output (1UL)
- #define GPIO_DIRCLR_PIN18_Clear (1UL)
- #define GPIO_DIRCLR_PIN17_Pos (17UL)
- #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos)
- #define GPIO_DIRCLR_PIN17_Input (0UL)
- #define GPIO_DIRCLR_PIN17_Output (1UL)
- #define GPIO_DIRCLR_PIN17_Clear (1UL)
- #define GPIO_DIRCLR_PIN16_Pos (16UL)
- #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos)
- #define GPIO_DIRCLR_PIN16_Input (0UL)
- #define GPIO_DIRCLR_PIN16_Output (1UL)
- #define GPIO_DIRCLR_PIN16_Clear (1UL)
- #define GPIO_DIRCLR_PIN15_Pos (15UL)
- #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos)
- #define GPIO_DIRCLR_PIN15_Input (0UL)
- #define GPIO_DIRCLR_PIN15_Output (1UL)
- #define GPIO_DIRCLR_PIN15_Clear (1UL)
- #define GPIO_DIRCLR_PIN14_Pos (14UL)
- #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos)
- #define GPIO_DIRCLR_PIN14_Input (0UL)
- #define GPIO_DIRCLR_PIN14_Output (1UL)
- #define GPIO_DIRCLR_PIN14_Clear (1UL)
- #define GPIO_DIRCLR_PIN13_Pos (13UL)
- #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos)
- #define GPIO_DIRCLR_PIN13_Input (0UL)
- #define GPIO_DIRCLR_PIN13_Output (1UL)
- #define GPIO_DIRCLR_PIN13_Clear (1UL)
- #define GPIO_DIRCLR_PIN12_Pos (12UL)
- #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos)
- #define GPIO_DIRCLR_PIN12_Input (0UL)
- #define GPIO_DIRCLR_PIN12_Output (1UL)
- #define GPIO_DIRCLR_PIN12_Clear (1UL)
- #define GPIO_DIRCLR_PIN11_Pos (11UL)
- #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos)
- #define GPIO_DIRCLR_PIN11_Input (0UL)
- #define GPIO_DIRCLR_PIN11_Output (1UL)
- #define GPIO_DIRCLR_PIN11_Clear (1UL)
- #define GPIO_DIRCLR_PIN10_Pos (10UL)
- #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos)
- #define GPIO_DIRCLR_PIN10_Input (0UL)
- #define GPIO_DIRCLR_PIN10_Output (1UL)
- #define GPIO_DIRCLR_PIN10_Clear (1UL)
- #define GPIO_DIRCLR_PIN9_Pos (9UL)
- #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos)
- #define GPIO_DIRCLR_PIN9_Input (0UL)
- #define GPIO_DIRCLR_PIN9_Output (1UL)
- #define GPIO_DIRCLR_PIN9_Clear (1UL)
- #define GPIO_DIRCLR_PIN8_Pos (8UL)
- #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos)
- #define GPIO_DIRCLR_PIN8_Input (0UL)
- #define GPIO_DIRCLR_PIN8_Output (1UL)
- #define GPIO_DIRCLR_PIN8_Clear (1UL)
- #define GPIO_DIRCLR_PIN7_Pos (7UL)
- #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos)
- #define GPIO_DIRCLR_PIN7_Input (0UL)
- #define GPIO_DIRCLR_PIN7_Output (1UL)
- #define GPIO_DIRCLR_PIN7_Clear (1UL)
- #define GPIO_DIRCLR_PIN6_Pos (6UL)
- #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos)
- #define GPIO_DIRCLR_PIN6_Input (0UL)
- #define GPIO_DIRCLR_PIN6_Output (1UL)
- #define GPIO_DIRCLR_PIN6_Clear (1UL)
- #define GPIO_DIRCLR_PIN5_Pos (5UL)
- #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos)
- #define GPIO_DIRCLR_PIN5_Input (0UL)
- #define GPIO_DIRCLR_PIN5_Output (1UL)
- #define GPIO_DIRCLR_PIN5_Clear (1UL)
- #define GPIO_DIRCLR_PIN4_Pos (4UL)
- #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos)
- #define GPIO_DIRCLR_PIN4_Input (0UL)
- #define GPIO_DIRCLR_PIN4_Output (1UL)
- #define GPIO_DIRCLR_PIN4_Clear (1UL)
- #define GPIO_DIRCLR_PIN3_Pos (3UL)
- #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos)
- #define GPIO_DIRCLR_PIN3_Input (0UL)
- #define GPIO_DIRCLR_PIN3_Output (1UL)
- #define GPIO_DIRCLR_PIN3_Clear (1UL)
- #define GPIO_DIRCLR_PIN2_Pos (2UL)
- #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos)
- #define GPIO_DIRCLR_PIN2_Input (0UL)
- #define GPIO_DIRCLR_PIN2_Output (1UL)
- #define GPIO_DIRCLR_PIN2_Clear (1UL)
- #define GPIO_DIRCLR_PIN1_Pos (1UL)
- #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos)
- #define GPIO_DIRCLR_PIN1_Input (0UL)
- #define GPIO_DIRCLR_PIN1_Output (1UL)
- #define GPIO_DIRCLR_PIN1_Clear (1UL)
- #define GPIO_DIRCLR_PIN0_Pos (0UL)
- #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos)
- #define GPIO_DIRCLR_PIN0_Input (0UL)
- #define GPIO_DIRCLR_PIN0_Output (1UL)
- #define GPIO_DIRCLR_PIN0_Clear (1UL)
- #define GPIO_LATCH_PIN31_Pos (31UL)
- #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos)
- #define GPIO_LATCH_PIN31_NotLatched (0UL)
- #define GPIO_LATCH_PIN31_Latched (1UL)
- #define GPIO_LATCH_PIN30_Pos (30UL)
- #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos)
- #define GPIO_LATCH_PIN30_NotLatched (0UL)
- #define GPIO_LATCH_PIN30_Latched (1UL)
- #define GPIO_LATCH_PIN29_Pos (29UL)
- #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos)
- #define GPIO_LATCH_PIN29_NotLatched (0UL)
- #define GPIO_LATCH_PIN29_Latched (1UL)
- #define GPIO_LATCH_PIN28_Pos (28UL)
- #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos)
- #define GPIO_LATCH_PIN28_NotLatched (0UL)
- #define GPIO_LATCH_PIN28_Latched (1UL)
- #define GPIO_LATCH_PIN27_Pos (27UL)
- #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos)
- #define GPIO_LATCH_PIN27_NotLatched (0UL)
- #define GPIO_LATCH_PIN27_Latched (1UL)
- #define GPIO_LATCH_PIN26_Pos (26UL)
- #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos)
- #define GPIO_LATCH_PIN26_NotLatched (0UL)
- #define GPIO_LATCH_PIN26_Latched (1UL)
- #define GPIO_LATCH_PIN25_Pos (25UL)
- #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos)
- #define GPIO_LATCH_PIN25_NotLatched (0UL)
- #define GPIO_LATCH_PIN25_Latched (1UL)
- #define GPIO_LATCH_PIN24_Pos (24UL)
- #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos)
- #define GPIO_LATCH_PIN24_NotLatched (0UL)
- #define GPIO_LATCH_PIN24_Latched (1UL)
- #define GPIO_LATCH_PIN23_Pos (23UL)
- #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos)
- #define GPIO_LATCH_PIN23_NotLatched (0UL)
- #define GPIO_LATCH_PIN23_Latched (1UL)
- #define GPIO_LATCH_PIN22_Pos (22UL)
- #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos)
- #define GPIO_LATCH_PIN22_NotLatched (0UL)
- #define GPIO_LATCH_PIN22_Latched (1UL)
- #define GPIO_LATCH_PIN21_Pos (21UL)
- #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos)
- #define GPIO_LATCH_PIN21_NotLatched (0UL)
- #define GPIO_LATCH_PIN21_Latched (1UL)
- #define GPIO_LATCH_PIN20_Pos (20UL)
- #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos)
- #define GPIO_LATCH_PIN20_NotLatched (0UL)
- #define GPIO_LATCH_PIN20_Latched (1UL)
- #define GPIO_LATCH_PIN19_Pos (19UL)
- #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos)
- #define GPIO_LATCH_PIN19_NotLatched (0UL)
- #define GPIO_LATCH_PIN19_Latched (1UL)
- #define GPIO_LATCH_PIN18_Pos (18UL)
- #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos)
- #define GPIO_LATCH_PIN18_NotLatched (0UL)
- #define GPIO_LATCH_PIN18_Latched (1UL)
- #define GPIO_LATCH_PIN17_Pos (17UL)
- #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos)
- #define GPIO_LATCH_PIN17_NotLatched (0UL)
- #define GPIO_LATCH_PIN17_Latched (1UL)
- #define GPIO_LATCH_PIN16_Pos (16UL)
- #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos)
- #define GPIO_LATCH_PIN16_NotLatched (0UL)
- #define GPIO_LATCH_PIN16_Latched (1UL)
- #define GPIO_LATCH_PIN15_Pos (15UL)
- #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos)
- #define GPIO_LATCH_PIN15_NotLatched (0UL)
- #define GPIO_LATCH_PIN15_Latched (1UL)
- #define GPIO_LATCH_PIN14_Pos (14UL)
- #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos)
- #define GPIO_LATCH_PIN14_NotLatched (0UL)
- #define GPIO_LATCH_PIN14_Latched (1UL)
- #define GPIO_LATCH_PIN13_Pos (13UL)
- #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos)
- #define GPIO_LATCH_PIN13_NotLatched (0UL)
- #define GPIO_LATCH_PIN13_Latched (1UL)
- #define GPIO_LATCH_PIN12_Pos (12UL)
- #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos)
- #define GPIO_LATCH_PIN12_NotLatched (0UL)
- #define GPIO_LATCH_PIN12_Latched (1UL)
- #define GPIO_LATCH_PIN11_Pos (11UL)
- #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos)
- #define GPIO_LATCH_PIN11_NotLatched (0UL)
- #define GPIO_LATCH_PIN11_Latched (1UL)
- #define GPIO_LATCH_PIN10_Pos (10UL)
- #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos)
- #define GPIO_LATCH_PIN10_NotLatched (0UL)
- #define GPIO_LATCH_PIN10_Latched (1UL)
- #define GPIO_LATCH_PIN9_Pos (9UL)
- #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos)
- #define GPIO_LATCH_PIN9_NotLatched (0UL)
- #define GPIO_LATCH_PIN9_Latched (1UL)
- #define GPIO_LATCH_PIN8_Pos (8UL)
- #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos)
- #define GPIO_LATCH_PIN8_NotLatched (0UL)
- #define GPIO_LATCH_PIN8_Latched (1UL)
- #define GPIO_LATCH_PIN7_Pos (7UL)
- #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos)
- #define GPIO_LATCH_PIN7_NotLatched (0UL)
- #define GPIO_LATCH_PIN7_Latched (1UL)
- #define GPIO_LATCH_PIN6_Pos (6UL)
- #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos)
- #define GPIO_LATCH_PIN6_NotLatched (0UL)
- #define GPIO_LATCH_PIN6_Latched (1UL)
- #define GPIO_LATCH_PIN5_Pos (5UL)
- #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos)
- #define GPIO_LATCH_PIN5_NotLatched (0UL)
- #define GPIO_LATCH_PIN5_Latched (1UL)
- #define GPIO_LATCH_PIN4_Pos (4UL)
- #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos)
- #define GPIO_LATCH_PIN4_NotLatched (0UL)
- #define GPIO_LATCH_PIN4_Latched (1UL)
- #define GPIO_LATCH_PIN3_Pos (3UL)
- #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos)
- #define GPIO_LATCH_PIN3_NotLatched (0UL)
- #define GPIO_LATCH_PIN3_Latched (1UL)
- #define GPIO_LATCH_PIN2_Pos (2UL)
- #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos)
- #define GPIO_LATCH_PIN2_NotLatched (0UL)
- #define GPIO_LATCH_PIN2_Latched (1UL)
- #define GPIO_LATCH_PIN1_Pos (1UL)
- #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos)
- #define GPIO_LATCH_PIN1_NotLatched (0UL)
- #define GPIO_LATCH_PIN1_Latched (1UL)
- #define GPIO_LATCH_PIN0_Pos (0UL)
- #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos)
- #define GPIO_LATCH_PIN0_NotLatched (0UL)
- #define GPIO_LATCH_PIN0_Latched (1UL)
- #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL)
- #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos)
- #define GPIO_DETECTMODE_DETECTMODE_Default (0UL)
- #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL)
- #define GPIO_DETECTMODE_SEC_DETECTMODE_Pos (0UL)
- #define GPIO_DETECTMODE_SEC_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_SEC_DETECTMODE_Pos)
- #define GPIO_DETECTMODE_SEC_DETECTMODE_Default (0UL)
- #define GPIO_DETECTMODE_SEC_DETECTMODE_LDETECT (1UL)
- #define GPIO_PIN_CNF_SENSE_Pos (16UL)
- #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos)
- #define GPIO_PIN_CNF_SENSE_Disabled (0UL)
- #define GPIO_PIN_CNF_SENSE_High (2UL)
- #define GPIO_PIN_CNF_SENSE_Low (3UL)
- #define GPIO_PIN_CNF_DRIVE_Pos (8UL)
- #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos)
- #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL)
- #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL)
- #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL)
- #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL)
- #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL)
- #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL)
- #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL)
- #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL)
- #define GPIO_PIN_CNF_PULL_Pos (2UL)
- #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos)
- #define GPIO_PIN_CNF_PULL_Disabled (0UL)
- #define GPIO_PIN_CNF_PULL_Pulldown (1UL)
- #define GPIO_PIN_CNF_PULL_Pullup (3UL)
- #define GPIO_PIN_CNF_INPUT_Pos (1UL)
- #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos)
- #define GPIO_PIN_CNF_INPUT_Connect (0UL)
- #define GPIO_PIN_CNF_INPUT_Disconnect (1UL)
- #define GPIO_PIN_CNF_DIR_Pos (0UL)
- #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos)
- #define GPIO_PIN_CNF_DIR_Input (0UL)
- #define GPIO_PIN_CNF_DIR_Output (1UL)
- #define PDM_TASKS_START_TASKS_START_Pos (0UL)
- #define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos)
- #define PDM_TASKS_START_TASKS_START_Trigger (1UL)
- #define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos)
- #define PDM_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define PDM_SUBSCRIBE_START_EN_Pos (31UL)
- #define PDM_SUBSCRIBE_START_EN_Msk (0x1UL << PDM_SUBSCRIBE_START_EN_Pos)
- #define PDM_SUBSCRIBE_START_EN_Disabled (0UL)
- #define PDM_SUBSCRIBE_START_EN_Enabled (1UL)
- #define PDM_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define PDM_SUBSCRIBE_START_CHIDX_Msk (0xFUL << PDM_SUBSCRIBE_START_CHIDX_Pos)
- #define PDM_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define PDM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PDM_SUBSCRIBE_STOP_EN_Pos)
- #define PDM_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define PDM_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define PDM_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define PDM_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << PDM_SUBSCRIBE_STOP_CHIDX_Pos)
- #define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL)
- #define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos)
- #define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL)
- #define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL)
- #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL)
- #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos)
- #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL)
- #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL)
- #define PDM_EVENTS_END_EVENTS_END_Pos (0UL)
- #define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos)
- #define PDM_EVENTS_END_EVENTS_END_NotGenerated (0UL)
- #define PDM_EVENTS_END_EVENTS_END_Generated (1UL)
- #define PDM_PUBLISH_STARTED_EN_Pos (31UL)
- #define PDM_PUBLISH_STARTED_EN_Msk (0x1UL << PDM_PUBLISH_STARTED_EN_Pos)
- #define PDM_PUBLISH_STARTED_EN_Disabled (0UL)
- #define PDM_PUBLISH_STARTED_EN_Enabled (1UL)
- #define PDM_PUBLISH_STARTED_CHIDX_Pos (0UL)
- #define PDM_PUBLISH_STARTED_CHIDX_Msk (0xFUL << PDM_PUBLISH_STARTED_CHIDX_Pos)
- #define PDM_PUBLISH_STOPPED_EN_Pos (31UL)
- #define PDM_PUBLISH_STOPPED_EN_Msk (0x1UL << PDM_PUBLISH_STOPPED_EN_Pos)
- #define PDM_PUBLISH_STOPPED_EN_Disabled (0UL)
- #define PDM_PUBLISH_STOPPED_EN_Enabled (1UL)
- #define PDM_PUBLISH_STOPPED_CHIDX_Pos (0UL)
- #define PDM_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << PDM_PUBLISH_STOPPED_CHIDX_Pos)
- #define PDM_PUBLISH_END_EN_Pos (31UL)
- #define PDM_PUBLISH_END_EN_Msk (0x1UL << PDM_PUBLISH_END_EN_Pos)
- #define PDM_PUBLISH_END_EN_Disabled (0UL)
- #define PDM_PUBLISH_END_EN_Enabled (1UL)
- #define PDM_PUBLISH_END_CHIDX_Pos (0UL)
- #define PDM_PUBLISH_END_CHIDX_Msk (0xFUL << PDM_PUBLISH_END_CHIDX_Pos)
- #define PDM_INTEN_END_Pos (2UL)
- #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos)
- #define PDM_INTEN_END_Disabled (0UL)
- #define PDM_INTEN_END_Enabled (1UL)
- #define PDM_INTEN_STOPPED_Pos (1UL)
- #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos)
- #define PDM_INTEN_STOPPED_Disabled (0UL)
- #define PDM_INTEN_STOPPED_Enabled (1UL)
- #define PDM_INTEN_STARTED_Pos (0UL)
- #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos)
- #define PDM_INTEN_STARTED_Disabled (0UL)
- #define PDM_INTEN_STARTED_Enabled (1UL)
- #define PDM_INTENSET_END_Pos (2UL)
- #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos)
- #define PDM_INTENSET_END_Disabled (0UL)
- #define PDM_INTENSET_END_Enabled (1UL)
- #define PDM_INTENSET_END_Set (1UL)
- #define PDM_INTENSET_STOPPED_Pos (1UL)
- #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos)
- #define PDM_INTENSET_STOPPED_Disabled (0UL)
- #define PDM_INTENSET_STOPPED_Enabled (1UL)
- #define PDM_INTENSET_STOPPED_Set (1UL)
- #define PDM_INTENSET_STARTED_Pos (0UL)
- #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos)
- #define PDM_INTENSET_STARTED_Disabled (0UL)
- #define PDM_INTENSET_STARTED_Enabled (1UL)
- #define PDM_INTENSET_STARTED_Set (1UL)
- #define PDM_INTENCLR_END_Pos (2UL)
- #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos)
- #define PDM_INTENCLR_END_Disabled (0UL)
- #define PDM_INTENCLR_END_Enabled (1UL)
- #define PDM_INTENCLR_END_Clear (1UL)
- #define PDM_INTENCLR_STOPPED_Pos (1UL)
- #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos)
- #define PDM_INTENCLR_STOPPED_Disabled (0UL)
- #define PDM_INTENCLR_STOPPED_Enabled (1UL)
- #define PDM_INTENCLR_STOPPED_Clear (1UL)
- #define PDM_INTENCLR_STARTED_Pos (0UL)
- #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos)
- #define PDM_INTENCLR_STARTED_Disabled (0UL)
- #define PDM_INTENCLR_STARTED_Enabled (1UL)
- #define PDM_INTENCLR_STARTED_Clear (1UL)
- #define PDM_ENABLE_ENABLE_Pos (0UL)
- #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos)
- #define PDM_ENABLE_ENABLE_Disabled (0UL)
- #define PDM_ENABLE_ENABLE_Enabled (1UL)
- #define PDM_PDMCLKCTRL_FREQ_Pos (0UL)
- #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos)
- #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL)
- #define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL)
- #define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL)
- #define PDM_PDMCLKCTRL_FREQ_1231K (0x09800000UL)
- #define PDM_PDMCLKCTRL_FREQ_1280K (0x0A000000UL)
- #define PDM_PDMCLKCTRL_FREQ_1333K (0x0A800000UL)
- #define PDM_MODE_EDGE_Pos (1UL)
- #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos)
- #define PDM_MODE_EDGE_LeftFalling (0UL)
- #define PDM_MODE_EDGE_LeftRising (1UL)
- #define PDM_MODE_OPERATION_Pos (0UL)
- #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos)
- #define PDM_MODE_OPERATION_Stereo (0UL)
- #define PDM_MODE_OPERATION_Mono (1UL)
- #define PDM_GAINL_GAINL_Pos (0UL)
- #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos)
- #define PDM_GAINL_GAINL_MinGain (0x00UL)
- #define PDM_GAINL_GAINL_DefaultGain (0x28UL)
- #define PDM_GAINL_GAINL_MaxGain (0x50UL)
- #define PDM_GAINR_GAINR_Pos (0UL)
- #define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos)
- #define PDM_GAINR_GAINR_MinGain (0x00UL)
- #define PDM_GAINR_GAINR_DefaultGain (0x28UL)
- #define PDM_GAINR_GAINR_MaxGain (0x50UL)
- #define PDM_RATIO_RATIO_Pos (0UL)
- #define PDM_RATIO_RATIO_Msk (0x1UL << PDM_RATIO_RATIO_Pos)
- #define PDM_RATIO_RATIO_Ratio64 (0UL)
- #define PDM_RATIO_RATIO_Ratio80 (1UL)
- #define PDM_PSEL_CLK_CONNECT_Pos (31UL)
- #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos)
- #define PDM_PSEL_CLK_CONNECT_Connected (0UL)
- #define PDM_PSEL_CLK_CONNECT_Disconnected (1UL)
- #define PDM_PSEL_CLK_PIN_Pos (0UL)
- #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos)
- #define PDM_PSEL_DIN_CONNECT_Pos (31UL)
- #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos)
- #define PDM_PSEL_DIN_CONNECT_Connected (0UL)
- #define PDM_PSEL_DIN_CONNECT_Disconnected (1UL)
- #define PDM_PSEL_DIN_PIN_Pos (0UL)
- #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos)
- #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL)
- #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos)
- #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL)
- #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos)
- #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL)
- #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos)
- #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL)
- #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL)
- #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos)
- #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL)
- #define POWER_SUBSCRIBE_CONSTLAT_EN_Pos (31UL)
- #define POWER_SUBSCRIBE_CONSTLAT_EN_Msk (0x1UL << POWER_SUBSCRIBE_CONSTLAT_EN_Pos)
- #define POWER_SUBSCRIBE_CONSTLAT_EN_Disabled (0UL)
- #define POWER_SUBSCRIBE_CONSTLAT_EN_Enabled (1UL)
- #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos (0UL)
- #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Msk (0xFUL << POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos)
- #define POWER_SUBSCRIBE_LOWPWR_EN_Pos (31UL)
- #define POWER_SUBSCRIBE_LOWPWR_EN_Msk (0x1UL << POWER_SUBSCRIBE_LOWPWR_EN_Pos)
- #define POWER_SUBSCRIBE_LOWPWR_EN_Disabled (0UL)
- #define POWER_SUBSCRIBE_LOWPWR_EN_Enabled (1UL)
- #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos (0UL)
- #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Msk (0xFUL << POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos)
- #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL)
- #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos)
- #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL)
- #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL)
- #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL)
- #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos)
- #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL)
- #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL)
- #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL)
- #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos)
- #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL)
- #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL)
- #define POWER_PUBLISH_POFWARN_EN_Pos (31UL)
- #define POWER_PUBLISH_POFWARN_EN_Msk (0x1UL << POWER_PUBLISH_POFWARN_EN_Pos)
- #define POWER_PUBLISH_POFWARN_EN_Disabled (0UL)
- #define POWER_PUBLISH_POFWARN_EN_Enabled (1UL)
- #define POWER_PUBLISH_POFWARN_CHIDX_Pos (0UL)
- #define POWER_PUBLISH_POFWARN_CHIDX_Msk (0xFUL << POWER_PUBLISH_POFWARN_CHIDX_Pos)
- #define POWER_PUBLISH_SLEEPENTER_EN_Pos (31UL)
- #define POWER_PUBLISH_SLEEPENTER_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPENTER_EN_Pos)
- #define POWER_PUBLISH_SLEEPENTER_EN_Disabled (0UL)
- #define POWER_PUBLISH_SLEEPENTER_EN_Enabled (1UL)
- #define POWER_PUBLISH_SLEEPENTER_CHIDX_Pos (0UL)
- #define POWER_PUBLISH_SLEEPENTER_CHIDX_Msk (0xFUL << POWER_PUBLISH_SLEEPENTER_CHIDX_Pos)
- #define POWER_PUBLISH_SLEEPEXIT_EN_Pos (31UL)
- #define POWER_PUBLISH_SLEEPEXIT_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPEXIT_EN_Pos)
- #define POWER_PUBLISH_SLEEPEXIT_EN_Disabled (0UL)
- #define POWER_PUBLISH_SLEEPEXIT_EN_Enabled (1UL)
- #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos (0UL)
- #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Msk (0xFUL << POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos)
- #define POWER_INTEN_SLEEPEXIT_Pos (6UL)
- #define POWER_INTEN_SLEEPEXIT_Msk (0x1UL << POWER_INTEN_SLEEPEXIT_Pos)
- #define POWER_INTEN_SLEEPEXIT_Disabled (0UL)
- #define POWER_INTEN_SLEEPEXIT_Enabled (1UL)
- #define POWER_INTEN_SLEEPENTER_Pos (5UL)
- #define POWER_INTEN_SLEEPENTER_Msk (0x1UL << POWER_INTEN_SLEEPENTER_Pos)
- #define POWER_INTEN_SLEEPENTER_Disabled (0UL)
- #define POWER_INTEN_SLEEPENTER_Enabled (1UL)
- #define POWER_INTEN_POFWARN_Pos (2UL)
- #define POWER_INTEN_POFWARN_Msk (0x1UL << POWER_INTEN_POFWARN_Pos)
- #define POWER_INTEN_POFWARN_Disabled (0UL)
- #define POWER_INTEN_POFWARN_Enabled (1UL)
- #define POWER_INTENSET_SLEEPEXIT_Pos (6UL)
- #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos)
- #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL)
- #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL)
- #define POWER_INTENSET_SLEEPEXIT_Set (1UL)
- #define POWER_INTENSET_SLEEPENTER_Pos (5UL)
- #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos)
- #define POWER_INTENSET_SLEEPENTER_Disabled (0UL)
- #define POWER_INTENSET_SLEEPENTER_Enabled (1UL)
- #define POWER_INTENSET_SLEEPENTER_Set (1UL)
- #define POWER_INTENSET_POFWARN_Pos (2UL)
- #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos)
- #define POWER_INTENSET_POFWARN_Disabled (0UL)
- #define POWER_INTENSET_POFWARN_Enabled (1UL)
- #define POWER_INTENSET_POFWARN_Set (1UL)
- #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL)
- #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos)
- #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL)
- #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL)
- #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL)
- #define POWER_INTENCLR_SLEEPENTER_Pos (5UL)
- #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos)
- #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL)
- #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL)
- #define POWER_INTENCLR_SLEEPENTER_Clear (1UL)
- #define POWER_INTENCLR_POFWARN_Pos (2UL)
- #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos)
- #define POWER_INTENCLR_POFWARN_Disabled (0UL)
- #define POWER_INTENCLR_POFWARN_Enabled (1UL)
- #define POWER_INTENCLR_POFWARN_Clear (1UL)
- #define POWER_RESETREAS_CTRLAP_Pos (18UL)
- #define POWER_RESETREAS_CTRLAP_Msk (0x1UL << POWER_RESETREAS_CTRLAP_Pos)
- #define POWER_RESETREAS_CTRLAP_NotDetected (0UL)
- #define POWER_RESETREAS_CTRLAP_Detected (1UL)
- #define POWER_RESETREAS_LOCKUP_Pos (17UL)
- #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos)
- #define POWER_RESETREAS_LOCKUP_NotDetected (0UL)
- #define POWER_RESETREAS_LOCKUP_Detected (1UL)
- #define POWER_RESETREAS_SREQ_Pos (16UL)
- #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos)
- #define POWER_RESETREAS_SREQ_NotDetected (0UL)
- #define POWER_RESETREAS_SREQ_Detected (1UL)
- #define POWER_RESETREAS_DIF_Pos (4UL)
- #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos)
- #define POWER_RESETREAS_DIF_NotDetected (0UL)
- #define POWER_RESETREAS_DIF_Detected (1UL)
- #define POWER_RESETREAS_OFF_Pos (2UL)
- #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos)
- #define POWER_RESETREAS_OFF_NotDetected (0UL)
- #define POWER_RESETREAS_OFF_Detected (1UL)
- #define POWER_RESETREAS_DOG_Pos (1UL)
- #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos)
- #define POWER_RESETREAS_DOG_NotDetected (0UL)
- #define POWER_RESETREAS_DOG_Detected (1UL)
- #define POWER_RESETREAS_RESETPIN_Pos (0UL)
- #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos)
- #define POWER_RESETREAS_RESETPIN_NotDetected (0UL)
- #define POWER_RESETREAS_RESETPIN_Detected (1UL)
- #define POWER_POWERSTATUS_LTEMODEM_Pos (0UL)
- #define POWER_POWERSTATUS_LTEMODEM_Msk (0x1UL << POWER_POWERSTATUS_LTEMODEM_Pos)
- #define POWER_POWERSTATUS_LTEMODEM_OFF (0UL)
- #define POWER_POWERSTATUS_LTEMODEM_ON (1UL)
- #define POWER_GPREGRET_GPREGRET_Pos (0UL)
- #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos)
- #define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos)
- #define PWM_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL)
- #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos)
- #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (1UL)
- #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL)
- #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos)
- #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (1UL)
- #define PWM_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define PWM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PWM_SUBSCRIBE_STOP_EN_Pos)
- #define PWM_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define PWM_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define PWM_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define PWM_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << PWM_SUBSCRIBE_STOP_CHIDX_Pos)
- #define PWM_SUBSCRIBE_SEQSTART_EN_Pos (31UL)
- #define PWM_SUBSCRIBE_SEQSTART_EN_Msk (0x1UL << PWM_SUBSCRIBE_SEQSTART_EN_Pos)
- #define PWM_SUBSCRIBE_SEQSTART_EN_Disabled (0UL)
- #define PWM_SUBSCRIBE_SEQSTART_EN_Enabled (1UL)
- #define PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos (0UL)
- #define PWM_SUBSCRIBE_SEQSTART_CHIDX_Msk (0xFUL << PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos)
- #define PWM_SUBSCRIBE_NEXTSTEP_EN_Pos (31UL)
- #define PWM_SUBSCRIBE_NEXTSTEP_EN_Msk (0x1UL << PWM_SUBSCRIBE_NEXTSTEP_EN_Pos)
- #define PWM_SUBSCRIBE_NEXTSTEP_EN_Disabled (0UL)
- #define PWM_SUBSCRIBE_NEXTSTEP_EN_Enabled (1UL)
- #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos (0UL)
- #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Msk (0xFUL << PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos)
- #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL)
- #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos)
- #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL)
- #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL)
- #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL)
- #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos)
- #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0UL)
- #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (1UL)
- #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL)
- #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos)
- #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0UL)
- #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (1UL)
- #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL)
- #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos)
- #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0UL)
- #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (1UL)
- #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL)
- #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos)
- #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0UL)
- #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (1UL)
- #define PWM_PUBLISH_STOPPED_EN_Pos (31UL)
- #define PWM_PUBLISH_STOPPED_EN_Msk (0x1UL << PWM_PUBLISH_STOPPED_EN_Pos)
- #define PWM_PUBLISH_STOPPED_EN_Disabled (0UL)
- #define PWM_PUBLISH_STOPPED_EN_Enabled (1UL)
- #define PWM_PUBLISH_STOPPED_CHIDX_Pos (0UL)
- #define PWM_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << PWM_PUBLISH_STOPPED_CHIDX_Pos)
- #define PWM_PUBLISH_SEQSTARTED_EN_Pos (31UL)
- #define PWM_PUBLISH_SEQSTARTED_EN_Msk (0x1UL << PWM_PUBLISH_SEQSTARTED_EN_Pos)
- #define PWM_PUBLISH_SEQSTARTED_EN_Disabled (0UL)
- #define PWM_PUBLISH_SEQSTARTED_EN_Enabled (1UL)
- #define PWM_PUBLISH_SEQSTARTED_CHIDX_Pos (0UL)
- #define PWM_PUBLISH_SEQSTARTED_CHIDX_Msk (0xFUL << PWM_PUBLISH_SEQSTARTED_CHIDX_Pos)
- #define PWM_PUBLISH_SEQEND_EN_Pos (31UL)
- #define PWM_PUBLISH_SEQEND_EN_Msk (0x1UL << PWM_PUBLISH_SEQEND_EN_Pos)
- #define PWM_PUBLISH_SEQEND_EN_Disabled (0UL)
- #define PWM_PUBLISH_SEQEND_EN_Enabled (1UL)
- #define PWM_PUBLISH_SEQEND_CHIDX_Pos (0UL)
- #define PWM_PUBLISH_SEQEND_CHIDX_Msk (0xFUL << PWM_PUBLISH_SEQEND_CHIDX_Pos)
- #define PWM_PUBLISH_PWMPERIODEND_EN_Pos (31UL)
- #define PWM_PUBLISH_PWMPERIODEND_EN_Msk (0x1UL << PWM_PUBLISH_PWMPERIODEND_EN_Pos)
- #define PWM_PUBLISH_PWMPERIODEND_EN_Disabled (0UL)
- #define PWM_PUBLISH_PWMPERIODEND_EN_Enabled (1UL)
- #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos (0UL)
- #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Msk (0xFUL << PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos)
- #define PWM_PUBLISH_LOOPSDONE_EN_Pos (31UL)
- #define PWM_PUBLISH_LOOPSDONE_EN_Msk (0x1UL << PWM_PUBLISH_LOOPSDONE_EN_Pos)
- #define PWM_PUBLISH_LOOPSDONE_EN_Disabled (0UL)
- #define PWM_PUBLISH_LOOPSDONE_EN_Enabled (1UL)
- #define PWM_PUBLISH_LOOPSDONE_CHIDX_Pos (0UL)
- #define PWM_PUBLISH_LOOPSDONE_CHIDX_Msk (0xFUL << PWM_PUBLISH_LOOPSDONE_CHIDX_Pos)
- #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL)
- #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos)
- #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL)
- #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL)
- #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL)
- #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos)
- #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL)
- #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL)
- #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL)
- #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos)
- #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL)
- #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL)
- #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL)
- #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos)
- #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL)
- #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL)
- #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL)
- #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos)
- #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL)
- #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL)
- #define PWM_INTEN_LOOPSDONE_Pos (7UL)
- #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos)
- #define PWM_INTEN_LOOPSDONE_Disabled (0UL)
- #define PWM_INTEN_LOOPSDONE_Enabled (1UL)
- #define PWM_INTEN_PWMPERIODEND_Pos (6UL)
- #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos)
- #define PWM_INTEN_PWMPERIODEND_Disabled (0UL)
- #define PWM_INTEN_PWMPERIODEND_Enabled (1UL)
- #define PWM_INTEN_SEQEND1_Pos (5UL)
- #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos)
- #define PWM_INTEN_SEQEND1_Disabled (0UL)
- #define PWM_INTEN_SEQEND1_Enabled (1UL)
- #define PWM_INTEN_SEQEND0_Pos (4UL)
- #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos)
- #define PWM_INTEN_SEQEND0_Disabled (0UL)
- #define PWM_INTEN_SEQEND0_Enabled (1UL)
- #define PWM_INTEN_SEQSTARTED1_Pos (3UL)
- #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos)
- #define PWM_INTEN_SEQSTARTED1_Disabled (0UL)
- #define PWM_INTEN_SEQSTARTED1_Enabled (1UL)
- #define PWM_INTEN_SEQSTARTED0_Pos (2UL)
- #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos)
- #define PWM_INTEN_SEQSTARTED0_Disabled (0UL)
- #define PWM_INTEN_SEQSTARTED0_Enabled (1UL)
- #define PWM_INTEN_STOPPED_Pos (1UL)
- #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos)
- #define PWM_INTEN_STOPPED_Disabled (0UL)
- #define PWM_INTEN_STOPPED_Enabled (1UL)
- #define PWM_INTENSET_LOOPSDONE_Pos (7UL)
- #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos)
- #define PWM_INTENSET_LOOPSDONE_Disabled (0UL)
- #define PWM_INTENSET_LOOPSDONE_Enabled (1UL)
- #define PWM_INTENSET_LOOPSDONE_Set (1UL)
- #define PWM_INTENSET_PWMPERIODEND_Pos (6UL)
- #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos)
- #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL)
- #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL)
- #define PWM_INTENSET_PWMPERIODEND_Set (1UL)
- #define PWM_INTENSET_SEQEND1_Pos (5UL)
- #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos)
- #define PWM_INTENSET_SEQEND1_Disabled (0UL)
- #define PWM_INTENSET_SEQEND1_Enabled (1UL)
- #define PWM_INTENSET_SEQEND1_Set (1UL)
- #define PWM_INTENSET_SEQEND0_Pos (4UL)
- #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos)
- #define PWM_INTENSET_SEQEND0_Disabled (0UL)
- #define PWM_INTENSET_SEQEND0_Enabled (1UL)
- #define PWM_INTENSET_SEQEND0_Set (1UL)
- #define PWM_INTENSET_SEQSTARTED1_Pos (3UL)
- #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos)
- #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL)
- #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL)
- #define PWM_INTENSET_SEQSTARTED1_Set (1UL)
- #define PWM_INTENSET_SEQSTARTED0_Pos (2UL)
- #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos)
- #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL)
- #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL)
- #define PWM_INTENSET_SEQSTARTED0_Set (1UL)
- #define PWM_INTENSET_STOPPED_Pos (1UL)
- #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos)
- #define PWM_INTENSET_STOPPED_Disabled (0UL)
- #define PWM_INTENSET_STOPPED_Enabled (1UL)
- #define PWM_INTENSET_STOPPED_Set (1UL)
- #define PWM_INTENCLR_LOOPSDONE_Pos (7UL)
- #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos)
- #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL)
- #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL)
- #define PWM_INTENCLR_LOOPSDONE_Clear (1UL)
- #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL)
- #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos)
- #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL)
- #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL)
- #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL)
- #define PWM_INTENCLR_SEQEND1_Pos (5UL)
- #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos)
- #define PWM_INTENCLR_SEQEND1_Disabled (0UL)
- #define PWM_INTENCLR_SEQEND1_Enabled (1UL)
- #define PWM_INTENCLR_SEQEND1_Clear (1UL)
- #define PWM_INTENCLR_SEQEND0_Pos (4UL)
- #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos)
- #define PWM_INTENCLR_SEQEND0_Disabled (0UL)
- #define PWM_INTENCLR_SEQEND0_Enabled (1UL)
- #define PWM_INTENCLR_SEQEND0_Clear (1UL)
- #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL)
- #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos)
- #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL)
- #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL)
- #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL)
- #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL)
- #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos)
- #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL)
- #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL)
- #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL)
- #define PWM_INTENCLR_STOPPED_Pos (1UL)
- #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos)
- #define PWM_INTENCLR_STOPPED_Disabled (0UL)
- #define PWM_INTENCLR_STOPPED_Enabled (1UL)
- #define PWM_INTENCLR_STOPPED_Clear (1UL)
- #define PWM_ENABLE_ENABLE_Pos (0UL)
- #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos)
- #define PWM_ENABLE_ENABLE_Disabled (0UL)
- #define PWM_ENABLE_ENABLE_Enabled (1UL)
- #define PWM_MODE_UPDOWN_Pos (0UL)
- #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos)
- #define PWM_MODE_UPDOWN_Up (0UL)
- #define PWM_MODE_UPDOWN_UpAndDown (1UL)
- #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL)
- #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos)
- #define PWM_PRESCALER_PRESCALER_Pos (0UL)
- #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos)
- #define PWM_PRESCALER_PRESCALER_DIV_1 (0UL)
- #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL)
- #define PWM_PRESCALER_PRESCALER_DIV_4 (2UL)
- #define PWM_PRESCALER_PRESCALER_DIV_8 (3UL)
- #define PWM_PRESCALER_PRESCALER_DIV_16 (4UL)
- #define PWM_PRESCALER_PRESCALER_DIV_32 (5UL)
- #define PWM_PRESCALER_PRESCALER_DIV_64 (6UL)
- #define PWM_PRESCALER_PRESCALER_DIV_128 (7UL)
- #define PWM_DECODER_MODE_Pos (8UL)
- #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos)
- #define PWM_DECODER_MODE_RefreshCount (0UL)
- #define PWM_DECODER_MODE_NextStep (1UL)
- #define PWM_DECODER_LOAD_Pos (0UL)
- #define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos)
- #define PWM_DECODER_LOAD_Common (0UL)
- #define PWM_DECODER_LOAD_Grouped (1UL)
- #define PWM_DECODER_LOAD_Individual (2UL)
- #define PWM_DECODER_LOAD_WaveForm (3UL)
- #define PWM_LOOP_CNT_Pos (0UL)
- #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos)
- #define PWM_LOOP_CNT_Disabled (0UL)
- #define PWM_SEQ_PTR_PTR_Pos (0UL)
- #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos)
- #define PWM_SEQ_CNT_CNT_Pos (0UL)
- #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos)
- #define PWM_SEQ_CNT_CNT_Disabled (0UL)
- #define PWM_SEQ_REFRESH_CNT_Pos (0UL)
- #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos)
- #define PWM_SEQ_REFRESH_CNT_Continuous (0UL)
- #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL)
- #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos)
- #define PWM_PSEL_OUT_CONNECT_Pos (31UL)
- #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos)
- #define PWM_PSEL_OUT_CONNECT_Connected (0UL)
- #define PWM_PSEL_OUT_CONNECT_Disconnected (1UL)
- #define PWM_PSEL_OUT_PIN_Pos (0UL)
- #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos)
- #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos (0UL)
- #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos)
- #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Enable (1UL)
- #define REGULATORS_DCDCEN_DCDCEN_Pos (0UL)
- #define REGULATORS_DCDCEN_DCDCEN_Msk (0x1UL << REGULATORS_DCDCEN_DCDCEN_Pos)
- #define REGULATORS_DCDCEN_DCDCEN_Disabled (0UL)
- #define REGULATORS_DCDCEN_DCDCEN_Enabled (1UL)
- #define RTC_TASKS_START_TASKS_START_Pos (0UL)
- #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos)
- #define RTC_TASKS_START_TASKS_START_Trigger (1UL)
- #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos)
- #define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL)
- #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos)
- #define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL)
- #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL)
- #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos)
- #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL)
- #define RTC_SUBSCRIBE_START_EN_Pos (31UL)
- #define RTC_SUBSCRIBE_START_EN_Msk (0x1UL << RTC_SUBSCRIBE_START_EN_Pos)
- #define RTC_SUBSCRIBE_START_EN_Disabled (0UL)
- #define RTC_SUBSCRIBE_START_EN_Enabled (1UL)
- #define RTC_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define RTC_SUBSCRIBE_START_CHIDX_Msk (0xFUL << RTC_SUBSCRIBE_START_CHIDX_Pos)
- #define RTC_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define RTC_SUBSCRIBE_STOP_EN_Msk (0x1UL << RTC_SUBSCRIBE_STOP_EN_Pos)
- #define RTC_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define RTC_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define RTC_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define RTC_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << RTC_SUBSCRIBE_STOP_CHIDX_Pos)
- #define RTC_SUBSCRIBE_CLEAR_EN_Pos (31UL)
- #define RTC_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << RTC_SUBSCRIBE_CLEAR_EN_Pos)
- #define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0UL)
- #define RTC_SUBSCRIBE_CLEAR_EN_Enabled (1UL)
- #define RTC_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL)
- #define RTC_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFUL << RTC_SUBSCRIBE_CLEAR_CHIDX_Pos)
- #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos (31UL)
- #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Msk (0x1UL << RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos)
- #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0UL)
- #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (1UL)
- #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos (0UL)
- #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Msk (0xFUL << RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos)
- #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL)
- #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos)
- #define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL)
- #define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL)
- #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL)
- #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos)
- #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL)
- #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL)
- #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL)
- #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos)
- #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL)
- #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL)
- #define RTC_PUBLISH_TICK_EN_Pos (31UL)
- #define RTC_PUBLISH_TICK_EN_Msk (0x1UL << RTC_PUBLISH_TICK_EN_Pos)
- #define RTC_PUBLISH_TICK_EN_Disabled (0UL)
- #define RTC_PUBLISH_TICK_EN_Enabled (1UL)
- #define RTC_PUBLISH_TICK_CHIDX_Pos (0UL)
- #define RTC_PUBLISH_TICK_CHIDX_Msk (0xFUL << RTC_PUBLISH_TICK_CHIDX_Pos)
- #define RTC_PUBLISH_OVRFLW_EN_Pos (31UL)
- #define RTC_PUBLISH_OVRFLW_EN_Msk (0x1UL << RTC_PUBLISH_OVRFLW_EN_Pos)
- #define RTC_PUBLISH_OVRFLW_EN_Disabled (0UL)
- #define RTC_PUBLISH_OVRFLW_EN_Enabled (1UL)
- #define RTC_PUBLISH_OVRFLW_CHIDX_Pos (0UL)
- #define RTC_PUBLISH_OVRFLW_CHIDX_Msk (0xFUL << RTC_PUBLISH_OVRFLW_CHIDX_Pos)
- #define RTC_PUBLISH_COMPARE_EN_Pos (31UL)
- #define RTC_PUBLISH_COMPARE_EN_Msk (0x1UL << RTC_PUBLISH_COMPARE_EN_Pos)
- #define RTC_PUBLISH_COMPARE_EN_Disabled (0UL)
- #define RTC_PUBLISH_COMPARE_EN_Enabled (1UL)
- #define RTC_PUBLISH_COMPARE_CHIDX_Pos (0UL)
- #define RTC_PUBLISH_COMPARE_CHIDX_Msk (0xFUL << RTC_PUBLISH_COMPARE_CHIDX_Pos)
- #define RTC_INTENSET_COMPARE3_Pos (19UL)
- #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos)
- #define RTC_INTENSET_COMPARE3_Disabled (0UL)
- #define RTC_INTENSET_COMPARE3_Enabled (1UL)
- #define RTC_INTENSET_COMPARE3_Set (1UL)
- #define RTC_INTENSET_COMPARE2_Pos (18UL)
- #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos)
- #define RTC_INTENSET_COMPARE2_Disabled (0UL)
- #define RTC_INTENSET_COMPARE2_Enabled (1UL)
- #define RTC_INTENSET_COMPARE2_Set (1UL)
- #define RTC_INTENSET_COMPARE1_Pos (17UL)
- #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos)
- #define RTC_INTENSET_COMPARE1_Disabled (0UL)
- #define RTC_INTENSET_COMPARE1_Enabled (1UL)
- #define RTC_INTENSET_COMPARE1_Set (1UL)
- #define RTC_INTENSET_COMPARE0_Pos (16UL)
- #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos)
- #define RTC_INTENSET_COMPARE0_Disabled (0UL)
- #define RTC_INTENSET_COMPARE0_Enabled (1UL)
- #define RTC_INTENSET_COMPARE0_Set (1UL)
- #define RTC_INTENSET_OVRFLW_Pos (1UL)
- #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos)
- #define RTC_INTENSET_OVRFLW_Disabled (0UL)
- #define RTC_INTENSET_OVRFLW_Enabled (1UL)
- #define RTC_INTENSET_OVRFLW_Set (1UL)
- #define RTC_INTENSET_TICK_Pos (0UL)
- #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos)
- #define RTC_INTENSET_TICK_Disabled (0UL)
- #define RTC_INTENSET_TICK_Enabled (1UL)
- #define RTC_INTENSET_TICK_Set (1UL)
- #define RTC_INTENCLR_COMPARE3_Pos (19UL)
- #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos)
- #define RTC_INTENCLR_COMPARE3_Disabled (0UL)
- #define RTC_INTENCLR_COMPARE3_Enabled (1UL)
- #define RTC_INTENCLR_COMPARE3_Clear (1UL)
- #define RTC_INTENCLR_COMPARE2_Pos (18UL)
- #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos)
- #define RTC_INTENCLR_COMPARE2_Disabled (0UL)
- #define RTC_INTENCLR_COMPARE2_Enabled (1UL)
- #define RTC_INTENCLR_COMPARE2_Clear (1UL)
- #define RTC_INTENCLR_COMPARE1_Pos (17UL)
- #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos)
- #define RTC_INTENCLR_COMPARE1_Disabled (0UL)
- #define RTC_INTENCLR_COMPARE1_Enabled (1UL)
- #define RTC_INTENCLR_COMPARE1_Clear (1UL)
- #define RTC_INTENCLR_COMPARE0_Pos (16UL)
- #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos)
- #define RTC_INTENCLR_COMPARE0_Disabled (0UL)
- #define RTC_INTENCLR_COMPARE0_Enabled (1UL)
- #define RTC_INTENCLR_COMPARE0_Clear (1UL)
- #define RTC_INTENCLR_OVRFLW_Pos (1UL)
- #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos)
- #define RTC_INTENCLR_OVRFLW_Disabled (0UL)
- #define RTC_INTENCLR_OVRFLW_Enabled (1UL)
- #define RTC_INTENCLR_OVRFLW_Clear (1UL)
- #define RTC_INTENCLR_TICK_Pos (0UL)
- #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos)
- #define RTC_INTENCLR_TICK_Disabled (0UL)
- #define RTC_INTENCLR_TICK_Enabled (1UL)
- #define RTC_INTENCLR_TICK_Clear (1UL)
- #define RTC_EVTEN_COMPARE3_Pos (19UL)
- #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos)
- #define RTC_EVTEN_COMPARE3_Disabled (0UL)
- #define RTC_EVTEN_COMPARE3_Enabled (1UL)
- #define RTC_EVTEN_COMPARE2_Pos (18UL)
- #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos)
- #define RTC_EVTEN_COMPARE2_Disabled (0UL)
- #define RTC_EVTEN_COMPARE2_Enabled (1UL)
- #define RTC_EVTEN_COMPARE1_Pos (17UL)
- #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos)
- #define RTC_EVTEN_COMPARE1_Disabled (0UL)
- #define RTC_EVTEN_COMPARE1_Enabled (1UL)
- #define RTC_EVTEN_COMPARE0_Pos (16UL)
- #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos)
- #define RTC_EVTEN_COMPARE0_Disabled (0UL)
- #define RTC_EVTEN_COMPARE0_Enabled (1UL)
- #define RTC_EVTEN_OVRFLW_Pos (1UL)
- #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos)
- #define RTC_EVTEN_OVRFLW_Disabled (0UL)
- #define RTC_EVTEN_OVRFLW_Enabled (1UL)
- #define RTC_EVTEN_TICK_Pos (0UL)
- #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos)
- #define RTC_EVTEN_TICK_Disabled (0UL)
- #define RTC_EVTEN_TICK_Enabled (1UL)
- #define RTC_EVTENSET_COMPARE3_Pos (19UL)
- #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos)
- #define RTC_EVTENSET_COMPARE3_Disabled (0UL)
- #define RTC_EVTENSET_COMPARE3_Enabled (1UL)
- #define RTC_EVTENSET_COMPARE3_Set (1UL)
- #define RTC_EVTENSET_COMPARE2_Pos (18UL)
- #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos)
- #define RTC_EVTENSET_COMPARE2_Disabled (0UL)
- #define RTC_EVTENSET_COMPARE2_Enabled (1UL)
- #define RTC_EVTENSET_COMPARE2_Set (1UL)
- #define RTC_EVTENSET_COMPARE1_Pos (17UL)
- #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos)
- #define RTC_EVTENSET_COMPARE1_Disabled (0UL)
- #define RTC_EVTENSET_COMPARE1_Enabled (1UL)
- #define RTC_EVTENSET_COMPARE1_Set (1UL)
- #define RTC_EVTENSET_COMPARE0_Pos (16UL)
- #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos)
- #define RTC_EVTENSET_COMPARE0_Disabled (0UL)
- #define RTC_EVTENSET_COMPARE0_Enabled (1UL)
- #define RTC_EVTENSET_COMPARE0_Set (1UL)
- #define RTC_EVTENSET_OVRFLW_Pos (1UL)
- #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos)
- #define RTC_EVTENSET_OVRFLW_Disabled (0UL)
- #define RTC_EVTENSET_OVRFLW_Enabled (1UL)
- #define RTC_EVTENSET_OVRFLW_Set (1UL)
- #define RTC_EVTENSET_TICK_Pos (0UL)
- #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos)
- #define RTC_EVTENSET_TICK_Disabled (0UL)
- #define RTC_EVTENSET_TICK_Enabled (1UL)
- #define RTC_EVTENSET_TICK_Set (1UL)
- #define RTC_EVTENCLR_COMPARE3_Pos (19UL)
- #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos)
- #define RTC_EVTENCLR_COMPARE3_Disabled (0UL)
- #define RTC_EVTENCLR_COMPARE3_Enabled (1UL)
- #define RTC_EVTENCLR_COMPARE3_Clear (1UL)
- #define RTC_EVTENCLR_COMPARE2_Pos (18UL)
- #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos)
- #define RTC_EVTENCLR_COMPARE2_Disabled (0UL)
- #define RTC_EVTENCLR_COMPARE2_Enabled (1UL)
- #define RTC_EVTENCLR_COMPARE2_Clear (1UL)
- #define RTC_EVTENCLR_COMPARE1_Pos (17UL)
- #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos)
- #define RTC_EVTENCLR_COMPARE1_Disabled (0UL)
- #define RTC_EVTENCLR_COMPARE1_Enabled (1UL)
- #define RTC_EVTENCLR_COMPARE1_Clear (1UL)
- #define RTC_EVTENCLR_COMPARE0_Pos (16UL)
- #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos)
- #define RTC_EVTENCLR_COMPARE0_Disabled (0UL)
- #define RTC_EVTENCLR_COMPARE0_Enabled (1UL)
- #define RTC_EVTENCLR_COMPARE0_Clear (1UL)
- #define RTC_EVTENCLR_OVRFLW_Pos (1UL)
- #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos)
- #define RTC_EVTENCLR_OVRFLW_Disabled (0UL)
- #define RTC_EVTENCLR_OVRFLW_Enabled (1UL)
- #define RTC_EVTENCLR_OVRFLW_Clear (1UL)
- #define RTC_EVTENCLR_TICK_Pos (0UL)
- #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos)
- #define RTC_EVTENCLR_TICK_Disabled (0UL)
- #define RTC_EVTENCLR_TICK_Enabled (1UL)
- #define RTC_EVTENCLR_TICK_Clear (1UL)
- #define RTC_COUNTER_COUNTER_Pos (0UL)
- #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos)
- #define RTC_PRESCALER_PRESCALER_Pos (0UL)
- #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos)
- #define RTC_CC_COMPARE_Pos (0UL)
- #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos)
- #define SAADC_TASKS_START_TASKS_START_Pos (0UL)
- #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos)
- #define SAADC_TASKS_START_TASKS_START_Trigger (1UL)
- #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL)
- #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos)
- #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL)
- #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos)
- #define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL)
- #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos)
- #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL)
- #define SAADC_SUBSCRIBE_START_EN_Pos (31UL)
- #define SAADC_SUBSCRIBE_START_EN_Msk (0x1UL << SAADC_SUBSCRIBE_START_EN_Pos)
- #define SAADC_SUBSCRIBE_START_EN_Disabled (0UL)
- #define SAADC_SUBSCRIBE_START_EN_Enabled (1UL)
- #define SAADC_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define SAADC_SUBSCRIBE_START_CHIDX_Msk (0xFUL << SAADC_SUBSCRIBE_START_CHIDX_Pos)
- #define SAADC_SUBSCRIBE_SAMPLE_EN_Pos (31UL)
- #define SAADC_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << SAADC_SUBSCRIBE_SAMPLE_EN_Pos)
- #define SAADC_SUBSCRIBE_SAMPLE_EN_Disabled (0UL)
- #define SAADC_SUBSCRIBE_SAMPLE_EN_Enabled (1UL)
- #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL)
- #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFUL << SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos)
- #define SAADC_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define SAADC_SUBSCRIBE_STOP_EN_Msk (0x1UL << SAADC_SUBSCRIBE_STOP_EN_Pos)
- #define SAADC_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define SAADC_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define SAADC_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define SAADC_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << SAADC_SUBSCRIBE_STOP_CHIDX_Pos)
- #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos (31UL)
- #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Msk (0x1UL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos)
- #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Disabled (0UL)
- #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Enabled (1UL)
- #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos (0UL)
- #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Msk (0xFUL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos)
- #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL)
- #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos)
- #define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL)
- #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL)
- #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL)
- #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos)
- #define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL)
- #define SAADC_EVENTS_END_EVENTS_END_Generated (1UL)
- #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL)
- #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos)
- #define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL)
- #define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL)
- #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL)
- #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos)
- #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL)
- #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL)
- #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL)
- #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos)
- #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL)
- #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL)
- #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL)
- #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos)
- #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL)
- #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL)
- #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL)
- #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos)
- #define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL)
- #define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL)
- #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL)
- #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos)
- #define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL)
- #define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL)
- #define SAADC_PUBLISH_STARTED_EN_Pos (31UL)
- #define SAADC_PUBLISH_STARTED_EN_Msk (0x1UL << SAADC_PUBLISH_STARTED_EN_Pos)
- #define SAADC_PUBLISH_STARTED_EN_Disabled (0UL)
- #define SAADC_PUBLISH_STARTED_EN_Enabled (1UL)
- #define SAADC_PUBLISH_STARTED_CHIDX_Pos (0UL)
- #define SAADC_PUBLISH_STARTED_CHIDX_Msk (0xFUL << SAADC_PUBLISH_STARTED_CHIDX_Pos)
- #define SAADC_PUBLISH_END_EN_Pos (31UL)
- #define SAADC_PUBLISH_END_EN_Msk (0x1UL << SAADC_PUBLISH_END_EN_Pos)
- #define SAADC_PUBLISH_END_EN_Disabled (0UL)
- #define SAADC_PUBLISH_END_EN_Enabled (1UL)
- #define SAADC_PUBLISH_END_CHIDX_Pos (0UL)
- #define SAADC_PUBLISH_END_CHIDX_Msk (0xFUL << SAADC_PUBLISH_END_CHIDX_Pos)
- #define SAADC_PUBLISH_DONE_EN_Pos (31UL)
- #define SAADC_PUBLISH_DONE_EN_Msk (0x1UL << SAADC_PUBLISH_DONE_EN_Pos)
- #define SAADC_PUBLISH_DONE_EN_Disabled (0UL)
- #define SAADC_PUBLISH_DONE_EN_Enabled (1UL)
- #define SAADC_PUBLISH_DONE_CHIDX_Pos (0UL)
- #define SAADC_PUBLISH_DONE_CHIDX_Msk (0xFUL << SAADC_PUBLISH_DONE_CHIDX_Pos)
- #define SAADC_PUBLISH_RESULTDONE_EN_Pos (31UL)
- #define SAADC_PUBLISH_RESULTDONE_EN_Msk (0x1UL << SAADC_PUBLISH_RESULTDONE_EN_Pos)
- #define SAADC_PUBLISH_RESULTDONE_EN_Disabled (0UL)
- #define SAADC_PUBLISH_RESULTDONE_EN_Enabled (1UL)
- #define SAADC_PUBLISH_RESULTDONE_CHIDX_Pos (0UL)
- #define SAADC_PUBLISH_RESULTDONE_CHIDX_Msk (0xFUL << SAADC_PUBLISH_RESULTDONE_CHIDX_Pos)
- #define SAADC_PUBLISH_CALIBRATEDONE_EN_Pos (31UL)
- #define SAADC_PUBLISH_CALIBRATEDONE_EN_Msk (0x1UL << SAADC_PUBLISH_CALIBRATEDONE_EN_Pos)
- #define SAADC_PUBLISH_CALIBRATEDONE_EN_Disabled (0UL)
- #define SAADC_PUBLISH_CALIBRATEDONE_EN_Enabled (1UL)
- #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos (0UL)
- #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Msk (0xFUL << SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos)
- #define SAADC_PUBLISH_STOPPED_EN_Pos (31UL)
- #define SAADC_PUBLISH_STOPPED_EN_Msk (0x1UL << SAADC_PUBLISH_STOPPED_EN_Pos)
- #define SAADC_PUBLISH_STOPPED_EN_Disabled (0UL)
- #define SAADC_PUBLISH_STOPPED_EN_Enabled (1UL)
- #define SAADC_PUBLISH_STOPPED_CHIDX_Pos (0UL)
- #define SAADC_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << SAADC_PUBLISH_STOPPED_CHIDX_Pos)
- #define SAADC_PUBLISH_CH_LIMITH_EN_Pos (31UL)
- #define SAADC_PUBLISH_CH_LIMITH_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITH_EN_Pos)
- #define SAADC_PUBLISH_CH_LIMITH_EN_Disabled (0UL)
- #define SAADC_PUBLISH_CH_LIMITH_EN_Enabled (1UL)
- #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos (0UL)
- #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Msk (0xFUL << SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos)
- #define SAADC_PUBLISH_CH_LIMITL_EN_Pos (31UL)
- #define SAADC_PUBLISH_CH_LIMITL_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITL_EN_Pos)
- #define SAADC_PUBLISH_CH_LIMITL_EN_Disabled (0UL)
- #define SAADC_PUBLISH_CH_LIMITL_EN_Enabled (1UL)
- #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos (0UL)
- #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Msk (0xFUL << SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos)
- #define SAADC_INTEN_CH7LIMITL_Pos (21UL)
- #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos)
- #define SAADC_INTEN_CH7LIMITL_Disabled (0UL)
- #define SAADC_INTEN_CH7LIMITL_Enabled (1UL)
- #define SAADC_INTEN_CH7LIMITH_Pos (20UL)
- #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos)
- #define SAADC_INTEN_CH7LIMITH_Disabled (0UL)
- #define SAADC_INTEN_CH7LIMITH_Enabled (1UL)
- #define SAADC_INTEN_CH6LIMITL_Pos (19UL)
- #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos)
- #define SAADC_INTEN_CH6LIMITL_Disabled (0UL)
- #define SAADC_INTEN_CH6LIMITL_Enabled (1UL)
- #define SAADC_INTEN_CH6LIMITH_Pos (18UL)
- #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos)
- #define SAADC_INTEN_CH6LIMITH_Disabled (0UL)
- #define SAADC_INTEN_CH6LIMITH_Enabled (1UL)
- #define SAADC_INTEN_CH5LIMITL_Pos (17UL)
- #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos)
- #define SAADC_INTEN_CH5LIMITL_Disabled (0UL)
- #define SAADC_INTEN_CH5LIMITL_Enabled (1UL)
- #define SAADC_INTEN_CH5LIMITH_Pos (16UL)
- #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos)
- #define SAADC_INTEN_CH5LIMITH_Disabled (0UL)
- #define SAADC_INTEN_CH5LIMITH_Enabled (1UL)
- #define SAADC_INTEN_CH4LIMITL_Pos (15UL)
- #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos)
- #define SAADC_INTEN_CH4LIMITL_Disabled (0UL)
- #define SAADC_INTEN_CH4LIMITL_Enabled (1UL)
- #define SAADC_INTEN_CH4LIMITH_Pos (14UL)
- #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos)
- #define SAADC_INTEN_CH4LIMITH_Disabled (0UL)
- #define SAADC_INTEN_CH4LIMITH_Enabled (1UL)
- #define SAADC_INTEN_CH3LIMITL_Pos (13UL)
- #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos)
- #define SAADC_INTEN_CH3LIMITL_Disabled (0UL)
- #define SAADC_INTEN_CH3LIMITL_Enabled (1UL)
- #define SAADC_INTEN_CH3LIMITH_Pos (12UL)
- #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos)
- #define SAADC_INTEN_CH3LIMITH_Disabled (0UL)
- #define SAADC_INTEN_CH3LIMITH_Enabled (1UL)
- #define SAADC_INTEN_CH2LIMITL_Pos (11UL)
- #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos)
- #define SAADC_INTEN_CH2LIMITL_Disabled (0UL)
- #define SAADC_INTEN_CH2LIMITL_Enabled (1UL)
- #define SAADC_INTEN_CH2LIMITH_Pos (10UL)
- #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos)
- #define SAADC_INTEN_CH2LIMITH_Disabled (0UL)
- #define SAADC_INTEN_CH2LIMITH_Enabled (1UL)
- #define SAADC_INTEN_CH1LIMITL_Pos (9UL)
- #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos)
- #define SAADC_INTEN_CH1LIMITL_Disabled (0UL)
- #define SAADC_INTEN_CH1LIMITL_Enabled (1UL)
- #define SAADC_INTEN_CH1LIMITH_Pos (8UL)
- #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos)
- #define SAADC_INTEN_CH1LIMITH_Disabled (0UL)
- #define SAADC_INTEN_CH1LIMITH_Enabled (1UL)
- #define SAADC_INTEN_CH0LIMITL_Pos (7UL)
- #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos)
- #define SAADC_INTEN_CH0LIMITL_Disabled (0UL)
- #define SAADC_INTEN_CH0LIMITL_Enabled (1UL)
- #define SAADC_INTEN_CH0LIMITH_Pos (6UL)
- #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos)
- #define SAADC_INTEN_CH0LIMITH_Disabled (0UL)
- #define SAADC_INTEN_CH0LIMITH_Enabled (1UL)
- #define SAADC_INTEN_STOPPED_Pos (5UL)
- #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos)
- #define SAADC_INTEN_STOPPED_Disabled (0UL)
- #define SAADC_INTEN_STOPPED_Enabled (1UL)
- #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL)
- #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos)
- #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL)
- #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL)
- #define SAADC_INTEN_RESULTDONE_Pos (3UL)
- #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos)
- #define SAADC_INTEN_RESULTDONE_Disabled (0UL)
- #define SAADC_INTEN_RESULTDONE_Enabled (1UL)
- #define SAADC_INTEN_DONE_Pos (2UL)
- #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos)
- #define SAADC_INTEN_DONE_Disabled (0UL)
- #define SAADC_INTEN_DONE_Enabled (1UL)
- #define SAADC_INTEN_END_Pos (1UL)
- #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos)
- #define SAADC_INTEN_END_Disabled (0UL)
- #define SAADC_INTEN_END_Enabled (1UL)
- #define SAADC_INTEN_STARTED_Pos (0UL)
- #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos)
- #define SAADC_INTEN_STARTED_Disabled (0UL)
- #define SAADC_INTEN_STARTED_Enabled (1UL)
- #define SAADC_INTENSET_CH7LIMITL_Pos (21UL)
- #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos)
- #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL)
- #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL)
- #define SAADC_INTENSET_CH7LIMITL_Set (1UL)
- #define SAADC_INTENSET_CH7LIMITH_Pos (20UL)
- #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos)
- #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL)
- #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL)
- #define SAADC_INTENSET_CH7LIMITH_Set (1UL)
- #define SAADC_INTENSET_CH6LIMITL_Pos (19UL)
- #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos)
- #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL)
- #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL)
- #define SAADC_INTENSET_CH6LIMITL_Set (1UL)
- #define SAADC_INTENSET_CH6LIMITH_Pos (18UL)
- #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos)
- #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL)
- #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL)
- #define SAADC_INTENSET_CH6LIMITH_Set (1UL)
- #define SAADC_INTENSET_CH5LIMITL_Pos (17UL)
- #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos)
- #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL)
- #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL)
- #define SAADC_INTENSET_CH5LIMITL_Set (1UL)
- #define SAADC_INTENSET_CH5LIMITH_Pos (16UL)
- #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos)
- #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL)
- #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL)
- #define SAADC_INTENSET_CH5LIMITH_Set (1UL)
- #define SAADC_INTENSET_CH4LIMITL_Pos (15UL)
- #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos)
- #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL)
- #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL)
- #define SAADC_INTENSET_CH4LIMITL_Set (1UL)
- #define SAADC_INTENSET_CH4LIMITH_Pos (14UL)
- #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos)
- #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL)
- #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL)
- #define SAADC_INTENSET_CH4LIMITH_Set (1UL)
- #define SAADC_INTENSET_CH3LIMITL_Pos (13UL)
- #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos)
- #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL)
- #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL)
- #define SAADC_INTENSET_CH3LIMITL_Set (1UL)
- #define SAADC_INTENSET_CH3LIMITH_Pos (12UL)
- #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos)
- #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL)
- #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL)
- #define SAADC_INTENSET_CH3LIMITH_Set (1UL)
- #define SAADC_INTENSET_CH2LIMITL_Pos (11UL)
- #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos)
- #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL)
- #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL)
- #define SAADC_INTENSET_CH2LIMITL_Set (1UL)
- #define SAADC_INTENSET_CH2LIMITH_Pos (10UL)
- #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos)
- #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL)
- #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL)
- #define SAADC_INTENSET_CH2LIMITH_Set (1UL)
- #define SAADC_INTENSET_CH1LIMITL_Pos (9UL)
- #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos)
- #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL)
- #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL)
- #define SAADC_INTENSET_CH1LIMITL_Set (1UL)
- #define SAADC_INTENSET_CH1LIMITH_Pos (8UL)
- #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos)
- #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL)
- #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL)
- #define SAADC_INTENSET_CH1LIMITH_Set (1UL)
- #define SAADC_INTENSET_CH0LIMITL_Pos (7UL)
- #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos)
- #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL)
- #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL)
- #define SAADC_INTENSET_CH0LIMITL_Set (1UL)
- #define SAADC_INTENSET_CH0LIMITH_Pos (6UL)
- #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos)
- #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL)
- #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL)
- #define SAADC_INTENSET_CH0LIMITH_Set (1UL)
- #define SAADC_INTENSET_STOPPED_Pos (5UL)
- #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos)
- #define SAADC_INTENSET_STOPPED_Disabled (0UL)
- #define SAADC_INTENSET_STOPPED_Enabled (1UL)
- #define SAADC_INTENSET_STOPPED_Set (1UL)
- #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL)
- #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos)
- #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL)
- #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL)
- #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL)
- #define SAADC_INTENSET_RESULTDONE_Pos (3UL)
- #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos)
- #define SAADC_INTENSET_RESULTDONE_Disabled (0UL)
- #define SAADC_INTENSET_RESULTDONE_Enabled (1UL)
- #define SAADC_INTENSET_RESULTDONE_Set (1UL)
- #define SAADC_INTENSET_DONE_Pos (2UL)
- #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos)
- #define SAADC_INTENSET_DONE_Disabled (0UL)
- #define SAADC_INTENSET_DONE_Enabled (1UL)
- #define SAADC_INTENSET_DONE_Set (1UL)
- #define SAADC_INTENSET_END_Pos (1UL)
- #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos)
- #define SAADC_INTENSET_END_Disabled (0UL)
- #define SAADC_INTENSET_END_Enabled (1UL)
- #define SAADC_INTENSET_END_Set (1UL)
- #define SAADC_INTENSET_STARTED_Pos (0UL)
- #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos)
- #define SAADC_INTENSET_STARTED_Disabled (0UL)
- #define SAADC_INTENSET_STARTED_Enabled (1UL)
- #define SAADC_INTENSET_STARTED_Set (1UL)
- #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL)
- #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos)
- #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL)
- #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL)
- #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL)
- #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL)
- #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos)
- #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL)
- #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL)
- #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL)
- #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL)
- #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos)
- #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL)
- #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL)
- #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL)
- #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL)
- #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos)
- #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL)
- #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL)
- #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL)
- #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL)
- #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos)
- #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL)
- #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL)
- #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL)
- #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL)
- #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos)
- #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL)
- #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL)
- #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL)
- #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL)
- #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos)
- #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL)
- #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL)
- #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL)
- #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL)
- #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos)
- #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL)
- #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL)
- #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL)
- #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL)
- #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos)
- #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL)
- #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL)
- #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL)
- #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL)
- #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos)
- #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL)
- #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL)
- #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL)
- #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL)
- #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos)
- #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL)
- #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL)
- #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL)
- #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL)
- #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos)
- #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL)
- #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL)
- #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL)
- #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL)
- #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos)
- #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL)
- #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL)
- #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL)
- #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL)
- #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos)
- #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL)
- #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL)
- #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL)
- #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL)
- #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos)
- #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL)
- #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL)
- #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL)
- #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL)
- #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos)
- #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL)
- #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL)
- #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL)
- #define SAADC_INTENCLR_STOPPED_Pos (5UL)
- #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos)
- #define SAADC_INTENCLR_STOPPED_Disabled (0UL)
- #define SAADC_INTENCLR_STOPPED_Enabled (1UL)
- #define SAADC_INTENCLR_STOPPED_Clear (1UL)
- #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL)
- #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos)
- #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL)
- #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL)
- #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL)
- #define SAADC_INTENCLR_RESULTDONE_Pos (3UL)
- #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos)
- #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL)
- #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL)
- #define SAADC_INTENCLR_RESULTDONE_Clear (1UL)
- #define SAADC_INTENCLR_DONE_Pos (2UL)
- #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos)
- #define SAADC_INTENCLR_DONE_Disabled (0UL)
- #define SAADC_INTENCLR_DONE_Enabled (1UL)
- #define SAADC_INTENCLR_DONE_Clear (1UL)
- #define SAADC_INTENCLR_END_Pos (1UL)
- #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos)
- #define SAADC_INTENCLR_END_Disabled (0UL)
- #define SAADC_INTENCLR_END_Enabled (1UL)
- #define SAADC_INTENCLR_END_Clear (1UL)
- #define SAADC_INTENCLR_STARTED_Pos (0UL)
- #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos)
- #define SAADC_INTENCLR_STARTED_Disabled (0UL)
- #define SAADC_INTENCLR_STARTED_Enabled (1UL)
- #define SAADC_INTENCLR_STARTED_Clear (1UL)
- #define SAADC_STATUS_STATUS_Pos (0UL)
- #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos)
- #define SAADC_STATUS_STATUS_Ready (0UL)
- #define SAADC_STATUS_STATUS_Busy (1UL)
- #define SAADC_ENABLE_ENABLE_Pos (0UL)
- #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos)
- #define SAADC_ENABLE_ENABLE_Disabled (0UL)
- #define SAADC_ENABLE_ENABLE_Enabled (1UL)
- #define SAADC_CH_PSELP_PSELP_Pos (0UL)
- #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos)
- #define SAADC_CH_PSELP_PSELP_NC (0UL)
- #define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL)
- #define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL)
- #define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL)
- #define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL)
- #define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL)
- #define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL)
- #define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL)
- #define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL)
- #define SAADC_CH_PSELP_PSELP_VDDGPIO (9UL)
- #define SAADC_CH_PSELN_PSELN_Pos (0UL)
- #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos)
- #define SAADC_CH_PSELN_PSELN_NC (0UL)
- #define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL)
- #define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL)
- #define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL)
- #define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL)
- #define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL)
- #define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL)
- #define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL)
- #define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL)
- #define SAADC_CH_PSELN_PSELN_VDD_GPIO (9UL)
- #define SAADC_CH_CONFIG_BURST_Pos (24UL)
- #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos)
- #define SAADC_CH_CONFIG_BURST_Disabled (0UL)
- #define SAADC_CH_CONFIG_BURST_Enabled (1UL)
- #define SAADC_CH_CONFIG_MODE_Pos (20UL)
- #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos)
- #define SAADC_CH_CONFIG_MODE_SE (0UL)
- #define SAADC_CH_CONFIG_MODE_Diff (1UL)
- #define SAADC_CH_CONFIG_TACQ_Pos (16UL)
- #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos)
- #define SAADC_CH_CONFIG_TACQ_3us (0UL)
- #define SAADC_CH_CONFIG_TACQ_5us (1UL)
- #define SAADC_CH_CONFIG_TACQ_10us (2UL)
- #define SAADC_CH_CONFIG_TACQ_15us (3UL)
- #define SAADC_CH_CONFIG_TACQ_20us (4UL)
- #define SAADC_CH_CONFIG_TACQ_40us (5UL)
- #define SAADC_CH_CONFIG_REFSEL_Pos (12UL)
- #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos)
- #define SAADC_CH_CONFIG_REFSEL_Internal (0UL)
- #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL)
- #define SAADC_CH_CONFIG_GAIN_Pos (8UL)
- #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos)
- #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL)
- #define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL)
- #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL)
- #define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL)
- #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL)
- #define SAADC_CH_CONFIG_GAIN_Gain1 (5UL)
- #define SAADC_CH_CONFIG_GAIN_Gain2 (6UL)
- #define SAADC_CH_CONFIG_GAIN_Gain4 (7UL)
- #define SAADC_CH_CONFIG_RESN_Pos (4UL)
- #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos)
- #define SAADC_CH_CONFIG_RESN_Bypass (0UL)
- #define SAADC_CH_CONFIG_RESN_Pulldown (1UL)
- #define SAADC_CH_CONFIG_RESN_Pullup (2UL)
- #define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL)
- #define SAADC_CH_CONFIG_RESP_Pos (0UL)
- #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos)
- #define SAADC_CH_CONFIG_RESP_Bypass (0UL)
- #define SAADC_CH_CONFIG_RESP_Pulldown (1UL)
- #define SAADC_CH_CONFIG_RESP_Pullup (2UL)
- #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL)
- #define SAADC_CH_LIMIT_HIGH_Pos (16UL)
- #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos)
- #define SAADC_CH_LIMIT_LOW_Pos (0UL)
- #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos)
- #define SAADC_RESOLUTION_VAL_Pos (0UL)
- #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos)
- #define SAADC_RESOLUTION_VAL_8bit (0UL)
- #define SAADC_RESOLUTION_VAL_10bit (1UL)
- #define SAADC_RESOLUTION_VAL_12bit (2UL)
- #define SAADC_RESOLUTION_VAL_14bit (3UL)
- #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL)
- #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos)
- #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL)
- #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL)
- #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL)
- #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL)
- #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL)
- #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL)
- #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL)
- #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL)
- #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL)
- #define SAADC_SAMPLERATE_MODE_Pos (12UL)
- #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos)
- #define SAADC_SAMPLERATE_MODE_Task (0UL)
- #define SAADC_SAMPLERATE_MODE_Timers (1UL)
- #define SAADC_SAMPLERATE_CC_Pos (0UL)
- #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos)
- #define SAADC_RESULT_PTR_PTR_Pos (0UL)
- #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos)
- #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL)
- #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos)
- #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL)
- #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos)
- #define SPIM_TASKS_START_TASKS_START_Pos (0UL)
- #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos)
- #define SPIM_TASKS_START_TASKS_START_Trigger (1UL)
- #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos)
- #define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL)
- #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos)
- #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL)
- #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL)
- #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos)
- #define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL)
- #define SPIM_SUBSCRIBE_START_EN_Pos (31UL)
- #define SPIM_SUBSCRIBE_START_EN_Msk (0x1UL << SPIM_SUBSCRIBE_START_EN_Pos)
- #define SPIM_SUBSCRIBE_START_EN_Disabled (0UL)
- #define SPIM_SUBSCRIBE_START_EN_Enabled (1UL)
- #define SPIM_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define SPIM_SUBSCRIBE_START_CHIDX_Msk (0xFUL << SPIM_SUBSCRIBE_START_CHIDX_Pos)
- #define SPIM_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define SPIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << SPIM_SUBSCRIBE_STOP_EN_Pos)
- #define SPIM_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define SPIM_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define SPIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define SPIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << SPIM_SUBSCRIBE_STOP_CHIDX_Pos)
- #define SPIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL)
- #define SPIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << SPIM_SUBSCRIBE_SUSPEND_EN_Pos)
- #define SPIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL)
- #define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL)
- #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL)
- #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFUL << SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos)
- #define SPIM_SUBSCRIBE_RESUME_EN_Pos (31UL)
- #define SPIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << SPIM_SUBSCRIBE_RESUME_EN_Pos)
- #define SPIM_SUBSCRIBE_RESUME_EN_Disabled (0UL)
- #define SPIM_SUBSCRIBE_RESUME_EN_Enabled (1UL)
- #define SPIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL)
- #define SPIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFUL << SPIM_SUBSCRIBE_RESUME_CHIDX_Pos)
- #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL)
- #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos)
- #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL)
- #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL)
- #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL)
- #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos)
- #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL)
- #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL)
- #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL)
- #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos)
- #define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL)
- #define SPIM_EVENTS_END_EVENTS_END_Generated (1UL)
- #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL)
- #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos)
- #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL)
- #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL)
- #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL)
- #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos)
- #define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL)
- #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL)
- #define SPIM_PUBLISH_STOPPED_EN_Pos (31UL)
- #define SPIM_PUBLISH_STOPPED_EN_Msk (0x1UL << SPIM_PUBLISH_STOPPED_EN_Pos)
- #define SPIM_PUBLISH_STOPPED_EN_Disabled (0UL)
- #define SPIM_PUBLISH_STOPPED_EN_Enabled (1UL)
- #define SPIM_PUBLISH_STOPPED_CHIDX_Pos (0UL)
- #define SPIM_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << SPIM_PUBLISH_STOPPED_CHIDX_Pos)
- #define SPIM_PUBLISH_ENDRX_EN_Pos (31UL)
- #define SPIM_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDRX_EN_Pos)
- #define SPIM_PUBLISH_ENDRX_EN_Disabled (0UL)
- #define SPIM_PUBLISH_ENDRX_EN_Enabled (1UL)
- #define SPIM_PUBLISH_ENDRX_CHIDX_Pos (0UL)
- #define SPIM_PUBLISH_ENDRX_CHIDX_Msk (0xFUL << SPIM_PUBLISH_ENDRX_CHIDX_Pos)
- #define SPIM_PUBLISH_END_EN_Pos (31UL)
- #define SPIM_PUBLISH_END_EN_Msk (0x1UL << SPIM_PUBLISH_END_EN_Pos)
- #define SPIM_PUBLISH_END_EN_Disabled (0UL)
- #define SPIM_PUBLISH_END_EN_Enabled (1UL)
- #define SPIM_PUBLISH_END_CHIDX_Pos (0UL)
- #define SPIM_PUBLISH_END_CHIDX_Msk (0xFUL << SPIM_PUBLISH_END_CHIDX_Pos)
- #define SPIM_PUBLISH_ENDTX_EN_Pos (31UL)
- #define SPIM_PUBLISH_ENDTX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDTX_EN_Pos)
- #define SPIM_PUBLISH_ENDTX_EN_Disabled (0UL)
- #define SPIM_PUBLISH_ENDTX_EN_Enabled (1UL)
- #define SPIM_PUBLISH_ENDTX_CHIDX_Pos (0UL)
- #define SPIM_PUBLISH_ENDTX_CHIDX_Msk (0xFUL << SPIM_PUBLISH_ENDTX_CHIDX_Pos)
- #define SPIM_PUBLISH_STARTED_EN_Pos (31UL)
- #define SPIM_PUBLISH_STARTED_EN_Msk (0x1UL << SPIM_PUBLISH_STARTED_EN_Pos)
- #define SPIM_PUBLISH_STARTED_EN_Disabled (0UL)
- #define SPIM_PUBLISH_STARTED_EN_Enabled (1UL)
- #define SPIM_PUBLISH_STARTED_CHIDX_Pos (0UL)
- #define SPIM_PUBLISH_STARTED_CHIDX_Msk (0xFUL << SPIM_PUBLISH_STARTED_CHIDX_Pos)
- #define SPIM_SHORTS_END_START_Pos (17UL)
- #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos)
- #define SPIM_SHORTS_END_START_Disabled (0UL)
- #define SPIM_SHORTS_END_START_Enabled (1UL)
- #define SPIM_INTENSET_STARTED_Pos (19UL)
- #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos)
- #define SPIM_INTENSET_STARTED_Disabled (0UL)
- #define SPIM_INTENSET_STARTED_Enabled (1UL)
- #define SPIM_INTENSET_STARTED_Set (1UL)
- #define SPIM_INTENSET_ENDTX_Pos (8UL)
- #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos)
- #define SPIM_INTENSET_ENDTX_Disabled (0UL)
- #define SPIM_INTENSET_ENDTX_Enabled (1UL)
- #define SPIM_INTENSET_ENDTX_Set (1UL)
- #define SPIM_INTENSET_END_Pos (6UL)
- #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos)
- #define SPIM_INTENSET_END_Disabled (0UL)
- #define SPIM_INTENSET_END_Enabled (1UL)
- #define SPIM_INTENSET_END_Set (1UL)
- #define SPIM_INTENSET_ENDRX_Pos (4UL)
- #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos)
- #define SPIM_INTENSET_ENDRX_Disabled (0UL)
- #define SPIM_INTENSET_ENDRX_Enabled (1UL)
- #define SPIM_INTENSET_ENDRX_Set (1UL)
- #define SPIM_INTENSET_STOPPED_Pos (1UL)
- #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos)
- #define SPIM_INTENSET_STOPPED_Disabled (0UL)
- #define SPIM_INTENSET_STOPPED_Enabled (1UL)
- #define SPIM_INTENSET_STOPPED_Set (1UL)
- #define SPIM_INTENCLR_STARTED_Pos (19UL)
- #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos)
- #define SPIM_INTENCLR_STARTED_Disabled (0UL)
- #define SPIM_INTENCLR_STARTED_Enabled (1UL)
- #define SPIM_INTENCLR_STARTED_Clear (1UL)
- #define SPIM_INTENCLR_ENDTX_Pos (8UL)
- #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos)
- #define SPIM_INTENCLR_ENDTX_Disabled (0UL)
- #define SPIM_INTENCLR_ENDTX_Enabled (1UL)
- #define SPIM_INTENCLR_ENDTX_Clear (1UL)
- #define SPIM_INTENCLR_END_Pos (6UL)
- #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos)
- #define SPIM_INTENCLR_END_Disabled (0UL)
- #define SPIM_INTENCLR_END_Enabled (1UL)
- #define SPIM_INTENCLR_END_Clear (1UL)
- #define SPIM_INTENCLR_ENDRX_Pos (4UL)
- #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos)
- #define SPIM_INTENCLR_ENDRX_Disabled (0UL)
- #define SPIM_INTENCLR_ENDRX_Enabled (1UL)
- #define SPIM_INTENCLR_ENDRX_Clear (1UL)
- #define SPIM_INTENCLR_STOPPED_Pos (1UL)
- #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos)
- #define SPIM_INTENCLR_STOPPED_Disabled (0UL)
- #define SPIM_INTENCLR_STOPPED_Enabled (1UL)
- #define SPIM_INTENCLR_STOPPED_Clear (1UL)
- #define SPIM_ENABLE_ENABLE_Pos (0UL)
- #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos)
- #define SPIM_ENABLE_ENABLE_Disabled (0UL)
- #define SPIM_ENABLE_ENABLE_Enabled (7UL)
- #define SPIM_PSEL_SCK_CONNECT_Pos (31UL)
- #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos)
- #define SPIM_PSEL_SCK_CONNECT_Connected (0UL)
- #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL)
- #define SPIM_PSEL_SCK_PIN_Pos (0UL)
- #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos)
- #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL)
- #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos)
- #define SPIM_PSEL_MOSI_CONNECT_Connected (0UL)
- #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL)
- #define SPIM_PSEL_MOSI_PIN_Pos (0UL)
- #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos)
- #define SPIM_PSEL_MISO_CONNECT_Pos (31UL)
- #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos)
- #define SPIM_PSEL_MISO_CONNECT_Connected (0UL)
- #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL)
- #define SPIM_PSEL_MISO_PIN_Pos (0UL)
- #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos)
- #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL)
- #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos)
- #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL)
- #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL)
- #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL)
- #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL)
- #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL)
- #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL)
- #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL)
- #define SPIM_RXD_PTR_PTR_Pos (0UL)
- #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos)
- #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL)
- #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos)
- #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL)
- #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos)
- #define SPIM_RXD_LIST_LIST_Pos (0UL)
- #define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos)
- #define SPIM_RXD_LIST_LIST_Disabled (0UL)
- #define SPIM_RXD_LIST_LIST_ArrayList (1UL)
- #define SPIM_TXD_PTR_PTR_Pos (0UL)
- #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos)
- #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL)
- #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos)
- #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL)
- #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos)
- #define SPIM_TXD_LIST_LIST_Pos (0UL)
- #define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos)
- #define SPIM_TXD_LIST_LIST_Disabled (0UL)
- #define SPIM_TXD_LIST_LIST_ArrayList (1UL)
- #define SPIM_CONFIG_CPOL_Pos (2UL)
- #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos)
- #define SPIM_CONFIG_CPOL_ActiveHigh (0UL)
- #define SPIM_CONFIG_CPOL_ActiveLow (1UL)
- #define SPIM_CONFIG_CPHA_Pos (1UL)
- #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos)
- #define SPIM_CONFIG_CPHA_Leading (0UL)
- #define SPIM_CONFIG_CPHA_Trailing (1UL)
- #define SPIM_CONFIG_ORDER_Pos (0UL)
- #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos)
- #define SPIM_CONFIG_ORDER_MsbFirst (0UL)
- #define SPIM_CONFIG_ORDER_LsbFirst (1UL)
- #define SPIM_ORC_ORC_Pos (0UL)
- #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos)
- #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL)
- #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos)
- #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL)
- #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL)
- #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos)
- #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL)
- #define SPIS_SUBSCRIBE_ACQUIRE_EN_Pos (31UL)
- #define SPIS_SUBSCRIBE_ACQUIRE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_ACQUIRE_EN_Pos)
- #define SPIS_SUBSCRIBE_ACQUIRE_EN_Disabled (0UL)
- #define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (1UL)
- #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos (0UL)
- #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Msk (0xFUL << SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos)
- #define SPIS_SUBSCRIBE_RELEASE_EN_Pos (31UL)
- #define SPIS_SUBSCRIBE_RELEASE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_RELEASE_EN_Pos)
- #define SPIS_SUBSCRIBE_RELEASE_EN_Disabled (0UL)
- #define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (1UL)
- #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos (0UL)
- #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Msk (0xFUL << SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos)
- #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL)
- #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos)
- #define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL)
- #define SPIS_EVENTS_END_EVENTS_END_Generated (1UL)
- #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL)
- #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos)
- #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL)
- #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL)
- #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL)
- #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos)
- #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL)
- #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL)
- #define SPIS_PUBLISH_END_EN_Pos (31UL)
- #define SPIS_PUBLISH_END_EN_Msk (0x1UL << SPIS_PUBLISH_END_EN_Pos)
- #define SPIS_PUBLISH_END_EN_Disabled (0UL)
- #define SPIS_PUBLISH_END_EN_Enabled (1UL)
- #define SPIS_PUBLISH_END_CHIDX_Pos (0UL)
- #define SPIS_PUBLISH_END_CHIDX_Msk (0xFUL << SPIS_PUBLISH_END_CHIDX_Pos)
- #define SPIS_PUBLISH_ENDRX_EN_Pos (31UL)
- #define SPIS_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIS_PUBLISH_ENDRX_EN_Pos)
- #define SPIS_PUBLISH_ENDRX_EN_Disabled (0UL)
- #define SPIS_PUBLISH_ENDRX_EN_Enabled (1UL)
- #define SPIS_PUBLISH_ENDRX_CHIDX_Pos (0UL)
- #define SPIS_PUBLISH_ENDRX_CHIDX_Msk (0xFUL << SPIS_PUBLISH_ENDRX_CHIDX_Pos)
- #define SPIS_PUBLISH_ACQUIRED_EN_Pos (31UL)
- #define SPIS_PUBLISH_ACQUIRED_EN_Msk (0x1UL << SPIS_PUBLISH_ACQUIRED_EN_Pos)
- #define SPIS_PUBLISH_ACQUIRED_EN_Disabled (0UL)
- #define SPIS_PUBLISH_ACQUIRED_EN_Enabled (1UL)
- #define SPIS_PUBLISH_ACQUIRED_CHIDX_Pos (0UL)
- #define SPIS_PUBLISH_ACQUIRED_CHIDX_Msk (0xFUL << SPIS_PUBLISH_ACQUIRED_CHIDX_Pos)
- #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL)
- #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos)
- #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL)
- #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL)
- #define SPIS_INTENSET_ACQUIRED_Pos (10UL)
- #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos)
- #define SPIS_INTENSET_ACQUIRED_Disabled (0UL)
- #define SPIS_INTENSET_ACQUIRED_Enabled (1UL)
- #define SPIS_INTENSET_ACQUIRED_Set (1UL)
- #define SPIS_INTENSET_ENDRX_Pos (4UL)
- #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos)
- #define SPIS_INTENSET_ENDRX_Disabled (0UL)
- #define SPIS_INTENSET_ENDRX_Enabled (1UL)
- #define SPIS_INTENSET_ENDRX_Set (1UL)
- #define SPIS_INTENSET_END_Pos (1UL)
- #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos)
- #define SPIS_INTENSET_END_Disabled (0UL)
- #define SPIS_INTENSET_END_Enabled (1UL)
- #define SPIS_INTENSET_END_Set (1UL)
- #define SPIS_INTENCLR_ACQUIRED_Pos (10UL)
- #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos)
- #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL)
- #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL)
- #define SPIS_INTENCLR_ACQUIRED_Clear (1UL)
- #define SPIS_INTENCLR_ENDRX_Pos (4UL)
- #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos)
- #define SPIS_INTENCLR_ENDRX_Disabled (0UL)
- #define SPIS_INTENCLR_ENDRX_Enabled (1UL)
- #define SPIS_INTENCLR_ENDRX_Clear (1UL)
- #define SPIS_INTENCLR_END_Pos (1UL)
- #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos)
- #define SPIS_INTENCLR_END_Disabled (0UL)
- #define SPIS_INTENCLR_END_Enabled (1UL)
- #define SPIS_INTENCLR_END_Clear (1UL)
- #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL)
- #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos)
- #define SPIS_SEMSTAT_SEMSTAT_Free (0UL)
- #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL)
- #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL)
- #define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL)
- #define SPIS_STATUS_OVERFLOW_Pos (1UL)
- #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos)
- #define SPIS_STATUS_OVERFLOW_NotPresent (0UL)
- #define SPIS_STATUS_OVERFLOW_Present (1UL)
- #define SPIS_STATUS_OVERFLOW_Clear (1UL)
- #define SPIS_STATUS_OVERREAD_Pos (0UL)
- #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos)
- #define SPIS_STATUS_OVERREAD_NotPresent (0UL)
- #define SPIS_STATUS_OVERREAD_Present (1UL)
- #define SPIS_STATUS_OVERREAD_Clear (1UL)
- #define SPIS_ENABLE_ENABLE_Pos (0UL)
- #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos)
- #define SPIS_ENABLE_ENABLE_Disabled (0UL)
- #define SPIS_ENABLE_ENABLE_Enabled (2UL)
- #define SPIS_PSEL_SCK_CONNECT_Pos (31UL)
- #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos)
- #define SPIS_PSEL_SCK_CONNECT_Connected (0UL)
- #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL)
- #define SPIS_PSEL_SCK_PIN_Pos (0UL)
- #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos)
- #define SPIS_PSEL_MISO_CONNECT_Pos (31UL)
- #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos)
- #define SPIS_PSEL_MISO_CONNECT_Connected (0UL)
- #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL)
- #define SPIS_PSEL_MISO_PIN_Pos (0UL)
- #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos)
- #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL)
- #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos)
- #define SPIS_PSEL_MOSI_CONNECT_Connected (0UL)
- #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL)
- #define SPIS_PSEL_MOSI_PIN_Pos (0UL)
- #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos)
- #define SPIS_PSEL_CSN_CONNECT_Pos (31UL)
- #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos)
- #define SPIS_PSEL_CSN_CONNECT_Connected (0UL)
- #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL)
- #define SPIS_PSEL_CSN_PIN_Pos (0UL)
- #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos)
- #define SPIS_RXD_PTR_PTR_Pos (0UL)
- #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos)
- #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL)
- #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos)
- #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL)
- #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos)
- #define SPIS_RXD_LIST_LIST_Pos (0UL)
- #define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos)
- #define SPIS_RXD_LIST_LIST_Disabled (0UL)
- #define SPIS_RXD_LIST_LIST_ArrayList (1UL)
- #define SPIS_TXD_PTR_PTR_Pos (0UL)
- #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos)
- #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL)
- #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos)
- #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL)
- #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos)
- #define SPIS_TXD_LIST_LIST_Pos (0UL)
- #define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos)
- #define SPIS_TXD_LIST_LIST_Disabled (0UL)
- #define SPIS_TXD_LIST_LIST_ArrayList (1UL)
- #define SPIS_CONFIG_CPOL_Pos (2UL)
- #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos)
- #define SPIS_CONFIG_CPOL_ActiveHigh (0UL)
- #define SPIS_CONFIG_CPOL_ActiveLow (1UL)
- #define SPIS_CONFIG_CPHA_Pos (1UL)
- #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos)
- #define SPIS_CONFIG_CPHA_Leading (0UL)
- #define SPIS_CONFIG_CPHA_Trailing (1UL)
- #define SPIS_CONFIG_ORDER_Pos (0UL)
- #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos)
- #define SPIS_CONFIG_ORDER_MsbFirst (0UL)
- #define SPIS_CONFIG_ORDER_LsbFirst (1UL)
- #define SPIS_DEF_DEF_Pos (0UL)
- #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos)
- #define SPIS_ORC_ORC_Pos (0UL)
- #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos)
- #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos (0UL)
- #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Msk (0x1UL << SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos)
- #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_NotGenerated (0UL)
- #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Generated (1UL)
- #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos (0UL)
- #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Msk (0x1UL << SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos)
- #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_NotGenerated (0UL)
- #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Generated (1UL)
- #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos (0UL)
- #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Msk (0x1UL << SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos)
- #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_NotGenerated (0UL)
- #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Generated (1UL)
- #define SPU_PUBLISH_RAMACCERR_EN_Pos (31UL)
- #define SPU_PUBLISH_RAMACCERR_EN_Msk (0x1UL << SPU_PUBLISH_RAMACCERR_EN_Pos)
- #define SPU_PUBLISH_RAMACCERR_EN_Disabled (0UL)
- #define SPU_PUBLISH_RAMACCERR_EN_Enabled (1UL)
- #define SPU_PUBLISH_RAMACCERR_CHIDX_Pos (0UL)
- #define SPU_PUBLISH_RAMACCERR_CHIDX_Msk (0xFUL << SPU_PUBLISH_RAMACCERR_CHIDX_Pos)
- #define SPU_PUBLISH_FLASHACCERR_EN_Pos (31UL)
- #define SPU_PUBLISH_FLASHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_FLASHACCERR_EN_Pos)
- #define SPU_PUBLISH_FLASHACCERR_EN_Disabled (0UL)
- #define SPU_PUBLISH_FLASHACCERR_EN_Enabled (1UL)
- #define SPU_PUBLISH_FLASHACCERR_CHIDX_Pos (0UL)
- #define SPU_PUBLISH_FLASHACCERR_CHIDX_Msk (0xFUL << SPU_PUBLISH_FLASHACCERR_CHIDX_Pos)
- #define SPU_PUBLISH_PERIPHACCERR_EN_Pos (31UL)
- #define SPU_PUBLISH_PERIPHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_PERIPHACCERR_EN_Pos)
- #define SPU_PUBLISH_PERIPHACCERR_EN_Disabled (0UL)
- #define SPU_PUBLISH_PERIPHACCERR_EN_Enabled (1UL)
- #define SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos (0UL)
- #define SPU_PUBLISH_PERIPHACCERR_CHIDX_Msk (0xFUL << SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos)
- #define SPU_INTEN_PERIPHACCERR_Pos (2UL)
- #define SPU_INTEN_PERIPHACCERR_Msk (0x1UL << SPU_INTEN_PERIPHACCERR_Pos)
- #define SPU_INTEN_PERIPHACCERR_Disabled (0UL)
- #define SPU_INTEN_PERIPHACCERR_Enabled (1UL)
- #define SPU_INTEN_FLASHACCERR_Pos (1UL)
- #define SPU_INTEN_FLASHACCERR_Msk (0x1UL << SPU_INTEN_FLASHACCERR_Pos)
- #define SPU_INTEN_FLASHACCERR_Disabled (0UL)
- #define SPU_INTEN_FLASHACCERR_Enabled (1UL)
- #define SPU_INTEN_RAMACCERR_Pos (0UL)
- #define SPU_INTEN_RAMACCERR_Msk (0x1UL << SPU_INTEN_RAMACCERR_Pos)
- #define SPU_INTEN_RAMACCERR_Disabled (0UL)
- #define SPU_INTEN_RAMACCERR_Enabled (1UL)
- #define SPU_INTENSET_PERIPHACCERR_Pos (2UL)
- #define SPU_INTENSET_PERIPHACCERR_Msk (0x1UL << SPU_INTENSET_PERIPHACCERR_Pos)
- #define SPU_INTENSET_PERIPHACCERR_Disabled (0UL)
- #define SPU_INTENSET_PERIPHACCERR_Enabled (1UL)
- #define SPU_INTENSET_PERIPHACCERR_Set (1UL)
- #define SPU_INTENSET_FLASHACCERR_Pos (1UL)
- #define SPU_INTENSET_FLASHACCERR_Msk (0x1UL << SPU_INTENSET_FLASHACCERR_Pos)
- #define SPU_INTENSET_FLASHACCERR_Disabled (0UL)
- #define SPU_INTENSET_FLASHACCERR_Enabled (1UL)
- #define SPU_INTENSET_FLASHACCERR_Set (1UL)
- #define SPU_INTENSET_RAMACCERR_Pos (0UL)
- #define SPU_INTENSET_RAMACCERR_Msk (0x1UL << SPU_INTENSET_RAMACCERR_Pos)
- #define SPU_INTENSET_RAMACCERR_Disabled (0UL)
- #define SPU_INTENSET_RAMACCERR_Enabled (1UL)
- #define SPU_INTENSET_RAMACCERR_Set (1UL)
- #define SPU_INTENCLR_PERIPHACCERR_Pos (2UL)
- #define SPU_INTENCLR_PERIPHACCERR_Msk (0x1UL << SPU_INTENCLR_PERIPHACCERR_Pos)
- #define SPU_INTENCLR_PERIPHACCERR_Disabled (0UL)
- #define SPU_INTENCLR_PERIPHACCERR_Enabled (1UL)
- #define SPU_INTENCLR_PERIPHACCERR_Clear (1UL)
- #define SPU_INTENCLR_FLASHACCERR_Pos (1UL)
- #define SPU_INTENCLR_FLASHACCERR_Msk (0x1UL << SPU_INTENCLR_FLASHACCERR_Pos)
- #define SPU_INTENCLR_FLASHACCERR_Disabled (0UL)
- #define SPU_INTENCLR_FLASHACCERR_Enabled (1UL)
- #define SPU_INTENCLR_FLASHACCERR_Clear (1UL)
- #define SPU_INTENCLR_RAMACCERR_Pos (0UL)
- #define SPU_INTENCLR_RAMACCERR_Msk (0x1UL << SPU_INTENCLR_RAMACCERR_Pos)
- #define SPU_INTENCLR_RAMACCERR_Disabled (0UL)
- #define SPU_INTENCLR_RAMACCERR_Enabled (1UL)
- #define SPU_INTENCLR_RAMACCERR_Clear (1UL)
- #define SPU_CAP_TZM_Pos (0UL)
- #define SPU_CAP_TZM_Msk (0x1UL << SPU_CAP_TZM_Pos)
- #define SPU_CAP_TZM_NotAvailable (0UL)
- #define SPU_CAP_TZM_Enabled (1UL)
- #define SPU_EXTDOMAIN_PERM_LOCK_Pos (8UL)
- #define SPU_EXTDOMAIN_PERM_LOCK_Msk (0x1UL << SPU_EXTDOMAIN_PERM_LOCK_Pos)
- #define SPU_EXTDOMAIN_PERM_LOCK_Unlocked (0UL)
- #define SPU_EXTDOMAIN_PERM_LOCK_Locked (1UL)
- #define SPU_EXTDOMAIN_PERM_SECATTR_Pos (4UL)
- #define SPU_EXTDOMAIN_PERM_SECATTR_Msk (0x1UL << SPU_EXTDOMAIN_PERM_SECATTR_Pos)
- #define SPU_EXTDOMAIN_PERM_SECATTR_NonSecure (0UL)
- #define SPU_EXTDOMAIN_PERM_SECATTR_Secure (1UL)
- #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos (0UL)
- #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Msk (0x3UL << SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos)
- #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_NonSecure (0UL)
- #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Secure (1UL)
- #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_UserSelectable (2UL)
- #define SPU_DPPI_PERM_CHANNEL15_Pos (15UL)
- #define SPU_DPPI_PERM_CHANNEL15_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL15_Pos)
- #define SPU_DPPI_PERM_CHANNEL15_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL15_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL14_Pos (14UL)
- #define SPU_DPPI_PERM_CHANNEL14_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL14_Pos)
- #define SPU_DPPI_PERM_CHANNEL14_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL14_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL13_Pos (13UL)
- #define SPU_DPPI_PERM_CHANNEL13_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL13_Pos)
- #define SPU_DPPI_PERM_CHANNEL13_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL13_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL12_Pos (12UL)
- #define SPU_DPPI_PERM_CHANNEL12_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL12_Pos)
- #define SPU_DPPI_PERM_CHANNEL12_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL12_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL11_Pos (11UL)
- #define SPU_DPPI_PERM_CHANNEL11_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL11_Pos)
- #define SPU_DPPI_PERM_CHANNEL11_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL11_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL10_Pos (10UL)
- #define SPU_DPPI_PERM_CHANNEL10_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL10_Pos)
- #define SPU_DPPI_PERM_CHANNEL10_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL10_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL9_Pos (9UL)
- #define SPU_DPPI_PERM_CHANNEL9_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL9_Pos)
- #define SPU_DPPI_PERM_CHANNEL9_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL9_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL8_Pos (8UL)
- #define SPU_DPPI_PERM_CHANNEL8_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL8_Pos)
- #define SPU_DPPI_PERM_CHANNEL8_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL8_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL7_Pos (7UL)
- #define SPU_DPPI_PERM_CHANNEL7_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL7_Pos)
- #define SPU_DPPI_PERM_CHANNEL7_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL7_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL6_Pos (6UL)
- #define SPU_DPPI_PERM_CHANNEL6_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL6_Pos)
- #define SPU_DPPI_PERM_CHANNEL6_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL6_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL5_Pos (5UL)
- #define SPU_DPPI_PERM_CHANNEL5_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL5_Pos)
- #define SPU_DPPI_PERM_CHANNEL5_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL5_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL4_Pos (4UL)
- #define SPU_DPPI_PERM_CHANNEL4_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL4_Pos)
- #define SPU_DPPI_PERM_CHANNEL4_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL4_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL3_Pos (3UL)
- #define SPU_DPPI_PERM_CHANNEL3_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL3_Pos)
- #define SPU_DPPI_PERM_CHANNEL3_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL3_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL2_Pos (2UL)
- #define SPU_DPPI_PERM_CHANNEL2_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL2_Pos)
- #define SPU_DPPI_PERM_CHANNEL2_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL2_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL1_Pos (1UL)
- #define SPU_DPPI_PERM_CHANNEL1_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL1_Pos)
- #define SPU_DPPI_PERM_CHANNEL1_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL1_Secure (1UL)
- #define SPU_DPPI_PERM_CHANNEL0_Pos (0UL)
- #define SPU_DPPI_PERM_CHANNEL0_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL0_Pos)
- #define SPU_DPPI_PERM_CHANNEL0_NonSecure (0UL)
- #define SPU_DPPI_PERM_CHANNEL0_Secure (1UL)
- #define SPU_DPPI_LOCK_LOCK_Pos (0UL)
- #define SPU_DPPI_LOCK_LOCK_Msk (0x1UL << SPU_DPPI_LOCK_LOCK_Pos)
- #define SPU_DPPI_LOCK_LOCK_Unlocked (0UL)
- #define SPU_DPPI_LOCK_LOCK_Locked (1UL)
- #define SPU_GPIOPORT_PERM_PIN31_Pos (31UL)
- #define SPU_GPIOPORT_PERM_PIN31_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN31_Pos)
- #define SPU_GPIOPORT_PERM_PIN31_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN31_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN30_Pos (30UL)
- #define SPU_GPIOPORT_PERM_PIN30_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN30_Pos)
- #define SPU_GPIOPORT_PERM_PIN30_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN30_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN29_Pos (29UL)
- #define SPU_GPIOPORT_PERM_PIN29_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN29_Pos)
- #define SPU_GPIOPORT_PERM_PIN29_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN29_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN28_Pos (28UL)
- #define SPU_GPIOPORT_PERM_PIN28_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN28_Pos)
- #define SPU_GPIOPORT_PERM_PIN28_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN28_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN27_Pos (27UL)
- #define SPU_GPIOPORT_PERM_PIN27_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN27_Pos)
- #define SPU_GPIOPORT_PERM_PIN27_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN27_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN26_Pos (26UL)
- #define SPU_GPIOPORT_PERM_PIN26_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN26_Pos)
- #define SPU_GPIOPORT_PERM_PIN26_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN26_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN25_Pos (25UL)
- #define SPU_GPIOPORT_PERM_PIN25_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN25_Pos)
- #define SPU_GPIOPORT_PERM_PIN25_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN25_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN24_Pos (24UL)
- #define SPU_GPIOPORT_PERM_PIN24_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN24_Pos)
- #define SPU_GPIOPORT_PERM_PIN24_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN24_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN23_Pos (23UL)
- #define SPU_GPIOPORT_PERM_PIN23_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN23_Pos)
- #define SPU_GPIOPORT_PERM_PIN23_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN23_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN22_Pos (22UL)
- #define SPU_GPIOPORT_PERM_PIN22_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN22_Pos)
- #define SPU_GPIOPORT_PERM_PIN22_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN22_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN21_Pos (21UL)
- #define SPU_GPIOPORT_PERM_PIN21_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN21_Pos)
- #define SPU_GPIOPORT_PERM_PIN21_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN21_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN20_Pos (20UL)
- #define SPU_GPIOPORT_PERM_PIN20_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN20_Pos)
- #define SPU_GPIOPORT_PERM_PIN20_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN20_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN19_Pos (19UL)
- #define SPU_GPIOPORT_PERM_PIN19_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN19_Pos)
- #define SPU_GPIOPORT_PERM_PIN19_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN19_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN18_Pos (18UL)
- #define SPU_GPIOPORT_PERM_PIN18_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN18_Pos)
- #define SPU_GPIOPORT_PERM_PIN18_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN18_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN17_Pos (17UL)
- #define SPU_GPIOPORT_PERM_PIN17_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN17_Pos)
- #define SPU_GPIOPORT_PERM_PIN17_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN17_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN16_Pos (16UL)
- #define SPU_GPIOPORT_PERM_PIN16_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN16_Pos)
- #define SPU_GPIOPORT_PERM_PIN16_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN16_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN15_Pos (15UL)
- #define SPU_GPIOPORT_PERM_PIN15_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN15_Pos)
- #define SPU_GPIOPORT_PERM_PIN15_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN15_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN14_Pos (14UL)
- #define SPU_GPIOPORT_PERM_PIN14_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN14_Pos)
- #define SPU_GPIOPORT_PERM_PIN14_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN14_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN13_Pos (13UL)
- #define SPU_GPIOPORT_PERM_PIN13_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN13_Pos)
- #define SPU_GPIOPORT_PERM_PIN13_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN13_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN12_Pos (12UL)
- #define SPU_GPIOPORT_PERM_PIN12_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN12_Pos)
- #define SPU_GPIOPORT_PERM_PIN12_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN12_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN11_Pos (11UL)
- #define SPU_GPIOPORT_PERM_PIN11_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN11_Pos)
- #define SPU_GPIOPORT_PERM_PIN11_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN11_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN10_Pos (10UL)
- #define SPU_GPIOPORT_PERM_PIN10_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN10_Pos)
- #define SPU_GPIOPORT_PERM_PIN10_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN10_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN9_Pos (9UL)
- #define SPU_GPIOPORT_PERM_PIN9_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN9_Pos)
- #define SPU_GPIOPORT_PERM_PIN9_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN9_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN8_Pos (8UL)
- #define SPU_GPIOPORT_PERM_PIN8_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN8_Pos)
- #define SPU_GPIOPORT_PERM_PIN8_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN8_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN7_Pos (7UL)
- #define SPU_GPIOPORT_PERM_PIN7_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN7_Pos)
- #define SPU_GPIOPORT_PERM_PIN7_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN7_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN6_Pos (6UL)
- #define SPU_GPIOPORT_PERM_PIN6_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN6_Pos)
- #define SPU_GPIOPORT_PERM_PIN6_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN6_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN5_Pos (5UL)
- #define SPU_GPIOPORT_PERM_PIN5_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN5_Pos)
- #define SPU_GPIOPORT_PERM_PIN5_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN5_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN4_Pos (4UL)
- #define SPU_GPIOPORT_PERM_PIN4_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN4_Pos)
- #define SPU_GPIOPORT_PERM_PIN4_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN4_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN3_Pos (3UL)
- #define SPU_GPIOPORT_PERM_PIN3_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN3_Pos)
- #define SPU_GPIOPORT_PERM_PIN3_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN3_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN2_Pos (2UL)
- #define SPU_GPIOPORT_PERM_PIN2_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN2_Pos)
- #define SPU_GPIOPORT_PERM_PIN2_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN2_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN1_Pos (1UL)
- #define SPU_GPIOPORT_PERM_PIN1_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN1_Pos)
- #define SPU_GPIOPORT_PERM_PIN1_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN1_Secure (1UL)
- #define SPU_GPIOPORT_PERM_PIN0_Pos (0UL)
- #define SPU_GPIOPORT_PERM_PIN0_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN0_Pos)
- #define SPU_GPIOPORT_PERM_PIN0_NonSecure (0UL)
- #define SPU_GPIOPORT_PERM_PIN0_Secure (1UL)
- #define SPU_GPIOPORT_LOCK_LOCK_Pos (0UL)
- #define SPU_GPIOPORT_LOCK_LOCK_Msk (0x1UL << SPU_GPIOPORT_LOCK_LOCK_Pos)
- #define SPU_GPIOPORT_LOCK_LOCK_Unlocked (0UL)
- #define SPU_GPIOPORT_LOCK_LOCK_Locked (1UL)
- #define SPU_FLASHNSC_REGION_LOCK_Pos (8UL)
- #define SPU_FLASHNSC_REGION_LOCK_Msk (0x1UL << SPU_FLASHNSC_REGION_LOCK_Pos)
- #define SPU_FLASHNSC_REGION_LOCK_Unlocked (0UL)
- #define SPU_FLASHNSC_REGION_LOCK_Locked (1UL)
- #define SPU_FLASHNSC_REGION_REGION_Pos (0UL)
- #define SPU_FLASHNSC_REGION_REGION_Msk (0x1FUL << SPU_FLASHNSC_REGION_REGION_Pos)
- #define SPU_FLASHNSC_SIZE_LOCK_Pos (8UL)
- #define SPU_FLASHNSC_SIZE_LOCK_Msk (0x1UL << SPU_FLASHNSC_SIZE_LOCK_Pos)
- #define SPU_FLASHNSC_SIZE_LOCK_Unlocked (0UL)
- #define SPU_FLASHNSC_SIZE_LOCK_Locked (1UL)
- #define SPU_FLASHNSC_SIZE_SIZE_Pos (0UL)
- #define SPU_FLASHNSC_SIZE_SIZE_Msk (0xFUL << SPU_FLASHNSC_SIZE_SIZE_Pos)
- #define SPU_FLASHNSC_SIZE_SIZE_Disabled (0UL)
- #define SPU_FLASHNSC_SIZE_SIZE_32 (1UL)
- #define SPU_FLASHNSC_SIZE_SIZE_64 (2UL)
- #define SPU_FLASHNSC_SIZE_SIZE_128 (3UL)
- #define SPU_FLASHNSC_SIZE_SIZE_256 (4UL)
- #define SPU_FLASHNSC_SIZE_SIZE_512 (5UL)
- #define SPU_FLASHNSC_SIZE_SIZE_1024 (6UL)
- #define SPU_FLASHNSC_SIZE_SIZE_2048 (7UL)
- #define SPU_FLASHNSC_SIZE_SIZE_4096 (8UL)
- #define SPU_RAMNSC_REGION_LOCK_Pos (8UL)
- #define SPU_RAMNSC_REGION_LOCK_Msk (0x1UL << SPU_RAMNSC_REGION_LOCK_Pos)
- #define SPU_RAMNSC_REGION_LOCK_Unlocked (0UL)
- #define SPU_RAMNSC_REGION_LOCK_Locked (1UL)
- #define SPU_RAMNSC_REGION_REGION_Pos (0UL)
- #define SPU_RAMNSC_REGION_REGION_Msk (0xFUL << SPU_RAMNSC_REGION_REGION_Pos)
- #define SPU_RAMNSC_SIZE_LOCK_Pos (8UL)
- #define SPU_RAMNSC_SIZE_LOCK_Msk (0x1UL << SPU_RAMNSC_SIZE_LOCK_Pos)
- #define SPU_RAMNSC_SIZE_LOCK_Unlocked (0UL)
- #define SPU_RAMNSC_SIZE_LOCK_Locked (1UL)
- #define SPU_RAMNSC_SIZE_SIZE_Pos (0UL)
- #define SPU_RAMNSC_SIZE_SIZE_Msk (0xFUL << SPU_RAMNSC_SIZE_SIZE_Pos)
- #define SPU_RAMNSC_SIZE_SIZE_Disabled (0UL)
- #define SPU_RAMNSC_SIZE_SIZE_32 (1UL)
- #define SPU_RAMNSC_SIZE_SIZE_64 (2UL)
- #define SPU_RAMNSC_SIZE_SIZE_128 (3UL)
- #define SPU_RAMNSC_SIZE_SIZE_256 (4UL)
- #define SPU_RAMNSC_SIZE_SIZE_512 (5UL)
- #define SPU_RAMNSC_SIZE_SIZE_1024 (6UL)
- #define SPU_RAMNSC_SIZE_SIZE_2048 (7UL)
- #define SPU_RAMNSC_SIZE_SIZE_4096 (8UL)
- #define SPU_FLASHREGION_PERM_LOCK_Pos (8UL)
- #define SPU_FLASHREGION_PERM_LOCK_Msk (0x1UL << SPU_FLASHREGION_PERM_LOCK_Pos)
- #define SPU_FLASHREGION_PERM_LOCK_Unlocked (0UL)
- #define SPU_FLASHREGION_PERM_LOCK_Locked (1UL)
- #define SPU_FLASHREGION_PERM_SECATTR_Pos (4UL)
- #define SPU_FLASHREGION_PERM_SECATTR_Msk (0x1UL << SPU_FLASHREGION_PERM_SECATTR_Pos)
- #define SPU_FLASHREGION_PERM_SECATTR_Non_Secure (0UL)
- #define SPU_FLASHREGION_PERM_SECATTR_Secure (1UL)
- #define SPU_FLASHREGION_PERM_READ_Pos (2UL)
- #define SPU_FLASHREGION_PERM_READ_Msk (0x1UL << SPU_FLASHREGION_PERM_READ_Pos)
- #define SPU_FLASHREGION_PERM_READ_Disable (0UL)
- #define SPU_FLASHREGION_PERM_READ_Enable (1UL)
- #define SPU_FLASHREGION_PERM_WRITE_Pos (1UL)
- #define SPU_FLASHREGION_PERM_WRITE_Msk (0x1UL << SPU_FLASHREGION_PERM_WRITE_Pos)
- #define SPU_FLASHREGION_PERM_WRITE_Disable (0UL)
- #define SPU_FLASHREGION_PERM_WRITE_Enable (1UL)
- #define SPU_FLASHREGION_PERM_EXECUTE_Pos (0UL)
- #define SPU_FLASHREGION_PERM_EXECUTE_Msk (0x1UL << SPU_FLASHREGION_PERM_EXECUTE_Pos)
- #define SPU_FLASHREGION_PERM_EXECUTE_Disable (0UL)
- #define SPU_FLASHREGION_PERM_EXECUTE_Enable (1UL)
- #define SPU_RAMREGION_PERM_LOCK_Pos (8UL)
- #define SPU_RAMREGION_PERM_LOCK_Msk (0x1UL << SPU_RAMREGION_PERM_LOCK_Pos)
- #define SPU_RAMREGION_PERM_LOCK_Unlocked (0UL)
- #define SPU_RAMREGION_PERM_LOCK_Locked (1UL)
- #define SPU_RAMREGION_PERM_SECATTR_Pos (4UL)
- #define SPU_RAMREGION_PERM_SECATTR_Msk (0x1UL << SPU_RAMREGION_PERM_SECATTR_Pos)
- #define SPU_RAMREGION_PERM_SECATTR_Non_Secure (0UL)
- #define SPU_RAMREGION_PERM_SECATTR_Secure (1UL)
- #define SPU_RAMREGION_PERM_READ_Pos (2UL)
- #define SPU_RAMREGION_PERM_READ_Msk (0x1UL << SPU_RAMREGION_PERM_READ_Pos)
- #define SPU_RAMREGION_PERM_READ_Disable (0UL)
- #define SPU_RAMREGION_PERM_READ_Enable (1UL)
- #define SPU_RAMREGION_PERM_WRITE_Pos (1UL)
- #define SPU_RAMREGION_PERM_WRITE_Msk (0x1UL << SPU_RAMREGION_PERM_WRITE_Pos)
- #define SPU_RAMREGION_PERM_WRITE_Disable (0UL)
- #define SPU_RAMREGION_PERM_WRITE_Enable (1UL)
- #define SPU_RAMREGION_PERM_EXECUTE_Pos (0UL)
- #define SPU_RAMREGION_PERM_EXECUTE_Msk (0x1UL << SPU_RAMREGION_PERM_EXECUTE_Pos)
- #define SPU_RAMREGION_PERM_EXECUTE_Disable (0UL)
- #define SPU_RAMREGION_PERM_EXECUTE_Enable (1UL)
- #define SPU_PERIPHID_PERM_PRESENT_Pos (31UL)
- #define SPU_PERIPHID_PERM_PRESENT_Msk (0x1UL << SPU_PERIPHID_PERM_PRESENT_Pos)
- #define SPU_PERIPHID_PERM_PRESENT_NotPresent (0UL)
- #define SPU_PERIPHID_PERM_PRESENT_IsPresent (1UL)
- #define SPU_PERIPHID_PERM_LOCK_Pos (8UL)
- #define SPU_PERIPHID_PERM_LOCK_Msk (0x1UL << SPU_PERIPHID_PERM_LOCK_Pos)
- #define SPU_PERIPHID_PERM_LOCK_Unlocked (0UL)
- #define SPU_PERIPHID_PERM_LOCK_Locked (1UL)
- #define SPU_PERIPHID_PERM_DMASEC_Pos (5UL)
- #define SPU_PERIPHID_PERM_DMASEC_Msk (0x1UL << SPU_PERIPHID_PERM_DMASEC_Pos)
- #define SPU_PERIPHID_PERM_DMASEC_NonSecure (0UL)
- #define SPU_PERIPHID_PERM_DMASEC_Secure (1UL)
- #define SPU_PERIPHID_PERM_SECATTR_Pos (4UL)
- #define SPU_PERIPHID_PERM_SECATTR_Msk (0x1UL << SPU_PERIPHID_PERM_SECATTR_Pos)
- #define SPU_PERIPHID_PERM_SECATTR_NonSecure (0UL)
- #define SPU_PERIPHID_PERM_SECATTR_Secure (1UL)
- #define SPU_PERIPHID_PERM_DMA_Pos (2UL)
- #define SPU_PERIPHID_PERM_DMA_Msk (0x3UL << SPU_PERIPHID_PERM_DMA_Pos)
- #define SPU_PERIPHID_PERM_DMA_NoDMA (0UL)
- #define SPU_PERIPHID_PERM_DMA_NoSeparateAttribute (1UL)
- #define SPU_PERIPHID_PERM_DMA_SeparateAttribute (2UL)
- #define SPU_PERIPHID_PERM_SECUREMAPPING_Pos (0UL)
- #define SPU_PERIPHID_PERM_SECUREMAPPING_Msk (0x3UL << SPU_PERIPHID_PERM_SECUREMAPPING_Pos)
- #define SPU_PERIPHID_PERM_SECUREMAPPING_NonSecure (0UL)
- #define SPU_PERIPHID_PERM_SECUREMAPPING_Secure (1UL)
- #define SPU_PERIPHID_PERM_SECUREMAPPING_UserSelectable (2UL)
- #define SPU_PERIPHID_PERM_SECUREMAPPING_Split (3UL)
- #define TAD_CLOCKSTART_START_Pos (0UL)
- #define TAD_CLOCKSTART_START_Msk (0x1UL << TAD_CLOCKSTART_START_Pos)
- #define TAD_CLOCKSTART_START_Start (1UL)
- #define TAD_CLOCKSTOP_STOP_Pos (0UL)
- #define TAD_CLOCKSTOP_STOP_Msk (0x1UL << TAD_CLOCKSTOP_STOP_Pos)
- #define TAD_CLOCKSTOP_STOP_Stop (1UL)
- #define TAD_ENABLE_ENABLE_Pos (0UL)
- #define TAD_ENABLE_ENABLE_Msk (0x1UL << TAD_ENABLE_ENABLE_Pos)
- #define TAD_ENABLE_ENABLE_DISABLED (0UL)
- #define TAD_ENABLE_ENABLE_ENABLED (1UL)
- #define TAD_PSEL_TRACECLK_CONNECT_Pos (31UL)
- #define TAD_PSEL_TRACECLK_CONNECT_Msk (0x1UL << TAD_PSEL_TRACECLK_CONNECT_Pos)
- #define TAD_PSEL_TRACECLK_CONNECT_Connected (0UL)
- #define TAD_PSEL_TRACECLK_CONNECT_Disconnected (1UL)
- #define TAD_PSEL_TRACECLK_PIN_Pos (0UL)
- #define TAD_PSEL_TRACECLK_PIN_Msk (0x1FUL << TAD_PSEL_TRACECLK_PIN_Pos)
- #define TAD_PSEL_TRACEDATA0_CONNECT_Pos (31UL)
- #define TAD_PSEL_TRACEDATA0_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA0_CONNECT_Pos)
- #define TAD_PSEL_TRACEDATA0_CONNECT_Connected (0UL)
- #define TAD_PSEL_TRACEDATA0_CONNECT_Disconnected (1UL)
- #define TAD_PSEL_TRACEDATA0_PIN_Pos (0UL)
- #define TAD_PSEL_TRACEDATA0_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA0_PIN_Pos)
- #define TAD_PSEL_TRACEDATA1_CONNECT_Pos (31UL)
- #define TAD_PSEL_TRACEDATA1_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA1_CONNECT_Pos)
- #define TAD_PSEL_TRACEDATA1_CONNECT_Connected (0UL)
- #define TAD_PSEL_TRACEDATA1_CONNECT_Disconnected (1UL)
- #define TAD_PSEL_TRACEDATA1_PIN_Pos (0UL)
- #define TAD_PSEL_TRACEDATA1_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA1_PIN_Pos)
- #define TAD_PSEL_TRACEDATA2_CONNECT_Pos (31UL)
- #define TAD_PSEL_TRACEDATA2_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA2_CONNECT_Pos)
- #define TAD_PSEL_TRACEDATA2_CONNECT_Connected (0UL)
- #define TAD_PSEL_TRACEDATA2_CONNECT_Disconnected (1UL)
- #define TAD_PSEL_TRACEDATA2_PIN_Pos (0UL)
- #define TAD_PSEL_TRACEDATA2_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA2_PIN_Pos)
- #define TAD_PSEL_TRACEDATA3_CONNECT_Pos (31UL)
- #define TAD_PSEL_TRACEDATA3_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA3_CONNECT_Pos)
- #define TAD_PSEL_TRACEDATA3_CONNECT_Connected (0UL)
- #define TAD_PSEL_TRACEDATA3_CONNECT_Disconnected (1UL)
- #define TAD_PSEL_TRACEDATA3_PIN_Pos (0UL)
- #define TAD_PSEL_TRACEDATA3_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA3_PIN_Pos)
- #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos (0UL)
- #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Msk (0x3UL << TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos)
- #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz (0UL)
- #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_16MHz (1UL)
- #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_8MHz (2UL)
- #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_4MHz (3UL)
- #define TIMER_TASKS_START_TASKS_START_Pos (0UL)
- #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos)
- #define TIMER_TASKS_START_TASKS_START_Trigger (1UL)
- #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos)
- #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL)
- #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos)
- #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL)
- #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL)
- #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos)
- #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL)
- #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL)
- #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos)
- #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL)
- #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL)
- #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos)
- #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL)
- #define TIMER_SUBSCRIBE_START_EN_Pos (31UL)
- #define TIMER_SUBSCRIBE_START_EN_Msk (0x1UL << TIMER_SUBSCRIBE_START_EN_Pos)
- #define TIMER_SUBSCRIBE_START_EN_Disabled (0UL)
- #define TIMER_SUBSCRIBE_START_EN_Enabled (1UL)
- #define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos)
- #define TIMER_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define TIMER_SUBSCRIBE_STOP_EN_Msk (0x1UL << TIMER_SUBSCRIBE_STOP_EN_Pos)
- #define TIMER_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define TIMER_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos)
- #define TIMER_SUBSCRIBE_COUNT_EN_Pos (31UL)
- #define TIMER_SUBSCRIBE_COUNT_EN_Msk (0x1UL << TIMER_SUBSCRIBE_COUNT_EN_Pos)
- #define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0UL)
- #define TIMER_SUBSCRIBE_COUNT_EN_Enabled (1UL)
- #define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL)
- #define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos)
- #define TIMER_SUBSCRIBE_CLEAR_EN_Pos (31UL)
- #define TIMER_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CLEAR_EN_Pos)
- #define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0UL)
- #define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (1UL)
- #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL)
- #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos)
- #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos (31UL)
- #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Msk (0x1UL << TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos)
- #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0UL)
- #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (1UL)
- #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos (0UL)
- #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos)
- #define TIMER_SUBSCRIBE_CAPTURE_EN_Pos (31UL)
- #define TIMER_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CAPTURE_EN_Pos)
- #define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0UL)
- #define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (1UL)
- #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL)
- #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos)
- #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL)
- #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos)
- #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL)
- #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL)
- #define TIMER_PUBLISH_COMPARE_EN_Pos (31UL)
- #define TIMER_PUBLISH_COMPARE_EN_Msk (0x1UL << TIMER_PUBLISH_COMPARE_EN_Pos)
- #define TIMER_PUBLISH_COMPARE_EN_Disabled (0UL)
- #define TIMER_PUBLISH_COMPARE_EN_Enabled (1UL)
- #define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL)
- #define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos)
- #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL)
- #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos)
- #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL)
- #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos)
- #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL)
- #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos)
- #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL)
- #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos)
- #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL)
- #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos)
- #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL)
- #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos)
- #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL)
- #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos)
- #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL)
- #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos)
- #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL)
- #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos)
- #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL)
- #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos)
- #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL)
- #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos)
- #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL)
- #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL)
- #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos)
- #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL)
- #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL)
- #define TIMER_INTENSET_COMPARE5_Pos (21UL)
- #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos)
- #define TIMER_INTENSET_COMPARE5_Disabled (0UL)
- #define TIMER_INTENSET_COMPARE5_Enabled (1UL)
- #define TIMER_INTENSET_COMPARE5_Set (1UL)
- #define TIMER_INTENSET_COMPARE4_Pos (20UL)
- #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos)
- #define TIMER_INTENSET_COMPARE4_Disabled (0UL)
- #define TIMER_INTENSET_COMPARE4_Enabled (1UL)
- #define TIMER_INTENSET_COMPARE4_Set (1UL)
- #define TIMER_INTENSET_COMPARE3_Pos (19UL)
- #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos)
- #define TIMER_INTENSET_COMPARE3_Disabled (0UL)
- #define TIMER_INTENSET_COMPARE3_Enabled (1UL)
- #define TIMER_INTENSET_COMPARE3_Set (1UL)
- #define TIMER_INTENSET_COMPARE2_Pos (18UL)
- #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos)
- #define TIMER_INTENSET_COMPARE2_Disabled (0UL)
- #define TIMER_INTENSET_COMPARE2_Enabled (1UL)
- #define TIMER_INTENSET_COMPARE2_Set (1UL)
- #define TIMER_INTENSET_COMPARE1_Pos (17UL)
- #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos)
- #define TIMER_INTENSET_COMPARE1_Disabled (0UL)
- #define TIMER_INTENSET_COMPARE1_Enabled (1UL)
- #define TIMER_INTENSET_COMPARE1_Set (1UL)
- #define TIMER_INTENSET_COMPARE0_Pos (16UL)
- #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos)
- #define TIMER_INTENSET_COMPARE0_Disabled (0UL)
- #define TIMER_INTENSET_COMPARE0_Enabled (1UL)
- #define TIMER_INTENSET_COMPARE0_Set (1UL)
- #define TIMER_INTENCLR_COMPARE5_Pos (21UL)
- #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos)
- #define TIMER_INTENCLR_COMPARE5_Disabled (0UL)
- #define TIMER_INTENCLR_COMPARE5_Enabled (1UL)
- #define TIMER_INTENCLR_COMPARE5_Clear (1UL)
- #define TIMER_INTENCLR_COMPARE4_Pos (20UL)
- #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos)
- #define TIMER_INTENCLR_COMPARE4_Disabled (0UL)
- #define TIMER_INTENCLR_COMPARE4_Enabled (1UL)
- #define TIMER_INTENCLR_COMPARE4_Clear (1UL)
- #define TIMER_INTENCLR_COMPARE3_Pos (19UL)
- #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos)
- #define TIMER_INTENCLR_COMPARE3_Disabled (0UL)
- #define TIMER_INTENCLR_COMPARE3_Enabled (1UL)
- #define TIMER_INTENCLR_COMPARE3_Clear (1UL)
- #define TIMER_INTENCLR_COMPARE2_Pos (18UL)
- #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos)
- #define TIMER_INTENCLR_COMPARE2_Disabled (0UL)
- #define TIMER_INTENCLR_COMPARE2_Enabled (1UL)
- #define TIMER_INTENCLR_COMPARE2_Clear (1UL)
- #define TIMER_INTENCLR_COMPARE1_Pos (17UL)
- #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos)
- #define TIMER_INTENCLR_COMPARE1_Disabled (0UL)
- #define TIMER_INTENCLR_COMPARE1_Enabled (1UL)
- #define TIMER_INTENCLR_COMPARE1_Clear (1UL)
- #define TIMER_INTENCLR_COMPARE0_Pos (16UL)
- #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos)
- #define TIMER_INTENCLR_COMPARE0_Disabled (0UL)
- #define TIMER_INTENCLR_COMPARE0_Enabled (1UL)
- #define TIMER_INTENCLR_COMPARE0_Clear (1UL)
- #define TIMER_MODE_MODE_Pos (0UL)
- #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos)
- #define TIMER_MODE_MODE_Timer (0UL)
- #define TIMER_MODE_MODE_Counter (1UL)
- #define TIMER_MODE_MODE_LowPowerCounter (2UL)
- #define TIMER_BITMODE_BITMODE_Pos (0UL)
- #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos)
- #define TIMER_BITMODE_BITMODE_16Bit (0UL)
- #define TIMER_BITMODE_BITMODE_08Bit (1UL)
- #define TIMER_BITMODE_BITMODE_24Bit (2UL)
- #define TIMER_BITMODE_BITMODE_32Bit (3UL)
- #define TIMER_PRESCALER_PRESCALER_Pos (0UL)
- #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos)
- #define TIMER_ONESHOTEN_ONESHOTEN_Pos (0UL)
- #define TIMER_ONESHOTEN_ONESHOTEN_Msk (0x1UL << TIMER_ONESHOTEN_ONESHOTEN_Pos)
- #define TIMER_ONESHOTEN_ONESHOTEN_Disable (0UL)
- #define TIMER_ONESHOTEN_ONESHOTEN_Enable (1UL)
- #define TIMER_CC_CC_Pos (0UL)
- #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos)
- #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL)
- #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos)
- #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL)
- #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL)
- #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos)
- #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL)
- #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos)
- #define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL)
- #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos)
- #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL)
- #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL)
- #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos)
- #define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL)
- #define TWIM_SUBSCRIBE_STARTRX_EN_Pos (31UL)
- #define TWIM_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTRX_EN_Pos)
- #define TWIM_SUBSCRIBE_STARTRX_EN_Disabled (0UL)
- #define TWIM_SUBSCRIBE_STARTRX_EN_Enabled (1UL)
- #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL)
- #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFUL << TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos)
- #define TWIM_SUBSCRIBE_STARTTX_EN_Pos (31UL)
- #define TWIM_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTTX_EN_Pos)
- #define TWIM_SUBSCRIBE_STARTTX_EN_Disabled (0UL)
- #define TWIM_SUBSCRIBE_STARTTX_EN_Enabled (1UL)
- #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL)
- #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFUL << TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos)
- #define TWIM_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define TWIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STOP_EN_Pos)
- #define TWIM_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define TWIM_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define TWIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define TWIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << TWIM_SUBSCRIBE_STOP_CHIDX_Pos)
- #define TWIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL)
- #define TWIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIM_SUBSCRIBE_SUSPEND_EN_Pos)
- #define TWIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL)
- #define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL)
- #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL)
- #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFUL << TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos)
- #define TWIM_SUBSCRIBE_RESUME_EN_Pos (31UL)
- #define TWIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIM_SUBSCRIBE_RESUME_EN_Pos)
- #define TWIM_SUBSCRIBE_RESUME_EN_Disabled (0UL)
- #define TWIM_SUBSCRIBE_RESUME_EN_Enabled (1UL)
- #define TWIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL)
- #define TWIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFUL << TWIM_SUBSCRIBE_RESUME_CHIDX_Pos)
- #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL)
- #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos)
- #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL)
- #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL)
- #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)
- #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos)
- #define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL)
- #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL)
- #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL)
- #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos)
- #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL)
- #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL)
- #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL)
- #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos)
- #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL)
- #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL)
- #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL)
- #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos)
- #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL)
- #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL)
- #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL)
- #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos)
- #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL)
- #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL)
- #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL)
- #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos)
- #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL)
- #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL)
- #define TWIM_PUBLISH_STOPPED_EN_Pos (31UL)
- #define TWIM_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIM_PUBLISH_STOPPED_EN_Pos)
- #define TWIM_PUBLISH_STOPPED_EN_Disabled (0UL)
- #define TWIM_PUBLISH_STOPPED_EN_Enabled (1UL)
- #define TWIM_PUBLISH_STOPPED_CHIDX_Pos (0UL)
- #define TWIM_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << TWIM_PUBLISH_STOPPED_CHIDX_Pos)
- #define TWIM_PUBLISH_ERROR_EN_Pos (31UL)
- #define TWIM_PUBLISH_ERROR_EN_Msk (0x1UL << TWIM_PUBLISH_ERROR_EN_Pos)
- #define TWIM_PUBLISH_ERROR_EN_Disabled (0UL)
- #define TWIM_PUBLISH_ERROR_EN_Enabled (1UL)
- #define TWIM_PUBLISH_ERROR_CHIDX_Pos (0UL)
- #define TWIM_PUBLISH_ERROR_CHIDX_Msk (0xFUL << TWIM_PUBLISH_ERROR_CHIDX_Pos)
- #define TWIM_PUBLISH_SUSPENDED_EN_Pos (31UL)
- #define TWIM_PUBLISH_SUSPENDED_EN_Msk (0x1UL << TWIM_PUBLISH_SUSPENDED_EN_Pos)
- #define TWIM_PUBLISH_SUSPENDED_EN_Disabled (0UL)
- #define TWIM_PUBLISH_SUSPENDED_EN_Enabled (1UL)
- #define TWIM_PUBLISH_SUSPENDED_CHIDX_Pos (0UL)
- #define TWIM_PUBLISH_SUSPENDED_CHIDX_Msk (0xFUL << TWIM_PUBLISH_SUSPENDED_CHIDX_Pos)
- #define TWIM_PUBLISH_RXSTARTED_EN_Pos (31UL)
- #define TWIM_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_RXSTARTED_EN_Pos)
- #define TWIM_PUBLISH_RXSTARTED_EN_Disabled (0UL)
- #define TWIM_PUBLISH_RXSTARTED_EN_Enabled (1UL)
- #define TWIM_PUBLISH_RXSTARTED_CHIDX_Pos (0UL)
- #define TWIM_PUBLISH_RXSTARTED_CHIDX_Msk (0xFUL << TWIM_PUBLISH_RXSTARTED_CHIDX_Pos)
- #define TWIM_PUBLISH_TXSTARTED_EN_Pos (31UL)
- #define TWIM_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_TXSTARTED_EN_Pos)
- #define TWIM_PUBLISH_TXSTARTED_EN_Disabled (0UL)
- #define TWIM_PUBLISH_TXSTARTED_EN_Enabled (1UL)
- #define TWIM_PUBLISH_TXSTARTED_CHIDX_Pos (0UL)
- #define TWIM_PUBLISH_TXSTARTED_CHIDX_Msk (0xFUL << TWIM_PUBLISH_TXSTARTED_CHIDX_Pos)
- #define TWIM_PUBLISH_LASTRX_EN_Pos (31UL)
- #define TWIM_PUBLISH_LASTRX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTRX_EN_Pos)
- #define TWIM_PUBLISH_LASTRX_EN_Disabled (0UL)
- #define TWIM_PUBLISH_LASTRX_EN_Enabled (1UL)
- #define TWIM_PUBLISH_LASTRX_CHIDX_Pos (0UL)
- #define TWIM_PUBLISH_LASTRX_CHIDX_Msk (0xFUL << TWIM_PUBLISH_LASTRX_CHIDX_Pos)
- #define TWIM_PUBLISH_LASTTX_EN_Pos (31UL)
- #define TWIM_PUBLISH_LASTTX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTTX_EN_Pos)
- #define TWIM_PUBLISH_LASTTX_EN_Disabled (0UL)
- #define TWIM_PUBLISH_LASTTX_EN_Enabled (1UL)
- #define TWIM_PUBLISH_LASTTX_CHIDX_Pos (0UL)
- #define TWIM_PUBLISH_LASTTX_CHIDX_Msk (0xFUL << TWIM_PUBLISH_LASTTX_CHIDX_Pos)
- #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL)
- #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos)
- #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL)
- #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL)
- #define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL)
- #define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos)
- #define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL)
- #define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL)
- #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL)
- #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos)
- #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL)
- #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL)
- #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL)
- #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos)
- #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL)
- #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL)
- #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL)
- #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos)
- #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL)
- #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL)
- #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL)
- #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos)
- #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL)
- #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL)
- #define TWIM_INTEN_LASTTX_Pos (24UL)
- #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos)
- #define TWIM_INTEN_LASTTX_Disabled (0UL)
- #define TWIM_INTEN_LASTTX_Enabled (1UL)
- #define TWIM_INTEN_LASTRX_Pos (23UL)
- #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos)
- #define TWIM_INTEN_LASTRX_Disabled (0UL)
- #define TWIM_INTEN_LASTRX_Enabled (1UL)
- #define TWIM_INTEN_TXSTARTED_Pos (20UL)
- #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos)
- #define TWIM_INTEN_TXSTARTED_Disabled (0UL)
- #define TWIM_INTEN_TXSTARTED_Enabled (1UL)
- #define TWIM_INTEN_RXSTARTED_Pos (19UL)
- #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos)
- #define TWIM_INTEN_RXSTARTED_Disabled (0UL)
- #define TWIM_INTEN_RXSTARTED_Enabled (1UL)
- #define TWIM_INTEN_SUSPENDED_Pos (18UL)
- #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos)
- #define TWIM_INTEN_SUSPENDED_Disabled (0UL)
- #define TWIM_INTEN_SUSPENDED_Enabled (1UL)
- #define TWIM_INTEN_ERROR_Pos (9UL)
- #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos)
- #define TWIM_INTEN_ERROR_Disabled (0UL)
- #define TWIM_INTEN_ERROR_Enabled (1UL)
- #define TWIM_INTEN_STOPPED_Pos (1UL)
- #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos)
- #define TWIM_INTEN_STOPPED_Disabled (0UL)
- #define TWIM_INTEN_STOPPED_Enabled (1UL)
- #define TWIM_INTENSET_LASTTX_Pos (24UL)
- #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos)
- #define TWIM_INTENSET_LASTTX_Disabled (0UL)
- #define TWIM_INTENSET_LASTTX_Enabled (1UL)
- #define TWIM_INTENSET_LASTTX_Set (1UL)
- #define TWIM_INTENSET_LASTRX_Pos (23UL)
- #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos)
- #define TWIM_INTENSET_LASTRX_Disabled (0UL)
- #define TWIM_INTENSET_LASTRX_Enabled (1UL)
- #define TWIM_INTENSET_LASTRX_Set (1UL)
- #define TWIM_INTENSET_TXSTARTED_Pos (20UL)
- #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos)
- #define TWIM_INTENSET_TXSTARTED_Disabled (0UL)
- #define TWIM_INTENSET_TXSTARTED_Enabled (1UL)
- #define TWIM_INTENSET_TXSTARTED_Set (1UL)
- #define TWIM_INTENSET_RXSTARTED_Pos (19UL)
- #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos)
- #define TWIM_INTENSET_RXSTARTED_Disabled (0UL)
- #define TWIM_INTENSET_RXSTARTED_Enabled (1UL)
- #define TWIM_INTENSET_RXSTARTED_Set (1UL)
- #define TWIM_INTENSET_SUSPENDED_Pos (18UL)
- #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos)
- #define TWIM_INTENSET_SUSPENDED_Disabled (0UL)
- #define TWIM_INTENSET_SUSPENDED_Enabled (1UL)
- #define TWIM_INTENSET_SUSPENDED_Set (1UL)
- #define TWIM_INTENSET_ERROR_Pos (9UL)
- #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos)
- #define TWIM_INTENSET_ERROR_Disabled (0UL)
- #define TWIM_INTENSET_ERROR_Enabled (1UL)
- #define TWIM_INTENSET_ERROR_Set (1UL)
- #define TWIM_INTENSET_STOPPED_Pos (1UL)
- #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos)
- #define TWIM_INTENSET_STOPPED_Disabled (0UL)
- #define TWIM_INTENSET_STOPPED_Enabled (1UL)
- #define TWIM_INTENSET_STOPPED_Set (1UL)
- #define TWIM_INTENCLR_LASTTX_Pos (24UL)
- #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos)
- #define TWIM_INTENCLR_LASTTX_Disabled (0UL)
- #define TWIM_INTENCLR_LASTTX_Enabled (1UL)
- #define TWIM_INTENCLR_LASTTX_Clear (1UL)
- #define TWIM_INTENCLR_LASTRX_Pos (23UL)
- #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos)
- #define TWIM_INTENCLR_LASTRX_Disabled (0UL)
- #define TWIM_INTENCLR_LASTRX_Enabled (1UL)
- #define TWIM_INTENCLR_LASTRX_Clear (1UL)
- #define TWIM_INTENCLR_TXSTARTED_Pos (20UL)
- #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos)
- #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL)
- #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL)
- #define TWIM_INTENCLR_TXSTARTED_Clear (1UL)
- #define TWIM_INTENCLR_RXSTARTED_Pos (19UL)
- #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos)
- #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL)
- #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL)
- #define TWIM_INTENCLR_RXSTARTED_Clear (1UL)
- #define TWIM_INTENCLR_SUSPENDED_Pos (18UL)
- #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos)
- #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL)
- #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL)
- #define TWIM_INTENCLR_SUSPENDED_Clear (1UL)
- #define TWIM_INTENCLR_ERROR_Pos (9UL)
- #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos)
- #define TWIM_INTENCLR_ERROR_Disabled (0UL)
- #define TWIM_INTENCLR_ERROR_Enabled (1UL)
- #define TWIM_INTENCLR_ERROR_Clear (1UL)
- #define TWIM_INTENCLR_STOPPED_Pos (1UL)
- #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos)
- #define TWIM_INTENCLR_STOPPED_Disabled (0UL)
- #define TWIM_INTENCLR_STOPPED_Enabled (1UL)
- #define TWIM_INTENCLR_STOPPED_Clear (1UL)
- #define TWIM_ERRORSRC_DNACK_Pos (2UL)
- #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos)
- #define TWIM_ERRORSRC_DNACK_NotReceived (0UL)
- #define TWIM_ERRORSRC_DNACK_Received (1UL)
- #define TWIM_ERRORSRC_ANACK_Pos (1UL)
- #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos)
- #define TWIM_ERRORSRC_ANACK_NotReceived (0UL)
- #define TWIM_ERRORSRC_ANACK_Received (1UL)
- #define TWIM_ERRORSRC_OVERRUN_Pos (0UL)
- #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos)
- #define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL)
- #define TWIM_ERRORSRC_OVERRUN_Received (1UL)
- #define TWIM_ENABLE_ENABLE_Pos (0UL)
- #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos)
- #define TWIM_ENABLE_ENABLE_Disabled (0UL)
- #define TWIM_ENABLE_ENABLE_Enabled (6UL)
- #define TWIM_PSEL_SCL_CONNECT_Pos (31UL)
- #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos)
- #define TWIM_PSEL_SCL_CONNECT_Connected (0UL)
- #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL)
- #define TWIM_PSEL_SCL_PIN_Pos (0UL)
- #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos)
- #define TWIM_PSEL_SDA_CONNECT_Pos (31UL)
- #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos)
- #define TWIM_PSEL_SDA_CONNECT_Connected (0UL)
- #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL)
- #define TWIM_PSEL_SDA_PIN_Pos (0UL)
- #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos)
- #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL)
- #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos)
- #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL)
- #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL)
- #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL)
- #define TWIM_RXD_PTR_PTR_Pos (0UL)
- #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos)
- #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL)
- #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos)
- #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL)
- #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos)
- #define TWIM_RXD_LIST_LIST_Pos (0UL)
- #define TWIM_RXD_LIST_LIST_Msk (0x3UL << TWIM_RXD_LIST_LIST_Pos)
- #define TWIM_RXD_LIST_LIST_Disabled (0UL)
- #define TWIM_RXD_LIST_LIST_ArrayList (1UL)
- #define TWIM_TXD_PTR_PTR_Pos (0UL)
- #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos)
- #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL)
- #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos)
- #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL)
- #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos)
- #define TWIM_TXD_LIST_LIST_Pos (0UL)
- #define TWIM_TXD_LIST_LIST_Msk (0x3UL << TWIM_TXD_LIST_LIST_Pos)
- #define TWIM_TXD_LIST_LIST_Disabled (0UL)
- #define TWIM_TXD_LIST_LIST_ArrayList (1UL)
- #define TWIM_ADDRESS_ADDRESS_Pos (0UL)
- #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos)
- #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL)
- #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos)
- #define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL)
- #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL)
- #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos)
- #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL)
- #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL)
- #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos)
- #define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL)
- #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL)
- #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos)
- #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL)
- #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL)
- #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos)
- #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL)
- #define TWIS_SUBSCRIBE_STOP_EN_Pos (31UL)
- #define TWIS_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIS_SUBSCRIBE_STOP_EN_Pos)
- #define TWIS_SUBSCRIBE_STOP_EN_Disabled (0UL)
- #define TWIS_SUBSCRIBE_STOP_EN_Enabled (1UL)
- #define TWIS_SUBSCRIBE_STOP_CHIDX_Pos (0UL)
- #define TWIS_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << TWIS_SUBSCRIBE_STOP_CHIDX_Pos)
- #define TWIS_SUBSCRIBE_SUSPEND_EN_Pos (31UL)
- #define TWIS_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIS_SUBSCRIBE_SUSPEND_EN_Pos)
- #define TWIS_SUBSCRIBE_SUSPEND_EN_Disabled (0UL)
- #define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (1UL)
- #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL)
- #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFUL << TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos)
- #define TWIS_SUBSCRIBE_RESUME_EN_Pos (31UL)
- #define TWIS_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIS_SUBSCRIBE_RESUME_EN_Pos)
- #define TWIS_SUBSCRIBE_RESUME_EN_Disabled (0UL)
- #define TWIS_SUBSCRIBE_RESUME_EN_Enabled (1UL)
- #define TWIS_SUBSCRIBE_RESUME_CHIDX_Pos (0UL)
- #define TWIS_SUBSCRIBE_RESUME_CHIDX_Msk (0xFUL << TWIS_SUBSCRIBE_RESUME_CHIDX_Pos)
- #define TWIS_SUBSCRIBE_PREPARERX_EN_Pos (31UL)
- #define TWIS_SUBSCRIBE_PREPARERX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARERX_EN_Pos)
- #define TWIS_SUBSCRIBE_PREPARERX_EN_Disabled (0UL)
- #define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (1UL)
- #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos (0UL)
- #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Msk (0xFUL << TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos)
- #define TWIS_SUBSCRIBE_PREPARETX_EN_Pos (31UL)
- #define TWIS_SUBSCRIBE_PREPARETX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARETX_EN_Pos)
- #define TWIS_SUBSCRIBE_PREPARETX_EN_Disabled (0UL)
- #define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (1UL)
- #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos (0UL)
- #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Msk (0xFUL << TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos)
- #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL)
- #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos)
- #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL)
- #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL)
- #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)
- #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos)
- #define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL)
- #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL)
- #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL)
- #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos)
- #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL)
- #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL)
- #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL)
- #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos)
- #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL)
- #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL)
- #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL)
- #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos)
- #define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL)
- #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL)
- #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL)
- #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos)
- #define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL)
- #define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL)
- #define TWIS_PUBLISH_STOPPED_EN_Pos (31UL)
- #define TWIS_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIS_PUBLISH_STOPPED_EN_Pos)
- #define TWIS_PUBLISH_STOPPED_EN_Disabled (0UL)
- #define TWIS_PUBLISH_STOPPED_EN_Enabled (1UL)
- #define TWIS_PUBLISH_STOPPED_CHIDX_Pos (0UL)
- #define TWIS_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << TWIS_PUBLISH_STOPPED_CHIDX_Pos)
- #define TWIS_PUBLISH_ERROR_EN_Pos (31UL)
- #define TWIS_PUBLISH_ERROR_EN_Msk (0x1UL << TWIS_PUBLISH_ERROR_EN_Pos)
- #define TWIS_PUBLISH_ERROR_EN_Disabled (0UL)
- #define TWIS_PUBLISH_ERROR_EN_Enabled (1UL)
- #define TWIS_PUBLISH_ERROR_CHIDX_Pos (0UL)
- #define TWIS_PUBLISH_ERROR_CHIDX_Msk (0xFUL << TWIS_PUBLISH_ERROR_CHIDX_Pos)
- #define TWIS_PUBLISH_RXSTARTED_EN_Pos (31UL)
- #define TWIS_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_RXSTARTED_EN_Pos)
- #define TWIS_PUBLISH_RXSTARTED_EN_Disabled (0UL)
- #define TWIS_PUBLISH_RXSTARTED_EN_Enabled (1UL)
- #define TWIS_PUBLISH_RXSTARTED_CHIDX_Pos (0UL)
- #define TWIS_PUBLISH_RXSTARTED_CHIDX_Msk (0xFUL << TWIS_PUBLISH_RXSTARTED_CHIDX_Pos)
- #define TWIS_PUBLISH_TXSTARTED_EN_Pos (31UL)
- #define TWIS_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_TXSTARTED_EN_Pos)
- #define TWIS_PUBLISH_TXSTARTED_EN_Disabled (0UL)
- #define TWIS_PUBLISH_TXSTARTED_EN_Enabled (1UL)
- #define TWIS_PUBLISH_TXSTARTED_CHIDX_Pos (0UL)
- #define TWIS_PUBLISH_TXSTARTED_CHIDX_Msk (0xFUL << TWIS_PUBLISH_TXSTARTED_CHIDX_Pos)
- #define TWIS_PUBLISH_WRITE_EN_Pos (31UL)
- #define TWIS_PUBLISH_WRITE_EN_Msk (0x1UL << TWIS_PUBLISH_WRITE_EN_Pos)
- #define TWIS_PUBLISH_WRITE_EN_Disabled (0UL)
- #define TWIS_PUBLISH_WRITE_EN_Enabled (1UL)
- #define TWIS_PUBLISH_WRITE_CHIDX_Pos (0UL)
- #define TWIS_PUBLISH_WRITE_CHIDX_Msk (0xFUL << TWIS_PUBLISH_WRITE_CHIDX_Pos)
- #define TWIS_PUBLISH_READ_EN_Pos (31UL)
- #define TWIS_PUBLISH_READ_EN_Msk (0x1UL << TWIS_PUBLISH_READ_EN_Pos)
- #define TWIS_PUBLISH_READ_EN_Disabled (0UL)
- #define TWIS_PUBLISH_READ_EN_Enabled (1UL)
- #define TWIS_PUBLISH_READ_CHIDX_Pos (0UL)
- #define TWIS_PUBLISH_READ_CHIDX_Msk (0xFUL << TWIS_PUBLISH_READ_CHIDX_Pos)
- #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL)
- #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos)
- #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL)
- #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL)
- #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL)
- #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos)
- #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL)
- #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL)
- #define TWIS_INTEN_READ_Pos (26UL)
- #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos)
- #define TWIS_INTEN_READ_Disabled (0UL)
- #define TWIS_INTEN_READ_Enabled (1UL)
- #define TWIS_INTEN_WRITE_Pos (25UL)
- #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos)
- #define TWIS_INTEN_WRITE_Disabled (0UL)
- #define TWIS_INTEN_WRITE_Enabled (1UL)
- #define TWIS_INTEN_TXSTARTED_Pos (20UL)
- #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos)
- #define TWIS_INTEN_TXSTARTED_Disabled (0UL)
- #define TWIS_INTEN_TXSTARTED_Enabled (1UL)
- #define TWIS_INTEN_RXSTARTED_Pos (19UL)
- #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos)
- #define TWIS_INTEN_RXSTARTED_Disabled (0UL)
- #define TWIS_INTEN_RXSTARTED_Enabled (1UL)
- #define TWIS_INTEN_ERROR_Pos (9UL)
- #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos)
- #define TWIS_INTEN_ERROR_Disabled (0UL)
- #define TWIS_INTEN_ERROR_Enabled (1UL)
- #define TWIS_INTEN_STOPPED_Pos (1UL)
- #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos)
- #define TWIS_INTEN_STOPPED_Disabled (0UL)
- #define TWIS_INTEN_STOPPED_Enabled (1UL)
- #define TWIS_INTENSET_READ_Pos (26UL)
- #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos)
- #define TWIS_INTENSET_READ_Disabled (0UL)
- #define TWIS_INTENSET_READ_Enabled (1UL)
- #define TWIS_INTENSET_READ_Set (1UL)
- #define TWIS_INTENSET_WRITE_Pos (25UL)
- #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos)
- #define TWIS_INTENSET_WRITE_Disabled (0UL)
- #define TWIS_INTENSET_WRITE_Enabled (1UL)
- #define TWIS_INTENSET_WRITE_Set (1UL)
- #define TWIS_INTENSET_TXSTARTED_Pos (20UL)
- #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos)
- #define TWIS_INTENSET_TXSTARTED_Disabled (0UL)
- #define TWIS_INTENSET_TXSTARTED_Enabled (1UL)
- #define TWIS_INTENSET_TXSTARTED_Set (1UL)
- #define TWIS_INTENSET_RXSTARTED_Pos (19UL)
- #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos)
- #define TWIS_INTENSET_RXSTARTED_Disabled (0UL)
- #define TWIS_INTENSET_RXSTARTED_Enabled (1UL)
- #define TWIS_INTENSET_RXSTARTED_Set (1UL)
- #define TWIS_INTENSET_ERROR_Pos (9UL)
- #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos)
- #define TWIS_INTENSET_ERROR_Disabled (0UL)
- #define TWIS_INTENSET_ERROR_Enabled (1UL)
- #define TWIS_INTENSET_ERROR_Set (1UL)
- #define TWIS_INTENSET_STOPPED_Pos (1UL)
- #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos)
- #define TWIS_INTENSET_STOPPED_Disabled (0UL)
- #define TWIS_INTENSET_STOPPED_Enabled (1UL)
- #define TWIS_INTENSET_STOPPED_Set (1UL)
- #define TWIS_INTENCLR_READ_Pos (26UL)
- #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos)
- #define TWIS_INTENCLR_READ_Disabled (0UL)
- #define TWIS_INTENCLR_READ_Enabled (1UL)
- #define TWIS_INTENCLR_READ_Clear (1UL)
- #define TWIS_INTENCLR_WRITE_Pos (25UL)
- #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos)
- #define TWIS_INTENCLR_WRITE_Disabled (0UL)
- #define TWIS_INTENCLR_WRITE_Enabled (1UL)
- #define TWIS_INTENCLR_WRITE_Clear (1UL)
- #define TWIS_INTENCLR_TXSTARTED_Pos (20UL)
- #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos)
- #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL)
- #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL)
- #define TWIS_INTENCLR_TXSTARTED_Clear (1UL)
- #define TWIS_INTENCLR_RXSTARTED_Pos (19UL)
- #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos)
- #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL)
- #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL)
- #define TWIS_INTENCLR_RXSTARTED_Clear (1UL)
- #define TWIS_INTENCLR_ERROR_Pos (9UL)
- #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos)
- #define TWIS_INTENCLR_ERROR_Disabled (0UL)
- #define TWIS_INTENCLR_ERROR_Enabled (1UL)
- #define TWIS_INTENCLR_ERROR_Clear (1UL)
- #define TWIS_INTENCLR_STOPPED_Pos (1UL)
- #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos)
- #define TWIS_INTENCLR_STOPPED_Disabled (0UL)
- #define TWIS_INTENCLR_STOPPED_Enabled (1UL)
- #define TWIS_INTENCLR_STOPPED_Clear (1UL)
- #define TWIS_ERRORSRC_OVERREAD_Pos (3UL)
- #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos)
- #define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL)
- #define TWIS_ERRORSRC_OVERREAD_Detected (1UL)
- #define TWIS_ERRORSRC_DNACK_Pos (2UL)
- #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos)
- #define TWIS_ERRORSRC_DNACK_NotReceived (0UL)
- #define TWIS_ERRORSRC_DNACK_Received (1UL)
- #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL)
- #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos)
- #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL)
- #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL)
- #define TWIS_MATCH_MATCH_Pos (0UL)
- #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos)
- #define TWIS_ENABLE_ENABLE_Pos (0UL)
- #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos)
- #define TWIS_ENABLE_ENABLE_Disabled (0UL)
- #define TWIS_ENABLE_ENABLE_Enabled (9UL)
- #define TWIS_PSEL_SCL_CONNECT_Pos (31UL)
- #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos)
- #define TWIS_PSEL_SCL_CONNECT_Connected (0UL)
- #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL)
- #define TWIS_PSEL_SCL_PIN_Pos (0UL)
- #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos)
- #define TWIS_PSEL_SDA_CONNECT_Pos (31UL)
- #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos)
- #define TWIS_PSEL_SDA_CONNECT_Connected (0UL)
- #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL)
- #define TWIS_PSEL_SDA_PIN_Pos (0UL)
- #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos)
- #define TWIS_RXD_PTR_PTR_Pos (0UL)
- #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos)
- #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL)
- #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos)
- #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL)
- #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos)
- #define TWIS_RXD_LIST_LIST_Pos (0UL)
- #define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos)
- #define TWIS_RXD_LIST_LIST_Disabled (0UL)
- #define TWIS_RXD_LIST_LIST_ArrayList (1UL)
- #define TWIS_TXD_PTR_PTR_Pos (0UL)
- #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos)
- #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL)
- #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos)
- #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL)
- #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos)
- #define TWIS_TXD_LIST_LIST_Pos (0UL)
- #define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos)
- #define TWIS_TXD_LIST_LIST_Disabled (0UL)
- #define TWIS_TXD_LIST_LIST_ArrayList (1UL)
- #define TWIS_ADDRESS_ADDRESS_Pos (0UL)
- #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos)
- #define TWIS_CONFIG_ADDRESS1_Pos (1UL)
- #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos)
- #define TWIS_CONFIG_ADDRESS1_Disabled (0UL)
- #define TWIS_CONFIG_ADDRESS1_Enabled (1UL)
- #define TWIS_CONFIG_ADDRESS0_Pos (0UL)
- #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos)
- #define TWIS_CONFIG_ADDRESS0_Disabled (0UL)
- #define TWIS_CONFIG_ADDRESS0_Enabled (1UL)
- #define TWIS_ORC_ORC_Pos (0UL)
- #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos)
- #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL)
- #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos)
- #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL)
- #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL)
- #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos)
- #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL)
- #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL)
- #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos)
- #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL)
- #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL)
- #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos)
- #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL)
- #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL)
- #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos)
- #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL)
- #define UARTE_SUBSCRIBE_STARTRX_EN_Pos (31UL)
- #define UARTE_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTRX_EN_Pos)
- #define UARTE_SUBSCRIBE_STARTRX_EN_Disabled (0UL)
- #define UARTE_SUBSCRIBE_STARTRX_EN_Enabled (1UL)
- #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL)
- #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFUL << UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos)
- #define UARTE_SUBSCRIBE_STOPRX_EN_Pos (31UL)
- #define UARTE_SUBSCRIBE_STOPRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPRX_EN_Pos)
- #define UARTE_SUBSCRIBE_STOPRX_EN_Disabled (0UL)
- #define UARTE_SUBSCRIBE_STOPRX_EN_Enabled (1UL)
- #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos (0UL)
- #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Msk (0xFUL << UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos)
- #define UARTE_SUBSCRIBE_STARTTX_EN_Pos (31UL)
- #define UARTE_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTTX_EN_Pos)
- #define UARTE_SUBSCRIBE_STARTTX_EN_Disabled (0UL)
- #define UARTE_SUBSCRIBE_STARTTX_EN_Enabled (1UL)
- #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL)
- #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFUL << UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos)
- #define UARTE_SUBSCRIBE_STOPTX_EN_Pos (31UL)
- #define UARTE_SUBSCRIBE_STOPTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPTX_EN_Pos)
- #define UARTE_SUBSCRIBE_STOPTX_EN_Disabled (0UL)
- #define UARTE_SUBSCRIBE_STOPTX_EN_Enabled (1UL)
- #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos (0UL)
- #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Msk (0xFUL << UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos)
- #define UARTE_SUBSCRIBE_FLUSHRX_EN_Pos (31UL)
- #define UARTE_SUBSCRIBE_FLUSHRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_FLUSHRX_EN_Pos)
- #define UARTE_SUBSCRIBE_FLUSHRX_EN_Disabled (0UL)
- #define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (1UL)
- #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos (0UL)
- #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Msk (0xFUL << UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos)
- #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL)
- #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos)
- #define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL)
- #define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL)
- #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL)
- #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos)
- #define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL)
- #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL)
- #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL)
- #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos)
- #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL)
- #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL)
- #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL)
- #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos)
- #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL)
- #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL)
- #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL)
- #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos)
- #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL)
- #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL)
- #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL)
- #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos)
- #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL)
- #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL)
- #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)
- #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos)
- #define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL)
- #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL)
- #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL)
- #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos)
- #define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL)
- #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL)
- #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL)
- #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos)
- #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL)
- #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL)
- #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL)
- #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos)
- #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL)
- #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL)
- #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL)
- #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos)
- #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL)
- #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL)
- #define UARTE_PUBLISH_CTS_EN_Pos (31UL)
- #define UARTE_PUBLISH_CTS_EN_Msk (0x1UL << UARTE_PUBLISH_CTS_EN_Pos)
- #define UARTE_PUBLISH_CTS_EN_Disabled (0UL)
- #define UARTE_PUBLISH_CTS_EN_Enabled (1UL)
- #define UARTE_PUBLISH_CTS_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_CTS_CHIDX_Msk (0xFUL << UARTE_PUBLISH_CTS_CHIDX_Pos)
- #define UARTE_PUBLISH_NCTS_EN_Pos (31UL)
- #define UARTE_PUBLISH_NCTS_EN_Msk (0x1UL << UARTE_PUBLISH_NCTS_EN_Pos)
- #define UARTE_PUBLISH_NCTS_EN_Disabled (0UL)
- #define UARTE_PUBLISH_NCTS_EN_Enabled (1UL)
- #define UARTE_PUBLISH_NCTS_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_NCTS_CHIDX_Msk (0xFUL << UARTE_PUBLISH_NCTS_CHIDX_Pos)
- #define UARTE_PUBLISH_RXDRDY_EN_Pos (31UL)
- #define UARTE_PUBLISH_RXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_RXDRDY_EN_Pos)
- #define UARTE_PUBLISH_RXDRDY_EN_Disabled (0UL)
- #define UARTE_PUBLISH_RXDRDY_EN_Enabled (1UL)
- #define UARTE_PUBLISH_RXDRDY_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_RXDRDY_CHIDX_Msk (0xFUL << UARTE_PUBLISH_RXDRDY_CHIDX_Pos)
- #define UARTE_PUBLISH_ENDRX_EN_Pos (31UL)
- #define UARTE_PUBLISH_ENDRX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDRX_EN_Pos)
- #define UARTE_PUBLISH_ENDRX_EN_Disabled (0UL)
- #define UARTE_PUBLISH_ENDRX_EN_Enabled (1UL)
- #define UARTE_PUBLISH_ENDRX_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_ENDRX_CHIDX_Msk (0xFUL << UARTE_PUBLISH_ENDRX_CHIDX_Pos)
- #define UARTE_PUBLISH_TXDRDY_EN_Pos (31UL)
- #define UARTE_PUBLISH_TXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_TXDRDY_EN_Pos)
- #define UARTE_PUBLISH_TXDRDY_EN_Disabled (0UL)
- #define UARTE_PUBLISH_TXDRDY_EN_Enabled (1UL)
- #define UARTE_PUBLISH_TXDRDY_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_TXDRDY_CHIDX_Msk (0xFUL << UARTE_PUBLISH_TXDRDY_CHIDX_Pos)
- #define UARTE_PUBLISH_ENDTX_EN_Pos (31UL)
- #define UARTE_PUBLISH_ENDTX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDTX_EN_Pos)
- #define UARTE_PUBLISH_ENDTX_EN_Disabled (0UL)
- #define UARTE_PUBLISH_ENDTX_EN_Enabled (1UL)
- #define UARTE_PUBLISH_ENDTX_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_ENDTX_CHIDX_Msk (0xFUL << UARTE_PUBLISH_ENDTX_CHIDX_Pos)
- #define UARTE_PUBLISH_ERROR_EN_Pos (31UL)
- #define UARTE_PUBLISH_ERROR_EN_Msk (0x1UL << UARTE_PUBLISH_ERROR_EN_Pos)
- #define UARTE_PUBLISH_ERROR_EN_Disabled (0UL)
- #define UARTE_PUBLISH_ERROR_EN_Enabled (1UL)
- #define UARTE_PUBLISH_ERROR_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_ERROR_CHIDX_Msk (0xFUL << UARTE_PUBLISH_ERROR_CHIDX_Pos)
- #define UARTE_PUBLISH_RXTO_EN_Pos (31UL)
- #define UARTE_PUBLISH_RXTO_EN_Msk (0x1UL << UARTE_PUBLISH_RXTO_EN_Pos)
- #define UARTE_PUBLISH_RXTO_EN_Disabled (0UL)
- #define UARTE_PUBLISH_RXTO_EN_Enabled (1UL)
- #define UARTE_PUBLISH_RXTO_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_RXTO_CHIDX_Msk (0xFUL << UARTE_PUBLISH_RXTO_CHIDX_Pos)
- #define UARTE_PUBLISH_RXSTARTED_EN_Pos (31UL)
- #define UARTE_PUBLISH_RXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_RXSTARTED_EN_Pos)
- #define UARTE_PUBLISH_RXSTARTED_EN_Disabled (0UL)
- #define UARTE_PUBLISH_RXSTARTED_EN_Enabled (1UL)
- #define UARTE_PUBLISH_RXSTARTED_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_RXSTARTED_CHIDX_Msk (0xFUL << UARTE_PUBLISH_RXSTARTED_CHIDX_Pos)
- #define UARTE_PUBLISH_TXSTARTED_EN_Pos (31UL)
- #define UARTE_PUBLISH_TXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTARTED_EN_Pos)
- #define UARTE_PUBLISH_TXSTARTED_EN_Disabled (0UL)
- #define UARTE_PUBLISH_TXSTARTED_EN_Enabled (1UL)
- #define UARTE_PUBLISH_TXSTARTED_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_TXSTARTED_CHIDX_Msk (0xFUL << UARTE_PUBLISH_TXSTARTED_CHIDX_Pos)
- #define UARTE_PUBLISH_TXSTOPPED_EN_Pos (31UL)
- #define UARTE_PUBLISH_TXSTOPPED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTOPPED_EN_Pos)
- #define UARTE_PUBLISH_TXSTOPPED_EN_Disabled (0UL)
- #define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (1UL)
- #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos (0UL)
- #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Msk (0xFUL << UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos)
- #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL)
- #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos)
- #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL)
- #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL)
- #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL)
- #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos)
- #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL)
- #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL)
- #define UARTE_INTEN_TXSTOPPED_Pos (22UL)
- #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos)
- #define UARTE_INTEN_TXSTOPPED_Disabled (0UL)
- #define UARTE_INTEN_TXSTOPPED_Enabled (1UL)
- #define UARTE_INTEN_TXSTARTED_Pos (20UL)
- #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos)
- #define UARTE_INTEN_TXSTARTED_Disabled (0UL)
- #define UARTE_INTEN_TXSTARTED_Enabled (1UL)
- #define UARTE_INTEN_RXSTARTED_Pos (19UL)
- #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos)
- #define UARTE_INTEN_RXSTARTED_Disabled (0UL)
- #define UARTE_INTEN_RXSTARTED_Enabled (1UL)
- #define UARTE_INTEN_RXTO_Pos (17UL)
- #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos)
- #define UARTE_INTEN_RXTO_Disabled (0UL)
- #define UARTE_INTEN_RXTO_Enabled (1UL)
- #define UARTE_INTEN_ERROR_Pos (9UL)
- #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos)
- #define UARTE_INTEN_ERROR_Disabled (0UL)
- #define UARTE_INTEN_ERROR_Enabled (1UL)
- #define UARTE_INTEN_ENDTX_Pos (8UL)
- #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos)
- #define UARTE_INTEN_ENDTX_Disabled (0UL)
- #define UARTE_INTEN_ENDTX_Enabled (1UL)
- #define UARTE_INTEN_TXDRDY_Pos (7UL)
- #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos)
- #define UARTE_INTEN_TXDRDY_Disabled (0UL)
- #define UARTE_INTEN_TXDRDY_Enabled (1UL)
- #define UARTE_INTEN_ENDRX_Pos (4UL)
- #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos)
- #define UARTE_INTEN_ENDRX_Disabled (0UL)
- #define UARTE_INTEN_ENDRX_Enabled (1UL)
- #define UARTE_INTEN_RXDRDY_Pos (2UL)
- #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos)
- #define UARTE_INTEN_RXDRDY_Disabled (0UL)
- #define UARTE_INTEN_RXDRDY_Enabled (1UL)
- #define UARTE_INTEN_NCTS_Pos (1UL)
- #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos)
- #define UARTE_INTEN_NCTS_Disabled (0UL)
- #define UARTE_INTEN_NCTS_Enabled (1UL)
- #define UARTE_INTEN_CTS_Pos (0UL)
- #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos)
- #define UARTE_INTEN_CTS_Disabled (0UL)
- #define UARTE_INTEN_CTS_Enabled (1UL)
- #define UARTE_INTENSET_TXSTOPPED_Pos (22UL)
- #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos)
- #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL)
- #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL)
- #define UARTE_INTENSET_TXSTOPPED_Set (1UL)
- #define UARTE_INTENSET_TXSTARTED_Pos (20UL)
- #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos)
- #define UARTE_INTENSET_TXSTARTED_Disabled (0UL)
- #define UARTE_INTENSET_TXSTARTED_Enabled (1UL)
- #define UARTE_INTENSET_TXSTARTED_Set (1UL)
- #define UARTE_INTENSET_RXSTARTED_Pos (19UL)
- #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos)
- #define UARTE_INTENSET_RXSTARTED_Disabled (0UL)
- #define UARTE_INTENSET_RXSTARTED_Enabled (1UL)
- #define UARTE_INTENSET_RXSTARTED_Set (1UL)
- #define UARTE_INTENSET_RXTO_Pos (17UL)
- #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos)
- #define UARTE_INTENSET_RXTO_Disabled (0UL)
- #define UARTE_INTENSET_RXTO_Enabled (1UL)
- #define UARTE_INTENSET_RXTO_Set (1UL)
- #define UARTE_INTENSET_ERROR_Pos (9UL)
- #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos)
- #define UARTE_INTENSET_ERROR_Disabled (0UL)
- #define UARTE_INTENSET_ERROR_Enabled (1UL)
- #define UARTE_INTENSET_ERROR_Set (1UL)
- #define UARTE_INTENSET_ENDTX_Pos (8UL)
- #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos)
- #define UARTE_INTENSET_ENDTX_Disabled (0UL)
- #define UARTE_INTENSET_ENDTX_Enabled (1UL)
- #define UARTE_INTENSET_ENDTX_Set (1UL)
- #define UARTE_INTENSET_TXDRDY_Pos (7UL)
- #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos)
- #define UARTE_INTENSET_TXDRDY_Disabled (0UL)
- #define UARTE_INTENSET_TXDRDY_Enabled (1UL)
- #define UARTE_INTENSET_TXDRDY_Set (1UL)
- #define UARTE_INTENSET_ENDRX_Pos (4UL)
- #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos)
- #define UARTE_INTENSET_ENDRX_Disabled (0UL)
- #define UARTE_INTENSET_ENDRX_Enabled (1UL)
- #define UARTE_INTENSET_ENDRX_Set (1UL)
- #define UARTE_INTENSET_RXDRDY_Pos (2UL)
- #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos)
- #define UARTE_INTENSET_RXDRDY_Disabled (0UL)
- #define UARTE_INTENSET_RXDRDY_Enabled (1UL)
- #define UARTE_INTENSET_RXDRDY_Set (1UL)
- #define UARTE_INTENSET_NCTS_Pos (1UL)
- #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos)
- #define UARTE_INTENSET_NCTS_Disabled (0UL)
- #define UARTE_INTENSET_NCTS_Enabled (1UL)
- #define UARTE_INTENSET_NCTS_Set (1UL)
- #define UARTE_INTENSET_CTS_Pos (0UL)
- #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos)
- #define UARTE_INTENSET_CTS_Disabled (0UL)
- #define UARTE_INTENSET_CTS_Enabled (1UL)
- #define UARTE_INTENSET_CTS_Set (1UL)
- #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL)
- #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos)
- #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL)
- #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL)
- #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL)
- #define UARTE_INTENCLR_TXSTARTED_Pos (20UL)
- #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos)
- #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL)
- #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL)
- #define UARTE_INTENCLR_TXSTARTED_Clear (1UL)
- #define UARTE_INTENCLR_RXSTARTED_Pos (19UL)
- #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos)
- #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL)
- #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL)
- #define UARTE_INTENCLR_RXSTARTED_Clear (1UL)
- #define UARTE_INTENCLR_RXTO_Pos (17UL)
- #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos)
- #define UARTE_INTENCLR_RXTO_Disabled (0UL)
- #define UARTE_INTENCLR_RXTO_Enabled (1UL)
- #define UARTE_INTENCLR_RXTO_Clear (1UL)
- #define UARTE_INTENCLR_ERROR_Pos (9UL)
- #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos)
- #define UARTE_INTENCLR_ERROR_Disabled (0UL)
- #define UARTE_INTENCLR_ERROR_Enabled (1UL)
- #define UARTE_INTENCLR_ERROR_Clear (1UL)
- #define UARTE_INTENCLR_ENDTX_Pos (8UL)
- #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos)
- #define UARTE_INTENCLR_ENDTX_Disabled (0UL)
- #define UARTE_INTENCLR_ENDTX_Enabled (1UL)
- #define UARTE_INTENCLR_ENDTX_Clear (1UL)
- #define UARTE_INTENCLR_TXDRDY_Pos (7UL)
- #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos)
- #define UARTE_INTENCLR_TXDRDY_Disabled (0UL)
- #define UARTE_INTENCLR_TXDRDY_Enabled (1UL)
- #define UARTE_INTENCLR_TXDRDY_Clear (1UL)
- #define UARTE_INTENCLR_ENDRX_Pos (4UL)
- #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos)
- #define UARTE_INTENCLR_ENDRX_Disabled (0UL)
- #define UARTE_INTENCLR_ENDRX_Enabled (1UL)
- #define UARTE_INTENCLR_ENDRX_Clear (1UL)
- #define UARTE_INTENCLR_RXDRDY_Pos (2UL)
- #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos)
- #define UARTE_INTENCLR_RXDRDY_Disabled (0UL)
- #define UARTE_INTENCLR_RXDRDY_Enabled (1UL)
- #define UARTE_INTENCLR_RXDRDY_Clear (1UL)
- #define UARTE_INTENCLR_NCTS_Pos (1UL)
- #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos)
- #define UARTE_INTENCLR_NCTS_Disabled (0UL)
- #define UARTE_INTENCLR_NCTS_Enabled (1UL)
- #define UARTE_INTENCLR_NCTS_Clear (1UL)
- #define UARTE_INTENCLR_CTS_Pos (0UL)
- #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos)
- #define UARTE_INTENCLR_CTS_Disabled (0UL)
- #define UARTE_INTENCLR_CTS_Enabled (1UL)
- #define UARTE_INTENCLR_CTS_Clear (1UL)
- #define UARTE_ERRORSRC_BREAK_Pos (3UL)
- #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos)
- #define UARTE_ERRORSRC_BREAK_NotPresent (0UL)
- #define UARTE_ERRORSRC_BREAK_Present (1UL)
- #define UARTE_ERRORSRC_FRAMING_Pos (2UL)
- #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos)
- #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL)
- #define UARTE_ERRORSRC_FRAMING_Present (1UL)
- #define UARTE_ERRORSRC_PARITY_Pos (1UL)
- #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos)
- #define UARTE_ERRORSRC_PARITY_NotPresent (0UL)
- #define UARTE_ERRORSRC_PARITY_Present (1UL)
- #define UARTE_ERRORSRC_OVERRUN_Pos (0UL)
- #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos)
- #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL)
- #define UARTE_ERRORSRC_OVERRUN_Present (1UL)
- #define UARTE_ENABLE_ENABLE_Pos (0UL)
- #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos)
- #define UARTE_ENABLE_ENABLE_Disabled (0UL)
- #define UARTE_ENABLE_ENABLE_Enabled (8UL)
- #define UARTE_PSEL_RTS_CONNECT_Pos (31UL)
- #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos)
- #define UARTE_PSEL_RTS_CONNECT_Connected (0UL)
- #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL)
- #define UARTE_PSEL_RTS_PIN_Pos (0UL)
- #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos)
- #define UARTE_PSEL_TXD_CONNECT_Pos (31UL)
- #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos)
- #define UARTE_PSEL_TXD_CONNECT_Connected (0UL)
- #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL)
- #define UARTE_PSEL_TXD_PIN_Pos (0UL)
- #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos)
- #define UARTE_PSEL_CTS_CONNECT_Pos (31UL)
- #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos)
- #define UARTE_PSEL_CTS_CONNECT_Connected (0UL)
- #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL)
- #define UARTE_PSEL_CTS_PIN_Pos (0UL)
- #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos)
- #define UARTE_PSEL_RXD_CONNECT_Pos (31UL)
- #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos)
- #define UARTE_PSEL_RXD_CONNECT_Connected (0UL)
- #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL)
- #define UARTE_PSEL_RXD_PIN_Pos (0UL)
- #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos)
- #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL)
- #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos)
- #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL)
- #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL)
- #define UARTE_RXD_PTR_PTR_Pos (0UL)
- #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos)
- #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL)
- #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos)
- #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL)
- #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos)
- #define UARTE_TXD_PTR_PTR_Pos (0UL)
- #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos)
- #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL)
- #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos)
- #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL)
- #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos)
- #define UARTE_CONFIG_STOP_Pos (4UL)
- #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos)
- #define UARTE_CONFIG_STOP_One (0UL)
- #define UARTE_CONFIG_STOP_Two (1UL)
- #define UARTE_CONFIG_PARITY_Pos (1UL)
- #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos)
- #define UARTE_CONFIG_PARITY_Excluded (0x0UL)
- #define UARTE_CONFIG_PARITY_Included (0x7UL)
- #define UARTE_CONFIG_HWFC_Pos (0UL)
- #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos)
- #define UARTE_CONFIG_HWFC_Disabled (0UL)
- #define UARTE_CONFIG_HWFC_Enabled (1UL)
- #define UICR_APPROTECT_PALL_Pos (0UL)
- #define UICR_APPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_APPROTECT_PALL_Pos)
- #define UICR_APPROTECT_PALL_Protected (0x00000000UL)
- #define UICR_APPROTECT_PALL_Unprotected (0xFFFFFFFFUL)
- #define UICR_XOSC32M_CTRL_Pos (0UL)
- #define UICR_XOSC32M_CTRL_Msk (0x3FUL << UICR_XOSC32M_CTRL_Pos)
- #define UICR_HFXOSRC_HFXOSRC_Pos (0UL)
- #define UICR_HFXOSRC_HFXOSRC_Msk (0x1UL << UICR_HFXOSRC_HFXOSRC_Pos)
- #define UICR_HFXOSRC_HFXOSRC_TCXO (0UL)
- #define UICR_HFXOSRC_HFXOSRC_XTAL (1UL)
- #define UICR_HFXOCNT_HFXOCNT_Pos (0UL)
- #define UICR_HFXOCNT_HFXOCNT_Msk (0xFFUL << UICR_HFXOCNT_HFXOCNT_Pos)
- #define UICR_HFXOCNT_HFXOCNT_MinDebounceTime (0UL)
- #define UICR_HFXOCNT_HFXOCNT_MaxDebounceTime (255UL)
- #define UICR_SECUREAPPROTECT_PALL_Pos (0UL)
- #define UICR_SECUREAPPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_SECUREAPPROTECT_PALL_Pos)
- #define UICR_SECUREAPPROTECT_PALL_Protected (0x00000000UL)
- #define UICR_SECUREAPPROTECT_PALL_Unprotected (0xFFFFFFFFUL)
- #define UICR_ERASEPROTECT_PALL_Pos (0UL)
- #define UICR_ERASEPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_ERASEPROTECT_PALL_Pos)
- #define UICR_ERASEPROTECT_PALL_Protected (0x00000000UL)
- #define UICR_ERASEPROTECT_PALL_Unprotected (0xFFFFFFFFUL)
- #define UICR_OTP_UPPER_Pos (16UL)
- #define UICR_OTP_UPPER_Msk (0xFFFFUL << UICR_OTP_UPPER_Pos)
- #define UICR_OTP_LOWER_Pos (0UL)
- #define UICR_OTP_LOWER_Msk (0xFFFFUL << UICR_OTP_LOWER_Pos)
- #define UICR_KEYSLOT_CONFIG_DEST_DEST_Pos (0UL)
- #define UICR_KEYSLOT_CONFIG_DEST_DEST_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_CONFIG_DEST_DEST_Pos)
- #define UICR_KEYSLOT_CONFIG_PERM_STATE_Pos (16UL)
- #define UICR_KEYSLOT_CONFIG_PERM_STATE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_STATE_Pos)
- #define UICR_KEYSLOT_CONFIG_PERM_STATE_Revoked (0UL)
- #define UICR_KEYSLOT_CONFIG_PERM_STATE_Active (1UL)
- #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos (2UL)
- #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos)
- #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Disabled (0UL)
- #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Enabled (1UL)
- #define UICR_KEYSLOT_CONFIG_PERM_READ_Pos (1UL)
- #define UICR_KEYSLOT_CONFIG_PERM_READ_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_READ_Pos)
- #define UICR_KEYSLOT_CONFIG_PERM_READ_Disabled (0UL)
- #define UICR_KEYSLOT_CONFIG_PERM_READ_Enabled (1UL)
- #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos (0UL)
- #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos)
- #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Disabled (0UL)
- #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Enabled (1UL)
- #define UICR_KEYSLOT_KEY_VALUE_VALUE_Pos (0UL)
- #define UICR_KEYSLOT_KEY_VALUE_VALUE_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_KEY_VALUE_VALUE_Pos)
- #define VMC_RAM_POWER_S3RETENTION_Pos (19UL)
- #define VMC_RAM_POWER_S3RETENTION_Msk (0x1UL << VMC_RAM_POWER_S3RETENTION_Pos)
- #define VMC_RAM_POWER_S3RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S3RETENTION_On (1UL)
- #define VMC_RAM_POWER_S2RETENTION_Pos (18UL)
- #define VMC_RAM_POWER_S2RETENTION_Msk (0x1UL << VMC_RAM_POWER_S2RETENTION_Pos)
- #define VMC_RAM_POWER_S2RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S2RETENTION_On (1UL)
- #define VMC_RAM_POWER_S1RETENTION_Pos (17UL)
- #define VMC_RAM_POWER_S1RETENTION_Msk (0x1UL << VMC_RAM_POWER_S1RETENTION_Pos)
- #define VMC_RAM_POWER_S1RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S1RETENTION_On (1UL)
- #define VMC_RAM_POWER_S0RETENTION_Pos (16UL)
- #define VMC_RAM_POWER_S0RETENTION_Msk (0x1UL << VMC_RAM_POWER_S0RETENTION_Pos)
- #define VMC_RAM_POWER_S0RETENTION_Off (0UL)
- #define VMC_RAM_POWER_S0RETENTION_On (1UL)
- #define VMC_RAM_POWER_S3POWER_Pos (3UL)
- #define VMC_RAM_POWER_S3POWER_Msk (0x1UL << VMC_RAM_POWER_S3POWER_Pos)
- #define VMC_RAM_POWER_S3POWER_Off (0UL)
- #define VMC_RAM_POWER_S3POWER_On (1UL)
- #define VMC_RAM_POWER_S2POWER_Pos (2UL)
- #define VMC_RAM_POWER_S2POWER_Msk (0x1UL << VMC_RAM_POWER_S2POWER_Pos)
- #define VMC_RAM_POWER_S2POWER_Off (0UL)
- #define VMC_RAM_POWER_S2POWER_On (1UL)
- #define VMC_RAM_POWER_S1POWER_Pos (1UL)
- #define VMC_RAM_POWER_S1POWER_Msk (0x1UL << VMC_RAM_POWER_S1POWER_Pos)
- #define VMC_RAM_POWER_S1POWER_Off (0UL)
- #define VMC_RAM_POWER_S1POWER_On (1UL)
- #define VMC_RAM_POWER_S0POWER_Pos (0UL)
- #define VMC_RAM_POWER_S0POWER_Msk (0x1UL << VMC_RAM_POWER_S0POWER_Pos)
- #define VMC_RAM_POWER_S0POWER_Off (0UL)
- #define VMC_RAM_POWER_S0POWER_On (1UL)
- #define VMC_RAM_POWERSET_S3RETENTION_Pos (19UL)
- #define VMC_RAM_POWERSET_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S3RETENTION_Pos)
- #define VMC_RAM_POWERSET_S3RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S2RETENTION_Pos (18UL)
- #define VMC_RAM_POWERSET_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S2RETENTION_Pos)
- #define VMC_RAM_POWERSET_S2RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S1RETENTION_Pos (17UL)
- #define VMC_RAM_POWERSET_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S1RETENTION_Pos)
- #define VMC_RAM_POWERSET_S1RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S0RETENTION_Pos (16UL)
- #define VMC_RAM_POWERSET_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S0RETENTION_Pos)
- #define VMC_RAM_POWERSET_S0RETENTION_On (1UL)
- #define VMC_RAM_POWERSET_S3POWER_Pos (3UL)
- #define VMC_RAM_POWERSET_S3POWER_Msk (0x1UL << VMC_RAM_POWERSET_S3POWER_Pos)
- #define VMC_RAM_POWERSET_S3POWER_On (1UL)
- #define VMC_RAM_POWERSET_S2POWER_Pos (2UL)
- #define VMC_RAM_POWERSET_S2POWER_Msk (0x1UL << VMC_RAM_POWERSET_S2POWER_Pos)
- #define VMC_RAM_POWERSET_S2POWER_On (1UL)
- #define VMC_RAM_POWERSET_S1POWER_Pos (1UL)
- #define VMC_RAM_POWERSET_S1POWER_Msk (0x1UL << VMC_RAM_POWERSET_S1POWER_Pos)
- #define VMC_RAM_POWERSET_S1POWER_On (1UL)
- #define VMC_RAM_POWERSET_S0POWER_Pos (0UL)
- #define VMC_RAM_POWERSET_S0POWER_Msk (0x1UL << VMC_RAM_POWERSET_S0POWER_Pos)
- #define VMC_RAM_POWERSET_S0POWER_On (1UL)
- #define VMC_RAM_POWERCLR_S3RETENTION_Pos (19UL)
- #define VMC_RAM_POWERCLR_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S3RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S3RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S2RETENTION_Pos (18UL)
- #define VMC_RAM_POWERCLR_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S2RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S2RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S1RETENTION_Pos (17UL)
- #define VMC_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S1RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S1RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S0RETENTION_Pos (16UL)
- #define VMC_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S0RETENTION_Pos)
- #define VMC_RAM_POWERCLR_S0RETENTION_Off (1UL)
- #define VMC_RAM_POWERCLR_S3POWER_Pos (3UL)
- #define VMC_RAM_POWERCLR_S3POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S3POWER_Pos)
- #define VMC_RAM_POWERCLR_S3POWER_Off (1UL)
- #define VMC_RAM_POWERCLR_S2POWER_Pos (2UL)
- #define VMC_RAM_POWERCLR_S2POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S2POWER_Pos)
- #define VMC_RAM_POWERCLR_S2POWER_Off (1UL)
- #define VMC_RAM_POWERCLR_S1POWER_Pos (1UL)
- #define VMC_RAM_POWERCLR_S1POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S1POWER_Pos)
- #define VMC_RAM_POWERCLR_S1POWER_Off (1UL)
- #define VMC_RAM_POWERCLR_S0POWER_Pos (0UL)
- #define VMC_RAM_POWERCLR_S0POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S0POWER_Pos)
- #define VMC_RAM_POWERCLR_S0POWER_Off (1UL)
- #define WDT_TASKS_START_TASKS_START_Pos (0UL)
- #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos)
- #define WDT_TASKS_START_TASKS_START_Trigger (1UL)
- #define WDT_SUBSCRIBE_START_EN_Pos (31UL)
- #define WDT_SUBSCRIBE_START_EN_Msk (0x1UL << WDT_SUBSCRIBE_START_EN_Pos)
- #define WDT_SUBSCRIBE_START_EN_Disabled (0UL)
- #define WDT_SUBSCRIBE_START_EN_Enabled (1UL)
- #define WDT_SUBSCRIBE_START_CHIDX_Pos (0UL)
- #define WDT_SUBSCRIBE_START_CHIDX_Msk (0xFUL << WDT_SUBSCRIBE_START_CHIDX_Pos)
- #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL)
- #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos)
- #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL)
- #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL)
- #define WDT_PUBLISH_TIMEOUT_EN_Pos (31UL)
- #define WDT_PUBLISH_TIMEOUT_EN_Msk (0x1UL << WDT_PUBLISH_TIMEOUT_EN_Pos)
- #define WDT_PUBLISH_TIMEOUT_EN_Disabled (0UL)
- #define WDT_PUBLISH_TIMEOUT_EN_Enabled (1UL)
- #define WDT_PUBLISH_TIMEOUT_CHIDX_Pos (0UL)
- #define WDT_PUBLISH_TIMEOUT_CHIDX_Msk (0xFUL << WDT_PUBLISH_TIMEOUT_CHIDX_Pos)
- #define WDT_INTENSET_TIMEOUT_Pos (0UL)
- #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos)
- #define WDT_INTENSET_TIMEOUT_Disabled (0UL)
- #define WDT_INTENSET_TIMEOUT_Enabled (1UL)
- #define WDT_INTENSET_TIMEOUT_Set (1UL)
- #define WDT_INTENCLR_TIMEOUT_Pos (0UL)
- #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos)
- #define WDT_INTENCLR_TIMEOUT_Disabled (0UL)
- #define WDT_INTENCLR_TIMEOUT_Enabled (1UL)
- #define WDT_INTENCLR_TIMEOUT_Clear (1UL)
- #define WDT_RUNSTATUS_RUNSTATUSWDT_Pos (0UL)
- #define WDT_RUNSTATUS_RUNSTATUSWDT_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUSWDT_Pos)
- #define WDT_RUNSTATUS_RUNSTATUSWDT_NotRunning (0UL)
- #define WDT_RUNSTATUS_RUNSTATUSWDT_Running (1UL)
- #define WDT_REQSTATUS_RR7_Pos (7UL)
- #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos)
- #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL)
- #define WDT_REQSTATUS_RR6_Pos (6UL)
- #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos)
- #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL)
- #define WDT_REQSTATUS_RR5_Pos (5UL)
- #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos)
- #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL)
- #define WDT_REQSTATUS_RR4_Pos (4UL)
- #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos)
- #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL)
- #define WDT_REQSTATUS_RR3_Pos (3UL)
- #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos)
- #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL)
- #define WDT_REQSTATUS_RR2_Pos (2UL)
- #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos)
- #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL)
- #define WDT_REQSTATUS_RR1_Pos (1UL)
- #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos)
- #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL)
- #define WDT_REQSTATUS_RR0_Pos (0UL)
- #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos)
- #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL)
- #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL)
- #define WDT_CRV_CRV_Pos (0UL)
- #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos)
- #define WDT_RREN_RR7_Pos (7UL)
- #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos)
- #define WDT_RREN_RR7_Disabled (0UL)
- #define WDT_RREN_RR7_Enabled (1UL)
- #define WDT_RREN_RR6_Pos (6UL)
- #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos)
- #define WDT_RREN_RR6_Disabled (0UL)
- #define WDT_RREN_RR6_Enabled (1UL)
- #define WDT_RREN_RR5_Pos (5UL)
- #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos)
- #define WDT_RREN_RR5_Disabled (0UL)
- #define WDT_RREN_RR5_Enabled (1UL)
- #define WDT_RREN_RR4_Pos (4UL)
- #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos)
- #define WDT_RREN_RR4_Disabled (0UL)
- #define WDT_RREN_RR4_Enabled (1UL)
- #define WDT_RREN_RR3_Pos (3UL)
- #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos)
- #define WDT_RREN_RR3_Disabled (0UL)
- #define WDT_RREN_RR3_Enabled (1UL)
- #define WDT_RREN_RR2_Pos (2UL)
- #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos)
- #define WDT_RREN_RR2_Disabled (0UL)
- #define WDT_RREN_RR2_Enabled (1UL)
- #define WDT_RREN_RR1_Pos (1UL)
- #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos)
- #define WDT_RREN_RR1_Disabled (0UL)
- #define WDT_RREN_RR1_Enabled (1UL)
- #define WDT_RREN_RR0_Pos (0UL)
- #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos)
- #define WDT_RREN_RR0_Disabled (0UL)
- #define WDT_RREN_RR0_Enabled (1UL)
- #define WDT_CONFIG_HALT_Pos (3UL)
- #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos)
- #define WDT_CONFIG_HALT_Pause (0UL)
- #define WDT_CONFIG_HALT_Run (1UL)
- #define WDT_CONFIG_SLEEP_Pos (0UL)
- #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos)
- #define WDT_CONFIG_SLEEP_Pause (0UL)
- #define WDT_CONFIG_SLEEP_Run (1UL)
- #define WDT_RR_RR_Pos (0UL)
- #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos)
- #define WDT_RR_RR_Reload (0x6E524635UL)
- #endif
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