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- #ifndef NRF_MWU_H__
- #define NRF_MWU_H__
- #include <nrfx.h>
- #ifdef __cplusplus
- extern "C" {
- #endif
- typedef enum
- {
- NRF_MWU_EVENT_REGION0_WRITE = offsetof(NRF_MWU_Type, EVENTS_REGION[0].WA),
- NRF_MWU_EVENT_REGION0_READ = offsetof(NRF_MWU_Type, EVENTS_REGION[0].RA),
- NRF_MWU_EVENT_REGION1_WRITE = offsetof(NRF_MWU_Type, EVENTS_REGION[1].WA),
- NRF_MWU_EVENT_REGION1_READ = offsetof(NRF_MWU_Type, EVENTS_REGION[1].RA),
- NRF_MWU_EVENT_REGION2_WRITE = offsetof(NRF_MWU_Type, EVENTS_REGION[2].WA),
- NRF_MWU_EVENT_REGION2_READ = offsetof(NRF_MWU_Type, EVENTS_REGION[2].RA),
- NRF_MWU_EVENT_REGION3_WRITE = offsetof(NRF_MWU_Type, EVENTS_REGION[3].WA),
- NRF_MWU_EVENT_REGION3_READ = offsetof(NRF_MWU_Type, EVENTS_REGION[3].RA),
- NRF_MWU_EVENT_PREGION0_WRITE = offsetof(NRF_MWU_Type, EVENTS_PREGION[0].WA),
- NRF_MWU_EVENT_PREGION0_READ = offsetof(NRF_MWU_Type, EVENTS_PREGION[0].RA),
- NRF_MWU_EVENT_PREGION1_WRITE = offsetof(NRF_MWU_Type, EVENTS_PREGION[1].WA),
- NRF_MWU_EVENT_PREGION1_READ = offsetof(NRF_MWU_Type, EVENTS_PREGION[1].RA),
- } nrf_mwu_event_t;
- typedef enum
- {
- NRF_MWU_INT_REGION0_WRITE_MASK = MWU_INTEN_REGION0WA_Msk,
- NRF_MWU_INT_REGION0_READ_MASK = MWU_INTEN_REGION0RA_Msk,
- NRF_MWU_INT_REGION1_WRITE_MASK = MWU_INTEN_REGION1WA_Msk,
- NRF_MWU_INT_REGION1_READ_MASK = MWU_INTEN_REGION1RA_Msk,
- NRF_MWU_INT_REGION2_WRITE_MASK = MWU_INTEN_REGION2WA_Msk,
- NRF_MWU_INT_REGION2_READ_MASK = MWU_INTEN_REGION2RA_Msk,
- NRF_MWU_INT_REGION3_WRITE_MASK = MWU_INTEN_REGION3WA_Msk,
- NRF_MWU_INT_REGION3_READ_MASK = MWU_INTEN_REGION3RA_Msk,
- NRF_MWU_INT_PREGION0_WRITE_MASK = MWU_INTEN_PREGION0WA_Msk,
- NRF_MWU_INT_PREGION0_READ_MASK = MWU_INTEN_PREGION0RA_Msk,
- NRF_MWU_INT_PREGION1_WRITE_MASK = MWU_INTEN_PREGION1WA_Msk,
- NRF_MWU_INT_PREGION1_READ_MASK = MWU_INTEN_PREGION1RA_Msk,
- } nrf_mwu_int_mask_t;
- typedef enum
- {
- NRF_MWU_WATCH_REGION0_WRITE = MWU_REGIONEN_RGN0WA_Msk,
- NRF_MWU_WATCH_REGION0_READ = MWU_REGIONEN_RGN0RA_Msk,
- NRF_MWU_WATCH_REGION1_WRITE = MWU_REGIONEN_RGN1WA_Msk,
- NRF_MWU_WATCH_REGION1_READ = MWU_REGIONEN_RGN1RA_Msk,
- NRF_MWU_WATCH_REGION2_WRITE = MWU_REGIONEN_RGN2WA_Msk,
- NRF_MWU_WATCH_REGION2_READ = MWU_REGIONEN_RGN2RA_Msk,
- NRF_MWU_WATCH_REGION3_WRITE = MWU_REGIONEN_RGN3WA_Msk,
- NRF_MWU_WATCH_REGION3_READ = MWU_REGIONEN_RGN3RA_Msk,
- NRF_MWU_WATCH_PREGION0_WRITE = MWU_REGIONEN_PRGN0WA_Msk,
- NRF_MWU_WATCH_PREGION0_READ = MWU_REGIONEN_PRGN0RA_Msk,
- NRF_MWU_WATCH_PREGION1_WRITE = MWU_REGIONEN_PRGN1WA_Msk,
- NRF_MWU_WATCH_PREGION1_READ = MWU_REGIONEN_PRGN1RA_Msk,
- } nrf_mwu_region_watch_t;
- __STATIC_INLINE bool nrf_mwu_event_check(NRF_MWU_Type const * p_reg,
- nrf_mwu_event_t event);
- __STATIC_INLINE void nrf_mwu_event_clear(NRF_MWU_Type * p_reg,
- nrf_mwu_event_t event);
- __STATIC_INLINE uint32_t nrf_mwu_event_address_get(NRF_MWU_Type const * p_reg,
- nrf_mwu_event_t event);
- __STATIC_INLINE void nrf_mwu_int_enable(NRF_MWU_Type * p_reg, uint32_t int_mask);
- __STATIC_INLINE bool nrf_mwu_int_enable_check(NRF_MWU_Type const * p_reg,
- nrf_mwu_int_mask_t mwu_int);
- __STATIC_INLINE void nrf_mwu_int_disable(NRF_MWU_Type * p_reg, uint32_t int_mask);
- __STATIC_INLINE void nrf_mwu_nmi_enable(NRF_MWU_Type * p_reg, uint32_t int_mask);
- __STATIC_INLINE bool nrf_mwu_nmi_enable_check(NRF_MWU_Type const * p_reg,
- nrf_mwu_int_mask_t mwu_int);
- __STATIC_INLINE void nrf_mwu_nmi_disable(NRF_MWU_Type * p_reg, uint32_t int_mask);
- __STATIC_INLINE void nrf_mwu_user_region_range_set(NRF_MWU_Type * p_reg,
- uint8_t region_idx,
- uint32_t start_addr,
- uint32_t end_addr);
- __STATIC_INLINE void nrf_mwu_region_watch_enable(NRF_MWU_Type * p_reg, uint32_t reg_watch_mask);
- __STATIC_INLINE void nrf_mwu_region_watch_disable(NRF_MWU_Type * p_reg, uint32_t reg_watch_mask);
- __STATIC_INLINE uint32_t nrf_mwu_region_watch_get(NRF_MWU_Type const * p_reg);
- __STATIC_INLINE void nrf_mwu_subregions_configure(NRF_MWU_Type * p_reg,
- uint8_t per_reg_idx,
- uint32_t subregion_mask);
- __STATIC_INLINE uint32_t nrf_mwu_subregions_write_accesses_get(NRF_MWU_Type const * p_reg,
- uint8_t per_reg_idx);
- __STATIC_INLINE void nrf_mwu_subregions_write_accesses_clear(NRF_MWU_Type * p_reg,
- uint8_t per_reg_idx,
- uint32_t subregion_mask);
- __STATIC_INLINE uint32_t nrf_mwu_subregions_read_accesses_get(NRF_MWU_Type const * p_reg,
- uint8_t per_reg_idx);
- __STATIC_INLINE void nrf_mwu_subregions_read_accesses_clear(NRF_MWU_Type * p_reg,
- uint8_t per_reg_idx,
- uint32_t subregion_mask);
- #ifndef SUPPRESS_INLINE_IMPLEMENTATION
- __STATIC_INLINE bool nrf_mwu_event_check(NRF_MWU_Type const * p_reg,
- nrf_mwu_event_t event)
- {
- return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
- }
- __STATIC_INLINE void nrf_mwu_event_clear(NRF_MWU_Type * p_reg,
- nrf_mwu_event_t event)
- {
- *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
- #if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
- #endif
- }
- __STATIC_INLINE uint32_t nrf_mwu_event_address_get(NRF_MWU_Type const * p_reg,
- nrf_mwu_event_t event)
- {
- return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
- }
- __STATIC_INLINE void nrf_mwu_int_enable(NRF_MWU_Type * p_reg, uint32_t int_mask)
- {
- p_reg->INTENSET = int_mask;
- }
- __STATIC_INLINE bool nrf_mwu_int_enable_check(NRF_MWU_Type const * p_reg,
- nrf_mwu_int_mask_t mwu_int)
- {
- return (bool)(p_reg->INTENSET & mwu_int);
- }
- __STATIC_INLINE void nrf_mwu_int_disable(NRF_MWU_Type * p_reg, uint32_t int_mask)
- {
- p_reg->INTENCLR = int_mask;
- }
- __STATIC_INLINE void nrf_mwu_nmi_enable(NRF_MWU_Type * p_reg, uint32_t int_mask)
- {
- p_reg->NMIENSET = int_mask;
- }
- __STATIC_INLINE bool nrf_mwu_nmi_enable_check(NRF_MWU_Type const * p_reg,
- nrf_mwu_int_mask_t mwu_int)
- {
- return (bool)(p_reg->NMIENSET & mwu_int);
- }
- __STATIC_INLINE void nrf_mwu_nmi_disable(NRF_MWU_Type * p_reg, uint32_t int_mask)
- {
- p_reg->NMIENCLR = int_mask;
- }
- __STATIC_INLINE void nrf_mwu_user_region_range_set(NRF_MWU_Type * p_reg,
- uint8_t region_idx,
- uint32_t start_addr,
- uint32_t end_addr)
- {
- NRFX_ASSERT(region_idx < NRFX_ARRAY_SIZE(NRF_MWU->REGION));
- NRFX_ASSERT(end_addr >= start_addr);
- p_reg->REGION[region_idx].START = start_addr;
- p_reg->REGION[region_idx].END = end_addr;
- }
- __STATIC_INLINE void nrf_mwu_region_watch_enable(NRF_MWU_Type * p_reg, uint32_t reg_watch_mask)
- {
- p_reg->REGIONENSET = reg_watch_mask;
- }
- __STATIC_INLINE void nrf_mwu_region_watch_disable(NRF_MWU_Type * p_reg, uint32_t reg_watch_mask)
- {
- p_reg->REGIONENCLR = reg_watch_mask;
- }
- __STATIC_INLINE uint32_t nrf_mwu_region_watch_get(NRF_MWU_Type const * p_reg)
- {
- return p_reg->REGIONENSET;
- }
- __STATIC_INLINE void nrf_mwu_subregions_configure(NRF_MWU_Type * p_reg,
- uint8_t per_reg_idx,
- uint32_t subregion_mask)
- {
- NRFX_ASSERT(per_reg_idx < NRFX_ARRAY_SIZE(NRF_MWU->PREGION));
- p_reg->PREGION[per_reg_idx].SUBS = subregion_mask;
- }
- __STATIC_INLINE uint32_t nrf_mwu_subregions_write_accesses_get(NRF_MWU_Type const * p_reg,
- uint8_t per_reg_idx)
- {
- NRFX_ASSERT(per_reg_idx < NRFX_ARRAY_SIZE(NRF_MWU->PREGION));
- return p_reg->PERREGION[per_reg_idx].SUBSTATWA;
- }
- __STATIC_INLINE void nrf_mwu_subregions_write_accesses_clear(NRF_MWU_Type * p_reg,
- uint8_t per_reg_idx,
- uint32_t subregion_mask)
- {
- NRFX_ASSERT(per_reg_idx < NRFX_ARRAY_SIZE(NRF_MWU->PREGION));
- p_reg->PERREGION[per_reg_idx].SUBSTATWA = subregion_mask;
- }
- __STATIC_INLINE uint32_t nrf_mwu_subregions_read_accesses_get(NRF_MWU_Type const * p_reg,
- uint8_t per_reg_idx)
- {
- NRFX_ASSERT(per_reg_idx < NRFX_ARRAY_SIZE(NRF_MWU->PREGION));
- return p_reg->PERREGION[per_reg_idx].SUBSTATRA;
- }
- __STATIC_INLINE void nrf_mwu_subregions_read_accesses_clear(NRF_MWU_Type * p_reg,
- uint8_t per_reg_idx,
- uint32_t subregion_mask)
- {
- NRFX_ASSERT(per_reg_idx < NRFX_ARRAY_SIZE(NRF_MWU->PREGION));
- p_reg->PERREGION[per_reg_idx].SUBSTATRA = subregion_mask;
- }
- #endif
- #ifdef __cplusplus
- }
- #endif
- #endif
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