/************************************************************************************** * Copyright (c) 2016-2017, ARM Limited or its affiliates. All rights reserved * * * * This file and the related binary are licensed under the following license: * * * * ARM Object Code and Header Files License, v1.0 Redistribution. * * * * Redistribution and use of object code, header files, and documentation, without * * modification, are permitted provided that the following conditions are met: * * * * 1) Redistributions must reproduce the above copyright notice and the * * following disclaimer in the documentation and/or other materials * * provided with the distribution. * * * * 2) Unless to the extent explicitly permitted by law, no reverse * * engineering, decompilation, or disassembly of is permitted. * * * * 3) Redistribution and use is permitted solely for the purpose of * * developing or executing applications that are targeted for use * * on an ARM-based product. * * * * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * * CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT * * NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, * * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED * * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR * * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * **************************************************************************************/ #ifndef __DX_REG_BASE_HOST_H__ #define __DX_REG_BASE_HOST_H__ /* Identify platform: Xilinx Zynq7000 ZC706 */ #define DX_PLAT_ZYNQ7000 1 #define DX_PLAT_ZYNQ7000_ZC706 1 /* SEP core clock frequency in MHz */ #define DX_SEP_FREQ_MHZ 64 #if defined(CRYPTOCELL_ARCH_BASE_ADDRESS) #define DX_BASE_CC CRYPTOCELL_ARCH_BASE_ADDRESS #else #error Please set CRYPTOCELL_ARCH_BASE_ADDRESS to a non-negative number #endif #define DX_BASE_ENV_REGS 0x40008000 #define DX_BASE_ENV_CC_MEMORIES 0x40008000 #define DX_BASE_ENV_FLASH 0x40008700 #define DX_BASE_ENV_PERF_RAM 0x40009000 #define DX_BASE_HOST_RGF 0x0UL #define DX_BASE_CRY_KERNEL 0x0UL #define DX_BASE_ROM 0x40000000 #define DX_BASE_RNG 0x0000UL #endif /*__DX_REG_BASE_HOST_H__*/